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Interconnect tiles

The interconnect tiles are 22×80 bits. The space on the left is unused by the interconnect tile, and contains data for whatever primitive is associated with the interconnect tile.

INT_CLB

Used with CLB tiles.

Tile INT_CLB

Cells: 1

Switchbox INT

virtex2 INT_CLB switchbox INT programmable inverters
DestinationSourceBit
IMUX_CLK_OPTINV[0]IMUX_CLK[0]MAIN[4][41]
IMUX_CLK_OPTINV[1]IMUX_CLK[1]MAIN[4][49]
IMUX_CLK_OPTINV[2]IMUX_CLK[2]MAIN[4][52]
IMUX_CLK_OPTINV[3]IMUX_CLK[3]MAIN[4][60]
IMUX_SR_OPTINV[0]IMUX_SR[0]!MAIN[4][1]
IMUX_SR_OPTINV[1]IMUX_SR[1]!MAIN[4][16]
IMUX_SR_OPTINV[2]IMUX_SR[2]!MAIN[4][7]
IMUX_SR_OPTINV[3]IMUX_SR[3]!MAIN[4][10]
IMUX_CE_OPTINV[0]IMUX_CE[0]!MAIN[4][63]
IMUX_CE_OPTINV[1]IMUX_CE[1]!MAIN[4][69]
IMUX_CE_OPTINV[2]IMUX_CE[2]!MAIN[4][72]
IMUX_CE_OPTINV[3]IMUX_CE[3]!MAIN[4][78]
IMUX_TI_OPTINV[0]IMUX_TI[0]!MAIN[4][19]
IMUX_TI_OPTINV[1]IMUX_TI[1]!MAIN[4][27]
IMUX_TS_OPTINV[0]IMUX_TS[0]MAIN[4][38]
IMUX_TS_OPTINV[1]IMUX_TS[1]MAIN[4][30]
virtex2 INT_CLB switchbox INT muxes OMUX[0]
BitsDestination
MAIN[7][0]MAIN[6][1]MAIN[7][2]MAIN[7][1]MAIN[6][0]MAIN[6][3]MAIN[7][5]MAIN[7][4]MAIN[6][6]MAIN[6][9]OMUX[0]
Source
0000000000off
0001000001OUT_FAN[0]
0001000010OUT_FAN[1]
0001000100OUT_FAN[2]
0001001000OUT_FAN[3]
0001010000OUT_FAN[4]
0001100000OUT_FAN[5]
0010000001OUT_FAN[6]
0010000010OUT_FAN[7]
0010000100OUT_SEC[9]
0010001000OUT_SEC[8]
0010010000OUT_SEC[10]
0010100000OUT_SEC[11]
0100000001OUT_SEC[12]
0100000010OUT_SEC[13]
0100000100OUT_SEC[15]
0100001000OUT_TBUS
0100010000OUT_SEC[16]
0100100000OUT_SEC[17]
1000000001OUT_SEC[18]
1000000010OUT_SEC[19]
1000000100OUT_SEC[21]
1000001000OUT_SEC[20]
1000010000OUT_SEC[22]
1000100000OUT_SEC[23]
virtex2 INT_CLB switchbox INT muxes OMUX[1]
BitsDestination
MAIN[7][9]MAIN[6][8]MAIN[7][7]MAIN[7][8]MAIN[6][2]MAIN[7][3]MAIN[6][5]MAIN[6][4]MAIN[7][6]MAIN[6][7]OMUX[1]
Source
0000000000off
0001000001OUT_FAN[0]
0001000010OUT_FAN[1]
0001000100OUT_FAN[2]
0001001000OUT_FAN[3]
0001010000OUT_FAN[4]
0001100000OUT_FAN[5]
0010000001OUT_FAN[6]
0010000010OUT_FAN[7]
0010000100OUT_SEC[9]
0010001000OUT_SEC[8]
0010010000OUT_SEC[10]
0010100000OUT_SEC[11]
0100000001OUT_SEC[12]
0100000010OUT_SEC[13]
0100000100OUT_SEC[15]
0100001000OUT_TBUS
0100010000OUT_SEC[16]
0100100000OUT_SEC[17]
1000000001OUT_SEC[18]
1000000010OUT_SEC[19]
1000000100OUT_SEC[21]
1000001000OUT_SEC[20]
1000010000OUT_SEC[22]
1000100000OUT_SEC[23]
virtex2 INT_CLB switchbox INT muxes OMUX[2]
BitsDestination
MAIN[7][10]MAIN[6][11]MAIN[7][12]MAIN[7][11]MAIN[6][10]MAIN[6][13]MAIN[7][15]MAIN[7][14]MAIN[6][16]MAIN[6][19]OMUX[2]
Source
0000000000off
0001000001OUT_FAN[0]
0001000010OUT_FAN[1]
0001000100OUT_FAN[2]
0001001000OUT_FAN[3]
0001010000OUT_FAN[4]
0001100000OUT_FAN[5]
0010000001OUT_FAN[6]
0010000010OUT_FAN[7]
0010000100OUT_SEC[9]
0010001000OUT_SEC[8]
0010010000OUT_SEC[10]
0010100000OUT_SEC[11]
0100000001OUT_SEC[12]
0100000010OUT_SEC[13]
0100000100OUT_SEC[15]
0100001000OUT_SEC[14]
0100010000OUT_SEC[16]
0100100000OUT_SEC[17]
1000000001OUT_SEC[18]
1000000010OUT_SEC[19]
1000000100OUT_SEC[21]
1000001000OUT_SEC[20]
1000010000OUT_SEC[22]
1000100000OUT_SEC[23]
virtex2 INT_CLB switchbox INT muxes OMUX[3]
BitsDestination
MAIN[7][19]MAIN[6][18]MAIN[7][17]MAIN[7][18]MAIN[6][12]MAIN[7][13]MAIN[6][15]MAIN[6][14]MAIN[7][16]MAIN[6][17]OMUX[3]
Source
0000000000off
0001000001OUT_FAN[0]
0001000010OUT_FAN[1]
0001000100OUT_FAN[2]
0001001000OUT_FAN[3]
0001010000OUT_FAN[4]
0001100000OUT_FAN[5]
0010000001OUT_FAN[6]
0010000010OUT_FAN[7]
0010000100OUT_SEC[9]
0010001000OUT_SEC[8]
0010010000OUT_SEC[10]
0010100000OUT_SEC[11]
0100000001OUT_SEC[12]
0100000010OUT_SEC[13]
0100000100OUT_SEC[15]
0100001000OUT_SEC[14]
0100010000OUT_SEC[16]
0100100000OUT_SEC[17]
1000000001OUT_SEC[18]
1000000010OUT_SEC[19]
1000000100OUT_SEC[21]
1000001000OUT_SEC[20]
1000010000OUT_SEC[22]
1000100000OUT_SEC[23]
virtex2 INT_CLB switchbox INT muxes OMUX[4]
BitsDestination
MAIN[7][20]MAIN[6][21]MAIN[7][22]MAIN[7][21]MAIN[6][20]MAIN[6][23]MAIN[7][25]MAIN[7][24]MAIN[6][26]MAIN[6][29]OMUX[4]
Source
0000000000off
0001000001OUT_FAN[0]
0001000010OUT_FAN[1]
0001000100OUT_FAN[2]
0001001000OUT_FAN[3]
0001010000OUT_FAN[4]
0001100000OUT_FAN[5]
0010000001OUT_FAN[6]
0010000010OUT_FAN[7]
0010000100OUT_SEC[9]
0010001000OUT_SEC[8]
0010010000OUT_SEC[10]
0010100000OUT_SEC[11]
0100000001OUT_SEC[12]
0100000010OUT_SEC[13]
0100000100OUT_SEC[15]
0100001000OUT_SEC[14]
0100010000OUT_SEC[16]
0100100000OUT_SEC[17]
1000000001OUT_SEC[18]
1000000010OUT_SEC[19]
1000000100OUT_SEC[21]
1000001000OUT_SEC[20]
1000010000OUT_SEC[22]
1000100000OUT_SEC[23]
virtex2 INT_CLB switchbox INT muxes OMUX[5]
BitsDestination
MAIN[7][29]MAIN[6][28]MAIN[7][27]MAIN[7][28]MAIN[6][22]MAIN[7][23]MAIN[6][25]MAIN[6][24]MAIN[7][26]MAIN[6][27]OMUX[5]
Source
0000000000off
0001000001OUT_FAN[0]
0001000010OUT_FAN[1]
0001000100OUT_FAN[2]
0001001000OUT_FAN[3]
0001010000OUT_FAN[4]
0001100000OUT_FAN[5]
0010000001OUT_FAN[6]
0010000010OUT_FAN[7]
0010000100OUT_SEC[9]
0010001000OUT_SEC[8]
0010010000OUT_SEC[10]
0010100000OUT_SEC[11]
0100000001OUT_SEC[12]
0100000010OUT_SEC[13]
0100000100OUT_SEC[15]
0100001000OUT_SEC[14]
0100010000OUT_SEC[16]
0100100000OUT_SEC[17]
1000000001OUT_SEC[18]
1000000010OUT_SEC[19]
1000000100OUT_SEC[21]
1000001000OUT_SEC[20]
1000010000OUT_SEC[22]
1000100000OUT_SEC[23]
virtex2 INT_CLB switchbox INT muxes OMUX[6]
BitsDestination
MAIN[7][30]MAIN[6][31]MAIN[7][32]MAIN[7][31]MAIN[6][30]MAIN[6][33]MAIN[7][35]MAIN[7][34]MAIN[6][36]MAIN[6][39]OMUX[6]
Source
0000000000off
0001000001OUT_FAN[0]
0001000010OUT_FAN[1]
0001000100OUT_FAN[2]
0001001000OUT_FAN[3]
0001010000OUT_FAN[4]
0001100000OUT_FAN[5]
0010000001OUT_FAN[6]
0010000010OUT_FAN[7]
0010000100OUT_SEC[9]
0010001000OUT_SEC[8]
0010010000OUT_SEC[10]
0010100000OUT_SEC[11]
0100000001OUT_TBUS
0100000010OUT_SEC[13]
0100000100OUT_SEC[15]
0100001000OUT_SEC[14]
0100010000OUT_SEC[16]
0100100000OUT_SEC[17]
1000000001OUT_SEC[18]
1000000010OUT_SEC[19]
1000000100OUT_SEC[21]
1000001000OUT_SEC[20]
1000010000OUT_SEC[22]
1000100000OUT_SEC[23]
virtex2 INT_CLB switchbox INT muxes OMUX[7]
BitsDestination
MAIN[7][39]MAIN[6][38]MAIN[7][37]MAIN[7][38]MAIN[6][32]MAIN[7][33]MAIN[6][35]MAIN[6][34]MAIN[7][36]MAIN[6][37]OMUX[7]
Source
0000000000off
0001000001OUT_FAN[0]
0001000010OUT_FAN[1]
0001000100OUT_FAN[2]
0001001000OUT_FAN[3]
0001010000OUT_FAN[4]
0001100000OUT_FAN[5]
0010000001OUT_FAN[6]
0010000010OUT_FAN[7]
0010000100OUT_SEC[9]
0010001000OUT_SEC[8]
0010010000OUT_SEC[10]
0010100000OUT_SEC[11]
0100000001OUT_TBUS
0100000010OUT_SEC[13]
0100000100OUT_SEC[15]
0100001000OUT_SEC[14]
0100010000OUT_SEC[16]
0100100000OUT_SEC[17]
1000000001OUT_SEC[18]
1000000010OUT_SEC[19]
1000000100OUT_SEC[21]
1000001000OUT_SEC[20]
1000010000OUT_SEC[22]
1000100000OUT_SEC[23]
virtex2 INT_CLB switchbox INT muxes OMUX[8]
BitsDestination
MAIN[7][40]MAIN[6][41]MAIN[7][42]MAIN[7][41]MAIN[6][40]MAIN[6][43]MAIN[7][45]MAIN[7][44]MAIN[6][46]MAIN[6][49]OMUX[8]
Source
0000000000off
0001000001OUT_FAN[0]
0001000010OUT_FAN[1]
0001000100OUT_FAN[2]
0001001000OUT_FAN[3]
0001010000OUT_FAN[4]
0001100000OUT_FAN[5]
0010000001OUT_FAN[6]
0010000010OUT_FAN[7]
0010000100OUT_SEC[9]
0010001000OUT_SEC[8]
0010010000OUT_SEC[10]
0010100000OUT_SEC[11]
0100000001OUT_SEC[12]
0100000010OUT_TBUS
0100000100OUT_SEC[15]
0100001000OUT_SEC[14]
0100010000OUT_SEC[16]
0100100000OUT_SEC[17]
1000000001OUT_SEC[18]
1000000010OUT_SEC[19]
1000000100OUT_SEC[21]
1000001000OUT_SEC[20]
1000010000OUT_SEC[22]
1000100000OUT_SEC[23]
virtex2 INT_CLB switchbox INT muxes OMUX[9]
BitsDestination
MAIN[7][49]MAIN[6][48]MAIN[7][47]MAIN[7][48]MAIN[6][42]MAIN[7][43]MAIN[6][45]MAIN[6][44]MAIN[7][46]MAIN[6][47]OMUX[9]
Source
0000000000off
0001000001OUT_FAN[0]
0001000010OUT_FAN[1]
0001000100OUT_FAN[2]
0001001000OUT_FAN[3]
0001010000OUT_FAN[4]
0001100000OUT_FAN[5]
0010000001OUT_FAN[6]
0010000010OUT_FAN[7]
0010000100OUT_SEC[9]
0010001000OUT_SEC[8]
0010010000OUT_SEC[10]
0010100000OUT_SEC[11]
0100000001OUT_SEC[12]
0100000010OUT_TBUS
0100000100OUT_SEC[15]
0100001000OUT_SEC[14]
0100010000OUT_SEC[16]
0100100000OUT_SEC[17]
1000000001OUT_SEC[18]
1000000010OUT_SEC[19]
1000000100OUT_SEC[21]
1000001000OUT_SEC[20]
1000010000OUT_SEC[22]
1000100000OUT_SEC[23]
virtex2 INT_CLB switchbox INT muxes OMUX[10]
BitsDestination
MAIN[7][50]MAIN[6][51]MAIN[7][52]MAIN[7][51]MAIN[6][50]MAIN[6][53]MAIN[7][55]MAIN[7][54]MAIN[6][56]MAIN[6][59]OMUX[10]
Source
0000000000off
0001000001OUT_FAN[0]
0001000010OUT_FAN[1]
0001000100OUT_FAN[2]
0001001000OUT_FAN[3]
0001010000OUT_FAN[4]
0001100000OUT_FAN[5]
0010000001OUT_FAN[6]
0010000010OUT_FAN[7]
0010000100OUT_SEC[9]
0010001000OUT_SEC[8]
0010010000OUT_SEC[10]
0010100000OUT_SEC[11]
0100000001OUT_SEC[12]
0100000010OUT_SEC[13]
0100000100OUT_SEC[15]
0100001000OUT_SEC[14]
0100010000OUT_SEC[16]
0100100000OUT_SEC[17]
1000000001OUT_SEC[18]
1000000010OUT_SEC[19]
1000000100OUT_SEC[21]
1000001000OUT_SEC[20]
1000010000OUT_SEC[22]
1000100000OUT_SEC[23]
virtex2 INT_CLB switchbox INT muxes OMUX[11]
BitsDestination
MAIN[7][59]MAIN[6][58]MAIN[7][57]MAIN[7][58]MAIN[6][52]MAIN[7][53]MAIN[6][55]MAIN[6][54]MAIN[7][56]MAIN[6][57]OMUX[11]
Source
0000000000off
0001000001OUT_FAN[0]
0001000010OUT_FAN[1]
0001000100OUT_FAN[2]
0001001000OUT_FAN[3]
0001010000OUT_FAN[4]
0001100000OUT_FAN[5]
0010000001OUT_FAN[6]
0010000010OUT_FAN[7]
0010000100OUT_SEC[9]
0010001000OUT_SEC[8]
0010010000OUT_SEC[10]
0010100000OUT_SEC[11]
0100000001OUT_SEC[12]
0100000010OUT_SEC[13]
0100000100OUT_SEC[15]
0100001000OUT_SEC[14]
0100010000OUT_SEC[16]
0100100000OUT_SEC[17]
1000000001OUT_SEC[18]
1000000010OUT_SEC[19]
1000000100OUT_SEC[21]
1000001000OUT_SEC[20]
1000010000OUT_SEC[22]
1000100000OUT_SEC[23]
virtex2 INT_CLB switchbox INT muxes OMUX[12]
BitsDestination
MAIN[7][60]MAIN[6][61]MAIN[7][62]MAIN[7][61]MAIN[6][60]MAIN[6][63]MAIN[7][65]MAIN[7][64]MAIN[6][66]MAIN[6][69]OMUX[12]
Source
0000000000off
0001000001OUT_FAN[0]
0001000010OUT_FAN[1]
0001000100OUT_FAN[2]
0001001000OUT_FAN[3]
0001010000OUT_FAN[4]
0001100000OUT_FAN[5]
0010000001OUT_FAN[6]
0010000010OUT_FAN[7]
0010000100OUT_SEC[9]
0010001000OUT_SEC[8]
0010010000OUT_SEC[10]
0010100000OUT_SEC[11]
0100000001OUT_SEC[12]
0100000010OUT_SEC[13]
0100000100OUT_SEC[15]
0100001000OUT_SEC[14]
0100010000OUT_SEC[16]
0100100000OUT_SEC[17]
1000000001OUT_SEC[18]
1000000010OUT_SEC[19]
1000000100OUT_SEC[21]
1000001000OUT_SEC[20]
1000010000OUT_SEC[22]
1000100000OUT_SEC[23]
virtex2 INT_CLB switchbox INT muxes OMUX[13]
BitsDestination
MAIN[7][69]MAIN[6][68]MAIN[7][67]MAIN[7][68]MAIN[6][62]MAIN[7][63]MAIN[6][65]MAIN[6][64]MAIN[7][66]MAIN[6][67]OMUX[13]
Source
0000000000off
0001000001OUT_FAN[0]
0001000010OUT_FAN[1]
0001000100OUT_FAN[2]
0001001000OUT_FAN[3]
0001010000OUT_FAN[4]
0001100000OUT_FAN[5]
0010000001OUT_FAN[6]
0010000010OUT_FAN[7]
0010000100OUT_SEC[9]
0010001000OUT_SEC[8]
0010010000OUT_SEC[10]
0010100000OUT_SEC[11]
0100000001OUT_SEC[12]
0100000010OUT_SEC[13]
0100000100OUT_SEC[15]
0100001000OUT_SEC[14]
0100010000OUT_SEC[16]
0100100000OUT_SEC[17]
1000000001OUT_SEC[18]
1000000010OUT_SEC[19]
1000000100OUT_SEC[21]
1000001000OUT_SEC[20]
1000010000OUT_SEC[22]
1000100000OUT_SEC[23]
virtex2 INT_CLB switchbox INT muxes OMUX[14]
BitsDestination
MAIN[7][70]MAIN[6][71]MAIN[7][72]MAIN[7][71]MAIN[6][70]MAIN[6][73]MAIN[7][75]MAIN[7][74]MAIN[6][76]MAIN[6][79]OMUX[14]
Source
0000000000off
0001000001OUT_FAN[0]
0001000010OUT_FAN[1]
0001000100OUT_FAN[2]
0001001000OUT_FAN[3]
0001010000OUT_FAN[4]
0001100000OUT_FAN[5]
0010000001OUT_FAN[6]
0010000010OUT_FAN[7]
0010000100OUT_SEC[9]
0010001000OUT_SEC[8]
0010010000OUT_SEC[10]
0010100000OUT_SEC[11]
0100000001OUT_SEC[12]
0100000010OUT_SEC[13]
0100000100OUT_SEC[15]
0100001000OUT_SEC[14]
0100010000OUT_SEC[16]
0100100000OUT_TBUS
1000000001OUT_SEC[18]
1000000010OUT_SEC[19]
1000000100OUT_SEC[21]
1000001000OUT_SEC[20]
1000010000OUT_SEC[22]
1000100000OUT_SEC[23]
virtex2 INT_CLB switchbox INT muxes OMUX[15]
BitsDestination
MAIN[7][79]MAIN[6][78]MAIN[7][77]MAIN[7][78]MAIN[6][72]MAIN[7][73]MAIN[6][75]MAIN[6][74]MAIN[7][76]MAIN[6][77]OMUX[15]
Source
0000000000off
0001000001OUT_FAN[0]
0001000010OUT_FAN[1]
0001000100OUT_FAN[2]
0001001000OUT_FAN[3]
0001010000OUT_FAN[4]
0001100000OUT_FAN[5]
0010000001OUT_FAN[6]
0010000010OUT_FAN[7]
0010000100OUT_SEC[9]
0010001000OUT_SEC[8]
0010010000OUT_SEC[10]
0010100000OUT_SEC[11]
0100000001OUT_SEC[12]
0100000010OUT_SEC[13]
0100000100OUT_SEC[15]
0100001000OUT_SEC[14]
0100010000OUT_SEC[16]
0100100000OUT_TBUS
1000000001OUT_SEC[18]
1000000010OUT_SEC[19]
1000000100OUT_SEC[21]
1000001000OUT_SEC[20]
1000010000OUT_SEC[22]
1000100000OUT_SEC[23]
virtex2 INT_CLB switchbox INT muxes DBL_W0[0]
BitsDestination
MAIN[16][5]MAIN[16][6]MAIN[17][6]MAIN[17][5]MAIN[15][7]MAIN[14][5]MAIN[14][4]MAIN[15][6]DBL_W0[0]
Source
00000000off
00010001OMUX_S0
00010010HEX_E6[0]
00010100OUT_FAN[3]
00011000HEX_N6[0]
00100001OMUX_NW10
00100010HEX_S6[1]
00100100OUT_FAN[4]
00101000HEX_W6[0]
01000001DBL_W2[0]
01000010HEX_N3[0]
01000100HEX_S3[0]
01001000DBL_N3[9]
10000001DBL_W2_N[8]
10000010DBL_S1[0]
10000100DBL_S2[2]
10001000DBL_N1[0]
virtex2 INT_CLB switchbox INT muxes DBL_W0[1]
BitsDestination
MAIN[16][13]MAIN[16][14]MAIN[17][14]MAIN[17][13]MAIN[15][15]MAIN[14][13]MAIN[14][12]MAIN[15][14]DBL_W0[1]
Source
00000000off
00010001OMUX[2]
00010010HEX_E6[1]
00010100OUT_FAN[2]
00011000HEX_N6[1]
00100001OMUX_W1
00100010HEX_S6[2]
00100100OUT_FAN[5]
00101000HEX_W6[1]
01000001DBL_W2[1]
01000010HEX_N3[1]
01000100HEX_S3[1]
01001000DBL_N2[0]
10000001DBL_W2_N[9]
10000010DBL_S1[1]
10000100DBL_S2[3]
10001000DBL_N1[1]
virtex2 INT_CLB switchbox INT muxes DBL_W0[2]
BitsDestination
MAIN[15][23]MAIN[14][20]MAIN[15][22]MAIN[14][21]MAIN[16][22]MAIN[16][21]MAIN[17][22]MAIN[17][21]DBL_W0[2]
Source
00000000off
00010001OMUX[4]
00010010OUT_FAN[3]
00010100DBL_S2[4]
00011000HEX_S3[2]
00100001OMUX[6]
00100010OMUX_WN14
00100100DBL_W2[0]
00101000DBL_W2[2]
01000001HEX_E6[2]
01000010HEX_S6[3]
01000100DBL_S1[2]
01001000HEX_N3[2]
10000001HEX_N6[2]
10000010HEX_W6[2]
10000100DBL_N1[2]
10001000DBL_N2[1]
virtex2 INT_CLB switchbox INT muxes DBL_W0[3]
BitsDestination
MAIN[16][30]MAIN[16][29]MAIN[17][30]MAIN[17][29]MAIN[15][31]MAIN[14][29]MAIN[14][28]MAIN[15][30]DBL_W0[3]
Source
00000000off
00010001OMUX_W6
00010010HEX_E6[3]
00010100OUT_FAN[4]
00011000HEX_N6[3]
00100001OMUX_NW10
00100010HEX_S6[4]
00100100OUT_FAN[2]
00101000HEX_W6[3]
01000001DBL_W2[1]
01000010DBL_S1[3]
01000100DBL_S2[5]
01001000DBL_N1[3]
10000001DBL_W2[3]
10000010HEX_N3[3]
10000100HEX_S3[3]
10001000DBL_N2[2]
virtex2 INT_CLB switchbox INT muxes DBL_W0[4]
BitsDestination
MAIN[16][38]MAIN[16][37]MAIN[17][38]MAIN[17][37]MAIN[15][39]MAIN[14][37]MAIN[14][36]MAIN[15][38]DBL_W0[4]
Source
00000000off
00010001OMUX_WS1
00010010HEX_E6[4]
00010100OUT_FAN[5]
00011000HEX_N6[4]
00100001OMUX_N12
00100010HEX_S6[5]
00100100OUT_FAN[6]
00101000HEX_W6[4]
01000001DBL_W2[2]
01000010DBL_S1[4]
01000100DBL_S2[6]
01001000DBL_N1[4]
10000001DBL_W2[4]
10000010HEX_N3[4]
10000100HEX_S3[4]
10001000DBL_N2[3]
virtex2 INT_CLB switchbox INT muxes DBL_W0[5]
BitsDestination
MAIN[16][46]MAIN[16][45]MAIN[17][46]MAIN[17][45]MAIN[15][47]MAIN[14][45]MAIN[14][44]MAIN[15][46]DBL_W0[5]
Source
00000000off
00010001OMUX_S3
00010010HEX_E6[5]
00010100OUT_FAN[1]
00011000HEX_N6[5]
00100001OMUX_WN14
00100010HEX_S6[6]
00100100OUT_FAN[7]
00101000HEX_W6[5]
01000001DBL_W2[3]
01000010DBL_S1[5]
01000100DBL_S2[7]
01001000DBL_N1[5]
10000001DBL_W2[5]
10000010HEX_N3[5]
10000100HEX_S3[5]
10001000DBL_N2[4]
virtex2 INT_CLB switchbox INT muxes DBL_W0[6]
BitsDestination
MAIN[15][55]MAIN[14][52]MAIN[15][54]MAIN[14][53]MAIN[16][54]MAIN[16][53]MAIN[17][53]MAIN[17][54]DBL_W0[6]
Source
00000000off
00010001OMUX[11]
00010010OUT_FAN[0]
00010100DBL_S2[8]
00011000HEX_S3[6]
00100001OMUX_W9
00100010OMUX_SW5
00100100DBL_W2[4]
00101000DBL_W2[6]
01000001HEX_S6[7]
01000010HEX_E6[6]
01000100DBL_S1[6]
01001000HEX_N3[6]
10000001HEX_W6[6]
10000010HEX_N6[6]
10000100DBL_N1[6]
10001000DBL_N2[5]
virtex2 INT_CLB switchbox INT muxes DBL_W0[7]
BitsDestination
MAIN[16][62]MAIN[16][61]MAIN[17][61]MAIN[17][62]MAIN[15][63]MAIN[14][61]MAIN[14][60]MAIN[15][62]DBL_W0[7]
Source
00000000off
00010001OMUX[9]
00010010HEX_S6[8]
00010100OUT_FAN[1]
00011000HEX_W6[7]
00100001OMUX_WS1
00100010HEX_E6[7]
00100100OUT_FAN[6]
00101000HEX_N6[7]
01000001DBL_W2[5]
01000010DBL_S1[7]
01000100DBL_S2[9]
01001000DBL_N1[7]
10000001DBL_W2[7]
10000010HEX_N3[7]
10000100HEX_S3[7]
10001000DBL_N2[6]
virtex2 INT_CLB switchbox INT muxes DBL_W0[8]
BitsDestination
MAIN[16][70]MAIN[16][69]MAIN[17][69]MAIN[17][70]MAIN[15][71]MAIN[14][69]MAIN[14][68]MAIN[15][70]DBL_W0[8]
Source
00000000off
00010001OMUX[13]
00010010HEX_S6[9]
00010100OUT_FAN[0]
00011000HEX_W6[8]
00100001OMUX_W14
00100010HEX_E6[8]
00100100OUT_FAN[7]
00101000HEX_N6[8]
01000001DBL_W2[6]
01000010DBL_S1[8]
01000100DBL_S3[0]
01001000DBL_N1[8]
10000001DBL_W2[8]
10000010HEX_N3[8]
10000100HEX_S3[8]
10001000DBL_N2[7]
virtex2 INT_CLB switchbox INT muxes DBL_W0[9]
BitsDestination
MAIN[15][79]MAIN[14][76]MAIN[14][77]MAIN[15][78]MAIN[16][78]MAIN[16][77]MAIN[17][77]MAIN[17][78]DBL_W0[9]
Source
00000000off
00010001OMUX[13]
00010010OMUX_SW5
00010100DBL_W2[7]
00011000DBL_W2[9]
00100001OMUX_S0
00100010OMUX[15]
00100100DBL_S3[1]
00101000HEX_S3[9]
01000001HEX_S7[0]
01000010HEX_E6[9]
01000100DBL_S1[9]
01001000HEX_N3[9]
10000001HEX_W6[9]
10000010HEX_N6[9]
10000100DBL_N1[9]
10001000DBL_N2[8]
virtex2 INT_CLB switchbox INT muxes DBL_E0[0]
BitsDestination
MAIN[17][7]MAIN[17][4]MAIN[16][4]MAIN[16][7]MAIN[15][5]MAIN[14][7]MAIN[15][4]MAIN[14][6]DBL_E0[0]
Source
00000000off
00010001OMUX_E2
00010010HEX_S6[1]
00010100OUT_FAN[4]
00011000HEX_W6[0]
00100001OMUX_EN8
00100010HEX_E6[0]
00100100OUT_FAN[3]
00101000HEX_N6[0]
01000001DBL_E2[0]
01000010DBL_S1[0]
01000100DBL_S2[2]
01001000DBL_N1[0]
10000001DBL_E2[2]
10000010HEX_N3[0]
10000100HEX_S3[0]
10001000DBL_N3[9]
virtex2 INT_CLB switchbox INT muxes DBL_E0[1]
BitsDestination
MAIN[17][15]MAIN[17][12]MAIN[16][12]MAIN[16][15]MAIN[15][13]MAIN[14][15]MAIN[15][12]MAIN[14][14]DBL_E0[1]
Source
00000000off
00010001OMUX_S4
00010010HEX_S6[2]
00010100OUT_FAN[5]
00011000HEX_W6[1]
00100001OMUX_N10
00100010HEX_E6[1]
00100100OUT_FAN[2]
00101000HEX_N6[1]
01000001DBL_E2[1]
01000010DBL_S1[1]
01000100DBL_S2[3]
01001000DBL_N1[1]
10000001DBL_E2[3]
10000010HEX_N3[1]
10000100HEX_S3[1]
10001000DBL_N2[0]
virtex2 INT_CLB switchbox INT muxes DBL_E0[2]
BitsDestination
MAIN[15][21]MAIN[15][20]MAIN[14][22]MAIN[14][23]MAIN[17][23]MAIN[17][20]MAIN[16][23]MAIN[16][20]DBL_E0[2]
Source
00000000off
00010001OMUX[4]
00010010OUT_FAN[3]
00010100DBL_S2[4]
00011000HEX_S3[2]
00100001OMUX_NE12
00100010OMUX[6]
00100100DBL_E2[2]
00101000DBL_E2[4]
01000001HEX_E6[2]
01000010HEX_S6[3]
01000100DBL_S1[2]
01001000HEX_N3[2]
10000001HEX_N6[2]
10000010HEX_W6[2]
10000100DBL_N1[2]
10001000DBL_N2[1]
virtex2 INT_CLB switchbox INT muxes DBL_E0[3]
BitsDestination
MAIN[17][31]MAIN[17][28]MAIN[16][28]MAIN[16][31]MAIN[15][29]MAIN[14][31]MAIN[15][28]MAIN[14][30]DBL_E0[3]
Source
00000000off
00010001OMUX_SE3
00010010HEX_S6[4]
00010100OUT_FAN[2]
00011000HEX_W6[3]
00100001OMUX_EN8
00100010HEX_E6[3]
00100100OUT_FAN[4]
00101000HEX_N6[3]
01000001DBL_E2[3]
01000010DBL_S1[3]
01000100DBL_S2[5]
01001000DBL_N1[3]
10000001DBL_E2[5]
10000010HEX_N3[3]
10000100HEX_S3[3]
10001000DBL_N2[2]
virtex2 INT_CLB switchbox INT muxes DBL_E0[4]
BitsDestination
MAIN[17][39]MAIN[17][36]MAIN[16][39]MAIN[16][36]MAIN[15][37]MAIN[14][39]MAIN[15][36]MAIN[14][38]DBL_E0[4]
Source
00000000off
00010001OMUX_E7
00010010HEX_E6[4]
00010100OUT_FAN[5]
00011000HEX_N6[4]
00100001OMUX_E8
00100010HEX_S6[5]
00100100OUT_FAN[6]
00101000HEX_W6[4]
01000001DBL_E2[4]
01000010DBL_S1[4]
01000100DBL_S2[6]
01001000DBL_N1[4]
10000001DBL_E2[6]
10000010HEX_N3[4]
10000100HEX_S3[4]
10001000DBL_N2[3]
virtex2 INT_CLB switchbox INT muxes DBL_E0[5]
BitsDestination
MAIN[17][47]MAIN[17][44]MAIN[16][44]MAIN[16][47]MAIN[15][45]MAIN[14][47]MAIN[15][44]MAIN[14][46]DBL_E0[5]
Source
00000000off
00010001OMUX_ES7
00010010HEX_S6[6]
00010100OUT_FAN[7]
00011000HEX_W6[5]
00100001OMUX_NE12
00100010HEX_E6[5]
00100100OUT_FAN[1]
00101000HEX_N6[5]
01000001DBL_E2[5]
01000010DBL_S1[5]
01000100DBL_S2[7]
01001000DBL_N1[5]
10000001DBL_E2[7]
10000010HEX_N3[5]
10000100HEX_S3[5]
10001000DBL_N2[4]
virtex2 INT_CLB switchbox INT muxes DBL_E0[6]
BitsDestination
MAIN[17][55]MAIN[17][52]MAIN[16][55]MAIN[16][52]MAIN[15][53]MAIN[15][52]MAIN[14][55]MAIN[14][54]DBL_E0[6]
Source
00000000off
00010001OMUX[9]
00010010OUT_FAN[0]
00010100HEX_E6[6]
00011000HEX_N6[6]
00100001OMUX_SE3
00100010OMUX[11]
00100100HEX_S6[7]
00101000HEX_W6[6]
01000001DBL_E2[6]
01000010DBL_S2[8]
01000100DBL_S1[6]
01001000DBL_N1[6]
10000001DBL_E2[8]
10000010HEX_S3[6]
10000100HEX_N3[6]
10001000DBL_N2[5]
virtex2 INT_CLB switchbox INT muxes DBL_E0[7]
BitsDestination
MAIN[17][63]MAIN[17][60]MAIN[16][60]MAIN[16][63]MAIN[15][61]MAIN[14][63]MAIN[15][60]MAIN[14][62]DBL_E0[7]
Source
00000000off
00010001OMUX_S5
00010010HEX_S6[8]
00010100OUT_FAN[1]
00011000HEX_W6[7]
00100001OMUX_N11
00100010HEX_E6[7]
00100100OUT_FAN[6]
00101000HEX_N6[7]
01000001DBL_E2[7]
01000010DBL_S1[7]
01000100DBL_S2[9]
01001000DBL_N1[7]
10000001DBL_E2[9]
10000010HEX_N3[7]
10000100HEX_S3[7]
10001000DBL_N2[6]
virtex2 INT_CLB switchbox INT muxes DBL_E0[8]
BitsDestination
MAIN[17][71]MAIN[17][68]MAIN[16][68]MAIN[16][71]MAIN[15][69]MAIN[14][71]MAIN[15][68]MAIN[14][70]DBL_E0[8]
Source
00000000off
00010001OMUX_ES7
00010010HEX_S6[9]
00010100OUT_FAN[0]
00011000HEX_W6[8]
00100001OMUX_E13
00100010HEX_E6[8]
00100100OUT_FAN[7]
00101000HEX_N6[8]
01000001DBL_E2[8]
01000010DBL_S1[8]
01000100DBL_S3[0]
01001000DBL_N1[8]
10000001DBL_E2_S[0]
10000010HEX_N3[8]
10000100HEX_S3[8]
10001000DBL_N2[7]
virtex2 INT_CLB switchbox INT muxes DBL_E0[9]
BitsDestination
MAIN[17][79]MAIN[17][76]MAIN[16][79]MAIN[16][76]MAIN[15][77]MAIN[15][76]MAIN[14][78]MAIN[14][79]DBL_E0[9]
Source
00000000off
00010001OMUX[15]
00010010OMUX_N15
00010100HEX_E6[9]
00011000HEX_N6[9]
00100001OMUX_S0
00100010OMUX_S2
00100100HEX_S7[0]
00101000HEX_W6[9]
01000001DBL_S3[1]
01000010DBL_E2[9]
01000100DBL_S1[9]
01001000DBL_N1[9]
10000001HEX_S3[9]
10000010DBL_E2_S[1]
10000100HEX_N3[9]
10001000DBL_N2[8]
virtex2 INT_CLB switchbox INT muxes DBL_S0[0]
BitsDestination
MAIN[15][0]MAIN[15][1]MAIN[14][2]MAIN[14][3]MAIN[17][3]MAIN[17][0]MAIN[16][3]MAIN[16][0]DBL_S0[0]
Source
00000000off
00010001OMUX[0]
00010010OUT_FAN[3]
00010100DBL_E2[1]
00011000HEX_E3[0]
00100001OMUX[2]
00100010OMUX_S0
00100100DBL_S2[0]
00101000DBL_S2[2]
01000001HEX_W6_N[9]
01000010HEX_N6[0]
01000100DBL_W1[0]
01001000DBL_W2_N[8]
10000001HEX_S6[0]
10000010HEX_E6[0]
10000100DBL_E1[0]
10001000HEX_W3[0]
virtex2 INT_CLB switchbox INT muxes DBL_S0[1]
BitsDestination
MAIN[17][11]MAIN[17][8]MAIN[16][8]MAIN[16][11]MAIN[14][11]MAIN[15][8]MAIN[15][9]MAIN[14][10]DBL_S0[1]
Source
00000000off
00010001OMUX[2]
00010010HEX_N6[1]
00010100HEX_E6[1]
00011000OUT_FAN[2]
00100001OMUX_E2
00100010HEX_W6[0]
00100100HEX_S6[1]
00101000OUT_FAN[4]
01000001DBL_S2[1]
01000010DBL_W1[1]
01000100DBL_E1[1]
01001000DBL_E2[2]
10000001DBL_S2[3]
10000010DBL_W2_N[9]
10000100HEX_W3[1]
10001000HEX_E3[1]
virtex2 INT_CLB switchbox INT muxes DBL_S0[2]
BitsDestination
MAIN[15][16]MAIN[15][17]MAIN[14][18]MAIN[14][19]MAIN[17][19]MAIN[17][16]MAIN[16][16]MAIN[16][19]DBL_S0[2]
Source
00000000off
00010001OMUX[4]
00010010OUT_FAN[5]
00010100DBL_E2[3]
00011000HEX_E3[2]
00100001OMUX[6]
00100010OMUX_S4
00100100DBL_S2[2]
00101000DBL_S2[4]
01000001HEX_N6[2]
01000010HEX_W6[1]
01000100DBL_W1[2]
01001000DBL_W2[0]
10000001HEX_E6[2]
10000010HEX_S6[2]
10000100DBL_E1[2]
10001000HEX_W3[2]
virtex2 INT_CLB switchbox INT muxes DBL_S0[3]
BitsDestination
MAIN[17][27]MAIN[17][24]MAIN[16][27]MAIN[16][24]MAIN[14][27]MAIN[15][24]MAIN[15][25]MAIN[14][26]DBL_S0[3]
Source
00000000off
00010001OMUX[6]
00010010HEX_W6[2]
00010100HEX_S6[3]
00011000OUT_FAN[3]
00100001OMUX_W6
00100010HEX_N6[3]
00100100HEX_E6[3]
00101000OUT_FAN[4]
01000001DBL_S2[3]
01000010DBL_W1[3]
01000100DBL_E1[3]
01001000DBL_E2[4]
10000001DBL_S2[5]
10000010DBL_W2[1]
10000100HEX_W3[3]
10001000HEX_E3[3]
virtex2 INT_CLB switchbox INT muxes DBL_S0[4]
BitsDestination
MAIN[17][35]MAIN[17][32]MAIN[16][32]MAIN[16][35]MAIN[14][35]MAIN[15][32]MAIN[15][33]MAIN[14][34]DBL_S0[4]
Source
00000000off
00010001OMUX_WS1
00010010HEX_N6[4]
00010100HEX_E6[4]
00011000OUT_FAN[5]
00100001OMUX_SE3
00100010HEX_W6[3]
00100100HEX_S6[4]
00101000OUT_FAN[2]
01000001DBL_S2[4]
01000010DBL_W1[4]
01000100DBL_E1[4]
01001000DBL_E2[5]
10000001DBL_S2[6]
10000010DBL_W2[2]
10000100HEX_W3[4]
10001000HEX_E3[4]
virtex2 INT_CLB switchbox INT muxes DBL_S0[5]
BitsDestination
MAIN[17][43]MAIN[17][40]MAIN[16][40]MAIN[16][43]MAIN[14][43]MAIN[15][40]MAIN[15][41]MAIN[14][42]DBL_S0[5]
Source
00000000off
00010001OMUX_S3
00010010HEX_N6[5]
00010100HEX_E6[5]
00011000OUT_FAN[1]
00100001OMUX_E8
00100010HEX_W6[4]
00100100HEX_S6[5]
00101000OUT_FAN[6]
01000001DBL_S2[5]
01000010DBL_W1[5]
01000100DBL_E1[5]
01001000DBL_E2[6]
10000001DBL_S2[7]
10000010DBL_W2[3]
10000100HEX_W3[5]
10001000HEX_E3[5]
virtex2 INT_CLB switchbox INT muxes DBL_S0[6]
BitsDestination
MAIN[17][51]MAIN[17][48]MAIN[16][48]MAIN[16][51]MAIN[14][51]MAIN[15][48]MAIN[15][49]MAIN[14][50]DBL_S0[6]
Source
00000000off
00010001OMUX_SW5
00010010HEX_N6[6]
00010100HEX_E6[6]
00011000OUT_FAN[0]
00100001OMUX_ES7
00100010HEX_W6[5]
00100100HEX_S6[6]
00101000OUT_FAN[7]
01000001DBL_S2[6]
01000010DBL_W1[6]
01000100DBL_E1[6]
01001000DBL_E2[7]
10000001DBL_S2[8]
10000010DBL_W2[4]
10000100HEX_W3[6]
10001000HEX_E3[6]
virtex2 INT_CLB switchbox INT muxes DBL_S0[7]
BitsDestination
MAIN[15][56]MAIN[15][57]MAIN[14][58]MAIN[14][59]MAIN[17][59]MAIN[17][56]MAIN[16][59]MAIN[16][56]DBL_S0[7]
Source
00000000off
00010001OMUX[11]
00010010OUT_FAN[6]
00010100DBL_E2[8]
00011000HEX_E3[7]
00100001OMUX_SE3
00100010OMUX_WS1
00100100DBL_S2[7]
00101000DBL_S2[9]
01000001HEX_W6[6]
01000010HEX_N6[7]
01000100DBL_W1[7]
01001000DBL_W2[5]
10000001HEX_S6[7]
10000010HEX_E6[7]
10000100DBL_E1[7]
10001000HEX_W3[7]
virtex2 INT_CLB switchbox INT muxes DBL_S0[8]
BitsDestination
MAIN[17][67]MAIN[17][64]MAIN[16][67]MAIN[16][64]MAIN[14][67]MAIN[15][64]MAIN[15][65]MAIN[14][66]DBL_S0[8]
Source
00000000off
00010001OMUX_S5
00010010HEX_W6[7]
00010100HEX_S6[8]
00011000OUT_FAN[1]
00100001OMUX_W14
00100010HEX_N6[8]
00100100HEX_E6[8]
00101000OUT_FAN[7]
01000001DBL_S2[8]
01000010DBL_W1[8]
01000100DBL_E1[8]
01001000DBL_E2[9]
10000001DBL_S3[0]
10000010DBL_W2[6]
10000100HEX_W3[8]
10001000HEX_E3[8]
virtex2 INT_CLB switchbox INT muxes DBL_S0[9]
BitsDestination
MAIN[15][72]MAIN[15][73]MAIN[14][74]MAIN[14][75]MAIN[17][75]MAIN[17][72]MAIN[16][72]MAIN[16][75]DBL_S0[9]
Source
00000000off
00010001OMUX[15]
00010010OUT_FAN[0]
00010100DBL_E2_S[0]
00011000HEX_E3[9]
00100001OMUX_SW5
00100010OMUX_ES7
00100100DBL_S2[9]
00101000DBL_S3[1]
01000001HEX_N6[9]
01000010HEX_W6[8]
01000100DBL_W1[9]
01001000DBL_W2[7]
10000001HEX_E6[9]
10000010HEX_S6[9]
10000100DBL_E1[9]
10001000HEX_W3[9]
virtex2 INT_CLB switchbox INT muxes DBL_N0[0]
BitsDestination
MAIN[14][0]MAIN[15][3]MAIN[15][2]MAIN[14][1]MAIN[16][2]MAIN[16][1]MAIN[17][2]MAIN[17][1]DBL_N0[0]
Source
00000000off
00010001OMUX[0]
00010010OUT_FAN[3]
00010100DBL_E2[1]
00011000HEX_E3[0]
00100001OMUX_N13
00100010OMUX_EN8
00100100DBL_N3[8]
00101000DBL_N2[0]
01000001HEX_W6_N[9]
01000010HEX_N6[0]
01000100DBL_W1[0]
01001000DBL_W2_N[8]
10000001HEX_S6[0]
10000010HEX_E6[0]
10000100DBL_E1[0]
10001000HEX_W3[0]
virtex2 INT_CLB switchbox INT muxes DBL_N0[1]
BitsDestination
MAIN[16][10]MAIN[16][9]MAIN[17][9]MAIN[17][10]MAIN[14][9]MAIN[14][8]MAIN[15][11]MAIN[15][10]DBL_N0[1]
Source
00000000off
00010001OMUX_N10
00010010HEX_N6[1]
00010100HEX_E6[1]
00011000OUT_FAN[2]
00100001OMUX_NW10
00100010HEX_W6[0]
00100100HEX_S6[1]
00101000OUT_FAN[4]
01000001DBL_N3[9]
01000010DBL_W1[1]
01000100DBL_E1[1]
01001000DBL_E2[2]
10000001DBL_N2[1]
10000010DBL_W2_N[9]
10000100HEX_W3[1]
10001000HEX_E3[1]
virtex2 INT_CLB switchbox INT muxes DBL_N0[2]
BitsDestination
MAIN[14][16]MAIN[15][19]MAIN[15][18]MAIN[14][17]MAIN[16][18]MAIN[16][17]MAIN[17][17]MAIN[17][18]DBL_N0[2]
Source
00000000off
00010001OMUX[4]
00010010OUT_FAN[5]
00010100DBL_E2[3]
00011000HEX_E3[2]
00100001OMUX_NE12
00100010OMUX_W1
00100100DBL_N2[0]
00101000DBL_N2[2]
01000001HEX_N6[2]
01000010HEX_W6[1]
01000100DBL_W1[2]
01001000DBL_W2[0]
10000001HEX_E6[2]
10000010HEX_S6[2]
10000100DBL_E1[2]
10001000HEX_W3[2]
virtex2 INT_CLB switchbox INT muxes DBL_N0[3]
BitsDestination
MAIN[16][26]MAIN[16][25]MAIN[17][25]MAIN[17][26]MAIN[14][25]MAIN[14][24]MAIN[15][27]MAIN[15][26]DBL_N0[3]
Source
00000000off
00010001OMUX_EN8
00010010HEX_N6[3]
00010100HEX_E6[3]
00011000OUT_FAN[4]
00100001OMUX_WN14
00100010HEX_W6[2]
00100100HEX_S6[3]
00101000OUT_FAN[3]
01000001DBL_N2[1]
01000010DBL_W1[3]
01000100DBL_E1[3]
01001000DBL_E2[4]
10000001DBL_N2[3]
10000010DBL_W2[1]
10000100HEX_W3[3]
10001000HEX_E3[3]
virtex2 INT_CLB switchbox INT muxes DBL_N0[4]
BitsDestination
MAIN[16][34]MAIN[16][33]MAIN[17][33]MAIN[17][34]MAIN[14][33]MAIN[14][32]MAIN[15][35]MAIN[15][34]DBL_N0[4]
Source
00000000off
00010001OMUX_E7
00010010HEX_N6[4]
00010100HEX_E6[4]
00011000OUT_FAN[5]
00100001OMUX_NW10
00100010HEX_W6[3]
00100100HEX_S6[4]
00101000OUT_FAN[2]
01000001DBL_N2[2]
01000010DBL_W1[4]
01000100DBL_E1[4]
01001000DBL_E2[5]
10000001DBL_N2[4]
10000010DBL_W2[2]
10000100HEX_W3[4]
10001000HEX_E3[4]
virtex2 INT_CLB switchbox INT muxes DBL_N0[5]
BitsDestination
MAIN[16][42]MAIN[16][41]MAIN[17][42]MAIN[17][41]MAIN[14][41]MAIN[14][40]MAIN[15][43]MAIN[15][42]DBL_N0[5]
Source
00000000off
00010001OMUX_N12
00010010HEX_W6[4]
00010100HEX_S6[5]
00011000OUT_FAN[6]
00100001OMUX_NE12
00100010HEX_N6[5]
00100100HEX_E6[5]
00101000OUT_FAN[1]
01000001DBL_N2[3]
01000010DBL_W1[5]
01000100DBL_E1[5]
01001000DBL_E2[6]
10000001DBL_N2[5]
10000010DBL_W2[3]
10000100HEX_W3[5]
10001000HEX_E3[5]
virtex2 INT_CLB switchbox INT muxes DBL_N0[6]
BitsDestination
MAIN[16][50]MAIN[16][49]MAIN[17][49]MAIN[17][50]MAIN[14][49]MAIN[14][48]MAIN[15][51]MAIN[15][50]DBL_N0[6]
Source
00000000off
00010001OMUX[9]
00010010HEX_N6[6]
00010100HEX_E6[6]
00011000OUT_FAN[0]
00100001OMUX_WN14
00100010HEX_W6[5]
00100100HEX_S6[6]
00101000OUT_FAN[7]
01000001DBL_N2[4]
01000010DBL_W1[6]
01000100DBL_E1[6]
01001000DBL_E2[7]
10000001DBL_N2[6]
10000010DBL_W2[4]
10000100HEX_W3[6]
10001000HEX_E3[6]
virtex2 INT_CLB switchbox INT muxes DBL_N0[7]
BitsDestination
MAIN[14][56]MAIN[15][59]MAIN[15][58]MAIN[14][57]MAIN[16][58]MAIN[16][57]MAIN[17][58]MAIN[17][57]DBL_N0[7]
Source
00000000off
00010001OMUX[11]
00010010OUT_FAN[6]
00010100DBL_E2[8]
00011000HEX_E3[7]
00100001OMUX_W9
00100010OMUX_N11
00100100DBL_N2[5]
00101000DBL_N2[7]
01000001HEX_W6[6]
01000010HEX_N6[7]
01000100DBL_W1[7]
01001000DBL_W2[5]
10000001HEX_S6[7]
10000010HEX_E6[7]
10000100DBL_E1[7]
10001000HEX_W3[7]
virtex2 INT_CLB switchbox INT muxes DBL_N0[8]
BitsDestination
MAIN[16][66]MAIN[16][65]MAIN[17][66]MAIN[17][65]MAIN[14][65]MAIN[14][64]MAIN[15][67]MAIN[15][66]DBL_N0[8]
Source
00000000off
00010001OMUX[9]
00010010HEX_W6[7]
00010100HEX_S6[8]
00011000OUT_FAN[1]
00100001OMUX_E13
00100010HEX_N6[8]
00100100HEX_E6[8]
00101000OUT_FAN[7]
01000001DBL_N2[6]
01000010DBL_W1[8]
01000100DBL_E1[8]
01001000DBL_E2[9]
10000001DBL_N2[8]
10000010DBL_W2[6]
10000100HEX_W3[8]
10001000HEX_E3[8]
virtex2 INT_CLB switchbox INT muxes DBL_N0[9]
BitsDestination
MAIN[16][74]MAIN[16][73]MAIN[17][74]MAIN[17][73]MAIN[14][72]MAIN[15][75]MAIN[14][73]MAIN[15][74]DBL_N0[9]
Source
00000000off
00010001OMUX[13]
00010010OUT_FAN[0]
00010100HEX_W6[8]
00011000HEX_S6[9]
00100001OMUX_N15
00100010OMUX[15]
00100100HEX_N6[9]
00101000HEX_E6[9]
01000001DBL_N2[7]
01000010DBL_E2_S[0]
01000100DBL_W1[9]
01001000DBL_E1[9]
10000001DBL_N2[9]
10000010HEX_E3[9]
10000100DBL_W2[7]
10001000HEX_W3[9]
virtex2 INT_CLB switchbox INT muxes HEX_W0[0]
BitsDestination
MAIN[20][4]MAIN[20][6]MAIN[20][5]MAIN[18][4]MAIN[19][6]MAIN[18][6]MAIN[19][4]HEX_W0[0]
Source
0000000off
0010001OMUX_S0
0010010HEX_S3[0]
0010100HEX_N3[0]
0011000LH[6]
0100001OUT_FAN[4]
0100010OMUX_NW10
0100100HEX_W6[0]
0101000HEX_W6_N[8]
1000001OUT_FAN[3]
1000010LH[18]
1000100HEX_N7[9]
1001000HEX_S6[2]
virtex2 INT_CLB switchbox INT muxes HEX_W0[1]
BitsDestination
MAIN[21][12]MAIN[20][15]MAIN[21][14]MAIN[18][13]MAIN[19][15]MAIN[18][15]MAIN[19][13]HEX_W0[1]
Source
0000000off
0010001OMUX[2]
0010010OUT_FAN[5]
0010100HEX_W6[1]
0011000HEX_W6_N[9]
0100001LH[0]
0100010OMUX_W1
0100100HEX_S3[1]
0101000HEX_N3[1]
1000001OUT_FAN[2]
1000010LH[12]
1000100HEX_N6[0]
1001000HEX_S6[3]
virtex2 INT_CLB switchbox INT muxes HEX_W0[2]
BitsDestination
MAIN[20][22]MAIN[20][21]MAIN[20][20]MAIN[19][22]MAIN[18][20]MAIN[18][22]MAIN[19][20]HEX_W0[2]
Source
0000000off
0010001OMUX[4]
0010010LH[18]
0010100HEX_S6[4]
0011000HEX_N6[1]
0100001OMUX[6]
0100010HEX_S3[2]
0100100LH[6]
0101000HEX_N3[2]
1000001OUT_FAN[3]
1000010OMUX_WN14
1000100HEX_W6[0]
1001000HEX_W6[2]
virtex2 INT_CLB switchbox INT muxes HEX_W0[3]
BitsDestination
MAIN[21][28]MAIN[20][31]MAIN[21][30]MAIN[19][31]MAIN[18][29]MAIN[18][31]MAIN[19][29]HEX_W0[3]
Source
0000000off
0010001OMUX_W6
0010010OUT_FAN[2]
0010100HEX_W6[1]
0011000HEX_W6[3]
0100001LH[0]
0100010OMUX_NW10
0100100HEX_N3[3]
0101000HEX_S3[3]
1000001OUT_FAN[4]
1000010LH[12]
1000100HEX_S6[5]
1001000HEX_N6[2]
virtex2 INT_CLB switchbox INT muxes HEX_W0[4]
BitsDestination
MAIN[20][36]MAIN[20][38]MAIN[20][37]MAIN[19][38]MAIN[18][36]MAIN[18][38]MAIN[19][36]HEX_W0[4]
Source
0000000off
0010001OMUX_WS1
0010010HEX_S3[4]
0010100LH[6]
0011000HEX_N3[4]
0100001OUT_FAN[6]
0100010OMUX_N12
0100100HEX_W6[2]
0101000HEX_W6[4]
1000001OUT_FAN[5]
1000010LH[18]
1000100HEX_S6[6]
1001000HEX_N6[3]
virtex2 INT_CLB switchbox INT muxes HEX_W0[5]
BitsDestination
MAIN[21][44]MAIN[20][47]MAIN[21][46]MAIN[19][47]MAIN[18][45]MAIN[18][47]MAIN[19][45]HEX_W0[5]
Source
0000000off
0010001OMUX_S3
0010010OUT_FAN[7]
0010100HEX_W6[3]
0011000HEX_W6[5]
0100001LH[0]
0100010OMUX_WN14
0100100HEX_N3[5]
0101000HEX_S3[5]
1000001OUT_FAN[1]
1000010LH[12]
1000100HEX_S6[7]
1001000HEX_N6[4]
virtex2 INT_CLB switchbox INT muxes HEX_W0[6]
BitsDestination
MAIN[20][52]MAIN[20][53]MAIN[20][54]MAIN[19][54]MAIN[18][52]MAIN[18][54]MAIN[19][52]HEX_W0[6]
Source
0000000off
0010001OMUX[11]
0010010OMUX_W9
0010100HEX_W6[4]
0011000HEX_W6[6]
0100001OMUX_SW5
0100010HEX_S3[6]
0100100LH[6]
0101000HEX_N3[6]
1000001OUT_FAN[0]
1000010LH[18]
1000100HEX_S6[8]
1001000HEX_N6[5]
virtex2 INT_CLB switchbox INT muxes HEX_W0[7]
BitsDestination
MAIN[21][60]MAIN[21][62]MAIN[20][63]MAIN[19][63]MAIN[18][61]MAIN[19][61]MAIN[18][63]HEX_W0[7]
Source
0000000off
0010001OMUX[9]
0010010LH[0]
0010100HEX_N3[7]
0011000HEX_S3[7]
0100001OUT_FAN[1]
0100010OMUX_WS1
0100100HEX_W6[5]
0101000HEX_W6[7]
1000001LH[12]
1000010OUT_FAN[6]
1000100HEX_S6[9]
1001000HEX_N6[6]
virtex2 INT_CLB switchbox INT muxes HEX_W0[8]
BitsDestination
MAIN[20][68]MAIN[20][69]MAIN[20][70]MAIN[19][70]MAIN[18][68]MAIN[19][68]MAIN[18][70]HEX_W0[8]
Source
0000000off
0010001OMUX[13]
0010010OUT_FAN[0]
0010100HEX_W6[6]
0011000HEX_W6[8]
0100001HEX_S3[8]
0100010OMUX_W14
0100100LH[6]
0101000HEX_N3[8]
1000001LH[18]
1000010OUT_FAN[7]
1000100HEX_S7[0]
1001000HEX_N6[7]
virtex2 INT_CLB switchbox INT muxes HEX_W0[9]
BitsDestination
MAIN[21][78]MAIN[21][76]MAIN[20][79]MAIN[19][79]MAIN[18][77]MAIN[19][77]MAIN[18][79]HEX_W0[9]
Source
0000000off
0010001OMUX[13]
0010010LH[0]
0010100HEX_N3[9]
0011000HEX_S3[9]
0100001LH[12]
0100010OMUX[15]
0100100HEX_S7[1]
0101000HEX_N6[8]
1000001OMUX_S0
1000010OMUX_SW5
1000100HEX_W6[7]
1001000HEX_W6[9]
virtex2 INT_CLB switchbox INT muxes HEX_E0[0]
BitsDestination
MAIN[21][4]MAIN[21][6]MAIN[20][7]MAIN[19][7]MAIN[18][5]MAIN[19][5]MAIN[18][7]HEX_E0[0]
Source
0000000off
0010001OMUX_E2
0010010LH[6]
0010100HEX_N3[0]
0011000HEX_S3[0]
0100001OUT_FAN[4]
0100010OMUX_EN8
0100100HEX_E6[0]
0101000HEX_E6[2]
1000001LH[18]
1000010OUT_FAN[3]
1000100HEX_S6[2]
1001000HEX_N7[9]
virtex2 INT_CLB switchbox INT muxes HEX_E0[1]
BitsDestination
MAIN[20][12]MAIN[20][13]MAIN[20][14]MAIN[19][14]MAIN[18][12]MAIN[19][12]MAIN[18][14]HEX_E0[1]
Source
0000000off
0010001OMUX_S4
0010010OUT_FAN[5]
0010100HEX_E6[1]
0011000HEX_E6[3]
0100001HEX_S3[1]
0100010OMUX_N10
0100100LH[0]
0101000HEX_N3[1]
1000001LH[12]
1000010OUT_FAN[2]
1000100HEX_S6[3]
1001000HEX_N6[0]
virtex2 INT_CLB switchbox INT muxes HEX_E0[2]
BitsDestination
MAIN[21][22]MAIN[20][23]MAIN[21][20]MAIN[19][23]MAIN[18][21]MAIN[18][23]MAIN[19][21]HEX_E0[2]
Source
0000000off
0010001OMUX[4]
0010010LH[18]
0010100HEX_S6[4]
0011000HEX_N6[1]
0100001LH[6]
0100010OMUX[6]
0100100HEX_N3[2]
0101000HEX_S3[2]
1000001OMUX_NE12
1000010OUT_FAN[3]
1000100HEX_E6[2]
1001000HEX_E6[4]
virtex2 INT_CLB switchbox INT muxes HEX_E0[3]
BitsDestination
MAIN[20][28]MAIN[20][29]MAIN[20][30]MAIN[19][30]MAIN[18][28]MAIN[19][28]MAIN[18][30]HEX_E0[3]
Source
0000000off
0010001OMUX_SE3
0010010OUT_FAN[2]
0010100HEX_E6[3]
0011000HEX_E6[5]
0100001HEX_S3[3]
0100010OMUX_EN8
0100100LH[0]
0101000HEX_N3[3]
1000001LH[12]
1000010OUT_FAN[4]
1000100HEX_S6[5]
1001000HEX_N6[2]
virtex2 INT_CLB switchbox INT muxes HEX_E0[4]
BitsDestination
MAIN[21][36]MAIN[20][39]MAIN[21][38]MAIN[19][39]MAIN[18][37]MAIN[18][39]MAIN[19][37]HEX_E0[4]
Source
0000000off
0010001OMUX_E7
0010010OUT_FAN[6]
0010100HEX_E6[4]
0011000HEX_E6[6]
0100001LH[6]
0100010OMUX_E8
0100100HEX_N3[4]
0101000HEX_S3[4]
1000001OUT_FAN[5]
1000010LH[18]
1000100HEX_S6[6]
1001000HEX_N6[3]
virtex2 INT_CLB switchbox INT muxes HEX_E0[5]
BitsDestination
MAIN[20][44]MAIN[20][45]MAIN[20][46]MAIN[19][46]MAIN[18][44]MAIN[19][44]MAIN[18][46]HEX_E0[5]
Source
0000000off
0010001OMUX_ES7
0010010OUT_FAN[7]
0010100HEX_E6[5]
0011000HEX_E6[7]
0100001HEX_S3[5]
0100010OMUX_NE12
0100100LH[0]
0101000HEX_N3[5]
1000001LH[12]
1000010OUT_FAN[1]
1000100HEX_S6[7]
1001000HEX_N6[4]
virtex2 INT_CLB switchbox INT muxes HEX_E0[6]
BitsDestination
MAIN[21][52]MAIN[20][55]MAIN[21][54]MAIN[19][55]MAIN[18][53]MAIN[18][55]MAIN[19][53]HEX_E0[6]
Source
0000000off
0010001OMUX[9]
0010010OMUX[11]
0010100HEX_E6[6]
0011000HEX_E6[8]
0100001LH[6]
0100010OMUX_SE3
0100100HEX_N3[6]
0101000HEX_S3[6]
1000001OUT_FAN[0]
1000010LH[18]
1000100HEX_S6[8]
1001000HEX_N6[5]
virtex2 INT_CLB switchbox INT muxes HEX_E0[7]
BitsDestination
MAIN[20][60]MAIN[20][61]MAIN[20][62]MAIN[19][62]MAIN[18][60]MAIN[19][60]MAIN[18][62]HEX_E0[7]
Source
0000000off
0010001OMUX_S5
0010010OUT_FAN[1]
0010100HEX_E6[7]
0011000HEX_E6[9]
0100001HEX_S3[7]
0100010OMUX_N11
0100100LH[0]
0101000HEX_N3[7]
1000001LH[12]
1000010OUT_FAN[6]
1000100HEX_S6[9]
1001000HEX_N6[6]
virtex2 INT_CLB switchbox INT muxes HEX_E0[8]
BitsDestination
MAIN[21][68]MAIN[21][70]MAIN[20][71]MAIN[19][71]MAIN[18][69]MAIN[19][69]MAIN[18][71]HEX_E0[8]
Source
0000000off
0010001OMUX_ES7
0010010LH[6]
0010100HEX_N3[8]
0011000HEX_S3[8]
0100001OUT_FAN[0]
0100010OMUX_E13
0100100HEX_E6[8]
0101000HEX_E6_S[0]
1000001LH[18]
1000010OUT_FAN[7]
1000100HEX_S7[0]
1001000HEX_N6[7]
virtex2 INT_CLB switchbox INT muxes HEX_E0[9]
BitsDestination
MAIN[20][77]MAIN[20][78]MAIN[20][76]MAIN[19][78]MAIN[18][76]MAIN[18][78]MAIN[19][76]HEX_E0[9]
Source
0000000off
0010001OMUX[15]
0010010LH[12]
0010100HEX_S7[1]
0011000HEX_N6[8]
0100001OMUX_S0
0100010OMUX_S2
0100100HEX_E6[9]
0101000HEX_E6_S[1]
1000001OMUX_N15
1000010HEX_S3[9]
1000100LH[0]
1001000HEX_N3[9]
virtex2 INT_CLB switchbox INT muxes HEX_S0[0]
BitsDestination
MAIN[20][3]MAIN[21][2]MAIN[21][0]MAIN[19][3]MAIN[18][1]MAIN[18][3]MAIN[19][1]HEX_S0[0]
Source
0000000off
0010001OMUX[0]
0010010LV[0]
0010100HEX_E6[1]
0011000HEX_W6_N[8]
0100001OMUX[2]
0100010OUT_FAN[3]
0100100HEX_S6[0]
0101000HEX_S6[2]
1000001LV[12]
1000010OMUX_S0
1000100HEX_W3[0]
1001000HEX_E3[0]
virtex2 INT_CLB switchbox INT muxes HEX_S0[1]
BitsDestination
MAIN[20][8]MAIN[20][9]MAIN[20][10]MAIN[18][8]MAIN[19][10]MAIN[19][8]MAIN[18][10]HEX_S0[1]
Source
0000000off
0010001OMUX[2]
0010010OUT_FAN[2]
0010100HEX_S6[3]
0011000HEX_S6[1]
0100001HEX_E3[1]
0100010OMUX_E2
0100100HEX_W3[1]
0101000LV[18]
1000001LV[6]
1000010OUT_FAN[4]
1000100HEX_W6_N[9]
1001000HEX_E6[2]
virtex2 INT_CLB switchbox INT muxes HEX_S0[2]
BitsDestination
MAIN[21][16]MAIN[20][19]MAIN[21][18]MAIN[19][19]MAIN[18][17]MAIN[19][17]MAIN[18][19]HEX_S0[2]
Source
0000000off
0010001OMUX[4]
0010010OMUX_S4
0010100HEX_S6[2]
0011000HEX_S6[4]
0100001OMUX[6]
0100010LV[12]
0100100HEX_W3[2]
0101000HEX_E3[2]
1000001LV[0]
1000010OUT_FAN[5]
1000100HEX_E6[3]
1001000HEX_W6[0]
virtex2 INT_CLB switchbox INT muxes HEX_S0[3]
BitsDestination
MAIN[20][24]MAIN[20][26]MAIN[20][25]MAIN[18][24]MAIN[19][26]MAIN[18][26]MAIN[19][24]HEX_S0[3]
Source
0000000off
0010001OMUX[6]
0010010HEX_E3[3]
0010100HEX_W3[3]
0011000LV[18]
0100001OUT_FAN[4]
0100010OMUX_W6
0100100HEX_S6[5]
0101000HEX_S6[3]
1000001OUT_FAN[3]
1000010LV[6]
1000100HEX_W6[1]
1001000HEX_E6[4]
virtex2 INT_CLB switchbox INT muxes HEX_S0[4]
BitsDestination
MAIN[21][32]MAIN[21][34]MAIN[20][35]MAIN[19][35]MAIN[18][33]MAIN[19][33]MAIN[18][35]HEX_S0[4]
Source
0000000off
0010001OMUX_WS1
0010010LV[12]
0010100HEX_W3[4]
0011000HEX_E3[4]
0100001OUT_FAN[5]
0100010OMUX_SE3
0100100HEX_S6[4]
0101000HEX_S6[6]
1000001LV[0]
1000010OUT_FAN[2]
1000100HEX_E6[5]
1001000HEX_W6[2]
virtex2 INT_CLB switchbox INT muxes HEX_S0[5]
BitsDestination
MAIN[20][40]MAIN[20][41]MAIN[20][42]MAIN[18][40]MAIN[19][42]MAIN[19][40]MAIN[18][42]HEX_S0[5]
Source
0000000off
0010001OMUX_S3
0010010OUT_FAN[1]
0010100HEX_S6[7]
0011000HEX_S6[5]
0100001HEX_E3[5]
0100010OMUX_E8
0100100HEX_W3[5]
0101000LV[18]
1000001LV[6]
1000010OUT_FAN[6]
1000100HEX_W6[3]
1001000HEX_E6[6]
virtex2 INT_CLB switchbox INT muxes HEX_S0[6]
BitsDestination
MAIN[21][48]MAIN[21][50]MAIN[20][51]MAIN[19][51]MAIN[18][49]MAIN[19][49]MAIN[18][51]HEX_S0[6]
Source
0000000off
0010001OMUX_SW5
0010010LV[12]
0010100HEX_W3[6]
0011000HEX_E3[6]
0100001OUT_FAN[0]
0100010OMUX_ES7
0100100HEX_S6[6]
0101000HEX_S6[8]
1000001LV[0]
1000010OUT_FAN[7]
1000100HEX_E6[7]
1001000HEX_W6[4]
virtex2 INT_CLB switchbox INT muxes HEX_S0[7]
BitsDestination
MAIN[20][57]MAIN[20][58]MAIN[20][56]MAIN[18][56]MAIN[19][58]MAIN[18][58]MAIN[19][56]HEX_S0[7]
Source
0000000off
0010001OMUX[11]
0010010LV[6]
0010100HEX_W6[5]
0011000HEX_E6[8]
0100001OUT_FAN[6]
0100010OMUX_WS1
0100100HEX_S6[9]
0101000HEX_S6[7]
1000001OMUX_SE3
1000010HEX_E3[7]
1000100HEX_W3[7]
1001000LV[18]
virtex2 INT_CLB switchbox INT muxes HEX_S0[8]
BitsDestination
MAIN[21][64]MAIN[20][67]MAIN[21][66]MAIN[19][67]MAIN[18][65]MAIN[18][67]MAIN[19][65]HEX_S0[8]
Source
0000000off
0010001OMUX_S5
0010010OUT_FAN[7]
0010100HEX_S6[8]
0011000HEX_S7[0]
0100001LV[12]
0100010OMUX_W14
0100100HEX_W3[8]
0101000HEX_E3[8]
1000001OUT_FAN[1]
1000010LV[0]
1000100HEX_E6[9]
1001000HEX_W6[6]
virtex2 INT_CLB switchbox INT muxes HEX_S0[9]
BitsDestination
MAIN[20][72]MAIN[20][73]MAIN[20][74]MAIN[18][72]MAIN[19][74]MAIN[18][74]MAIN[19][72]HEX_S0[9]
Source
0000000off
0010001OMUX[15]
0010010OMUX_SW5
0010100HEX_S7[1]
0011000HEX_S6[9]
0100001OMUX_ES7
0100010HEX_E3[9]
0100100HEX_W3[9]
0101000LV[18]
1000001OUT_FAN[0]
1000010LV[6]
1000100HEX_W6[7]
1001000HEX_E6_S[0]
virtex2 INT_CLB switchbox INT muxes HEX_N0[0]
BitsDestination
MAIN[20][1]MAIN[20][2]MAIN[20][0]MAIN[18][0]MAIN[19][2]MAIN[18][2]MAIN[19][0]HEX_N0[0]
Source
0000000off
0010001OMUX[0]
0010010LV[0]
0010100HEX_W6_N[8]
0011000HEX_E6[1]
0100001OUT_FAN[3]
0100010OMUX_EN8
0100100HEX_N6[0]
0101000HEX_N7[8]
1000001OMUX_N13
1000010HEX_E3[0]
1000100HEX_W3[0]
1001000LV[12]
virtex2 INT_CLB switchbox INT muxes HEX_N0[1]
BitsDestination
MAIN[21][8]MAIN[21][10]MAIN[20][11]MAIN[19][11]MAIN[18][9]MAIN[19][9]MAIN[18][11]HEX_N0[1]
Source
0000000off
0010001OMUX_N10
0010010LV[18]
0010100HEX_W3[1]
0011000HEX_E3[1]
0100001OUT_FAN[2]
0100010OMUX_NW10
0100100HEX_N7[9]
0101000HEX_N6[1]
1000001LV[6]
1000010OUT_FAN[4]
1000100HEX_E6[2]
1001000HEX_W6_N[9]
virtex2 INT_CLB switchbox INT muxes HEX_N0[2]
BitsDestination
MAIN[20][16]MAIN[20][17]MAIN[20][18]MAIN[18][16]MAIN[19][18]MAIN[18][18]MAIN[19][16]HEX_N0[2]
Source
0000000off
0010001OMUX[4]
0010010OMUX_NE12
0010100HEX_N6[2]
0011000HEX_N6[0]
0100001OMUX_W1
0100010HEX_E3[2]
0100100HEX_W3[2]
0101000LV[12]
1000001OUT_FAN[5]
1000010LV[0]
1000100HEX_W6[0]
1001000HEX_E6[3]
virtex2 INT_CLB switchbox INT muxes HEX_N0[3]
BitsDestination
MAIN[21][24]MAIN[21][26]MAIN[20][27]MAIN[19][27]MAIN[18][25]MAIN[19][25]MAIN[18][27]HEX_N0[3]
Source
0000000off
0010001OMUX_EN8
0010010LV[18]
0010100HEX_W3[3]
0011000HEX_E3[3]
0100001OUT_FAN[4]
0100010OMUX_WN14
0100100HEX_N6[1]
0101000HEX_N6[3]
1000001LV[6]
1000010OUT_FAN[3]
1000100HEX_E6[4]
1001000HEX_W6[1]
virtex2 INT_CLB switchbox INT muxes HEX_N0[4]
BitsDestination
MAIN[20][32]MAIN[20][33]MAIN[20][34]MAIN[18][32]MAIN[19][34]MAIN[19][32]MAIN[18][34]HEX_N0[4]
Source
0000000off
0010001OMUX_E7
0010010OUT_FAN[5]
0010100HEX_N6[4]
0011000HEX_N6[2]
0100001HEX_E3[4]
0100010OMUX_NW10
0100100HEX_W3[4]
0101000LV[12]
1000001LV[0]
1000010OUT_FAN[2]
1000100HEX_W6[2]
1001000HEX_E6[5]
virtex2 INT_CLB switchbox INT muxes HEX_N0[5]
BitsDestination
MAIN[21][40]MAIN[20][43]MAIN[21][42]MAIN[19][43]MAIN[18][41]MAIN[18][43]MAIN[19][41]HEX_N0[5]
Source
0000000off
0010001OMUX_N12
0010010OUT_FAN[1]
0010100HEX_N6[3]
0011000HEX_N6[5]
0100001LV[18]
0100010OMUX_NE12
0100100HEX_W3[5]
0101000HEX_E3[5]
1000001OUT_FAN[6]
1000010LV[6]
1000100HEX_E6[6]
1001000HEX_W6[3]
virtex2 INT_CLB switchbox INT muxes HEX_N0[6]
BitsDestination
MAIN[20][48]MAIN[20][49]MAIN[20][50]MAIN[18][48]MAIN[19][50]MAIN[19][48]MAIN[18][50]HEX_N0[6]
Source
0000000off
0010001OMUX[9]
0010010OUT_FAN[0]
0010100HEX_N6[6]
0011000HEX_N6[4]
0100001HEX_E3[6]
0100010OMUX_WN14
0100100HEX_W3[6]
0101000LV[12]
1000001LV[0]
1000010OUT_FAN[7]
1000100HEX_W6[4]
1001000HEX_E6[7]
virtex2 INT_CLB switchbox INT muxes HEX_N0[7]
BitsDestination
MAIN[20][59]MAIN[21][58]MAIN[21][56]MAIN[19][59]MAIN[18][57]MAIN[18][59]MAIN[19][57]HEX_N0[7]
Source
0000000off
0010001OMUX[11]
0010010LV[6]
0010100HEX_E6[8]
0011000HEX_W6[5]
0100001OMUX_W9
0100010OUT_FAN[6]
0100100HEX_N6[5]
0101000HEX_N6[7]
1000001LV[18]
1000010OMUX_N11
1000100HEX_W3[7]
1001000HEX_E3[7]
virtex2 INT_CLB switchbox INT muxes HEX_N0[8]
BitsDestination
MAIN[20][64]MAIN[20][66]MAIN[20][65]MAIN[18][64]MAIN[19][66]MAIN[18][66]MAIN[19][64]HEX_N0[8]
Source
0000000off
0010001OMUX[9]
0010010HEX_E3[8]
0010100HEX_W3[8]
0011000LV[12]
0100001OUT_FAN[7]
0100010OMUX_E13
0100100HEX_N6[8]
0101000HEX_N6[6]
1000001OUT_FAN[1]
1000010LV[0]
1000100HEX_W6[6]
1001000HEX_E6[9]
virtex2 INT_CLB switchbox INT muxes HEX_N0[9]
BitsDestination
MAIN[21][72]MAIN[20][75]MAIN[21][74]MAIN[19][75]MAIN[18][73]MAIN[18][75]MAIN[19][73]HEX_N0[9]
Source
0000000off
0010001OMUX[13]
0010010OMUX[15]
0010100HEX_N6[7]
0011000HEX_N6[9]
0100001LV[18]
0100010OMUX_N15
0100100HEX_W3[9]
0101000HEX_E3[9]
1000001OUT_FAN[0]
1000010LV[6]
1000100HEX_E6_S[0]
1001000HEX_W6[7]
virtex2 INT_CLB switchbox INT muxes LH[0]
BitsDestination
MAIN[21][47]MAIN[21][49]MAIN[21][51]LH[0]
Source
000off
001DBL_W1[5]
011OMUX_S4
101DBL_E1[6]
111OMUX[11]
virtex2 INT_CLB switchbox INT muxes LH[6]
BitsDestination
MAIN[21][31]MAIN[21][33]MAIN[21][29]LH[6]
Source
000off
001OMUX[4]
011OMUX_N15
101DBL_E1[4]
111DBL_W1[3]
virtex2 INT_CLB switchbox INT muxes LH[12]
BitsDestination
MAIN[21][41]MAIN[21][45]MAIN[21][43]LH[12]
Source
000off
001DBL_W1[5]
011OMUX_S4
101DBL_E1[6]
111OMUX[11]
virtex2 INT_CLB switchbox INT muxes LH[18]
BitsDestination
MAIN[21][39]MAIN[21][37]MAIN[21][35]LH[18]
Source
000off
001OMUX[4]
011OMUX_N15
101DBL_E1[4]
111DBL_W1[3]
virtex2 INT_CLB switchbox INT muxes LV[0]
BitsDestination
MAIN[21][7]MAIN[21][9]MAIN[21][19]MAIN[21][25]MAIN[21][21]MAIN[21][11]MAIN[21][5]LV[0]
Source
0000000off
0000011HEX_E1[1]
0000101OMUX_E2
0001001DBL_W1[1]
0010001HEX_E6[1]
0100001HEX_E4[1]
1000011OMUX[0]
1000101HEX_E2[1]
1001001HEX_E5[1]
1010001DBL_E1[2]
1100001HEX_E3[1]
virtex2 INT_CLB switchbox INT muxes LV[6]
BitsDestination
MAIN[21][73]MAIN[21][61]MAIN[21][55]MAIN[21][69]MAIN[21][71]MAIN[21][65]MAIN[21][75]LV[6]
Source
0000000off
0000011OMUX_W9
0000101DBL_W1[7]
0001001HEX_W5[7]
0010001HEX_W3[7]
0100001HEX_W4[7]
1000011OMUX[15]
1000101HEX_W2[7]
1001001DBL_E1[8]
1010001HEX_W0[7]
1100001HEX_W1[7]
virtex2 INT_CLB switchbox INT muxes LV[12]
BitsDestination
MAIN[21][13]MAIN[21][1]MAIN[21][27]MAIN[21][23]MAIN[21][17]MAIN[21][3]MAIN[21][15]LV[12]
Source
0000000off
0000011HEX_E1[1]
0000101OMUX_E2
0001001DBL_W1[1]
0010001HEX_E6[1]
0100001HEX_E4[1]
1000011OMUX[0]
1000101HEX_E2[1]
1001001HEX_E5[1]
1010001DBL_E1[2]
1100001HEX_E3[1]
virtex2 INT_CLB switchbox INT muxes LV[18]
BitsDestination
MAIN[21][67]MAIN[21][53]MAIN[21][57]MAIN[21][77]MAIN[21][59]MAIN[21][79]MAIN[21][63]LV[18]
Source
0000000off
0000011OMUX_W9
0000101DBL_W1[7]
0001001HEX_W5[7]
0010001HEX_W3[7]
0100001HEX_W4[7]
1000011OMUX[15]
1000101HEX_W2[7]
1001001DBL_E1[8]
1010001HEX_W0[7]
1100001HEX_W1[7]
virtex2 INT_CLB switchbox INT muxes IMUX_CLK[0]
BitsDestination
MAIN[5][41]MAIN[5][42]MAIN[5][40]MAIN[4][42]MAIN[5][49]MAIN[4][47]MAIN[4][43]MAIN[5][45]MAIN[4][45]MAIN[5][43]IMUX_CLK[0]
Source
0000000000PULLUP
0001000001GCLK[0]
0001000010GCLK[1]
0001000100GCLK[2]
0001001000HEX_N0[6]
0001010000HEX_N3[6]
0001100000HEX_S4[6]
0010000001GCLK[3]
0010000010HEX_S3[6]
0010000100GCLK[4]
0010001000HEX_S6[6]
0010010000HEX_N1[6]
0010100000HEX_N4[6]
0100000001GCLK[5]
0100000010HEX_N2[6]
0100000100HEX_N5[6]
0100001000GCLK[6]
0100010000HEX_S5[6]
0100100000HEX_S2[6]
1000000001GCLK[7]
1000000010DBL_W1[5]
1000000100DBL_E0[5]
1000001000DBL_E1[5]
1000010000DBL_W2[5]
1000100000HEX_S1[6]
virtex2 INT_CLB switchbox INT muxes IMUX_CLK[1]
BitsDestination
MAIN[5][47]MAIN[5][48]MAIN[5][50]MAIN[4][48]MAIN[4][50]MAIN[4][46]MAIN[4][44]MAIN[5][46]MAIN[5][44]MAIN[4][40]IMUX_CLK[1]
Source
0000000000PULLUP
0001000001GCLK[0]
0001000010GCLK[1]
0001000100GCLK[2]
0001001000HEX_N0[6]
0001010000HEX_N3[6]
0001100000HEX_S4[6]
0010000001GCLK[3]
0010000010HEX_S3[6]
0010000100GCLK[4]
0010001000HEX_S6[6]
0010010000HEX_N1[6]
0010100000HEX_N4[6]
0100000001GCLK[5]
0100000010HEX_N2[6]
0100000100HEX_N5[6]
0100001000GCLK[6]
0100010000HEX_S5[6]
0100100000HEX_S2[6]
1000000001GCLK[7]
1000000010DBL_W1[5]
1000000100DBL_E0[5]
1000001000DBL_E1[5]
1000010000DBL_W2[5]
1000100000HEX_S1[6]
virtex2 INT_CLB switchbox INT muxes IMUX_CLK[2]
BitsDestination
MAIN[5][54]MAIN[5][53]MAIN[5][51]MAIN[4][53]MAIN[4][51]MAIN[4][55]MAIN[4][57]MAIN[5][55]MAIN[5][57]MAIN[4][61]IMUX_CLK[2]
Source
0000000000PULLUP
0001000001GCLK[0]
0001000010GCLK[1]
0001000100GCLK[2]
0001001000HEX_N0[6]
0001010000HEX_N3[6]
0001100000HEX_S4[6]
0010000001GCLK[3]
0010000010HEX_S3[6]
0010000100GCLK[4]
0010001000HEX_S6[6]
0010010000HEX_N1[6]
0010100000HEX_N4[6]
0100000001GCLK[5]
0100000010HEX_N2[6]
0100000100HEX_N5[6]
0100001000GCLK[6]
0100010000HEX_S5[6]
0100100000HEX_S2[6]
1000000001GCLK[7]
1000000010DBL_W2[6]
1000000100DBL_E0[6]
1000001000DBL_E1[6]
1000010000DBL_W1[6]
1000100000HEX_S1[6]
virtex2 INT_CLB switchbox INT muxes IMUX_CLK[3]
BitsDestination
MAIN[5][60]MAIN[5][59]MAIN[5][61]MAIN[4][59]MAIN[5][52]MAIN[4][54]MAIN[4][58]MAIN[5][56]MAIN[4][56]MAIN[5][58]IMUX_CLK[3]
Source
0000000000PULLUP
0001000001GCLK[0]
0001000010GCLK[1]
0001000100GCLK[2]
0001001000HEX_N0[6]
0001010000HEX_N3[6]
0001100000HEX_S4[6]
0010000001GCLK[3]
0010000010HEX_S3[6]
0010000100GCLK[4]
0010001000HEX_S6[6]
0010010000HEX_N1[6]
0010100000HEX_N4[6]
0100000001GCLK[5]
0100000010HEX_N2[6]
0100000100HEX_N5[6]
0100001000GCLK[6]
0100010000HEX_S5[6]
0100100000HEX_S2[6]
1000000001GCLK[7]
1000000010DBL_W2[6]
1000000100DBL_E0[6]
1000001000DBL_E1[6]
1000010000DBL_W1[6]
1000100000HEX_S1[6]
virtex2 INT_CLB switchbox INT muxes IMUX_SR[0]
BitsDestination
MAIN[5][3]MAIN[4][3]MAIN[5][5]MAIN[4][5]MAIN[5][1]MAIN[5][2]MAIN[4][2]MAIN[5][0]IMUX_SR[0]
Source
00000000PULLUP
00010001DBL_W1[0]
00010010HEX_N1[0]
00010100HEX_N5[0]
00011000HEX_S4[0]
00100001DBL_W2[0]
00100010HEX_S5[0]
00100100HEX_S1[0]
00101000HEX_N3[0]
01000001HEX_N2[0]
01000010DBL_E0[0]
01000100HEX_S2[0]
01001000HEX_N0[0]
10000001HEX_S3[0]
10000010DBL_E1[0]
10000100HEX_N4[0]
10001000HEX_S6[0]
virtex2 INT_CLB switchbox INT muxes IMUX_SR[1]
BitsDestination
MAIN[4][12]MAIN[5][12]MAIN[5][14]MAIN[4][14]MAIN[5][16]MAIN[5][15]MAIN[5][17]MAIN[4][15]IMUX_SR[1]
Source
00000000PULLUP
00010001DBL_W1[1]
00010010HEX_N2[0]
00010100HEX_S2[0]
00011000HEX_N0[0]
00100001DBL_W2[1]
00100010HEX_S3[0]
00100100HEX_N4[0]
00101000HEX_S6[0]
01000001HEX_S5[0]
01000010DBL_E0[1]
01000100HEX_S1[0]
01001000HEX_N3[0]
10000001HEX_N1[0]
10000010DBL_E1[1]
10000100HEX_N5[0]
10001000HEX_S4[0]
virtex2 INT_CLB switchbox INT muxes IMUX_SR[2]
BitsDestination
MAIN[4][0]MAIN[4][4]MAIN[4][8]MAIN[5][4]MAIN[5][7]MAIN[5][8]MAIN[4][6]MAIN[5][6]IMUX_SR[2]
Source
00000000PULLUP
00010001DBL_W1[0]
00010010HEX_N1[0]
00010100HEX_N5[0]
00011000HEX_S4[0]
00100001DBL_W2[0]
00100010HEX_S5[0]
00100100HEX_S1[0]
00101000HEX_N3[0]
01000001HEX_N2[0]
01000010DBL_E0[0]
01000100HEX_S2[0]
01001000HEX_N0[0]
10000001HEX_S3[0]
10000010DBL_E1[0]
10000100HEX_N4[0]
10001000HEX_S6[0]
virtex2 INT_CLB switchbox INT muxes IMUX_SR[3]
BitsDestination
MAIN[5][13]MAIN[4][9]MAIN[4][17]MAIN[4][13]MAIN[5][10]MAIN[5][9]MAIN[5][11]MAIN[4][11]IMUX_SR[3]
Source
00000000PULLUP
00010001DBL_W1[1]
00010010HEX_N2[0]
00010100HEX_S2[0]
00011000HEX_N0[0]
00100001DBL_W2[1]
00100010HEX_S3[0]
00100100HEX_N4[0]
00101000HEX_S6[0]
01000001HEX_S5[0]
01000010DBL_E0[1]
01000100HEX_S1[0]
01001000HEX_N3[0]
10000001HEX_N1[0]
10000010DBL_E1[1]
10000100HEX_N5[0]
10001000HEX_S4[0]
virtex2 INT_CLB switchbox INT muxes IMUX_CE[0]
BitsDestination
MAIN[5][65]MAIN[4][65]MAIN[5][67]MAIN[4][67]MAIN[5][63]MAIN[5][64]MAIN[4][64]MAIN[5][62]IMUX_CE[0]
Source
00000000PULLUP
00010001DBL_W1[8]
00010010HEX_N0[9]
00010100HEX_N2[9]
00011000HEX_N3[9]
00100001DBL_W2[8]
00100010HEX_S6[9]
00100100HEX_S4[9]
00101000HEX_S3[9]
01000001HEX_S1[9]
01000010DBL_E0[8]
01000100HEX_S2[9]
01001000HEX_S5[9]
10000001HEX_N5[9]
10000010DBL_E1[8]
10000100HEX_N4[9]
10001000HEX_N1[9]
virtex2 INT_CLB switchbox INT muxes IMUX_CE[1]
BitsDestination
MAIN[4][62]MAIN[4][66]MAIN[4][70]MAIN[5][66]MAIN[5][69]MAIN[5][70]MAIN[4][68]MAIN[5][68]IMUX_CE[1]
Source
00000000PULLUP
00010001DBL_W1[8]
00010010HEX_N0[9]
00010100HEX_N2[9]
00011000HEX_N3[9]
00100001DBL_W2[8]
00100010HEX_S6[9]
00100100HEX_S4[9]
00101000HEX_S3[9]
01000001HEX_S1[9]
01000010DBL_E0[8]
01000100HEX_S2[9]
01001000HEX_S5[9]
10000001HEX_N5[9]
10000010DBL_E1[8]
10000100HEX_N4[9]
10001000HEX_N1[9]
virtex2 INT_CLB switchbox INT muxes IMUX_CE[2]
BitsDestination
MAIN[5][75]MAIN[4][71]MAIN[4][79]MAIN[4][75]MAIN[5][72]MAIN[5][71]MAIN[5][73]MAIN[4][73]IMUX_CE[2]
Source
00000000PULLUP
00010001DBL_W1[9]
00010010HEX_S1[9]
00010100HEX_S2[9]
00011000HEX_S5[9]
00100001DBL_W2[9]
00100010HEX_N5[9]
00100100HEX_N4[9]
00101000HEX_N1[9]
01000001HEX_S6[9]
01000010DBL_E0[9]
01000100HEX_S4[9]
01001000HEX_S3[9]
10000001HEX_N0[9]
10000010DBL_E1[9]
10000100HEX_N2[9]
10001000HEX_N3[9]
virtex2 INT_CLB switchbox INT muxes IMUX_CE[3]
BitsDestination
MAIN[4][74]MAIN[5][74]MAIN[5][76]MAIN[4][76]MAIN[5][78]MAIN[5][77]MAIN[5][79]MAIN[4][77]IMUX_CE[3]
Source
00000000PULLUP
00010001DBL_W1[9]
00010010HEX_S1[9]
00010100HEX_S2[9]
00011000HEX_S5[9]
00100001DBL_W2[9]
00100010HEX_N5[9]
00100100HEX_N4[9]
00101000HEX_N1[9]
01000001HEX_S6[9]
01000010DBL_E0[9]
01000100HEX_S4[9]
01001000HEX_S3[9]
10000001HEX_N0[9]
10000010DBL_E1[9]
10000100HEX_N2[9]
10001000HEX_N3[9]
virtex2 INT_CLB switchbox INT muxes IMUX_TI[0]
BitsDestination
MAIN[5][18]MAIN[5][19]MAIN[4][20]MAIN[5][20]MAIN[5][27]MAIN[4][25]MAIN[4][23]MAIN[5][23]MAIN[4][21]MAIN[5][21]IMUX_TI[0]
Source
0000000000PULLUP
0001000001OMUX[2]
0001000010OMUX[3]
0001000100HEX_N5[3]
0001001000HEX_N2[3]
0001010000HEX_S5[3]
0001100000HEX_S2[3]
0010000001OMUX[4]
0010000010HEX_N0[3]
0010000100DBL_W1[2]
0010001000DBL_W2[2]
0010010000HEX_N3[3]
0010100000HEX_S4[3]
0100000001OMUX[5]
0100000010DBL_W2[3]
0100000100DBL_W1[3]
0100001000DBL_E1[3]
0100010000DBL_E0[3]
0100100000HEX_S1[3]
1000000001DBL_E0[2]
1000000010HEX_S6[3]
1000000100DBL_E1[2]
1000001000HEX_S3[3]
1000010000HEX_N1[3]
1000100000HEX_N4[3]
virtex2 INT_CLB switchbox INT muxes IMUX_TI[1]
BitsDestination
MAIN[5][28]MAIN[5][25]MAIN[4][26]MAIN[5][26]MAIN[4][28]MAIN[4][24]MAIN[5][22]MAIN[5][24]MAIN[4][22]MAIN[4][18]IMUX_TI[1]
Source
0000000000PULLUP
0001000001OMUX[2]
0001000010OMUX[3]
0001000100HEX_N5[3]
0001001000HEX_N2[3]
0001010000HEX_S5[3]
0001100000HEX_S2[3]
0010000001OMUX[4]
0010000010HEX_N0[3]
0010000100DBL_W1[2]
0010001000DBL_W2[2]
0010010000HEX_N3[3]
0010100000HEX_S4[3]
0100000001OMUX[5]
0100000010DBL_W2[3]
0100000100DBL_W1[3]
0100001000DBL_E1[3]
0100010000DBL_E0[3]
0100100000HEX_S1[3]
1000000001DBL_E0[2]
1000000010HEX_S6[3]
1000000100DBL_E1[2]
1000001000HEX_S3[3]
1000010000HEX_N1[3]
1000100000HEX_N4[3]
virtex2 INT_CLB switchbox INT muxes IMUX_TS[0]
BitsDestination
MAIN[4][37]MAIN[5][39]MAIN[5][37]MAIN[5][38]MAIN[5][30]MAIN[4][32]MAIN[5][34]MAIN[4][34]MAIN[4][36]IMUX_TS[0]
Source
000000000PULLUP
000100001DBL_W1[4]
000100010HEX_N2[3]
000100100DBL_E0[4]
000101000DBL_E1[4]
000110000HEX_S1[3]
001000010DBL_W2[4]
001000100HEX_N5[3]
001001000HEX_S5[3]
001010000HEX_S2[3]
010000001HEX_S6[3]
010000010HEX_S3[3]
010001000HEX_N1[3]
010010000HEX_N4[3]
100000001HEX_N0[3]
100001000HEX_N3[3]
100010000HEX_S4[3]
virtex2 INT_CLB switchbox INT muxes IMUX_TS[1]
BitsDestination
MAIN[4][31]MAIN[5][29]MAIN[5][31]MAIN[5][32]MAIN[4][29]MAIN[4][33]MAIN[5][33]MAIN[5][35]MAIN[4][35]IMUX_TS[1]
Source
000000000PULLUP
000100001DBL_W1[4]
000100010HEX_N2[3]
000100100DBL_E0[4]
000101000DBL_E1[4]
000110000HEX_S1[3]
001000010DBL_W2[4]
001000100HEX_N5[3]
001001000HEX_S5[3]
001010000HEX_S2[3]
010000001HEX_S6[3]
010000010HEX_S3[3]
010001000HEX_N1[3]
010010000HEX_N4[3]
100000001HEX_N0[3]
100001000HEX_N3[3]
100010000HEX_S4[3]
virtex2 INT_CLB switchbox INT muxes IMUX_CLB_F1[0]
BitsDestination
MAIN[8][71]MAIN[9][69]MAIN[8][69]MAIN[9][71]MAIN[10][71]MAIN[10][69]MAIN[11][71]MAIN[11][69]MAIN[13][71]MAIN[12][71]MAIN[12][69]MAIN[13][69]MAIN[3][71]IMUX_CLB_F1[0]
Source
0000000000000PULLUP
0001000000001OMUX[13]
0001000000010OMUX_S5
0001000000100OMUX_W14
0001000001000OMUX_ES7
0001000010000OMUX_E13
0001000100000IMUX_CLB_BY[2]
0001001000000DBL_S1[8]
0001010000000DBL_E1[9]
0001100000000IMUX_CLB_BY[3]
0010000000001OUT_FAN[0]
0010000000010DBL_W0[8]
0010000000100OMUX_SW5
0010000001000DBL_S0[8]
0010000010000DBL_E0[9]
0010000100000DBL_W1[7]
0010001000000DBL_N1[9]
0010010000000DBL_W2[9]
0010100000000DBL_N2[9]
0100000000001OMUX_N15
0100000000010DBL_N0[7]
0100000000100DBL_E2[9]
0100000001000DBL_E2[8]
0100000010000DBL_W2[8]
0100000100000DBL_N1[7]
0100001000000DBL_W1[8]
0100010000000DBL_W1[9]
0100100000000DBL_N2[8]
1000000000001OUT_FAN[7]
1000000000010DBL_W2[7]
1000000000100DBL_N0[9]
1000000001000DBL_S2[9]
1000000010000DBL_S2[8]
1000000100000DBL_S1[9]
1000001000000DBL_E1[8]
1000010000000DBL_N2[7]
1000100000000DBL_N1[8]
virtex2 INT_CLB switchbox INT muxes IMUX_CLB_F1[1]
BitsDestination
MAIN[9][12]MAIN[9][14]MAIN[8][14]MAIN[8][12]MAIN[10][14]MAIN[10][12]MAIN[11][12]MAIN[11][14]MAIN[13][14]MAIN[12][12]MAIN[13][12]MAIN[12][14]MAIN[3][12]IMUX_CLB_F1[1]
Source
0000000000000PULLUP
0001000000001OMUX[2]
0001000000010DBL_E0[1]
0001000000100DBL_S0[0]
0001000001000OMUX_EN8
0001000010000DBL_W0[0]
0001000100000DBL_N1[1]
0001001000000DBL_S1[2]
0001010000000DBL_W2[1]
0001100000000DBL_S1[1]
0010000000001OMUX_S0
0010000000010DBL_S2[0]
0010000000100DBL_S2[2]
0010000001000DBL_N0[1]
0010000010000DBL_S2[1]
0010000100000DBL_E1[0]
0010001000000DBL_W1[1]
0010010000000DBL_W2[0]
0010100000000DBL_N1[0]
0100000000001OUT_FAN[4]
0100000000010OMUX_W1
0100000000100OMUX_E2
0100000001000OMUX_NW10
0100000010000OMUX_N10
0100000100000DBL_S1[0]
0100001000000IMUX_CLB_BY[0]
0100010000000DBL_N2[0]
0100100000000IMUX_CLB_BY[1]
1000000000001OUT_FAN[3]
1000000000010DBL_E2[1]
1000000000100DBL_S0[2]
1000000001000DBL_E2[0]
1000000010000DBL_E2[2]
1000000100000DBL_W1[0]
1000001000000DBL_E1[2]
1000010000000DBL_E1[1]
1000100000000DBL_N2[1]
virtex2 INT_CLB switchbox INT muxes IMUX_CLB_F1[2]
BitsDestination
MAIN[9][67]MAIN[8][65]MAIN[9][65]MAIN[8][67]MAIN[10][65]MAIN[10][67]MAIN[11][65]MAIN[11][67]MAIN[13][65]MAIN[12][65]MAIN[12][67]MAIN[13][67]MAIN[3][67]IMUX_CLB_F1[2]
Source
0000000000000PULLUP
0001000000001OMUX[13]
0001000000010DBL_W0[8]
0001000000100OMUX_SW5
0001000001000DBL_S0[8]
0001000010000DBL_E0[9]
0001000100000DBL_W1[7]
0001001000000DBL_N1[9]
0001010000000DBL_W2[9]
0001100000000DBL_N2[9]
0010000000001OUT_FAN[7]
0010000000010OMUX_S5
0010000000100OMUX_W14
0010000001000OMUX_ES7
0010000010000OMUX_E13
0010000100000IMUX_CLB_BY[2]
0010001000000DBL_S1[8]
0010010000000DBL_E1[9]
0010100000000IMUX_CLB_BY[3]
0100000000001OMUX_N15
0100000000010DBL_W2[7]
0100000000100DBL_N0[9]
0100000001000DBL_S2[9]
0100000010000DBL_S2[8]
0100000100000DBL_S1[9]
0100001000000DBL_E1[8]
0100010000000DBL_N2[7]
0100100000000DBL_N1[8]
1000000000001OUT_FAN[0]
1000000000010DBL_N0[7]
1000000000100DBL_E2[9]
1000000001000DBL_E2[8]
1000000010000DBL_W2[8]
1000000100000DBL_N1[7]
1000001000000DBL_W1[8]
1000010000000DBL_W1[9]
1000100000000DBL_N2[8]
virtex2 INT_CLB switchbox INT muxes IMUX_CLB_F1[3]
BitsDestination
MAIN[8][8]MAIN[8][10]MAIN[9][10]MAIN[9][8]MAIN[10][8]MAIN[10][10]MAIN[11][10]MAIN[11][8]MAIN[13][8]MAIN[12][10]MAIN[13][10]MAIN[12][8]MAIN[3][8]IMUX_CLB_F1[3]
Source
0000000000000PULLUP
0001000000001OMUX[2]
0001000000010OMUX_W1
0001000000100OMUX_E2
0001000001000OMUX_NW10
0001000010000OMUX_N10
0001000100000DBL_S1[0]
0001001000000IMUX_CLB_BY[0]
0001010000000DBL_N2[0]
0001100000000IMUX_CLB_BY[1]
0010000000001OMUX_S0
0010000000010DBL_E2[1]
0010000000100DBL_S0[2]
0010000001000DBL_E2[0]
0010000010000DBL_E2[2]
0010000100000DBL_W1[0]
0010001000000DBL_E1[2]
0010010000000DBL_E1[1]
0010100000000DBL_N2[1]
0100000000001OUT_FAN[3]
0100000000010DBL_E0[1]
0100000000100DBL_S0[0]
0100000001000OMUX_EN8
0100000010000DBL_W0[0]
0100000100000DBL_N1[1]
0100001000000DBL_S1[2]
0100010000000DBL_W2[1]
0100100000000DBL_S1[1]
1000000000001OUT_FAN[4]
1000000000010DBL_S2[0]
1000000000100DBL_S2[2]
1000000001000DBL_N0[1]
1000000010000DBL_S2[1]
1000000100000DBL_E1[0]
1000001000000DBL_W1[1]
1000010000000DBL_W2[0]
1000100000000DBL_N1[0]
virtex2 INT_CLB switchbox INT muxes IMUX_CLB_F2[0]
BitsDestination
MAIN[8][31]MAIN[8][29]MAIN[9][29]MAIN[9][31]MAIN[10][31]MAIN[10][29]MAIN[11][31]MAIN[11][29]MAIN[13][29]MAIN[13][31]MAIN[12][31]MAIN[12][29]MAIN[3][31]IMUX_CLB_F2[0]
Source
0000000000000PULLUP
0001000000001OMUX[6]
0001000000010OMUX_N12
0001000000100OMUX_E7
0001000001000OMUX_NE12
0001000010000OMUX_WN14
0001000100000IMUX_CLB_BX[3]
0001001000000DBL_S1[3]
0001010000000DBL_E1[4]
0001100000000IMUX_CLB_BX[2]
0010000000001OMUX_S4
0010000000010DBL_E2[4]
0010000000100DBL_E2[3]
0010000001000DBL_W2[3]
0010000010000DBL_W0[2]
0010000100000DBL_N1[2]
0010001000000DBL_W1[3]
0010010000000DBL_W1[4]
0010100000000DBL_N2[3]
0100000000001OUT_FAN[2]
0100000000010OMUX_W6
0100000000100DBL_S0[4]
0100000001000DBL_W0[4]
0100000010000DBL_E0[3]
0100000100000DBL_W1[2]
0100001000000DBL_N1[4]
0100010000000DBL_W2[4]
0100100000000DBL_N2[4]
1000000000001OUT_FAN[5]
1000000000010DBL_N0[3]
1000000000100DBL_S2[4]
1000000001000DBL_S2[3]
1000000010000DBL_W2[2]
1000000100000DBL_S1[4]
1000001000000DBL_E1[3]
1000010000000DBL_N2[2]
1000100000000DBL_N1[3]
virtex2 INT_CLB switchbox INT muxes IMUX_CLB_F2[1]
BitsDestination
MAIN[9][52]MAIN[8][54]MAIN[9][54]MAIN[8][52]MAIN[10][54]MAIN[10][52]MAIN[11][52]MAIN[11][54]MAIN[13][52]MAIN[13][54]MAIN[12][52]MAIN[12][54]MAIN[3][52]IMUX_CLB_F2[1]
Source
0000000000000PULLUP
0001000000001OMUX[9]
0001000000010DBL_E0[5]
0001000000100OMUX_S3
0001000001000DBL_W0[6]
0001000010000DBL_S0[6]
0001000100000DBL_N1[6]
0001001000000DBL_S1[7]
0001010000000DBL_W2[6]
0001100000000DBL_S1[6]
0010000000001OUT_FAN[6]
0010000000010OMUX_WS1
0010000000100OMUX_E8
0010000001000OMUX_SE3
0010000010000OMUX_W9
0010000100000DBL_S1[5]
0010001000000IMUX_CLB_BX[1]
0010010000000DBL_N2[5]
0010100000000IMUX_CLB_BX[0]
0100000000001OMUX_N11
0100000000010DBL_S2[5]
0100000000100DBL_N0[5]
0100000001000DBL_S2[6]
0100000010000DBL_S2[7]
0100000100000DBL_E1[5]
0100001000000DBL_W1[6]
0100010000000DBL_W2[5]
0100100000000DBL_N1[5]
1000000000001OUT_FAN[1]
1000000000010DBL_E2[6]
1000000000100DBL_E2[5]
1000000001000DBL_E2[7]
1000000010000DBL_E0[7]
1000000100000DBL_W1[5]
1000001000000DBL_E1[7]
1000010000000DBL_E1[6]
1000100000000DBL_N2[6]
virtex2 INT_CLB switchbox INT muxes IMUX_CLB_F2[2]
BitsDestination
MAIN[9][27]MAIN[9][25]MAIN[8][25]MAIN[8][27]MAIN[10][25]MAIN[10][27]MAIN[11][25]MAIN[11][27]MAIN[13][27]MAIN[13][25]MAIN[12][25]MAIN[12][27]MAIN[3][27]IMUX_CLB_F2[2]
Source
0000000000000PULLUP
0001000000001OMUX[6]
0001000000010OMUX_W6
0001000000100DBL_S0[4]
0001000001000DBL_W0[4]
0001000010000DBL_E0[3]
0001000100000DBL_W1[2]
0001001000000DBL_N1[4]
0001010000000DBL_W2[4]
0001100000000DBL_N2[4]
0010000000001OMUX_S4
0010000000010DBL_N0[3]
0010000000100DBL_S2[4]
0010000001000DBL_S2[3]
0010000010000DBL_W2[2]
0010000100000DBL_S1[4]
0010001000000DBL_E1[3]
0010010000000DBL_N2[2]
0010100000000DBL_N1[3]
0100000000001OUT_FAN[5]
0100000000010OMUX_N12
0100000000100OMUX_E7
0100000001000OMUX_NE12
0100000010000OMUX_WN14
0100000100000IMUX_CLB_BX[3]
0100001000000DBL_S1[3]
0100010000000DBL_E1[4]
0100100000000IMUX_CLB_BX[2]
1000000000001OUT_FAN[2]
1000000000010DBL_E2[4]
1000000000100DBL_E2[3]
1000000001000DBL_W2[3]
1000000010000DBL_W0[2]
1000000100000DBL_N1[2]
1000001000000DBL_W1[3]
1000010000000DBL_W1[4]
1000100000000DBL_N2[3]
virtex2 INT_CLB switchbox INT muxes IMUX_CLB_F2[3]
BitsDestination
MAIN[8][48]MAIN[9][50]MAIN[8][50]MAIN[9][48]MAIN[10][48]MAIN[10][50]MAIN[11][50]MAIN[11][48]MAIN[13][50]MAIN[13][48]MAIN[12][50]MAIN[12][48]MAIN[3][48]IMUX_CLB_F2[3]
Source
0000000000000PULLUP
0001000000001OMUX[9]
0001000000010OMUX_WS1
0001000000100OMUX_E8
0001000001000OMUX_SE3
0001000010000OMUX_W9
0001000100000DBL_S1[5]
0001001000000IMUX_CLB_BX[1]
0001010000000DBL_N2[5]
0001100000000IMUX_CLB_BX[0]
0010000000001OUT_FAN[1]
0010000000010DBL_E0[5]
0010000000100OMUX_S3
0010000001000DBL_W0[6]
0010000010000DBL_S0[6]
0010000100000DBL_N1[6]
0010001000000DBL_S1[7]
0010010000000DBL_W2[6]
0010100000000DBL_S1[6]
0100000000001OMUX_N11
0100000000010DBL_E2[6]
0100000000100DBL_E2[5]
0100000001000DBL_E2[7]
0100000010000DBL_E0[7]
0100000100000DBL_W1[5]
0100001000000DBL_E1[7]
0100010000000DBL_E1[6]
0100100000000DBL_N2[6]
1000000000001OUT_FAN[6]
1000000000010DBL_S2[5]
1000000000100DBL_N0[5]
1000000001000DBL_S2[6]
1000000010000DBL_S2[7]
1000000100000DBL_E1[5]
1000001000000DBL_W1[6]
1000010000000DBL_W2[5]
1000100000000DBL_N1[5]
virtex2 INT_CLB switchbox INT muxes IMUX_CLB_F3[0]
BitsDestination
MAIN[9][44]MAIN[8][46]MAIN[9][46]MAIN[8][44]MAIN[10][46]MAIN[10][44]MAIN[11][44]MAIN[11][46]MAIN[13][44]MAIN[13][46]MAIN[12][44]MAIN[12][46]MAIN[3][44]IMUX_CLB_F3[0]
Source
0000000000000PULLUP
0001000000001OMUX[9]
0001000000010DBL_E0[5]
0001000000100OMUX_S3
0001000001000DBL_W0[6]
0001000010000DBL_S0[6]
0001000100000DBL_N1[6]
0001001000000DBL_S1[7]
0001010000000DBL_W2[6]
0001100000000DBL_S1[6]
0010000000001OUT_FAN[6]
0010000000010OMUX_WS1
0010000000100OMUX_E8
0010000001000OMUX_SE3
0010000010000OMUX_W9
0010000100000DBL_S1[5]
0010001000000IMUX_CLB_BX[1]
0010010000000DBL_N2[5]
0010100000000IMUX_CLB_BX[0]
0100000000001OMUX_N11
0100000000010DBL_S2[5]
0100000000100DBL_N0[5]
0100000001000DBL_S2[6]
0100000010000DBL_S2[7]
0100000100000DBL_E1[5]
0100001000000DBL_W1[6]
0100010000000DBL_W2[5]
0100100000000DBL_N1[5]
1000000000001OUT_FAN[1]
1000000000010DBL_E2[6]
1000000000100DBL_E2[5]
1000000001000DBL_E2[7]
1000000010000DBL_E0[7]
1000000100000DBL_W1[5]
1000001000000DBL_E1[7]
1000010000000DBL_E1[6]
1000100000000DBL_N2[6]
virtex2 INT_CLB switchbox INT muxes IMUX_CLB_F3[1]
BitsDestination
MAIN[8][39]MAIN[8][37]MAIN[9][37]MAIN[9][39]MAIN[10][39]MAIN[10][37]MAIN[11][39]MAIN[11][37]MAIN[13][37]MAIN[13][39]MAIN[12][39]MAIN[12][37]MAIN[3][39]IMUX_CLB_F3[1]
Source
0000000000000PULLUP
0001000000001OMUX[6]
0001000000010OMUX_N12
0001000000100OMUX_E7
0001000001000OMUX_NE12
0001000010000OMUX_WN14
0001000100000IMUX_CLB_BX[3]
0001001000000DBL_S1[3]
0001010000000DBL_E1[4]
0001100000000IMUX_CLB_BX[2]
0010000000001OMUX_S4
0010000000010DBL_E2[4]
0010000000100DBL_E2[3]
0010000001000DBL_W2[3]
0010000010000DBL_W0[2]
0010000100000DBL_N1[2]
0010001000000DBL_W1[3]
0010010000000DBL_W1[4]
0010100000000DBL_N2[3]
0100000000001OUT_FAN[2]
0100000000010OMUX_W6
0100000000100DBL_S0[4]
0100000001000DBL_W0[4]
0100000010000DBL_E0[3]
0100000100000DBL_W1[2]
0100001000000DBL_N1[4]
0100010000000DBL_W2[4]
0100100000000DBL_N2[4]
1000000000001OUT_FAN[5]
1000000000010DBL_N0[3]
1000000000100DBL_S2[4]
1000000001000DBL_S2[3]
1000000010000DBL_W2[2]
1000000100000DBL_S1[4]
1000001000000DBL_E1[3]
1000010000000DBL_N2[2]
1000100000000DBL_N1[3]
virtex2 INT_CLB switchbox INT muxes IMUX_CLB_F3[2]
BitsDestination
MAIN[8][40]MAIN[9][42]MAIN[8][42]MAIN[9][40]MAIN[10][40]MAIN[10][42]MAIN[11][42]MAIN[11][40]MAIN[13][42]MAIN[13][40]MAIN[12][42]MAIN[12][40]MAIN[3][40]IMUX_CLB_F3[2]
Source
0000000000000PULLUP
0001000000001OMUX[9]
0001000000010OMUX_WS1
0001000000100OMUX_E8
0001000001000OMUX_SE3
0001000010000OMUX_W9
0001000100000DBL_S1[5]
0001001000000IMUX_CLB_BX[1]
0001010000000DBL_N2[5]
0001100000000IMUX_CLB_BX[0]
0010000000001OUT_FAN[1]
0010000000010DBL_E0[5]
0010000000100OMUX_S3
0010000001000DBL_W0[6]
0010000010000DBL_S0[6]
0010000100000DBL_N1[6]
0010001000000DBL_S1[7]
0010010000000DBL_W2[6]
0010100000000DBL_S1[6]
0100000000001OMUX_N11
0100000000010DBL_E2[6]
0100000000100DBL_E2[5]
0100000001000DBL_E2[7]
0100000010000DBL_E0[7]
0100000100000DBL_W1[5]
0100001000000DBL_E1[7]
0100010000000DBL_E1[6]
0100100000000DBL_N2[6]
1000000000001OUT_FAN[6]
1000000000010DBL_S2[5]
1000000000100DBL_N0[5]
1000000001000DBL_S2[6]
1000000010000DBL_S2[7]
1000000100000DBL_E1[5]
1000001000000DBL_W1[6]
1000010000000DBL_W2[5]
1000100000000DBL_N1[5]
virtex2 INT_CLB switchbox INT muxes IMUX_CLB_F3[3]
BitsDestination
MAIN[9][35]MAIN[9][33]MAIN[8][33]MAIN[8][35]MAIN[10][33]MAIN[10][35]MAIN[11][33]MAIN[11][35]MAIN[13][35]MAIN[13][33]MAIN[12][33]MAIN[12][35]MAIN[3][35]IMUX_CLB_F3[3]
Source
0000000000000PULLUP
0001000000001OMUX[6]
0001000000010OMUX_W6
0001000000100DBL_S0[4]
0001000001000DBL_W0[4]
0001000010000DBL_E0[3]
0001000100000DBL_W1[2]
0001001000000DBL_N1[4]
0001010000000DBL_W2[4]
0001100000000DBL_N2[4]
0010000000001OMUX_S4
0010000000010DBL_N0[3]
0010000000100DBL_S2[4]
0010000001000DBL_S2[3]
0010000010000DBL_W2[2]
0010000100000DBL_S1[4]
0010001000000DBL_E1[3]
0010010000000DBL_N2[2]
0010100000000DBL_N1[3]
0100000000001OUT_FAN[5]
0100000000010OMUX_N12
0100000000100OMUX_E7
0100000001000OMUX_NE12
0100000010000OMUX_WN14
0100000100000IMUX_CLB_BX[3]
0100001000000DBL_S1[3]
0100010000000DBL_E1[4]
0100100000000IMUX_CLB_BX[2]
1000000000001OUT_FAN[2]
1000000000010DBL_E2[4]
1000000000100DBL_E2[3]
1000000001000DBL_W2[3]
1000000010000DBL_W0[2]
1000000100000DBL_N1[2]
1000001000000DBL_W1[3]
1000010000000DBL_W1[4]
1000100000000DBL_N2[3]
virtex2 INT_CLB switchbox INT muxes IMUX_CLB_F4[0]
BitsDestination
MAIN[9][4]MAIN[9][6]MAIN[8][6]MAIN[8][4]MAIN[10][6]MAIN[10][4]MAIN[11][4]MAIN[11][6]MAIN[13][6]MAIN[12][4]MAIN[13][4]MAIN[12][6]MAIN[3][4]IMUX_CLB_F4[0]
Source
0000000000000PULLUP
0001000000001OMUX[2]
0001000000010DBL_E0[1]
0001000000100DBL_S0[0]
0001000001000OMUX_EN8
0001000010000DBL_W0[0]
0001000100000DBL_N1[1]
0001001000000DBL_S1[2]
0001010000000DBL_W2[1]
0001100000000DBL_S1[1]
0010000000001OMUX_S0
0010000000010DBL_S2[0]
0010000000100DBL_S2[2]
0010000001000DBL_N0[1]
0010000010000DBL_S2[1]
0010000100000DBL_E1[0]
0010001000000DBL_W1[1]
0010010000000DBL_W2[0]
0010100000000DBL_N1[0]
0100000000001OUT_FAN[4]
0100000000010OMUX_W1
0100000000100OMUX_E2
0100000001000OMUX_NW10
0100000010000OMUX_N10
0100000100000DBL_S1[0]
0100001000000IMUX_CLB_BY[0]
0100010000000DBL_N2[0]
0100100000000IMUX_CLB_BY[1]
1000000000001OUT_FAN[3]
1000000000010DBL_E2[1]
1000000000100DBL_S0[2]
1000000001000DBL_E2[0]
1000000010000DBL_E2[2]
1000000100000DBL_W1[0]
1000001000000DBL_E1[2]
1000010000000DBL_E1[1]
1000100000000DBL_N2[1]
virtex2 INT_CLB switchbox INT muxes IMUX_CLB_F4[1]
BitsDestination
MAIN[8][79]MAIN[9][77]MAIN[8][77]MAIN[9][79]MAIN[10][79]MAIN[10][77]MAIN[11][79]MAIN[11][77]MAIN[13][79]MAIN[12][79]MAIN[12][77]MAIN[13][77]MAIN[3][79]IMUX_CLB_F4[1]
Source
0000000000000PULLUP
0001000000001OMUX[13]
0001000000010OMUX_S5
0001000000100OMUX_W14
0001000001000OMUX_ES7
0001000010000OMUX_E13
0001000100000IMUX_CLB_BY[2]
0001001000000DBL_S1[8]
0001010000000DBL_E1[9]
0001100000000IMUX_CLB_BY[3]
0010000000001OUT_FAN[0]
0010000000010DBL_W0[8]
0010000000100OMUX_SW5
0010000001000DBL_S0[8]
0010000010000DBL_E0[9]
0010000100000DBL_W1[7]
0010001000000DBL_N1[9]
0010010000000DBL_W2[9]
0010100000000DBL_N2[9]
0100000000001OMUX_N15
0100000000010DBL_N0[7]
0100000000100DBL_E2[9]
0100000001000DBL_E2[8]
0100000010000DBL_W2[8]
0100000100000DBL_N1[7]
0100001000000DBL_W1[8]
0100010000000DBL_W1[9]
0100100000000DBL_N2[8]
1000000000001OUT_FAN[7]
1000000000010DBL_W2[7]
1000000000100DBL_N0[9]
1000000001000DBL_S2[9]
1000000010000DBL_S2[8]
1000000100000DBL_S1[9]
1000001000000DBL_E1[8]
1000010000000DBL_N2[7]
1000100000000DBL_N1[8]
virtex2 INT_CLB switchbox INT muxes IMUX_CLB_F4[2]
BitsDestination
MAIN[8][0]MAIN[8][2]MAIN[9][2]MAIN[9][0]MAIN[10][0]MAIN[10][2]MAIN[11][2]MAIN[11][0]MAIN[13][0]MAIN[12][2]MAIN[13][2]MAIN[12][0]MAIN[3][0]IMUX_CLB_F4[2]
Source
0000000000000PULLUP
0001000000001OMUX[2]
0001000000010OMUX_W1
0001000000100OMUX_E2
0001000001000OMUX_NW10
0001000010000OMUX_N10
0001000100000DBL_S1[0]
0001001000000IMUX_CLB_BY[0]
0001010000000DBL_N2[0]
0001100000000IMUX_CLB_BY[1]
0010000000001OMUX_S0
0010000000010DBL_E2[1]
0010000000100DBL_S0[2]
0010000001000DBL_E2[0]
0010000010000DBL_E2[2]
0010000100000DBL_W1[0]
0010001000000DBL_E1[2]
0010010000000DBL_E1[1]
0010100000000DBL_N2[1]
0100000000001OUT_FAN[3]
0100000000010DBL_E0[1]
0100000000100DBL_S0[0]
0100000001000OMUX_EN8
0100000010000DBL_W0[0]
0100000100000DBL_N1[1]
0100001000000DBL_S1[2]
0100010000000DBL_W2[1]
0100100000000DBL_S1[1]
1000000000001OUT_FAN[4]
1000000000010DBL_S2[0]
1000000000100DBL_S2[2]
1000000001000DBL_N0[1]
1000000010000DBL_S2[1]
1000000100000DBL_E1[0]
1000001000000DBL_W1[1]
1000010000000DBL_W2[0]
1000100000000DBL_N1[0]
virtex2 INT_CLB switchbox INT muxes IMUX_CLB_F4[3]
BitsDestination
MAIN[9][75]MAIN[8][73]MAIN[9][73]MAIN[8][75]MAIN[10][73]MAIN[10][75]MAIN[11][73]MAIN[11][75]MAIN[13][73]MAIN[12][73]MAIN[12][75]MAIN[13][75]MAIN[3][75]IMUX_CLB_F4[3]
Source
0000000000000PULLUP
0001000000001OMUX[13]
0001000000010DBL_W0[8]
0001000000100OMUX_SW5
0001000001000DBL_S0[8]
0001000010000DBL_E0[9]
0001000100000DBL_W1[7]
0001001000000DBL_N1[9]
0001010000000DBL_W2[9]
0001100000000DBL_N2[9]
0010000000001OUT_FAN[7]
0010000000010OMUX_S5
0010000000100OMUX_W14
0010000001000OMUX_ES7
0010000010000OMUX_E13
0010000100000IMUX_CLB_BY[2]
0010001000000DBL_S1[8]
0010010000000DBL_E1[9]
0010100000000IMUX_CLB_BY[3]
0100000000001OMUX_N15
0100000000010DBL_W2[7]
0100000000100DBL_N0[9]
0100000001000DBL_S2[9]
0100000010000DBL_S2[8]
0100000100000DBL_S1[9]
0100001000000DBL_E1[8]
0100010000000DBL_N2[7]
0100100000000DBL_N1[8]
1000000000001OUT_FAN[0]
1000000000010DBL_N0[7]
1000000000100DBL_E2[9]
1000000001000DBL_E2[8]
1000000010000DBL_W2[8]
1000000100000DBL_N1[7]
1000001000000DBL_W1[8]
1000010000000DBL_W1[9]
1000100000000DBL_N2[8]
virtex2 INT_CLB switchbox INT muxes IMUX_CLB_G1[0]
BitsDestination
MAIN[9][68]MAIN[8][70]MAIN[9][70]MAIN[8][68]MAIN[10][70]MAIN[10][68]MAIN[11][70]MAIN[11][68]MAIN[13][70]MAIN[12][70]MAIN[12][68]MAIN[13][68]MAIN[3][68]IMUX_CLB_G1[0]
Source
0000000000000PULLUP
0001000000001OMUX[13]
0001000000010DBL_W0[8]
0001000000100OMUX_SW5
0001000001000DBL_S0[8]
0001000010000DBL_E0[9]
0001000100000DBL_W1[7]
0001001000000DBL_N1[9]
0001010000000DBL_W2[9]
0001100000000DBL_N2[9]
0010000000001OUT_FAN[7]
0010000000010OMUX_S5
0010000000100OMUX_W14
0010000001000OMUX_ES7
0010000010000OMUX_E13
0010000100000IMUX_CLB_BY[2]
0010001000000DBL_S1[8]
0010010000000DBL_E1[9]
0010100000000IMUX_CLB_BY[3]
0100000000001OMUX_N15
0100000000010DBL_W2[7]
0100000000100DBL_N0[9]
0100000001000DBL_S2[9]
0100000010000DBL_S2[8]
0100000100000DBL_S1[9]
0100001000000DBL_E1[8]
0100010000000DBL_N2[7]
0100100000000DBL_N1[8]
1000000000001OUT_FAN[0]
1000000000010DBL_N0[7]
1000000000100DBL_E2[9]
1000000001000DBL_E2[8]
1000000010000DBL_W2[8]
1000000100000DBL_N1[7]
1000001000000DBL_W1[8]
1000010000000DBL_W1[9]
1000100000000DBL_N2[8]
virtex2 INT_CLB switchbox INT muxes IMUX_CLB_G1[1]
BitsDestination
MAIN[8][15]MAIN[8][13]MAIN[9][13]MAIN[9][15]MAIN[10][15]MAIN[10][13]MAIN[11][13]MAIN[11][15]MAIN[13][15]MAIN[12][13]MAIN[13][13]MAIN[12][15]MAIN[3][15]IMUX_CLB_G1[1]
Source
0000000000000PULLUP
0001000000001OMUX[2]
0001000000010OMUX_W1
0001000000100OMUX_E2
0001000001000OMUX_NW10
0001000010000OMUX_N10
0001000100000DBL_S1[0]
0001001000000IMUX_CLB_BY[0]
0001010000000DBL_N2[0]
0001100000000IMUX_CLB_BY[1]
0010000000001OMUX_S0
0010000000010DBL_E2[1]
0010000000100DBL_S0[2]
0010000001000DBL_E2[0]
0010000010000DBL_E2[2]
0010000100000DBL_W1[0]
0010001000000DBL_E1[2]
0010010000000DBL_E1[1]
0010100000000DBL_N2[1]
0100000000001OUT_FAN[3]
0100000000010DBL_E0[1]
0100000000100DBL_S0[0]
0100000001000OMUX_EN8
0100000010000DBL_W0[0]
0100000100000DBL_N1[1]
0100001000000DBL_S1[2]
0100010000000DBL_W2[1]
0100100000000DBL_S1[1]
1000000000001OUT_FAN[4]
1000000000010DBL_S2[0]
1000000000100DBL_S2[2]
1000000001000DBL_N0[1]
1000000010000DBL_S2[1]
1000000100000DBL_E1[0]
1000001000000DBL_W1[1]
1000010000000DBL_W2[0]
1000100000000DBL_N1[0]
virtex2 INT_CLB switchbox INT muxes IMUX_CLB_G1[2]
BitsDestination
MAIN[8][64]MAIN[9][66]MAIN[8][66]MAIN[9][64]MAIN[10][64]MAIN[10][66]MAIN[11][64]MAIN[11][66]MAIN[13][64]MAIN[12][64]MAIN[12][66]MAIN[13][66]MAIN[3][64]IMUX_CLB_G1[2]
Source
0000000000000PULLUP
0001000000001OMUX[13]
0001000000010OMUX_S5
0001000000100OMUX_W14
0001000001000OMUX_ES7
0001000010000OMUX_E13
0001000100000IMUX_CLB_BY[2]
0001001000000DBL_S1[8]
0001010000000DBL_E1[9]
0001100000000IMUX_CLB_BY[3]
0010000000001OUT_FAN[0]
0010000000010DBL_W0[8]
0010000000100OMUX_SW5
0010000001000DBL_S0[8]
0010000010000DBL_E0[9]
0010000100000DBL_W1[7]
0010001000000DBL_N1[9]
0010010000000DBL_W2[9]
0010100000000DBL_N2[9]
0100000000001OMUX_N15
0100000000010DBL_N0[7]
0100000000100DBL_E2[9]
0100000001000DBL_E2[8]
0100000010000DBL_W2[8]
0100000100000DBL_N1[7]
0100001000000DBL_W1[8]
0100010000000DBL_W1[9]
0100100000000DBL_N2[8]
1000000000001OUT_FAN[7]
1000000000010DBL_W2[7]
1000000000100DBL_N0[9]
1000000001000DBL_S2[9]
1000000010000DBL_S2[8]
1000000100000DBL_S1[9]
1000001000000DBL_E1[8]
1000010000000DBL_N2[7]
1000100000000DBL_N1[8]
virtex2 INT_CLB switchbox INT muxes IMUX_CLB_G1[3]
BitsDestination
MAIN[9][11]MAIN[9][9]MAIN[8][9]MAIN[8][11]MAIN[10][9]MAIN[10][11]MAIN[11][11]MAIN[11][9]MAIN[13][9]MAIN[12][11]MAIN[13][11]MAIN[12][9]MAIN[3][11]IMUX_CLB_G1[3]
Source
0000000000000PULLUP
0001000000001OMUX[2]
0001000000010DBL_E0[1]
0001000000100DBL_S0[0]
0001000001000OMUX_EN8
0001000010000DBL_W0[0]
0001000100000DBL_N1[1]
0001001000000DBL_S1[2]
0001010000000DBL_W2[1]
0001100000000DBL_S1[1]
0010000000001OMUX_S0
0010000000010DBL_S2[0]
0010000000100DBL_S2[2]
0010000001000DBL_N0[1]
0010000010000DBL_S2[1]
0010000100000DBL_E1[0]
0010001000000DBL_W1[1]
0010010000000DBL_W2[0]
0010100000000DBL_N1[0]
0100000000001OUT_FAN[4]
0100000000010OMUX_W1
0100000000100OMUX_E2
0100000001000OMUX_NW10
0100000010000OMUX_N10
0100000100000DBL_S1[0]
0100001000000IMUX_CLB_BY[0]
0100010000000DBL_N2[0]
0100100000000IMUX_CLB_BY[1]
1000000000001OUT_FAN[3]
1000000000010DBL_E2[1]
1000000000100DBL_S0[2]
1000000001000DBL_E2[0]
1000000010000DBL_E2[2]
1000000100000DBL_W1[0]
1000001000000DBL_E1[2]
1000010000000DBL_E1[1]
1000100000000DBL_N2[1]
virtex2 INT_CLB switchbox INT muxes IMUX_CLB_G2[0]
BitsDestination
MAIN[9][28]MAIN[9][30]MAIN[8][30]MAIN[8][28]MAIN[10][30]MAIN[10][28]MAIN[11][30]MAIN[11][28]MAIN[13][28]MAIN[13][30]MAIN[12][30]MAIN[12][28]MAIN[3][28]IMUX_CLB_G2[0]
Source
0000000000000PULLUP
0001000000001OMUX[6]
0001000000010OMUX_W6
0001000000100DBL_S0[4]
0001000001000DBL_W0[4]
0001000010000DBL_E0[3]
0001000100000DBL_W1[2]
0001001000000DBL_N1[4]
0001010000000DBL_W2[4]
0001100000000DBL_N2[4]
0010000000001OMUX_S4
0010000000010DBL_N0[3]
0010000000100DBL_S2[4]
0010000001000DBL_S2[3]
0010000010000DBL_W2[2]
0010000100000DBL_S1[4]
0010001000000DBL_E1[3]
0010010000000DBL_N2[2]
0010100000000DBL_N1[3]
0100000000001OUT_FAN[5]
0100000000010OMUX_N12
0100000000100OMUX_E7
0100000001000OMUX_NE12
0100000010000OMUX_WN14
0100000100000IMUX_CLB_BX[3]
0100001000000DBL_S1[3]
0100010000000DBL_E1[4]
0100100000000IMUX_CLB_BX[2]
1000000000001OUT_FAN[2]
1000000000010DBL_E2[4]
1000000000100DBL_E2[3]
1000000001000DBL_W2[3]
1000000010000DBL_W0[2]
1000000100000DBL_N1[2]
1000001000000DBL_W1[3]
1000010000000DBL_W1[4]
1000100000000DBL_N2[3]
virtex2 INT_CLB switchbox INT muxes IMUX_CLB_G2[1]
BitsDestination
MAIN[8][55]MAIN[9][53]MAIN[8][53]MAIN[9][55]MAIN[10][55]MAIN[10][53]MAIN[11][53]MAIN[11][55]MAIN[13][53]MAIN[13][55]MAIN[12][53]MAIN[12][55]MAIN[3][55]IMUX_CLB_G2[1]
Source
0000000000000PULLUP
0001000000001OMUX[9]
0001000000010OMUX_WS1
0001000000100OMUX_E8
0001000001000OMUX_SE3
0001000010000OMUX_W9
0001000100000DBL_S1[5]
0001001000000IMUX_CLB_BX[1]
0001010000000DBL_N2[5]
0001100000000IMUX_CLB_BX[0]
0010000000001OUT_FAN[1]
0010000000010DBL_E0[5]
0010000000100OMUX_S3
0010000001000DBL_W0[6]
0010000010000DBL_S0[6]
0010000100000DBL_N1[6]
0010001000000DBL_S1[7]
0010010000000DBL_W2[6]
0010100000000DBL_S1[6]
0100000000001OMUX_N11
0100000000010DBL_E2[6]
0100000000100DBL_E2[5]
0100000001000DBL_E2[7]
0100000010000DBL_E0[7]
0100000100000DBL_W1[5]
0100001000000DBL_E1[7]
0100010000000DBL_E1[6]
0100100000000DBL_N2[6]
1000000000001OUT_FAN[6]
1000000000010DBL_S2[5]
1000000000100DBL_N0[5]
1000000001000DBL_S2[6]
1000000010000DBL_S2[7]
1000000100000DBL_E1[5]
1000001000000DBL_W1[6]
1000010000000DBL_W2[5]
1000100000000DBL_N1[5]
virtex2 INT_CLB switchbox INT muxes IMUX_CLB_G2[2]
BitsDestination
MAIN[8][24]MAIN[8][26]MAIN[9][26]MAIN[9][24]MAIN[10][24]MAIN[10][26]MAIN[11][24]MAIN[11][26]MAIN[13][26]MAIN[13][24]MAIN[12][24]MAIN[12][26]MAIN[3][24]IMUX_CLB_G2[2]
Source
0000000000000PULLUP
0001000000001OMUX[6]
0001000000010OMUX_N12
0001000000100OMUX_E7
0001000001000OMUX_NE12
0001000010000OMUX_WN14
0001000100000IMUX_CLB_BX[3]
0001001000000DBL_S1[3]
0001010000000DBL_E1[4]
0001100000000IMUX_CLB_BX[2]
0010000000001OMUX_S4
0010000000010DBL_E2[4]
0010000000100DBL_E2[3]
0010000001000DBL_W2[3]
0010000010000DBL_W0[2]
0010000100000DBL_N1[2]
0010001000000DBL_W1[3]
0010010000000DBL_W1[4]
0010100000000DBL_N2[3]
0100000000001OUT_FAN[2]
0100000000010OMUX_W6
0100000000100DBL_S0[4]
0100000001000DBL_W0[4]
0100000010000DBL_E0[3]
0100000100000DBL_W1[2]
0100001000000DBL_N1[4]
0100010000000DBL_W2[4]
0100100000000DBL_N2[4]
1000000000001OUT_FAN[5]
1000000000010DBL_N0[3]
1000000000100DBL_S2[4]
1000000001000DBL_S2[3]
1000000010000DBL_W2[2]
1000000100000DBL_S1[4]
1000001000000DBL_E1[3]
1000010000000DBL_N2[2]
1000100000000DBL_N1[3]
virtex2 INT_CLB switchbox INT muxes IMUX_CLB_G2[3]
BitsDestination
MAIN[9][51]MAIN[8][49]MAIN[9][49]MAIN[8][51]MAIN[10][49]MAIN[10][51]MAIN[11][51]MAIN[11][49]MAIN[13][51]MAIN[13][49]MAIN[12][51]MAIN[12][49]MAIN[3][51]IMUX_CLB_G2[3]
Source
0000000000000PULLUP
0001000000001OMUX[9]
0001000000010DBL_E0[5]
0001000000100OMUX_S3
0001000001000DBL_W0[6]
0001000010000DBL_S0[6]
0001000100000DBL_N1[6]
0001001000000DBL_S1[7]
0001010000000DBL_W2[6]
0001100000000DBL_S1[6]
0010000000001OUT_FAN[6]
0010000000010OMUX_WS1
0010000000100OMUX_E8
0010000001000OMUX_SE3
0010000010000OMUX_W9
0010000100000DBL_S1[5]
0010001000000IMUX_CLB_BX[1]
0010010000000DBL_N2[5]
0010100000000IMUX_CLB_BX[0]
0100000000001OMUX_N11
0100000000010DBL_S2[5]
0100000000100DBL_N0[5]
0100000001000DBL_S2[6]
0100000010000DBL_S2[7]
0100000100000DBL_E1[5]
0100001000000DBL_W1[6]
0100010000000DBL_W2[5]
0100100000000DBL_N1[5]
1000000000001OUT_FAN[1]
1000000000010DBL_E2[6]
1000000000100DBL_E2[5]
1000000001000DBL_E2[7]
1000000010000DBL_E0[7]
1000000100000DBL_W1[5]
1000001000000DBL_E1[7]
1000010000000DBL_E1[6]
1000100000000DBL_N2[6]
virtex2 INT_CLB switchbox INT muxes IMUX_CLB_G3[0]
BitsDestination
MAIN[8][47]MAIN[9][45]MAIN[8][45]MAIN[9][47]MAIN[10][47]MAIN[10][45]MAIN[11][45]MAIN[11][47]MAIN[13][45]MAIN[13][47]MAIN[12][45]MAIN[12][47]MAIN[3][47]IMUX_CLB_G3[0]
Source
0000000000000PULLUP
0001000000001OMUX[9]
0001000000010OMUX_WS1
0001000000100OMUX_E8
0001000001000OMUX_SE3
0001000010000OMUX_W9
0001000100000DBL_S1[5]
0001001000000IMUX_CLB_BX[1]
0001010000000DBL_N2[5]
0001100000000IMUX_CLB_BX[0]
0010000000001OUT_FAN[1]
0010000000010DBL_E0[5]
0010000000100OMUX_S3
0010000001000DBL_W0[6]
0010000010000DBL_S0[6]
0010000100000DBL_N1[6]
0010001000000DBL_S1[7]
0010010000000DBL_W2[6]
0010100000000DBL_S1[6]
0100000000001OMUX_N11
0100000000010DBL_E2[6]
0100000000100DBL_E2[5]
0100000001000DBL_E2[7]
0100000010000DBL_E0[7]
0100000100000DBL_W1[5]
0100001000000DBL_E1[7]
0100010000000DBL_E1[6]
0100100000000DBL_N2[6]
1000000000001OUT_FAN[6]
1000000000010DBL_S2[5]
1000000000100DBL_N0[5]
1000000001000DBL_S2[6]
1000000010000DBL_S2[7]
1000000100000DBL_E1[5]
1000001000000DBL_W1[6]
1000010000000DBL_W2[5]
1000100000000DBL_N1[5]
virtex2 INT_CLB switchbox INT muxes IMUX_CLB_G3[1]
BitsDestination
MAIN[9][36]MAIN[9][38]MAIN[8][38]MAIN[8][36]MAIN[10][38]MAIN[10][36]MAIN[11][38]MAIN[11][36]MAIN[13][36]MAIN[13][38]MAIN[12][38]MAIN[12][36]MAIN[3][36]IMUX_CLB_G3[1]
Source
0000000000000PULLUP
0001000000001OMUX[6]
0001000000010OMUX_W6
0001000000100DBL_S0[4]
0001000001000DBL_W0[4]
0001000010000DBL_E0[3]
0001000100000DBL_W1[2]
0001001000000DBL_N1[4]
0001010000000DBL_W2[4]
0001100000000DBL_N2[4]
0010000000001OMUX_S4
0010000000010DBL_N0[3]
0010000000100DBL_S2[4]
0010000001000DBL_S2[3]
0010000010000DBL_W2[2]
0010000100000DBL_S1[4]
0010001000000DBL_E1[3]
0010010000000DBL_N2[2]
0010100000000DBL_N1[3]
0100000000001OUT_FAN[5]
0100000000010OMUX_N12
0100000000100OMUX_E7
0100000001000OMUX_NE12
0100000010000OMUX_WN14
0100000100000IMUX_CLB_BX[3]
0100001000000DBL_S1[3]
0100010000000DBL_E1[4]
0100100000000IMUX_CLB_BX[2]
1000000000001OUT_FAN[2]
1000000000010DBL_E2[4]
1000000000100DBL_E2[3]
1000000001000DBL_W2[3]
1000000010000DBL_W0[2]
1000000100000DBL_N1[2]
1000001000000DBL_W1[3]
1000010000000DBL_W1[4]
1000100000000DBL_N2[3]
virtex2 INT_CLB switchbox INT muxes IMUX_CLB_G3[2]
BitsDestination
MAIN[9][43]MAIN[8][41]MAIN[9][41]MAIN[8][43]MAIN[10][41]MAIN[10][43]MAIN[11][43]MAIN[11][41]MAIN[13][43]MAIN[13][41]MAIN[12][43]MAIN[12][41]MAIN[3][43]IMUX_CLB_G3[2]
Source
0000000000000PULLUP
0001000000001OMUX[9]
0001000000010DBL_E0[5]
0001000000100OMUX_S3
0001000001000DBL_W0[6]
0001000010000DBL_S0[6]
0001000100000DBL_N1[6]
0001001000000DBL_S1[7]
0001010000000DBL_W2[6]
0001100000000DBL_S1[6]
0010000000001OUT_FAN[6]
0010000000010OMUX_WS1
0010000000100OMUX_E8
0010000001000OMUX_SE3
0010000010000OMUX_W9
0010000100000DBL_S1[5]
0010001000000IMUX_CLB_BX[1]
0010010000000DBL_N2[5]
0010100000000IMUX_CLB_BX[0]
0100000000001OMUX_N11
0100000000010DBL_S2[5]
0100000000100DBL_N0[5]
0100000001000DBL_S2[6]
0100000010000DBL_S2[7]
0100000100000DBL_E1[5]
0100001000000DBL_W1[6]
0100010000000DBL_W2[5]
0100100000000DBL_N1[5]
1000000000001OUT_FAN[1]
1000000000010DBL_E2[6]
1000000000100DBL_E2[5]
1000000001000DBL_E2[7]
1000000010000DBL_E0[7]
1000000100000DBL_W1[5]
1000001000000DBL_E1[7]
1000010000000DBL_E1[6]
1000100000000DBL_N2[6]
virtex2 INT_CLB switchbox INT muxes IMUX_CLB_G3[3]
BitsDestination
MAIN[8][32]MAIN[8][34]MAIN[9][34]MAIN[9][32]MAIN[10][32]MAIN[10][34]MAIN[11][32]MAIN[11][34]MAIN[13][34]MAIN[13][32]MAIN[12][32]MAIN[12][34]MAIN[3][32]IMUX_CLB_G3[3]
Source
0000000000000PULLUP
0001000000001OMUX[6]
0001000000010OMUX_N12
0001000000100OMUX_E7
0001000001000OMUX_NE12
0001000010000OMUX_WN14
0001000100000IMUX_CLB_BX[3]
0001001000000DBL_S1[3]
0001010000000DBL_E1[4]
0001100000000IMUX_CLB_BX[2]
0010000000001OMUX_S4
0010000000010DBL_E2[4]
0010000000100DBL_E2[3]
0010000001000DBL_W2[3]
0010000010000DBL_W0[2]
0010000100000DBL_N1[2]
0010001000000DBL_W1[3]
0010010000000DBL_W1[4]
0010100000000DBL_N2[3]
0100000000001OUT_FAN[2]
0100000000010OMUX_W6
0100000000100DBL_S0[4]
0100000001000DBL_W0[4]
0100000010000DBL_E0[3]
0100000100000DBL_W1[2]
0100001000000DBL_N1[4]
0100010000000DBL_W2[4]
0100100000000DBL_N2[4]
1000000000001OUT_FAN[5]
1000000000010DBL_N0[3]
1000000000100DBL_S2[4]
1000000001000DBL_S2[3]
1000000010000DBL_W2[2]
1000000100000DBL_S1[4]
1000001000000DBL_E1[3]
1000010000000DBL_N2[2]
1000100000000DBL_N1[3]
virtex2 INT_CLB switchbox INT muxes IMUX_CLB_G4[0]
BitsDestination
MAIN[8][7]MAIN[8][5]MAIN[9][5]MAIN[9][7]MAIN[10][7]MAIN[10][5]MAIN[11][5]MAIN[11][7]MAIN[13][7]MAIN[12][5]MAIN[13][5]MAIN[12][7]MAIN[3][7]IMUX_CLB_G4[0]
Source
0000000000000PULLUP
0001000000001OMUX[2]
0001000000010OMUX_W1
0001000000100OMUX_E2
0001000001000OMUX_NW10
0001000010000OMUX_N10
0001000100000DBL_S1[0]
0001001000000IMUX_CLB_BY[0]
0001010000000DBL_N2[0]
0001100000000IMUX_CLB_BY[1]
0010000000001OMUX_S0
0010000000010DBL_E2[1]
0010000000100DBL_S0[2]
0010000001000DBL_E2[0]
0010000010000DBL_E2[2]
0010000100000DBL_W1[0]
0010001000000DBL_E1[2]
0010010000000DBL_E1[1]
0010100000000DBL_N2[1]
0100000000001OUT_FAN[3]
0100000000010DBL_E0[1]
0100000000100DBL_S0[0]
0100000001000OMUX_EN8
0100000010000DBL_W0[0]
0100000100000DBL_N1[1]
0100001000000DBL_S1[2]
0100010000000DBL_W2[1]
0100100000000DBL_S1[1]
1000000000001OUT_FAN[4]
1000000000010DBL_S2[0]
1000000000100DBL_S2[2]
1000000001000DBL_N0[1]
1000000010000DBL_S2[1]
1000000100000DBL_E1[0]
1000001000000DBL_W1[1]
1000010000000DBL_W2[0]
1000100000000DBL_N1[0]
virtex2 INT_CLB switchbox INT muxes IMUX_CLB_G4[1]
BitsDestination
MAIN[9][76]MAIN[8][78]MAIN[9][78]MAIN[8][76]MAIN[10][78]MAIN[10][76]MAIN[11][78]MAIN[11][76]MAIN[13][78]MAIN[12][78]MAIN[12][76]MAIN[13][76]MAIN[3][76]IMUX_CLB_G4[1]
Source
0000000000000PULLUP
0001000000001OMUX[13]
0001000000010DBL_W0[8]
0001000000100OMUX_SW5
0001000001000DBL_S0[8]
0001000010000DBL_E0[9]
0001000100000DBL_W1[7]
0001001000000DBL_N1[9]
0001010000000DBL_W2[9]
0001100000000DBL_N2[9]
0010000000001OUT_FAN[7]
0010000000010OMUX_S5
0010000000100OMUX_W14
0010000001000OMUX_ES7
0010000010000OMUX_E13
0010000100000IMUX_CLB_BY[2]
0010001000000DBL_S1[8]
0010010000000DBL_E1[9]
0010100000000IMUX_CLB_BY[3]
0100000000001OMUX_N15
0100000000010DBL_W2[7]
0100000000100DBL_N0[9]
0100000001000DBL_S2[9]
0100000010000DBL_S2[8]
0100000100000DBL_S1[9]
0100001000000DBL_E1[8]
0100010000000DBL_N2[7]
0100100000000DBL_N1[8]
1000000000001OUT_FAN[0]
1000000000010DBL_N0[7]
1000000000100DBL_E2[9]
1000000001000DBL_E2[8]
1000000010000DBL_W2[8]
1000000100000DBL_N1[7]
1000001000000DBL_W1[8]
1000010000000DBL_W1[9]
1000100000000DBL_N2[8]
virtex2 INT_CLB switchbox INT muxes IMUX_CLB_G4[2]
BitsDestination
MAIN[9][3]MAIN[9][1]MAIN[8][1]MAIN[8][3]MAIN[10][1]MAIN[10][3]MAIN[11][3]MAIN[11][1]MAIN[13][1]MAIN[12][3]MAIN[13][3]MAIN[12][1]MAIN[3][3]IMUX_CLB_G4[2]
Source
0000000000000PULLUP
0001000000001OMUX[2]
0001000000010DBL_E0[1]
0001000000100DBL_S0[0]
0001000001000OMUX_EN8
0001000010000DBL_W0[0]
0001000100000DBL_N1[1]
0001001000000DBL_S1[2]
0001010000000DBL_W2[1]
0001100000000DBL_S1[1]
0010000000001OMUX_S0
0010000000010DBL_S2[0]
0010000000100DBL_S2[2]
0010000001000DBL_N0[1]
0010000010000DBL_S2[1]
0010000100000DBL_E1[0]
0010001000000DBL_W1[1]
0010010000000DBL_W2[0]
0010100000000DBL_N1[0]
0100000000001OUT_FAN[4]
0100000000010OMUX_W1
0100000000100OMUX_E2
0100000001000OMUX_NW10
0100000010000OMUX_N10
0100000100000DBL_S1[0]
0100001000000IMUX_CLB_BY[0]
0100010000000DBL_N2[0]
0100100000000IMUX_CLB_BY[1]
1000000000001OUT_FAN[3]
1000000000010DBL_E2[1]
1000000000100DBL_S0[2]
1000000001000DBL_E2[0]
1000000010000DBL_E2[2]
1000000100000DBL_W1[0]
1000001000000DBL_E1[2]
1000010000000DBL_E1[1]
1000100000000DBL_N2[1]
virtex2 INT_CLB switchbox INT muxes IMUX_CLB_G4[3]
BitsDestination
MAIN[8][72]MAIN[9][74]MAIN[8][74]MAIN[9][72]MAIN[10][72]MAIN[10][74]MAIN[11][72]MAIN[11][74]MAIN[13][72]MAIN[12][72]MAIN[12][74]MAIN[13][74]MAIN[3][72]IMUX_CLB_G4[3]
Source
0000000000000PULLUP
0001000000001OMUX[13]
0001000000010OMUX_S5
0001000000100OMUX_W14
0001000001000OMUX_ES7
0001000010000OMUX_E13
0001000100000IMUX_CLB_BY[2]
0001001000000DBL_S1[8]
0001010000000DBL_E1[9]
0001100000000IMUX_CLB_BY[3]
0010000000001OUT_FAN[0]
0010000000010DBL_W0[8]
0010000000100OMUX_SW5
0010000001000DBL_S0[8]
0010000010000DBL_E0[9]
0010000100000DBL_W1[7]
0010001000000DBL_N1[9]
0010010000000DBL_W2[9]
0010100000000DBL_N2[9]
0100000000001OMUX_N15
0100000000010DBL_N0[7]
0100000000100DBL_E2[9]
0100000001000DBL_E2[8]
0100000010000DBL_W2[8]
0100000100000DBL_N1[7]
0100001000000DBL_W1[8]
0100010000000DBL_W1[9]
0100100000000DBL_N2[8]
1000000000001OUT_FAN[7]
1000000000010DBL_W2[7]
1000000000100DBL_N0[9]
1000000001000DBL_S2[9]
1000000010000DBL_S2[8]
1000000100000DBL_S1[9]
1000001000000DBL_E1[8]
1000010000000DBL_N2[7]
1000100000000DBL_N1[8]
virtex2 INT_CLB switchbox INT muxes IMUX_CLB_BX[0]
BitsDestination
MAIN[9][16]MAIN[9][19]MAIN[3][19]MAIN[3][16]MAIN[10][17]MAIN[10][19]MAIN[11][19]MAIN[11][17]MAIN[13][17]MAIN[12][19]MAIN[13][19]MAIN[12][17]IMUX_CLB_BX[0]
Source
000000000000PULLUP
000100000001OMUX_W1
000100000010OMUX_E2
000100000100OMUX_NW10
000100001000OMUX_N10
000100010000DBL_S1[0]
000100100000IMUX_CLB_BY[0]
000101000000DBL_N2[0]
000110000000IMUX_CLB_BY[1]
001000000001DBL_E0[1]
001000000010DBL_S0[0]
001000000100OMUX_EN8
001000001000DBL_W0[0]
001000010000DBL_N1[1]
001000100000DBL_S1[2]
001001000000DBL_W2[1]
001010000000DBL_S1[1]
010000000001DBL_E2[1]
010000000010DBL_S0[2]
010000000100DBL_E2[0]
010000001000DBL_E2[2]
010000010000DBL_W1[0]
010000100000DBL_E1[2]
010001000000DBL_E1[1]
010010000000DBL_N2[1]
100000000001DBL_S2[0]
100000000010DBL_S2[2]
100000000100DBL_N0[1]
100000001000DBL_S2[1]
100000010000DBL_E1[0]
100000100000DBL_W1[1]
100001000000DBL_W2[0]
100010000000DBL_N1[0]
virtex2 INT_CLB switchbox INT muxes IMUX_CLB_BX[1]
BitsDestination
MAIN[9][63]MAIN[9][60]MAIN[3][60]MAIN[3][63]MAIN[10][62]MAIN[10][60]MAIN[11][62]MAIN[11][60]MAIN[13][62]MAIN[12][62]MAIN[12][60]MAIN[13][60]IMUX_CLB_BX[1]
Source
000000000000PULLUP
000100000001OMUX_S5
000100000010OMUX_W14
000100000100OMUX_ES7
000100001000OMUX_E13
000100010000IMUX_CLB_BY[2]
000100100000DBL_S1[8]
000101000000DBL_E1[9]
000110000000IMUX_CLB_BY[3]
001000000001DBL_W0[8]
001000000010OMUX_SW5
001000000100DBL_S0[8]
001000001000DBL_E0[9]
001000010000DBL_W1[7]
001000100000DBL_N1[9]
001001000000DBL_W2[9]
001010000000DBL_N2[9]
010000000001DBL_N0[7]
010000000010DBL_E2[9]
010000000100DBL_E2[8]
010000001000DBL_W2[8]
010000010000DBL_N1[7]
010000100000DBL_W1[8]
010001000000DBL_W1[9]
010010000000DBL_N2[8]
100000000001DBL_W2[7]
100000000010DBL_N0[9]
100000000100DBL_S2[9]
100000001000DBL_S2[8]
100000010000DBL_S1[9]
100000100000DBL_E1[8]
100001000000DBL_N2[7]
100010000000DBL_N1[8]
virtex2 INT_CLB switchbox INT muxes IMUX_CLB_BX[2]
BitsDestination
MAIN[9][17]MAIN[9][18]MAIN[8][18]MAIN[8][17]MAIN[10][16]MAIN[10][18]MAIN[11][18]MAIN[11][16]MAIN[13][16]MAIN[12][18]MAIN[13][18]MAIN[12][16]IMUX_CLB_BX[2]
Source
000000000000PULLUP
000100000001OMUX_W1
000100000010OMUX_E2
000100000100OMUX_NW10
000100001000OMUX_N10
000100010000DBL_S1[0]
000100100000IMUX_CLB_BY[0]
000101000000DBL_N2[0]
000110000000IMUX_CLB_BY[1]
001000000001DBL_E0[1]
001000000010DBL_S0[0]
001000000100OMUX_EN8
001000001000DBL_W0[0]
001000010000DBL_N1[1]
001000100000DBL_S1[2]
001001000000DBL_W2[1]
001010000000DBL_S1[1]
010000000001DBL_E2[1]
010000000010DBL_S0[2]
010000000100DBL_E2[0]
010000001000DBL_E2[2]
010000010000DBL_W1[0]
010000100000DBL_E1[2]
010001000000DBL_E1[1]
010010000000DBL_N2[1]
100000000001DBL_S2[0]
100000000010DBL_S2[2]
100000000100DBL_N0[1]
100000001000DBL_S2[1]
100000010000DBL_E1[0]
100000100000DBL_W1[1]
100001000000DBL_W2[0]
100010000000DBL_N1[0]
virtex2 INT_CLB switchbox INT muxes IMUX_CLB_BX[3]
BitsDestination
MAIN[9][62]MAIN[9][61]MAIN[8][61]MAIN[8][62]MAIN[10][63]MAIN[10][61]MAIN[11][63]MAIN[11][61]MAIN[13][63]MAIN[12][63]MAIN[12][61]MAIN[13][61]IMUX_CLB_BX[3]
Source
000000000000PULLUP
000100000001OMUX_S5
000100000010OMUX_W14
000100000100OMUX_ES7
000100001000OMUX_E13
000100010000IMUX_CLB_BY[2]
000100100000DBL_S1[8]
000101000000DBL_E1[9]
000110000000IMUX_CLB_BY[3]
001000000001DBL_W0[8]
001000000010OMUX_SW5
001000000100DBL_S0[8]
001000001000DBL_E0[9]
001000010000DBL_W1[7]
001000100000DBL_N1[9]
001001000000DBL_W2[9]
001010000000DBL_N2[9]
010000000001DBL_N0[7]
010000000010DBL_E2[9]
010000000100DBL_E2[8]
010000001000DBL_W2[8]
010000010000DBL_N1[7]
010000100000DBL_W1[8]
010001000000DBL_W1[9]
010010000000DBL_N2[8]
100000000001DBL_W2[7]
100000000010DBL_N0[9]
100000000100DBL_S2[9]
100000001000DBL_S2[8]
100000010000DBL_S1[9]
100000100000DBL_E1[8]
100001000000DBL_N2[7]
100010000000DBL_N1[8]
virtex2 INT_CLB switchbox INT muxes IMUX_CLB_BY[0]
BitsDestination
MAIN[9][23]MAIN[9][20]MAIN[3][23]MAIN[3][20]MAIN[10][22]MAIN[10][20]MAIN[11][22]MAIN[11][20]MAIN[13][20]MAIN[13][22]MAIN[12][22]MAIN[12][20]IMUX_CLB_BY[0]
Source
000000000000PULLUP
000100000001OMUX_W6
000100000010DBL_S0[4]
000100000100DBL_W0[4]
000100001000DBL_E0[3]
000100010000DBL_W1[2]
000100100000DBL_N1[4]
000101000000DBL_W2[4]
000110000000DBL_N2[4]
001000000001OMUX_N12
001000000010OMUX_E7
001000000100OMUX_NE12
001000001000OMUX_WN14
001000010000IMUX_CLB_BX[3]
001000100000DBL_S1[3]
001001000000DBL_E1[4]
001010000000IMUX_CLB_BX[2]
010000000001DBL_E2[4]
010000000010DBL_E2[3]
010000000100DBL_W2[3]
010000001000DBL_W0[2]
010000010000DBL_N1[2]
010000100000DBL_W1[3]
010001000000DBL_W1[4]
010010000000DBL_N2[3]
100000000001DBL_N0[3]
100000000010DBL_S2[4]
100000000100DBL_S2[3]
100000001000DBL_W2[2]
100000010000DBL_S1[4]
100000100000DBL_E1[3]
100001000000DBL_N2[2]
100010000000DBL_N1[3]
virtex2 INT_CLB switchbox INT muxes IMUX_CLB_BY[1]
BitsDestination
MAIN[9][56]MAIN[9][59]MAIN[3][59]MAIN[3][56]MAIN[10][57]MAIN[10][59]MAIN[11][59]MAIN[11][57]MAIN[13][59]MAIN[13][57]MAIN[12][59]MAIN[12][57]IMUX_CLB_BY[1]
Source
000000000000PULLUP
000100000001OMUX_WS1
000100000010OMUX_E8
000100000100OMUX_SE3
000100001000OMUX_W9
000100010000DBL_S1[5]
000100100000IMUX_CLB_BX[1]
000101000000DBL_N2[5]
000110000000IMUX_CLB_BX[0]
001000000001DBL_E0[5]
001000000010OMUX_S3
001000000100DBL_W0[6]
001000001000DBL_S0[6]
001000010000DBL_N1[6]
001000100000DBL_S1[7]
001001000000DBL_W2[6]
001010000000DBL_S1[6]
010000000001DBL_E2[6]
010000000010DBL_E2[5]
010000000100DBL_E2[7]
010000001000DBL_E0[7]
010000010000DBL_W1[5]
010000100000DBL_E1[7]
010001000000DBL_E1[6]
010010000000DBL_N2[6]
100000000001DBL_S2[5]
100000000010DBL_N0[5]
100000000100DBL_S2[6]
100000001000DBL_S2[7]
100000010000DBL_E1[5]
100000100000DBL_W1[6]
100001000000DBL_W2[5]
100010000000DBL_N1[5]
virtex2 INT_CLB switchbox INT muxes IMUX_CLB_BY[2]
BitsDestination
MAIN[9][22]MAIN[9][21]MAIN[8][22]MAIN[8][21]MAIN[10][23]MAIN[10][21]MAIN[11][23]MAIN[11][21]MAIN[13][21]MAIN[13][23]MAIN[12][23]MAIN[12][21]IMUX_CLB_BY[2]
Source
000000000000PULLUP
000100000001OMUX_W6
000100000010DBL_S0[4]
000100000100DBL_W0[4]
000100001000DBL_E0[3]
000100010000DBL_W1[2]
000100100000DBL_N1[4]
000101000000DBL_W2[4]
000110000000DBL_N2[4]
001000000001OMUX_N12
001000000010OMUX_E7
001000000100OMUX_NE12
001000001000OMUX_WN14
001000010000IMUX_CLB_BX[3]
001000100000DBL_S1[3]
001001000000DBL_E1[4]
001010000000IMUX_CLB_BX[2]
010000000001DBL_E2[4]
010000000010DBL_E2[3]
010000000100DBL_W2[3]
010000001000DBL_W0[2]
010000010000DBL_N1[2]
010000100000DBL_W1[3]
010001000000DBL_W1[4]
010010000000DBL_N2[3]
100000000001DBL_N0[3]
100000000010DBL_S2[4]
100000000100DBL_S2[3]
100000001000DBL_W2[2]
100000010000DBL_S1[4]
100000100000DBL_E1[3]
100001000000DBL_N2[2]
100010000000DBL_N1[3]
virtex2 INT_CLB switchbox INT muxes IMUX_CLB_BY[3]
BitsDestination
MAIN[9][57]MAIN[9][58]MAIN[8][58]MAIN[8][57]MAIN[10][56]MAIN[10][58]MAIN[11][58]MAIN[11][56]MAIN[13][58]MAIN[13][56]MAIN[12][58]MAIN[12][56]IMUX_CLB_BY[3]
Source
000000000000PULLUP
000100000001OMUX_WS1
000100000010OMUX_E8
000100000100OMUX_SE3
000100001000OMUX_W9
000100010000DBL_S1[5]
000100100000IMUX_CLB_BX[1]
000101000000DBL_N2[5]
000110000000IMUX_CLB_BX[0]
001000000001DBL_E0[5]
001000000010OMUX_S3
001000000100DBL_W0[6]
001000001000DBL_S0[6]
001000010000DBL_N1[6]
001000100000DBL_S1[7]
001001000000DBL_W2[6]
001010000000DBL_S1[6]
010000000001DBL_E2[6]
010000000010DBL_E2[5]
010000000100DBL_E2[7]
010000001000DBL_E0[7]
010000010000DBL_W1[5]
010000100000DBL_E1[7]
010001000000DBL_E1[6]
010010000000DBL_N2[6]
100000000001DBL_S2[5]
100000000010DBL_N0[5]
100000000100DBL_S2[6]
100000001000DBL_S2[7]
100000010000DBL_E1[5]
100000100000DBL_W1[6]
100001000000DBL_W2[5]
100010000000DBL_N1[5]

Bitstream

virtex2 INT_CLB rect MAIN
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21
B79 - - - INT: mux IMUX_CLB_F4[1] bit 0 INT: mux IMUX_CE[2] bit 5 INT: mux IMUX_CE[3] bit 1 INT: mux OMUX[14] bit 0 INT: mux OMUX[15] bit 9 INT: mux IMUX_CLB_F4[1] bit 12 INT: mux IMUX_CLB_F4[1] bit 9 INT: mux IMUX_CLB_F4[1] bit 8 INT: mux IMUX_CLB_F4[1] bit 6 INT: mux IMUX_CLB_F4[1] bit 3 INT: mux IMUX_CLB_F4[1] bit 4 INT: mux DBL_E0[9] bit 0 INT: mux DBL_W0[9] bit 7 INT: mux DBL_E0[9] bit 5 INT: mux DBL_E0[9] bit 7 INT: mux HEX_W0[9] bit 0 INT: mux HEX_W0[9] bit 3 INT: mux HEX_W0[9] bit 4 INT: mux LV[18] bit 1
B78 - - - - INT: !invert IMUX_CE_OPTINV[3] ← IMUX_CE[3] INT: mux IMUX_CE[3] bit 3 INT: mux OMUX[15] bit 8 INT: mux OMUX[15] bit 6 INT: mux IMUX_CLB_G4[1] bit 11 INT: mux IMUX_CLB_G4[1] bit 10 INT: mux IMUX_CLB_G4[1] bit 8 INT: mux IMUX_CLB_G4[1] bit 6 INT: mux IMUX_CLB_G4[1] bit 3 INT: mux IMUX_CLB_G4[1] bit 4 INT: mux DBL_E0[9] bit 1 INT: mux DBL_W0[9] bit 4 INT: mux DBL_W0[9] bit 3 INT: mux DBL_W0[9] bit 0 INT: mux HEX_E0[9] bit 1 INT: mux HEX_E0[9] bit 3 INT: mux HEX_E0[9] bit 5 INT: mux HEX_W0[9] bit 6
B77 - - - - INT: mux IMUX_CE[3] bit 0 INT: mux IMUX_CE[3] bit 2 INT: mux OMUX[15] bit 0 INT: mux OMUX[15] bit 7 INT: mux IMUX_CLB_F4[1] bit 10 INT: mux IMUX_CLB_F4[1] bit 11 INT: mux IMUX_CLB_F4[1] bit 7 INT: mux IMUX_CLB_F4[1] bit 5 INT: mux IMUX_CLB_F4[1] bit 2 INT: mux IMUX_CLB_F4[1] bit 1 INT: mux DBL_W0[9] bit 5 INT: mux DBL_E0[9] bit 3 INT: mux DBL_W0[9] bit 2 INT: mux DBL_W0[9] bit 1 INT: mux HEX_W0[9] bit 2 INT: mux HEX_W0[9] bit 1 INT: mux HEX_E0[9] bit 6 INT: mux LV[18] bit 3
B76 - - - INT: mux IMUX_CLB_G4[1] bit 0 INT: mux IMUX_CE[3] bit 4 INT: mux IMUX_CE[3] bit 5 INT: mux OMUX[14] bit 1 INT: mux OMUX[15] bit 1 INT: mux IMUX_CLB_G4[1] bit 9 INT: mux IMUX_CLB_G4[1] bit 12 INT: mux IMUX_CLB_G4[1] bit 7 INT: mux IMUX_CLB_G4[1] bit 5 INT: mux IMUX_CLB_G4[1] bit 2 INT: mux IMUX_CLB_G4[1] bit 1 INT: mux DBL_W0[9] bit 6 INT: mux DBL_E0[9] bit 2 INT: mux DBL_E0[9] bit 4 INT: mux DBL_E0[9] bit 6 INT: mux HEX_E0[9] bit 2 INT: mux HEX_E0[9] bit 0 INT: mux HEX_E0[9] bit 4 INT: mux HEX_W0[9] bit 5
B75 - - - INT: mux IMUX_CLB_F4[3] bit 0 INT: mux IMUX_CE[2] bit 4 INT: mux IMUX_CE[2] bit 7 INT: mux OMUX[15] bit 3 INT: mux OMUX[14] bit 3 INT: mux IMUX_CLB_F4[3] bit 9 INT: mux IMUX_CLB_F4[3] bit 12 INT: mux IMUX_CLB_F4[3] bit 7 INT: mux IMUX_CLB_F4[3] bit 5 INT: mux IMUX_CLB_F4[3] bit 2 INT: mux IMUX_CLB_F4[3] bit 1 INT: mux DBL_S0[9] bit 4 INT: mux DBL_N0[9] bit 2 INT: mux DBL_S0[9] bit 0 INT: mux DBL_S0[9] bit 3 INT: mux HEX_N0[9] bit 1 INT: mux HEX_N0[9] bit 3 INT: mux HEX_N0[9] bit 5 INT: mux LV[6] bit 0
B74 - - - - INT: mux IMUX_CE[3] bit 7 INT: mux IMUX_CE[3] bit 6 INT: mux OMUX[15] bit 2 INT: mux OMUX[14] bit 2 INT: mux IMUX_CLB_G4[3] bit 10 INT: mux IMUX_CLB_G4[3] bit 11 INT: mux IMUX_CLB_G4[3] bit 7 INT: mux IMUX_CLB_G4[3] bit 5 INT: mux IMUX_CLB_G4[3] bit 2 INT: mux IMUX_CLB_G4[3] bit 1 INT: mux DBL_S0[9] bit 5 INT: mux DBL_N0[9] bit 0 INT: mux DBL_N0[9] bit 7 INT: mux DBL_N0[9] bit 5 INT: mux HEX_S0[9] bit 1 INT: mux HEX_S0[9] bit 2 INT: mux HEX_S0[9] bit 4 INT: mux HEX_N0[9] bit 4
B73 - - - - INT: mux IMUX_CE[2] bit 0 INT: mux IMUX_CE[2] bit 1 INT: mux OMUX[14] bit 4 INT: mux OMUX[15] bit 4 INT: mux IMUX_CLB_F4[3] bit 11 INT: mux IMUX_CLB_F4[3] bit 10 INT: mux IMUX_CLB_F4[3] bit 8 INT: mux IMUX_CLB_F4[3] bit 6 INT: mux IMUX_CLB_F4[3] bit 3 INT: mux IMUX_CLB_F4[3] bit 4 INT: mux DBL_N0[9] bit 1 INT: mux DBL_S0[9] bit 6 INT: mux DBL_N0[9] bit 6 INT: mux DBL_N0[9] bit 4 INT: mux HEX_N0[9] bit 2 INT: mux HEX_N0[9] bit 0 INT: mux HEX_S0[9] bit 5 INT: mux LV[6] bit 6
B72 - - - INT: mux IMUX_CLB_G4[3] bit 0 INT: !invert IMUX_CE_OPTINV[2] ← IMUX_CE[2] INT: mux IMUX_CE[2] bit 3 INT: mux OMUX[15] bit 5 INT: mux OMUX[14] bit 7 INT: mux IMUX_CLB_G4[3] bit 12 INT: mux IMUX_CLB_G4[3] bit 9 INT: mux IMUX_CLB_G4[3] bit 8 INT: mux IMUX_CLB_G4[3] bit 6 INT: mux IMUX_CLB_G4[3] bit 3 INT: mux IMUX_CLB_G4[3] bit 4 INT: mux DBL_N0[9] bit 3 INT: mux DBL_S0[9] bit 7 INT: mux DBL_S0[9] bit 1 INT: mux DBL_S0[9] bit 2 INT: mux HEX_S0[9] bit 3 INT: mux HEX_S0[9] bit 0 INT: mux HEX_S0[9] bit 6 INT: mux HEX_N0[9] bit 6
B71 - - - INT: mux IMUX_CLB_F1[0] bit 0 INT: mux IMUX_CE[2] bit 6 INT: mux IMUX_CE[2] bit 2 INT: mux OMUX[14] bit 8 INT: mux OMUX[14] bit 6 INT: mux IMUX_CLB_F1[0] bit 12 INT: mux IMUX_CLB_F1[0] bit 9 INT: mux IMUX_CLB_F1[0] bit 8 INT: mux IMUX_CLB_F1[0] bit 6 INT: mux IMUX_CLB_F1[0] bit 3 INT: mux IMUX_CLB_F1[0] bit 4 INT: mux DBL_E0[8] bit 2 INT: mux DBL_W0[8] bit 3 INT: mux DBL_E0[8] bit 4 INT: mux DBL_E0[8] bit 7 INT: mux HEX_E0[8] bit 0 INT: mux HEX_E0[8] bit 3 INT: mux HEX_E0[8] bit 4 INT: mux LV[6] bit 2
B70 - - - - INT: mux IMUX_CE[1] bit 5 INT: mux IMUX_CE[1] bit 2 INT: mux OMUX[14] bit 5 INT: mux OMUX[14] bit 9 INT: mux IMUX_CLB_G1[0] bit 11 INT: mux IMUX_CLB_G1[0] bit 10 INT: mux IMUX_CLB_G1[0] bit 8 INT: mux IMUX_CLB_G1[0] bit 6 INT: mux IMUX_CLB_G1[0] bit 3 INT: mux IMUX_CLB_G1[0] bit 4 INT: mux DBL_E0[8] bit 0 INT: mux DBL_W0[8] bit 0 INT: mux DBL_W0[8] bit 7 INT: mux DBL_W0[8] bit 4 INT: mux HEX_W0[8] bit 0 INT: mux HEX_W0[8] bit 3 INT: mux HEX_W0[8] bit 4 INT: mux HEX_E0[8] bit 5
B69 - - - - INT: !invert IMUX_CE_OPTINV[1] ← IMUX_CE[1] INT: mux IMUX_CE[1] bit 3 INT: mux OMUX[12] bit 0 INT: mux OMUX[13] bit 9 INT: mux IMUX_CLB_F1[0] bit 10 INT: mux IMUX_CLB_F1[0] bit 11 INT: mux IMUX_CLB_F1[0] bit 7 INT: mux IMUX_CLB_F1[0] bit 5 INT: mux IMUX_CLB_F1[0] bit 2 INT: mux IMUX_CLB_F1[0] bit 1 INT: mux DBL_W0[8] bit 2 INT: mux DBL_E0[8] bit 3 INT: mux DBL_W0[8] bit 6 INT: mux DBL_W0[8] bit 5 INT: mux HEX_E0[8] bit 2 INT: mux HEX_E0[8] bit 1 INT: mux HEX_W0[8] bit 5 INT: mux LV[6] bit 3
B68 - - - INT: mux IMUX_CLB_G1[0] bit 0 INT: mux IMUX_CE[1] bit 1 INT: mux IMUX_CE[1] bit 0 INT: mux OMUX[13] bit 8 INT: mux OMUX[13] bit 6 INT: mux IMUX_CLB_G1[0] bit 9 INT: mux IMUX_CLB_G1[0] bit 12 INT: mux IMUX_CLB_G1[0] bit 7 INT: mux IMUX_CLB_G1[0] bit 5 INT: mux IMUX_CLB_G1[0] bit 2 INT: mux IMUX_CLB_G1[0] bit 1 INT: mux DBL_W0[8] bit 1 INT: mux DBL_E0[8] bit 1 INT: mux DBL_E0[8] bit 5 INT: mux DBL_E0[8] bit 6 INT: mux HEX_W0[8] bit 2 INT: mux HEX_W0[8] bit 1 INT: mux HEX_W0[8] bit 6 INT: mux HEX_E0[8] bit 6
B67 - - - INT: mux IMUX_CLB_F1[2] bit 0 INT: mux IMUX_CE[0] bit 4 INT: mux IMUX_CE[0] bit 5 INT: mux OMUX[13] bit 0 INT: mux OMUX[13] bit 7 INT: mux IMUX_CLB_F1[2] bit 9 INT: mux IMUX_CLB_F1[2] bit 12 INT: mux IMUX_CLB_F1[2] bit 7 INT: mux IMUX_CLB_F1[2] bit 5 INT: mux IMUX_CLB_F1[2] bit 2 INT: mux IMUX_CLB_F1[2] bit 1 INT: mux DBL_S0[8] bit 3 INT: mux DBL_N0[8] bit 1 INT: mux DBL_S0[8] bit 5 INT: mux DBL_S0[8] bit 7 INT: mux HEX_S0[8] bit 1 INT: mux HEX_S0[8] bit 3 INT: mux HEX_S0[8] bit 5 INT: mux LV[18] bit 6
B66 - - - - INT: mux IMUX_CE[1] bit 6 INT: mux IMUX_CE[1] bit 4 INT: mux OMUX[12] bit 1 INT: mux OMUX[13] bit 1 INT: mux IMUX_CLB_G1[2] bit 10 INT: mux IMUX_CLB_G1[2] bit 11 INT: mux IMUX_CLB_G1[2] bit 7 INT: mux IMUX_CLB_G1[2] bit 5 INT: mux IMUX_CLB_G1[2] bit 2 INT: mux IMUX_CLB_G1[2] bit 1 INT: mux DBL_S0[8] bit 0 INT: mux DBL_N0[8] bit 0 INT: mux DBL_N0[8] bit 7 INT: mux DBL_N0[8] bit 5 INT: mux HEX_N0[8] bit 1 INT: mux HEX_N0[8] bit 2 INT: mux HEX_N0[8] bit 5 INT: mux HEX_S0[8] bit 4
B65 - - - - INT: mux IMUX_CE[0] bit 6 INT: mux IMUX_CE[0] bit 7 INT: mux OMUX[13] bit 3 INT: mux OMUX[12] bit 3 INT: mux IMUX_CLB_F1[2] bit 11 INT: mux IMUX_CLB_F1[2] bit 10 INT: mux IMUX_CLB_F1[2] bit 8 INT: mux IMUX_CLB_F1[2] bit 6 INT: mux IMUX_CLB_F1[2] bit 3 INT: mux IMUX_CLB_F1[2] bit 4 INT: mux DBL_N0[8] bit 3 INT: mux DBL_S0[8] bit 1 INT: mux DBL_N0[8] bit 6 INT: mux DBL_N0[8] bit 4 INT: mux HEX_S0[8] bit 2 INT: mux HEX_S0[8] bit 0 INT: mux HEX_N0[8] bit 4 INT: mux LV[6] bit 1
B64 - - - INT: mux IMUX_CLB_G1[2] bit 0 INT: mux IMUX_CE[0] bit 1 INT: mux IMUX_CE[0] bit 2 INT: mux OMUX[13] bit 2 INT: mux OMUX[12] bit 2 INT: mux IMUX_CLB_G1[2] bit 12 INT: mux IMUX_CLB_G1[2] bit 9 INT: mux IMUX_CLB_G1[2] bit 8 INT: mux IMUX_CLB_G1[2] bit 6 INT: mux IMUX_CLB_G1[2] bit 3 INT: mux IMUX_CLB_G1[2] bit 4 INT: mux DBL_N0[8] bit 2 INT: mux DBL_S0[8] bit 2 INT: mux DBL_S0[8] bit 4 INT: mux DBL_S0[8] bit 6 INT: mux HEX_N0[8] bit 3 INT: mux HEX_N0[8] bit 0 INT: mux HEX_N0[8] bit 6 INT: mux HEX_S0[8] bit 6
B63 - - - INT: mux IMUX_CLB_BX[1] bit 8 INT: !invert IMUX_CE_OPTINV[0] ← IMUX_CE[0] INT: mux IMUX_CE[0] bit 3 INT: mux OMUX[12] bit 4 INT: mux OMUX[13] bit 4 - INT: mux IMUX_CLB_BX[1] bit 11 INT: mux IMUX_CLB_BX[3] bit 7 INT: mux IMUX_CLB_BX[3] bit 5 INT: mux IMUX_CLB_BX[3] bit 2 INT: mux IMUX_CLB_BX[3] bit 3 INT: mux DBL_E0[7] bit 2 INT: mux DBL_W0[7] bit 3 INT: mux DBL_E0[7] bit 4 INT: mux DBL_E0[7] bit 7 INT: mux HEX_W0[7] bit 0 INT: mux HEX_W0[7] bit 3 INT: mux HEX_W0[7] bit 4 INT: mux LV[18] bit 0
B62 - - - - INT: mux IMUX_CE[1] bit 7 INT: mux IMUX_CE[0] bit 0 INT: mux OMUX[13] bit 5 INT: mux OMUX[12] bit 7 INT: mux IMUX_CLB_BX[3] bit 8 INT: mux IMUX_CLB_BX[3] bit 11 INT: mux IMUX_CLB_BX[1] bit 7 INT: mux IMUX_CLB_BX[1] bit 5 INT: mux IMUX_CLB_BX[1] bit 2 INT: mux IMUX_CLB_BX[1] bit 3 INT: mux DBL_E0[7] bit 0 INT: mux DBL_W0[7] bit 0 INT: mux DBL_W0[7] bit 7 INT: mux DBL_W0[7] bit 4 INT: mux HEX_E0[7] bit 0 INT: mux HEX_E0[7] bit 3 INT: mux HEX_E0[7] bit 4 INT: mux HEX_W0[7] bit 5
B61 - - - - INT: mux IMUX_CLK[2] bit 0 INT: mux IMUX_CLK[3] bit 7 INT: mux OMUX[12] bit 8 INT: mux OMUX[12] bit 6 INT: mux IMUX_CLB_BX[3] bit 9 INT: mux IMUX_CLB_BX[3] bit 10 INT: mux IMUX_CLB_BX[3] bit 6 INT: mux IMUX_CLB_BX[3] bit 4 INT: mux IMUX_CLB_BX[3] bit 1 INT: mux IMUX_CLB_BX[3] bit 0 INT: mux DBL_W0[7] bit 2 INT: mux DBL_E0[7] bit 3 INT: mux DBL_W0[7] bit 6 INT: mux DBL_W0[7] bit 5 INT: mux HEX_W0[7] bit 2 INT: mux HEX_W0[7] bit 1 INT: mux HEX_E0[7] bit 5 INT: mux LV[6] bit 5
B60 - - - INT: mux IMUX_CLB_BX[1] bit 9 INT: invert IMUX_CLK_OPTINV[3] ← IMUX_CLK[3] INT: mux IMUX_CLK[3] bit 9 INT: mux OMUX[12] bit 5 INT: mux OMUX[12] bit 9 - INT: mux IMUX_CLB_BX[1] bit 10 INT: mux IMUX_CLB_BX[1] bit 6 INT: mux IMUX_CLB_BX[1] bit 4 INT: mux IMUX_CLB_BX[1] bit 1 INT: mux IMUX_CLB_BX[1] bit 0 INT: mux DBL_W0[7] bit 1 INT: mux DBL_E0[7] bit 1 INT: mux DBL_E0[7] bit 5 INT: mux DBL_E0[7] bit 6 INT: mux HEX_E0[7] bit 2 INT: mux HEX_E0[7] bit 1 INT: mux HEX_E0[7] bit 6 INT: mux HEX_W0[7] bit 6
B59 - - - INT: mux IMUX_CLB_BY[1] bit 9 INT: mux IMUX_CLK[3] bit 6 INT: mux IMUX_CLK[3] bit 8 INT: mux OMUX[10] bit 0 INT: mux OMUX[11] bit 9 - INT: mux IMUX_CLB_BY[1] bit 10 INT: mux IMUX_CLB_BY[1] bit 6 INT: mux IMUX_CLB_BY[1] bit 5 INT: mux IMUX_CLB_BY[1] bit 1 INT: mux IMUX_CLB_BY[1] bit 3 INT: mux DBL_S0[7] bit 4 INT: mux DBL_N0[7] bit 6 INT: mux DBL_S0[7] bit 1 INT: mux DBL_S0[7] bit 3 INT: mux HEX_N0[7] bit 1 INT: mux HEX_N0[7] bit 3 INT: mux HEX_N0[7] bit 6 INT: mux LV[18] bit 2
B58 - - - - INT: mux IMUX_CLK[3] bit 3 INT: mux IMUX_CLK[3] bit 0 INT: mux OMUX[11] bit 8 INT: mux OMUX[11] bit 6 INT: mux IMUX_CLB_BY[3] bit 9 INT: mux IMUX_CLB_BY[3] bit 10 INT: mux IMUX_CLB_BY[3] bit 6 INT: mux IMUX_CLB_BY[3] bit 5 INT: mux IMUX_CLB_BY[3] bit 1 INT: mux IMUX_CLB_BY[3] bit 3 INT: mux DBL_S0[7] bit 5 INT: mux DBL_N0[7] bit 5 INT: mux DBL_N0[7] bit 3 INT: mux DBL_N0[7] bit 1 INT: mux HEX_S0[7] bit 1 INT: mux HEX_S0[7] bit 2 INT: mux HEX_S0[7] bit 5 INT: mux HEX_N0[7] bit 5
B57 - - - - INT: mux IMUX_CLK[2] bit 3 INT: mux IMUX_CLK[2] bit 1 INT: mux OMUX[11] bit 0 INT: mux OMUX[11] bit 7 INT: mux IMUX_CLB_BY[3] bit 8 INT: mux IMUX_CLB_BY[3] bit 11 INT: mux IMUX_CLB_BY[1] bit 7 INT: mux IMUX_CLB_BY[1] bit 4 INT: mux IMUX_CLB_BY[1] bit 0 INT: mux IMUX_CLB_BY[1] bit 2 INT: mux DBL_N0[7] bit 4 INT: mux DBL_S0[7] bit 6 INT: mux DBL_N0[7] bit 2 INT: mux DBL_N0[7] bit 0 INT: mux HEX_N0[7] bit 2 INT: mux HEX_N0[7] bit 0 INT: mux HEX_S0[7] bit 6 INT: mux LV[18] bit 4
B56 - - - INT: mux IMUX_CLB_BY[1] bit 8 INT: mux IMUX_CLK[3] bit 1 INT: mux IMUX_CLK[3] bit 2 INT: mux OMUX[10] bit 1 INT: mux OMUX[11] bit 1 - INT: mux IMUX_CLB_BY[1] bit 11 INT: mux IMUX_CLB_BY[3] bit 7 INT: mux IMUX_CLB_BY[3] bit 4 INT: mux IMUX_CLB_BY[3] bit 0 INT: mux IMUX_CLB_BY[3] bit 2 INT: mux DBL_N0[7] bit 7 INT: mux DBL_S0[7] bit 7 INT: mux DBL_S0[7] bit 0 INT: mux DBL_S0[7] bit 2 INT: mux HEX_S0[7] bit 3 INT: mux HEX_S0[7] bit 0 INT: mux HEX_S0[7] bit 4 INT: mux HEX_N0[7] bit 4
B55 - - - INT: mux IMUX_CLB_G2[1] bit 0 INT: mux IMUX_CLK[2] bit 4 INT: mux IMUX_CLK[2] bit 2 INT: mux OMUX[11] bit 3 INT: mux OMUX[10] bit 3 INT: mux IMUX_CLB_G2[1] bit 12 INT: mux IMUX_CLB_G2[1] bit 9 INT: mux IMUX_CLB_G2[1] bit 8 INT: mux IMUX_CLB_G2[1] bit 5 INT: mux IMUX_CLB_G2[1] bit 1 INT: mux IMUX_CLB_G2[1] bit 3 INT: mux DBL_E0[6] bit 1 INT: mux DBL_W0[6] bit 7 INT: mux DBL_E0[6] bit 5 INT: mux DBL_E0[6] bit 7 INT: mux HEX_E0[6] bit 1 INT: mux HEX_E0[6] bit 3 INT: mux HEX_E0[6] bit 5 INT: mux LV[6] bit 4
B54 - - - - INT: mux IMUX_CLK[3] bit 4 INT: mux IMUX_CLK[2] bit 9 INT: mux OMUX[11] bit 2 INT: mux OMUX[10] bit 2 INT: mux IMUX_CLB_F2[1] bit 11 INT: mux IMUX_CLB_F2[1] bit 10 INT: mux IMUX_CLB_F2[1] bit 8 INT: mux IMUX_CLB_F2[1] bit 5 INT: mux IMUX_CLB_F2[1] bit 1 INT: mux IMUX_CLB_F2[1] bit 3 INT: mux DBL_E0[6] bit 0 INT: mux DBL_W0[6] bit 5 INT: mux DBL_W0[6] bit 3 INT: mux DBL_W0[6] bit 0 INT: mux HEX_W0[6] bit 1 INT: mux HEX_W0[6] bit 3 INT: mux HEX_W0[6] bit 4 INT: mux HEX_E0[6] bit 4
B53 - - - - INT: mux IMUX_CLK[2] bit 6 INT: mux IMUX_CLK[2] bit 8 INT: mux OMUX[10] bit 4 INT: mux OMUX[11] bit 4 INT: mux IMUX_CLB_G2[1] bit 10 INT: mux IMUX_CLB_G2[1] bit 11 INT: mux IMUX_CLB_G2[1] bit 7 INT: mux IMUX_CLB_G2[1] bit 6 INT: mux IMUX_CLB_G2[1] bit 2 INT: mux IMUX_CLB_G2[1] bit 4 INT: mux DBL_W0[6] bit 4 INT: mux DBL_E0[6] bit 3 INT: mux DBL_W0[6] bit 2 INT: mux DBL_W0[6] bit 1 INT: mux HEX_E0[6] bit 2 INT: mux HEX_E0[6] bit 0 INT: mux HEX_W0[6] bit 5 INT: mux LV[18] bit 5
B52 - - - INT: mux IMUX_CLB_F2[1] bit 0 INT: invert IMUX_CLK_OPTINV[2] ← IMUX_CLK[2] INT: mux IMUX_CLK[3] bit 5 INT: mux OMUX[11] bit 5 INT: mux OMUX[10] bit 7 INT: mux IMUX_CLB_F2[1] bit 9 INT: mux IMUX_CLB_F2[1] bit 12 INT: mux IMUX_CLB_F2[1] bit 7 INT: mux IMUX_CLB_F2[1] bit 6 INT: mux IMUX_CLB_F2[1] bit 2 INT: mux IMUX_CLB_F2[1] bit 4 INT: mux DBL_W0[6] bit 6 INT: mux DBL_E0[6] bit 2 INT: mux DBL_E0[6] bit 4 INT: mux DBL_E0[6] bit 6 INT: mux HEX_W0[6] bit 2 INT: mux HEX_W0[6] bit 0 INT: mux HEX_W0[6] bit 6 INT: mux HEX_E0[6] bit 6
B51 - - - INT: mux IMUX_CLB_G2[3] bit 0 INT: mux IMUX_CLK[2] bit 5 INT: mux IMUX_CLK[2] bit 7 INT: mux OMUX[10] bit 8 INT: mux OMUX[10] bit 6 INT: mux IMUX_CLB_G2[3] bit 9 INT: mux IMUX_CLB_G2[3] bit 12 INT: mux IMUX_CLB_G2[3] bit 7 INT: mux IMUX_CLB_G2[3] bit 6 INT: mux IMUX_CLB_G2[3] bit 2 INT: mux IMUX_CLB_G2[3] bit 4 INT: mux DBL_S0[6] bit 3 INT: mux DBL_N0[6] bit 1 INT: mux DBL_S0[6] bit 4 INT: mux DBL_S0[6] bit 7 INT: mux HEX_S0[6] bit 0 INT: mux HEX_S0[6] bit 3 INT: mux HEX_S0[6] bit 4 INT: mux LH[0] bit 0
B50 - - - - INT: mux IMUX_CLK[1] bit 5 INT: mux IMUX_CLK[1] bit 7 INT: mux OMUX[10] bit 5 INT: mux OMUX[10] bit 9 INT: mux IMUX_CLB_F2[3] bit 10 INT: mux IMUX_CLB_F2[3] bit 11 INT: mux IMUX_CLB_F2[3] bit 7 INT: mux IMUX_CLB_F2[3] bit 6 INT: mux IMUX_CLB_F2[3] bit 2 INT: mux IMUX_CLB_F2[3] bit 4 INT: mux DBL_S0[6] bit 0 INT: mux DBL_N0[6] bit 0 INT: mux DBL_N0[6] bit 7 INT: mux DBL_N0[6] bit 4 INT: mux HEX_N0[6] bit 0 INT: mux HEX_N0[6] bit 2 INT: mux HEX_N0[6] bit 4 INT: mux HEX_S0[6] bit 5
B49 - - - - INT: invert IMUX_CLK_OPTINV[1] ← IMUX_CLK[1] INT: mux IMUX_CLK[0] bit 5 INT: mux OMUX[8] bit 0 INT: mux OMUX[9] bit 9 INT: mux IMUX_CLB_G2[3] bit 11 INT: mux IMUX_CLB_G2[3] bit 10 INT: mux IMUX_CLB_G2[3] bit 8 INT: mux IMUX_CLB_G2[3] bit 5 INT: mux IMUX_CLB_G2[3] bit 1 INT: mux IMUX_CLB_G2[3] bit 3 INT: mux DBL_N0[6] bit 3 INT: mux DBL_S0[6] bit 1 INT: mux DBL_N0[6] bit 6 INT: mux DBL_N0[6] bit 5 INT: mux HEX_S0[6] bit 2 INT: mux HEX_S0[6] bit 1 INT: mux HEX_N0[6] bit 5 INT: mux LH[0] bit 1
B48 - - - INT: mux IMUX_CLB_F2[3] bit 0 INT: mux IMUX_CLK[1] bit 6 INT: mux IMUX_CLK[1] bit 8 INT: mux OMUX[9] bit 8 INT: mux OMUX[9] bit 6 INT: mux IMUX_CLB_F2[3] bit 12 INT: mux IMUX_CLB_F2[3] bit 9 INT: mux IMUX_CLB_F2[3] bit 8 INT: mux IMUX_CLB_F2[3] bit 5 INT: mux IMUX_CLB_F2[3] bit 1 INT: mux IMUX_CLB_F2[3] bit 3 INT: mux DBL_N0[6] bit 2 INT: mux DBL_S0[6] bit 2 INT: mux DBL_S0[6] bit 5 INT: mux DBL_S0[6] bit 6 INT: mux HEX_N0[6] bit 3 INT: mux HEX_N0[6] bit 1 INT: mux HEX_N0[6] bit 6 INT: mux HEX_S0[6] bit 6
B47 - - - INT: mux IMUX_CLB_G3[0] bit 0 INT: mux IMUX_CLK[0] bit 4 INT: mux IMUX_CLK[1] bit 9 INT: mux OMUX[9] bit 0 INT: mux OMUX[9] bit 7 INT: mux IMUX_CLB_G3[0] bit 12 INT: mux IMUX_CLB_G3[0] bit 9 INT: mux IMUX_CLB_G3[0] bit 8 INT: mux IMUX_CLB_G3[0] bit 5 INT: mux IMUX_CLB_G3[0] bit 1 INT: mux IMUX_CLB_G3[0] bit 3 INT: mux DBL_E0[5] bit 2 INT: mux DBL_W0[5] bit 3 INT: mux DBL_E0[5] bit 4 INT: mux DBL_E0[5] bit 7 INT: mux HEX_W0[5] bit 1 INT: mux HEX_W0[5] bit 3 INT: mux HEX_W0[5] bit 5 INT: mux LH[0] bit 2
B46 - - - - INT: mux IMUX_CLK[1] bit 4 INT: mux IMUX_CLK[1] bit 2 INT: mux OMUX[8] bit 1 INT: mux OMUX[9] bit 1 INT: mux IMUX_CLB_F3[0] bit 11 INT: mux IMUX_CLB_F3[0] bit 10 INT: mux IMUX_CLB_F3[0] bit 8 INT: mux IMUX_CLB_F3[0] bit 5 INT: mux IMUX_CLB_F3[0] bit 1 INT: mux IMUX_CLB_F3[0] bit 3 INT: mux DBL_E0[5] bit 0 INT: mux DBL_W0[5] bit 0 INT: mux DBL_W0[5] bit 7 INT: mux DBL_W0[5] bit 5 INT: mux HEX_E0[5] bit 0 INT: mux HEX_E0[5] bit 3 INT: mux HEX_E0[5] bit 4 INT: mux HEX_W0[5] bit 4
B45 - - - - INT: mux IMUX_CLK[0] bit 1 INT: mux IMUX_CLK[0] bit 2 INT: mux OMUX[9] bit 3 INT: mux OMUX[8] bit 3 INT: mux IMUX_CLB_G3[0] bit 10 INT: mux IMUX_CLB_G3[0] bit 11 INT: mux IMUX_CLB_G3[0] bit 7 INT: mux IMUX_CLB_G3[0] bit 6 INT: mux IMUX_CLB_G3[0] bit 2 INT: mux IMUX_CLB_G3[0] bit 4 INT: mux DBL_W0[5] bit 2 INT: mux DBL_E0[5] bit 3 INT: mux DBL_W0[5] bit 6 INT: mux DBL_W0[5] bit 4 INT: mux HEX_W0[5] bit 2 INT: mux HEX_W0[5] bit 0 INT: mux HEX_E0[5] bit 5 INT: mux LH[12] bit 1
B44 - - - INT: mux IMUX_CLB_F3[0] bit 0 INT: mux IMUX_CLK[1] bit 3 INT: mux IMUX_CLK[1] bit 1 INT: mux OMUX[9] bit 2 INT: mux OMUX[8] bit 2 INT: mux IMUX_CLB_F3[0] bit 9 INT: mux IMUX_CLB_F3[0] bit 12 INT: mux IMUX_CLB_F3[0] bit 7 INT: mux IMUX_CLB_F3[0] bit 6 INT: mux IMUX_CLB_F3[0] bit 2 INT: mux IMUX_CLB_F3[0] bit 4 INT: mux DBL_W0[5] bit 1 INT: mux DBL_E0[5] bit 1 INT: mux DBL_E0[5] bit 5 INT: mux DBL_E0[5] bit 6 INT: mux HEX_E0[5] bit 2 INT: mux HEX_E0[5] bit 1 INT: mux HEX_E0[5] bit 6 INT: mux HEX_W0[5] bit 6
B43 - - - INT: mux IMUX_CLB_G3[2] bit 0 INT: mux IMUX_CLK[0] bit 3 INT: mux IMUX_CLK[0] bit 0 INT: mux OMUX[8] bit 4 INT: mux OMUX[9] bit 4 INT: mux IMUX_CLB_G3[2] bit 9 INT: mux IMUX_CLB_G3[2] bit 12 INT: mux IMUX_CLB_G3[2] bit 7 INT: mux IMUX_CLB_G3[2] bit 6 INT: mux IMUX_CLB_G3[2] bit 2 INT: mux IMUX_CLB_G3[2] bit 4 INT: mux DBL_S0[5] bit 3 INT: mux DBL_N0[5] bit 1 INT: mux DBL_S0[5] bit 4 INT: mux DBL_S0[5] bit 7 INT: mux HEX_N0[5] bit 1 INT: mux HEX_N0[5] bit 3 INT: mux HEX_N0[5] bit 5 INT: mux LH[12] bit 0
B42 - - - - INT: mux IMUX_CLK[0] bit 6 INT: mux IMUX_CLK[0] bit 8 INT: mux OMUX[9] bit 5 INT: mux OMUX[8] bit 7 INT: mux IMUX_CLB_F3[2] bit 10 INT: mux IMUX_CLB_F3[2] bit 11 INT: mux IMUX_CLB_F3[2] bit 7 INT: mux IMUX_CLB_F3[2] bit 6 INT: mux IMUX_CLB_F3[2] bit 2 INT: mux IMUX_CLB_F3[2] bit 4 INT: mux DBL_S0[5] bit 0 INT: mux DBL_N0[5] bit 0 INT: mux DBL_N0[5] bit 7 INT: mux DBL_N0[5] bit 5 INT: mux HEX_S0[5] bit 0 INT: mux HEX_S0[5] bit 2 INT: mux HEX_S0[5] bit 4 INT: mux HEX_N0[5] bit 4
B41 - - - - INT: invert IMUX_CLK_OPTINV[0] ← IMUX_CLK[0] INT: mux IMUX_CLK[0] bit 9 INT: mux OMUX[8] bit 8 INT: mux OMUX[8] bit 6 INT: mux IMUX_CLB_G3[2] bit 11 INT: mux IMUX_CLB_G3[2] bit 10 INT: mux IMUX_CLB_G3[2] bit 8 INT: mux IMUX_CLB_G3[2] bit 5 INT: mux IMUX_CLB_G3[2] bit 1 INT: mux IMUX_CLB_G3[2] bit 3 INT: mux DBL_N0[5] bit 3 INT: mux DBL_S0[5] bit 1 INT: mux DBL_N0[5] bit 6 INT: mux DBL_N0[5] bit 4 INT: mux HEX_N0[5] bit 2 INT: mux HEX_N0[5] bit 0 INT: mux HEX_S0[5] bit 5 INT: mux LH[12] bit 2
B40 - - - INT: mux IMUX_CLB_F3[2] bit 0 INT: mux IMUX_CLK[1] bit 0 INT: mux IMUX_CLK[0] bit 7 INT: mux OMUX[8] bit 5 INT: mux OMUX[8] bit 9 INT: mux IMUX_CLB_F3[2] bit 12 INT: mux IMUX_CLB_F3[2] bit 9 INT: mux IMUX_CLB_F3[2] bit 8 INT: mux IMUX_CLB_F3[2] bit 5 INT: mux IMUX_CLB_F3[2] bit 1 INT: mux IMUX_CLB_F3[2] bit 3 INT: mux DBL_N0[5] bit 2 INT: mux DBL_S0[5] bit 2 INT: mux DBL_S0[5] bit 5 INT: mux DBL_S0[5] bit 6 INT: mux HEX_S0[5] bit 3 INT: mux HEX_S0[5] bit 1 INT: mux HEX_S0[5] bit 6 INT: mux HEX_N0[5] bit 6
B39 - - - INT: mux IMUX_CLB_F3[1] bit 0 - INT: mux IMUX_TS[0] bit 7 INT: mux OMUX[6] bit 0 INT: mux OMUX[7] bit 9 INT: mux IMUX_CLB_F3[1] bit 12 INT: mux IMUX_CLB_F3[1] bit 9 INT: mux IMUX_CLB_F3[1] bit 8 INT: mux IMUX_CLB_F3[1] bit 6 INT: mux IMUX_CLB_F3[1] bit 2 INT: mux IMUX_CLB_F3[1] bit 3 INT: mux DBL_E0[4] bit 2 INT: mux DBL_W0[4] bit 3 INT: mux DBL_E0[4] bit 5 INT: mux DBL_E0[4] bit 7 INT: mux HEX_E0[4] bit 1 INT: mux HEX_E0[4] bit 3 INT: mux HEX_E0[4] bit 5 INT: mux LH[18] bit 2
B38 - - - - INT: invert IMUX_TS_OPTINV[0] ← IMUX_TS[0] INT: mux IMUX_TS[0] bit 5 INT: mux OMUX[7] bit 8 INT: mux OMUX[7] bit 6 INT: mux IMUX_CLB_G3[1] bit 10 INT: mux IMUX_CLB_G3[1] bit 11 INT: mux IMUX_CLB_G3[1] bit 8 INT: mux IMUX_CLB_G3[1] bit 6 INT: mux IMUX_CLB_G3[1] bit 2 INT: mux IMUX_CLB_G3[1] bit 3 INT: mux DBL_E0[4] bit 0 INT: mux DBL_W0[4] bit 0 INT: mux DBL_W0[4] bit 7 INT: mux DBL_W0[4] bit 5 INT: mux HEX_W0[4] bit 1 INT: mux HEX_W0[4] bit 3 INT: mux HEX_W0[4] bit 5 INT: mux HEX_E0[4] bit 4
B37 - - - - INT: mux IMUX_TS[0] bit 8 INT: mux IMUX_TS[0] bit 6 INT: mux OMUX[7] bit 0 INT: mux OMUX[7] bit 7 INT: mux IMUX_CLB_F3[1] bit 11 INT: mux IMUX_CLB_F3[1] bit 10 INT: mux IMUX_CLB_F3[1] bit 7 INT: mux IMUX_CLB_F3[1] bit 5 INT: mux IMUX_CLB_F3[1] bit 1 INT: mux IMUX_CLB_F3[1] bit 4 INT: mux DBL_W0[4] bit 2 INT: mux DBL_E0[4] bit 3 INT: mux DBL_W0[4] bit 6 INT: mux DBL_W0[4] bit 4 INT: mux HEX_E0[4] bit 2 INT: mux HEX_E0[4] bit 0 INT: mux HEX_W0[4] bit 4 INT: mux LH[18] bit 1
B36 - - - INT: mux IMUX_CLB_G3[1] bit 0 INT: mux IMUX_TS[0] bit 0 - INT: mux OMUX[6] bit 1 INT: mux OMUX[7] bit 1 INT: mux IMUX_CLB_G3[1] bit 9 INT: mux IMUX_CLB_G3[1] bit 12 INT: mux IMUX_CLB_G3[1] bit 7 INT: mux IMUX_CLB_G3[1] bit 5 INT: mux IMUX_CLB_G3[1] bit 1 INT: mux IMUX_CLB_G3[1] bit 4 INT: mux DBL_W0[4] bit 1 INT: mux DBL_E0[4] bit 1 INT: mux DBL_E0[4] bit 4 INT: mux DBL_E0[4] bit 6 INT: mux HEX_W0[4] bit 2 INT: mux HEX_W0[4] bit 0 INT: mux HEX_W0[4] bit 6 INT: mux HEX_E0[4] bit 6
B35 - - - INT: mux IMUX_CLB_F3[3] bit 0 INT: mux IMUX_TS[1] bit 0 INT: mux IMUX_TS[1] bit 1 INT: mux OMUX[7] bit 3 INT: mux OMUX[6] bit 3 INT: mux IMUX_CLB_F3[3] bit 9 INT: mux IMUX_CLB_F3[3] bit 12 INT: mux IMUX_CLB_F3[3] bit 7 INT: mux IMUX_CLB_F3[3] bit 5 INT: mux IMUX_CLB_F3[3] bit 1 INT: mux IMUX_CLB_F3[3] bit 4 INT: mux DBL_S0[4] bit 3 INT: mux DBL_N0[4] bit 1 INT: mux DBL_S0[4] bit 4 INT: mux DBL_S0[4] bit 7 INT: mux HEX_S0[4] bit 0 INT: mux HEX_S0[4] bit 3 INT: mux HEX_S0[4] bit 4 INT: mux LH[18] bit 0
B34 - - - - INT: mux IMUX_TS[0] bit 1 INT: mux IMUX_TS[0] bit 2 INT: mux OMUX[7] bit 2 INT: mux OMUX[6] bit 2 INT: mux IMUX_CLB_G3[3] bit 11 INT: mux IMUX_CLB_G3[3] bit 10 INT: mux IMUX_CLB_G3[3] bit 7 INT: mux IMUX_CLB_G3[3] bit 5 INT: mux IMUX_CLB_G3[3] bit 1 INT: mux IMUX_CLB_G3[3] bit 4 INT: mux DBL_S0[4] bit 0 INT: mux DBL_N0[4] bit 0 INT: mux DBL_N0[4] bit 7 INT: mux DBL_N0[4] bit 4 INT: mux HEX_N0[4] bit 0 INT: mux HEX_N0[4] bit 2 INT: mux HEX_N0[4] bit 4 INT: mux HEX_S0[4] bit 5
B33 - - - - INT: mux IMUX_TS[1] bit 3 INT: mux IMUX_TS[1] bit 2 INT: mux OMUX[6] bit 4 INT: mux OMUX[7] bit 4 INT: mux IMUX_CLB_F3[3] bit 10 INT: mux IMUX_CLB_F3[3] bit 11 INT: mux IMUX_CLB_F3[3] bit 8 INT: mux IMUX_CLB_F3[3] bit 6 INT: mux IMUX_CLB_F3[3] bit 2 INT: mux IMUX_CLB_F3[3] bit 3 INT: mux DBL_N0[4] bit 3 INT: mux DBL_S0[4] bit 1 INT: mux DBL_N0[4] bit 6 INT: mux DBL_N0[4] bit 5 INT: mux HEX_S0[4] bit 2 INT: mux HEX_S0[4] bit 1 INT: mux HEX_N0[4] bit 5 INT: mux LH[6] bit 1
B32 - - - INT: mux IMUX_CLB_G3[3] bit 0 INT: mux IMUX_TS[0] bit 3 INT: mux IMUX_TS[1] bit 5 INT: mux OMUX[7] bit 5 INT: mux OMUX[6] bit 7 INT: mux IMUX_CLB_G3[3] bit 12 INT: mux IMUX_CLB_G3[3] bit 9 INT: mux IMUX_CLB_G3[3] bit 8 INT: mux IMUX_CLB_G3[3] bit 6 INT: mux IMUX_CLB_G3[3] bit 2 INT: mux IMUX_CLB_G3[3] bit 3 INT: mux DBL_N0[4] bit 2 INT: mux DBL_S0[4] bit 2 INT: mux DBL_S0[4] bit 5 INT: mux DBL_S0[4] bit 6 INT: mux HEX_N0[4] bit 3 INT: mux HEX_N0[4] bit 1 INT: mux HEX_N0[4] bit 6 INT: mux HEX_S0[4] bit 6
B31 - - - INT: mux IMUX_CLB_F2[0] bit 0 INT: mux IMUX_TS[1] bit 8 INT: mux IMUX_TS[1] bit 6 INT: mux OMUX[6] bit 8 INT: mux OMUX[6] bit 6 INT: mux IMUX_CLB_F2[0] bit 12 INT: mux IMUX_CLB_F2[0] bit 9 INT: mux IMUX_CLB_F2[0] bit 8 INT: mux IMUX_CLB_F2[0] bit 6 INT: mux IMUX_CLB_F2[0] bit 2 INT: mux IMUX_CLB_F2[0] bit 3 INT: mux DBL_E0[3] bit 2 INT: mux DBL_W0[3] bit 3 INT: mux DBL_E0[3] bit 4 INT: mux DBL_E0[3] bit 7 INT: mux HEX_W0[3] bit 1 INT: mux HEX_W0[3] bit 3 INT: mux HEX_W0[3] bit 5 INT: mux LH[6] bit 2
B30 - - - - INT: invert IMUX_TS_OPTINV[1] ← IMUX_TS[1] INT: mux IMUX_TS[0] bit 4 INT: mux OMUX[6] bit 5 INT: mux OMUX[6] bit 9 INT: mux IMUX_CLB_G2[0] bit 10 INT: mux IMUX_CLB_G2[0] bit 11 INT: mux IMUX_CLB_G2[0] bit 8 INT: mux IMUX_CLB_G2[0] bit 6 INT: mux IMUX_CLB_G2[0] bit 2 INT: mux IMUX_CLB_G2[0] bit 3 INT: mux DBL_E0[3] bit 0 INT: mux DBL_W0[3] bit 0 INT: mux DBL_W0[3] bit 7 INT: mux DBL_W0[3] bit 5 INT: mux HEX_E0[3] bit 0 INT: mux HEX_E0[3] bit 3 INT: mux HEX_E0[3] bit 4 INT: mux HEX_W0[3] bit 4
B29 - - - - INT: mux IMUX_TS[1] bit 4 INT: mux IMUX_TS[1] bit 7 INT: mux OMUX[4] bit 0 INT: mux OMUX[5] bit 9 INT: mux IMUX_CLB_F2[0] bit 11 INT: mux IMUX_CLB_F2[0] bit 10 INT: mux IMUX_CLB_F2[0] bit 7 INT: mux IMUX_CLB_F2[0] bit 5 INT: mux IMUX_CLB_F2[0] bit 1 INT: mux IMUX_CLB_F2[0] bit 4 INT: mux DBL_W0[3] bit 2 INT: mux DBL_E0[3] bit 3 INT: mux DBL_W0[3] bit 6 INT: mux DBL_W0[3] bit 4 INT: mux HEX_W0[3] bit 2 INT: mux HEX_W0[3] bit 0 INT: mux HEX_E0[3] bit 5 INT: mux LH[6] bit 0
B28 - - - INT: mux IMUX_CLB_G2[0] bit 0 INT: mux IMUX_TI[1] bit 5 INT: mux IMUX_TI[1] bit 9 INT: mux OMUX[5] bit 8 INT: mux OMUX[5] bit 6 INT: mux IMUX_CLB_G2[0] bit 9 INT: mux IMUX_CLB_G2[0] bit 12 INT: mux IMUX_CLB_G2[0] bit 7 INT: mux IMUX_CLB_G2[0] bit 5 INT: mux IMUX_CLB_G2[0] bit 1 INT: mux IMUX_CLB_G2[0] bit 4 INT: mux DBL_W0[3] bit 1 INT: mux DBL_E0[3] bit 1 INT: mux DBL_E0[3] bit 5 INT: mux DBL_E0[3] bit 6 INT: mux HEX_E0[3] bit 2 INT: mux HEX_E0[3] bit 1 INT: mux HEX_E0[3] bit 6 INT: mux HEX_W0[3] bit 6
B27 - - - INT: mux IMUX_CLB_F2[2] bit 0 INT: !invert IMUX_TI_OPTINV[1] ← IMUX_TI[1] INT: mux IMUX_TI[0] bit 5 INT: mux OMUX[5] bit 0 INT: mux OMUX[5] bit 7 INT: mux IMUX_CLB_F2[2] bit 9 INT: mux IMUX_CLB_F2[2] bit 12 INT: mux IMUX_CLB_F2[2] bit 7 INT: mux IMUX_CLB_F2[2] bit 5 INT: mux IMUX_CLB_F2[2] bit 1 INT: mux IMUX_CLB_F2[2] bit 4 INT: mux DBL_S0[3] bit 3 INT: mux DBL_N0[3] bit 1 INT: mux DBL_S0[3] bit 5 INT: mux DBL_S0[3] bit 7 INT: mux HEX_N0[3] bit 0 INT: mux HEX_N0[3] bit 3 INT: mux HEX_N0[3] bit 4 INT: mux LV[12] bit 4
B26 - - - - INT: mux IMUX_TI[1] bit 7 INT: mux IMUX_TI[1] bit 6 INT: mux OMUX[4] bit 1 INT: mux OMUX[5] bit 1 INT: mux IMUX_CLB_G2[2] bit 11 INT: mux IMUX_CLB_G2[2] bit 10 INT: mux IMUX_CLB_G2[2] bit 7 INT: mux IMUX_CLB_G2[2] bit 5 INT: mux IMUX_CLB_G2[2] bit 1 INT: mux IMUX_CLB_G2[2] bit 4 INT: mux DBL_S0[3] bit 0 INT: mux DBL_N0[3] bit 0 INT: mux DBL_N0[3] bit 7 INT: mux DBL_N0[3] bit 4 INT: mux HEX_S0[3] bit 1 INT: mux HEX_S0[3] bit 2 INT: mux HEX_S0[3] bit 5 INT: mux HEX_N0[3] bit 5
B25 - - - - INT: mux IMUX_TI[0] bit 4 INT: mux IMUX_TI[1] bit 8 INT: mux OMUX[5] bit 3 INT: mux OMUX[4] bit 3 INT: mux IMUX_CLB_F2[2] bit 10 INT: mux IMUX_CLB_F2[2] bit 11 INT: mux IMUX_CLB_F2[2] bit 8 INT: mux IMUX_CLB_F2[2] bit 6 INT: mux IMUX_CLB_F2[2] bit 2 INT: mux IMUX_CLB_F2[2] bit 3 INT: mux DBL_N0[3] bit 3 INT: mux DBL_S0[3] bit 1 INT: mux DBL_N0[3] bit 6 INT: mux DBL_N0[3] bit 5 INT: mux HEX_N0[3] bit 2 INT: mux HEX_N0[3] bit 1 INT: mux HEX_S0[3] bit 4 INT: mux LV[0] bit 3
B24 - - - INT: mux IMUX_CLB_G2[2] bit 0 INT: mux IMUX_TI[1] bit 4 INT: mux IMUX_TI[1] bit 2 INT: mux OMUX[5] bit 2 INT: mux OMUX[4] bit 2 INT: mux IMUX_CLB_G2[2] bit 12 INT: mux IMUX_CLB_G2[2] bit 9 INT: mux IMUX_CLB_G2[2] bit 8 INT: mux IMUX_CLB_G2[2] bit 6 INT: mux IMUX_CLB_G2[2] bit 2 INT: mux IMUX_CLB_G2[2] bit 3 INT: mux DBL_N0[3] bit 2 INT: mux DBL_S0[3] bit 2 INT: mux DBL_S0[3] bit 4 INT: mux DBL_S0[3] bit 6 INT: mux HEX_S0[3] bit 3 INT: mux HEX_S0[3] bit 0 INT: mux HEX_S0[3] bit 6 INT: mux HEX_N0[3] bit 6
B23 - - - INT: mux IMUX_CLB_BY[0] bit 9 INT: mux IMUX_TI[0] bit 3 INT: mux IMUX_TI[0] bit 2 INT: mux OMUX[4] bit 4 INT: mux OMUX[5] bit 4 - INT: mux IMUX_CLB_BY[0] bit 11 INT: mux IMUX_CLB_BY[2] bit 7 INT: mux IMUX_CLB_BY[2] bit 5 INT: mux IMUX_CLB_BY[2] bit 1 INT: mux IMUX_CLB_BY[2] bit 2 INT: mux DBL_E0[2] bit 4 INT: mux DBL_W0[2] bit 7 INT: mux DBL_E0[2] bit 1 INT: mux DBL_E0[2] bit 3 INT: mux HEX_E0[2] bit 1 INT: mux HEX_E0[2] bit 3 INT: mux HEX_E0[2] bit 5 INT: mux LV[12] bit 3
B22 - - - - INT: mux IMUX_TI[1] bit 1 INT: mux IMUX_TI[1] bit 3 INT: mux OMUX[5] bit 5 INT: mux OMUX[4] bit 7 INT: mux IMUX_CLB_BY[2] bit 9 INT: mux IMUX_CLB_BY[2] bit 11 INT: mux IMUX_CLB_BY[0] bit 7 INT: mux IMUX_CLB_BY[0] bit 5 INT: mux IMUX_CLB_BY[0] bit 1 INT: mux IMUX_CLB_BY[0] bit 2 INT: mux DBL_E0[2] bit 5 INT: mux DBL_W0[2] bit 5 INT: mux DBL_W0[2] bit 3 INT: mux DBL_W0[2] bit 1 INT: mux HEX_W0[2] bit 1 INT: mux HEX_W0[2] bit 3 INT: mux HEX_W0[2] bit 6 INT: mux HEX_E0[2] bit 6
B21 - - - - INT: mux IMUX_TI[0] bit 1 INT: mux IMUX_TI[0] bit 0 INT: mux OMUX[4] bit 8 INT: mux OMUX[4] bit 6 INT: mux IMUX_CLB_BY[2] bit 8 INT: mux IMUX_CLB_BY[2] bit 10 INT: mux IMUX_CLB_BY[2] bit 6 INT: mux IMUX_CLB_BY[2] bit 4 INT: mux IMUX_CLB_BY[2] bit 0 INT: mux IMUX_CLB_BY[2] bit 3 INT: mux DBL_W0[2] bit 4 INT: mux DBL_E0[2] bit 7 INT: mux DBL_W0[2] bit 2 INT: mux DBL_W0[2] bit 0 INT: mux HEX_E0[2] bit 2 INT: mux HEX_E0[2] bit 0 INT: mux HEX_W0[2] bit 5 INT: mux LV[0] bit 2
B20 - - - INT: mux IMUX_CLB_BY[0] bit 8 INT: mux IMUX_TI[0] bit 7 INT: mux IMUX_TI[0] bit 6 INT: mux OMUX[4] bit 5 INT: mux OMUX[4] bit 9 - INT: mux IMUX_CLB_BY[0] bit 10 INT: mux IMUX_CLB_BY[0] bit 6 INT: mux IMUX_CLB_BY[0] bit 4 INT: mux IMUX_CLB_BY[0] bit 0 INT: mux IMUX_CLB_BY[0] bit 3 INT: mux DBL_W0[2] bit 6 INT: mux DBL_E0[2] bit 6 INT: mux DBL_E0[2] bit 0 INT: mux DBL_E0[2] bit 2 INT: mux HEX_W0[2] bit 2 INT: mux HEX_W0[2] bit 0 INT: mux HEX_W0[2] bit 4 INT: mux HEX_E0[2] bit 4
B19 - - - INT: mux IMUX_CLB_BX[0] bit 9 INT: !invert IMUX_TI_OPTINV[0] ← IMUX_TI[0] INT: mux IMUX_TI[0] bit 8 INT: mux OMUX[2] bit 0 INT: mux OMUX[3] bit 9 - INT: mux IMUX_CLB_BX[0] bit 10 INT: mux IMUX_CLB_BX[0] bit 6 INT: mux IMUX_CLB_BX[0] bit 5 INT: mux IMUX_CLB_BX[0] bit 2 INT: mux IMUX_CLB_BX[0] bit 1 INT: mux DBL_S0[2] bit 4 INT: mux DBL_N0[2] bit 6 INT: mux DBL_S0[2] bit 0 INT: mux DBL_S0[2] bit 3 INT: mux HEX_S0[2] bit 0 INT: mux HEX_S0[2] bit 3 INT: mux HEX_S0[2] bit 5 INT: mux LV[0] bit 4
B18 - - - - INT: mux IMUX_TI[1] bit 0 INT: mux IMUX_TI[0] bit 9 INT: mux OMUX[3] bit 8 INT: mux OMUX[3] bit 6 INT: mux IMUX_CLB_BX[2] bit 9 INT: mux IMUX_CLB_BX[2] bit 10 INT: mux IMUX_CLB_BX[2] bit 6 INT: mux IMUX_CLB_BX[2] bit 5 INT: mux IMUX_CLB_BX[2] bit 2 INT: mux IMUX_CLB_BX[2] bit 1 INT: mux DBL_S0[2] bit 5 INT: mux DBL_N0[2] bit 5 INT: mux DBL_N0[2] bit 3 INT: mux DBL_N0[2] bit 0 INT: mux HEX_N0[2] bit 1 INT: mux HEX_N0[2] bit 2 INT: mux HEX_N0[2] bit 4 INT: mux HEX_S0[2] bit 4
B17 - - - - INT: mux IMUX_SR[3] bit 5 INT: mux IMUX_SR[1] bit 1 INT: mux OMUX[3] bit 0 INT: mux OMUX[3] bit 7 INT: mux IMUX_CLB_BX[2] bit 8 INT: mux IMUX_CLB_BX[2] bit 11 INT: mux IMUX_CLB_BX[0] bit 7 INT: mux IMUX_CLB_BX[0] bit 4 INT: mux IMUX_CLB_BX[0] bit 0 INT: mux IMUX_CLB_BX[0] bit 3 INT: mux DBL_N0[2] bit 4 INT: mux DBL_S0[2] bit 6 INT: mux DBL_N0[2] bit 2 INT: mux DBL_N0[2] bit 1 INT: mux HEX_S0[2] bit 2 INT: mux HEX_S0[2] bit 1 INT: mux HEX_N0[2] bit 5 INT: mux LV[12] bit 2
B16 - - - INT: mux IMUX_CLB_BX[0] bit 8 INT: !invert IMUX_SR_OPTINV[1] ← IMUX_SR[1] INT: mux IMUX_SR[1] bit 3 INT: mux OMUX[2] bit 1 INT: mux OMUX[3] bit 1 - INT: mux IMUX_CLB_BX[0] bit 11 INT: mux IMUX_CLB_BX[2] bit 7 INT: mux IMUX_CLB_BX[2] bit 4 INT: mux IMUX_CLB_BX[2] bit 0 INT: mux IMUX_CLB_BX[2] bit 3 INT: mux DBL_N0[2] bit 7 INT: mux DBL_S0[2] bit 7 INT: mux DBL_S0[2] bit 1 INT: mux DBL_S0[2] bit 2 INT: mux HEX_N0[2] bit 3 INT: mux HEX_N0[2] bit 0 INT: mux HEX_N0[2] bit 6 INT: mux HEX_S0[2] bit 6
B15 - - - INT: mux IMUX_CLB_G1[1] bit 0 INT: mux IMUX_SR[1] bit 0 INT: mux IMUX_SR[1] bit 2 INT: mux OMUX[3] bit 3 INT: mux OMUX[2] bit 3 INT: mux IMUX_CLB_G1[1] bit 12 INT: mux IMUX_CLB_G1[1] bit 9 INT: mux IMUX_CLB_G1[1] bit 8 INT: mux IMUX_CLB_G1[1] bit 5 INT: mux IMUX_CLB_G1[1] bit 1 INT: mux IMUX_CLB_G1[1] bit 4 INT: mux DBL_E0[1] bit 2 INT: mux DBL_W0[1] bit 3 INT: mux DBL_E0[1] bit 4 INT: mux DBL_E0[1] bit 7 INT: mux HEX_W0[1] bit 1 INT: mux HEX_W0[1] bit 2 INT: mux HEX_W0[1] bit 5 INT: mux LV[12] bit 0
B14 - - - - INT: mux IMUX_SR[1] bit 4 INT: mux IMUX_SR[1] bit 5 INT: mux OMUX[3] bit 2 INT: mux OMUX[2] bit 2 INT: mux IMUX_CLB_F1[1] bit 10 INT: mux IMUX_CLB_F1[1] bit 11 INT: mux IMUX_CLB_F1[1] bit 8 INT: mux IMUX_CLB_F1[1] bit 5 INT: mux IMUX_CLB_F1[1] bit 1 INT: mux IMUX_CLB_F1[1] bit 4 INT: mux DBL_E0[1] bit 0 INT: mux DBL_W0[1] bit 0 INT: mux DBL_W0[1] bit 6 INT: mux DBL_W0[1] bit 5 INT: mux HEX_E0[1] bit 0 INT: mux HEX_E0[1] bit 3 INT: mux HEX_E0[1] bit 4 INT: mux HEX_W0[1] bit 4
B13 - - - - INT: mux IMUX_SR[3] bit 4 INT: mux IMUX_SR[3] bit 7 INT: mux OMUX[2] bit 4 INT: mux OMUX[3] bit 4 INT: mux IMUX_CLB_G1[1] bit 11 INT: mux IMUX_CLB_G1[1] bit 10 INT: mux IMUX_CLB_G1[1] bit 7 INT: mux IMUX_CLB_G1[1] bit 6 INT: mux IMUX_CLB_G1[1] bit 3 INT: mux IMUX_CLB_G1[1] bit 2 INT: mux DBL_W0[1] bit 2 INT: mux DBL_E0[1] bit 3 INT: mux DBL_W0[1] bit 7 INT: mux DBL_W0[1] bit 4 INT: mux HEX_W0[1] bit 3 INT: mux HEX_W0[1] bit 0 INT: mux HEX_E0[1] bit 5 INT: mux LV[12] bit 6
B12 - - - INT: mux IMUX_CLB_F1[1] bit 0 INT: mux IMUX_SR[1] bit 7 INT: mux IMUX_SR[1] bit 6 INT: mux OMUX[3] bit 5 INT: mux OMUX[2] bit 7 INT: mux IMUX_CLB_F1[1] bit 9 INT: mux IMUX_CLB_F1[1] bit 12 INT: mux IMUX_CLB_F1[1] bit 7 INT: mux IMUX_CLB_F1[1] bit 6 INT: mux IMUX_CLB_F1[1] bit 3 INT: mux IMUX_CLB_F1[1] bit 2 INT: mux DBL_W0[1] bit 1 INT: mux DBL_E0[1] bit 1 INT: mux DBL_E0[1] bit 5 INT: mux DBL_E0[1] bit 6 INT: mux HEX_E0[1] bit 2 INT: mux HEX_E0[1] bit 1 INT: mux HEX_E0[1] bit 6 INT: mux HEX_W0[1] bit 6
B11 - - - INT: mux IMUX_CLB_G1[3] bit 0 INT: mux IMUX_SR[3] bit 0 INT: mux IMUX_SR[3] bit 1 INT: mux OMUX[2] bit 8 INT: mux OMUX[2] bit 6 INT: mux IMUX_CLB_G1[3] bit 9 INT: mux IMUX_CLB_G1[3] bit 12 INT: mux IMUX_CLB_G1[3] bit 7 INT: mux IMUX_CLB_G1[3] bit 6 INT: mux IMUX_CLB_G1[3] bit 3 INT: mux IMUX_CLB_G1[3] bit 2 INT: mux DBL_S0[1] bit 3 INT: mux DBL_N0[1] bit 1 INT: mux DBL_S0[1] bit 4 INT: mux DBL_S0[1] bit 7 INT: mux HEX_N0[1] bit 0 INT: mux HEX_N0[1] bit 3 INT: mux HEX_N0[1] bit 4 INT: mux LV[0] bit 1
B10 - - - - INT: !invert IMUX_SR_OPTINV[3] ← IMUX_SR[3] INT: mux IMUX_SR[3] bit 3 INT: mux OMUX[2] bit 5 INT: mux OMUX[2] bit 9 INT: mux IMUX_CLB_F1[3] bit 11 INT: mux IMUX_CLB_F1[3] bit 10 INT: mux IMUX_CLB_F1[3] bit 7 INT: mux IMUX_CLB_F1[3] bit 6 INT: mux IMUX_CLB_F1[3] bit 3 INT: mux IMUX_CLB_F1[3] bit 2 INT: mux DBL_S0[1] bit 0 INT: mux DBL_N0[1] bit 0 INT: mux DBL_N0[1] bit 7 INT: mux DBL_N0[1] bit 4 INT: mux HEX_S0[1] bit 0 INT: mux HEX_S0[1] bit 2 INT: mux HEX_S0[1] bit 4 INT: mux HEX_N0[1] bit 5
B9 - - - - INT: mux IMUX_SR[3] bit 6 INT: mux IMUX_SR[3] bit 2 INT: mux OMUX[0] bit 0 INT: mux OMUX[1] bit 9 INT: mux IMUX_CLB_G1[3] bit 10 INT: mux IMUX_CLB_G1[3] bit 11 INT: mux IMUX_CLB_G1[3] bit 8 INT: mux IMUX_CLB_G1[3] bit 5 INT: mux IMUX_CLB_G1[3] bit 1 INT: mux IMUX_CLB_G1[3] bit 4 INT: mux DBL_N0[1] bit 3 INT: mux DBL_S0[1] bit 1 INT: mux DBL_N0[1] bit 6 INT: mux DBL_N0[1] bit 5 INT: mux HEX_N0[1] bit 2 INT: mux HEX_N0[1] bit 1 INT: mux HEX_S0[1] bit 5 INT: mux LV[0] bit 5
B8 - - - INT: mux IMUX_CLB_F1[3] bit 0 INT: mux IMUX_SR[2] bit 5 INT: mux IMUX_SR[2] bit 2 INT: mux OMUX[1] bit 8 INT: mux OMUX[1] bit 6 INT: mux IMUX_CLB_F1[3] bit 12 INT: mux IMUX_CLB_F1[3] bit 9 INT: mux IMUX_CLB_F1[3] bit 8 INT: mux IMUX_CLB_F1[3] bit 5 INT: mux IMUX_CLB_F1[3] bit 1 INT: mux IMUX_CLB_F1[3] bit 4 INT: mux DBL_N0[1] bit 2 INT: mux DBL_S0[1] bit 2 INT: mux DBL_S0[1] bit 5 INT: mux DBL_S0[1] bit 6 INT: mux HEX_S0[1] bit 3 INT: mux HEX_S0[1] bit 1 INT: mux HEX_S0[1] bit 6 INT: mux HEX_N0[1] bit 6
B7 - - - INT: mux IMUX_CLB_G4[0] bit 0 INT: !invert IMUX_SR_OPTINV[2] ← IMUX_SR[2] INT: mux IMUX_SR[2] bit 3 INT: mux OMUX[1] bit 0 INT: mux OMUX[1] bit 7 INT: mux IMUX_CLB_G4[0] bit 12 INT: mux IMUX_CLB_G4[0] bit 9 INT: mux IMUX_CLB_G4[0] bit 8 INT: mux IMUX_CLB_G4[0] bit 5 INT: mux IMUX_CLB_G4[0] bit 1 INT: mux IMUX_CLB_G4[0] bit 4 INT: mux DBL_E0[0] bit 2 INT: mux DBL_W0[0] bit 3 INT: mux DBL_E0[0] bit 4 INT: mux DBL_E0[0] bit 7 INT: mux HEX_E0[0] bit 0 INT: mux HEX_E0[0] bit 3 INT: mux HEX_E0[0] bit 4 INT: mux LV[0] bit 6
B6 - - - - INT: mux IMUX_SR[2] bit 1 INT: mux IMUX_SR[2] bit 0 INT: mux OMUX[0] bit 1 INT: mux OMUX[1] bit 1 INT: mux IMUX_CLB_F4[0] bit 10 INT: mux IMUX_CLB_F4[0] bit 11 INT: mux IMUX_CLB_F4[0] bit 8 INT: mux IMUX_CLB_F4[0] bit 5 INT: mux IMUX_CLB_F4[0] bit 1 INT: mux IMUX_CLB_F4[0] bit 4 INT: mux DBL_E0[0] bit 0 INT: mux DBL_W0[0] bit 0 INT: mux DBL_W0[0] bit 6 INT: mux DBL_W0[0] bit 5 INT: mux HEX_W0[0] bit 1 INT: mux HEX_W0[0] bit 2 INT: mux HEX_W0[0] bit 5 INT: mux HEX_E0[0] bit 5
B5 - - - - INT: mux IMUX_SR[0] bit 4 INT: mux IMUX_SR[0] bit 5 INT: mux OMUX[1] bit 3 INT: mux OMUX[0] bit 3 INT: mux IMUX_CLB_G4[0] bit 11 INT: mux IMUX_CLB_G4[0] bit 10 INT: mux IMUX_CLB_G4[0] bit 7 INT: mux IMUX_CLB_G4[0] bit 6 INT: mux IMUX_CLB_G4[0] bit 3 INT: mux IMUX_CLB_G4[0] bit 2 INT: mux DBL_W0[0] bit 2 INT: mux DBL_E0[0] bit 3 INT: mux DBL_W0[0] bit 7 INT: mux DBL_W0[0] bit 4 INT: mux HEX_E0[0] bit 2 INT: mux HEX_E0[0] bit 1 INT: mux HEX_W0[0] bit 4 INT: mux LV[0] bit 0
B4 - - - INT: mux IMUX_CLB_F4[0] bit 0 INT: mux IMUX_SR[2] bit 6 INT: mux IMUX_SR[2] bit 4 INT: mux OMUX[1] bit 2 INT: mux OMUX[0] bit 2 INT: mux IMUX_CLB_F4[0] bit 9 INT: mux IMUX_CLB_F4[0] bit 12 INT: mux IMUX_CLB_F4[0] bit 7 INT: mux IMUX_CLB_F4[0] bit 6 INT: mux IMUX_CLB_F4[0] bit 3 INT: mux IMUX_CLB_F4[0] bit 2 INT: mux DBL_W0[0] bit 1 INT: mux DBL_E0[0] bit 1 INT: mux DBL_E0[0] bit 5 INT: mux DBL_E0[0] bit 6 INT: mux HEX_W0[0] bit 3 INT: mux HEX_W0[0] bit 0 INT: mux HEX_W0[0] bit 6 INT: mux HEX_E0[0] bit 6
B3 - - - INT: mux IMUX_CLB_G4[2] bit 0 INT: mux IMUX_SR[0] bit 6 INT: mux IMUX_SR[0] bit 7 INT: mux OMUX[0] bit 4 INT: mux OMUX[1] bit 4 INT: mux IMUX_CLB_G4[2] bit 9 INT: mux IMUX_CLB_G4[2] bit 12 INT: mux IMUX_CLB_G4[2] bit 7 INT: mux IMUX_CLB_G4[2] bit 6 INT: mux IMUX_CLB_G4[2] bit 3 INT: mux IMUX_CLB_G4[2] bit 2 INT: mux DBL_S0[0] bit 4 INT: mux DBL_N0[0] bit 6 INT: mux DBL_S0[0] bit 1 INT: mux DBL_S0[0] bit 3 INT: mux HEX_S0[0] bit 1 INT: mux HEX_S0[0] bit 3 INT: mux HEX_S0[0] bit 6 INT: mux LV[12] bit 1
B2 - - - - INT: mux IMUX_SR[0] bit 1 INT: mux IMUX_SR[0] bit 2 INT: mux OMUX[1] bit 5 INT: mux OMUX[0] bit 7 INT: mux IMUX_CLB_F4[2] bit 11 INT: mux IMUX_CLB_F4[2] bit 10 INT: mux IMUX_CLB_F4[2] bit 7 INT: mux IMUX_CLB_F4[2] bit 6 INT: mux IMUX_CLB_F4[2] bit 3 INT: mux IMUX_CLB_F4[2] bit 2 INT: mux DBL_S0[0] bit 5 INT: mux DBL_N0[0] bit 5 INT: mux DBL_N0[0] bit 3 INT: mux DBL_N0[0] bit 1 INT: mux HEX_N0[0] bit 1 INT: mux HEX_N0[0] bit 2 INT: mux HEX_N0[0] bit 5 INT: mux HEX_S0[0] bit 5
B1 - - - - INT: !invert IMUX_SR_OPTINV[0] ← IMUX_SR[0] INT: mux IMUX_SR[0] bit 3 INT: mux OMUX[0] bit 8 INT: mux OMUX[0] bit 6 INT: mux IMUX_CLB_G4[2] bit 10 INT: mux IMUX_CLB_G4[2] bit 11 INT: mux IMUX_CLB_G4[2] bit 8 INT: mux IMUX_CLB_G4[2] bit 5 INT: mux IMUX_CLB_G4[2] bit 1 INT: mux IMUX_CLB_G4[2] bit 4 INT: mux DBL_N0[0] bit 4 INT: mux DBL_S0[0] bit 6 INT: mux DBL_N0[0] bit 2 INT: mux DBL_N0[0] bit 0 INT: mux HEX_S0[0] bit 2 INT: mux HEX_S0[0] bit 0 INT: mux HEX_N0[0] bit 6 INT: mux LV[12] bit 5
B0 - - - INT: mux IMUX_CLB_F4[2] bit 0 INT: mux IMUX_SR[2] bit 7 INT: mux IMUX_SR[0] bit 0 INT: mux OMUX[0] bit 5 INT: mux OMUX[0] bit 9 INT: mux IMUX_CLB_F4[2] bit 12 INT: mux IMUX_CLB_F4[2] bit 9 INT: mux IMUX_CLB_F4[2] bit 8 INT: mux IMUX_CLB_F4[2] bit 5 INT: mux IMUX_CLB_F4[2] bit 1 INT: mux IMUX_CLB_F4[2] bit 4 INT: mux DBL_N0[0] bit 7 INT: mux DBL_S0[0] bit 7 INT: mux DBL_S0[0] bit 0 INT: mux DBL_S0[0] bit 2 INT: mux HEX_N0[0] bit 3 INT: mux HEX_N0[0] bit 0 INT: mux HEX_N0[0] bit 4 INT: mux HEX_S0[0] bit 4

INT_BRAM

Used with BRAM tiles.

Tile INT_BRAM

Cells: 1

Switchbox INT

virtex2 INT_BRAM switchbox INT programmable inverters
DestinationSourceBit
IMUX_CLK_OPTINV[1]IMUX_CLK[1]MAIN[4][49]
IMUX_CLK_OPTINV[2]IMUX_CLK[2]MAIN[4][52]
IMUX_CLK_OPTINV[3]IMUX_CLK[3]MAIN[4][60]
IMUX_SR_OPTINV[0]IMUX_SR[0]!MAIN[4][1]
IMUX_SR_OPTINV[1]IMUX_SR[1]!MAIN[4][16]
IMUX_SR_OPTINV[2]IMUX_SR[2]!MAIN[4][7]
IMUX_CE_OPTINV[1]IMUX_CE[1]!MAIN[4][69]
IMUX_CE_OPTINV[2]IMUX_CE[2]!MAIN[4][72]
IMUX_CE_OPTINV[3]IMUX_CE[3]!MAIN[4][78]
IMUX_TS_OPTINV[0]IMUX_TS[0]MAIN[4][38]
IMUX_TS_OPTINV[1]IMUX_TS[1]MAIN[4][30]
virtex2 INT_BRAM switchbox INT muxes OMUX[0]
BitsDestination
MAIN[7][0]MAIN[6][1]MAIN[7][2]MAIN[7][1]MAIN[6][3]MAIN[6][0]MAIN[6][6]MAIN[6][9]MAIN[7][5]MAIN[7][4]OMUX[0]
Source
0000000000off
0001000001OUT_FAN[0]
0001000010OUT_FAN[1]
0001000100OUT_FAN[2]
0001001000OUT_FAN[3]
0001010000OUT_FAN[4]
0001100000OUT_FAN[5]
0010000001OUT_HALF0[9]
0010000010OUT_HALF0[8]
0010000100OUT_FAN[7]
0010001000OUT_FAN[6]
0010010000OUT_HALF0[11]
0010100000OUT_HALF0[10]
0100000001OUT_SEC[15]
0100000100OUT_SEC[12]
0100001000OUT_SEC[13]
0100010000OUT_SEC[17]
0100100000OUT_SEC[16]
1000000001OUT_SEC[21]
1000000010OUT_SEC[20]
1000000100OUT_SEC[18]
1000001000OUT_SEC[19]
1000010000OUT_SEC[23]
1000100000OUT_SEC[22]
virtex2 INT_BRAM switchbox INT muxes OMUX[1]
BitsDestination
MAIN[7][9]MAIN[6][8]MAIN[7][7]MAIN[7][8]MAIN[7][3]MAIN[6][2]MAIN[7][6]MAIN[6][7]MAIN[6][5]MAIN[6][4]OMUX[1]
Source
0000000000off
0001000001OUT_FAN[0]
0001000010OUT_FAN[1]
0001000100OUT_FAN[2]
0001001000OUT_FAN[3]
0001010000OUT_FAN[4]
0001100000OUT_FAN[5]
0010000001OUT_HALF0[9]
0010000010OUT_HALF0[8]
0010000100OUT_FAN[7]
0010001000OUT_FAN[6]
0010010000OUT_HALF0[11]
0010100000OUT_HALF0[10]
0100000001OUT_SEC[15]
0100000100OUT_SEC[12]
0100001000OUT_SEC[13]
0100010000OUT_SEC[17]
0100100000OUT_SEC[16]
1000000001OUT_SEC[21]
1000000010OUT_SEC[20]
1000000100OUT_SEC[18]
1000001000OUT_SEC[19]
1000010000OUT_SEC[23]
1000100000OUT_SEC[22]
virtex2 INT_BRAM switchbox INT muxes OMUX[2]
BitsDestination
MAIN[7][10]MAIN[6][11]MAIN[7][12]MAIN[7][11]MAIN[6][13]MAIN[6][10]MAIN[6][16]MAIN[6][19]MAIN[7][15]MAIN[7][14]OMUX[2]
Source
0000000000off
0001000001OUT_FAN[0]
0001000010OUT_FAN[1]
0001000100OUT_FAN[2]
0001001000OUT_FAN[3]
0001010000OUT_FAN[4]
0001100000OUT_FAN[5]
0010000001OUT_HALF0[9]
0010000010OUT_HALF0[8]
0010000100OUT_FAN[7]
0010001000OUT_FAN[6]
0010010000OUT_HALF0[11]
0010100000OUT_HALF0[10]
0100000001OUT_SEC[15]
0100000100OUT_SEC[12]
0100001000OUT_SEC[13]
0100010000OUT_SEC[17]
0100100000OUT_SEC[16]
1000000001OUT_SEC[21]
1000000010OUT_SEC[20]
1000000100OUT_SEC[18]
1000001000OUT_SEC[19]
1000010000OUT_SEC[23]
1000100000OUT_SEC[22]
virtex2 INT_BRAM switchbox INT muxes OMUX[3]
BitsDestination
MAIN[7][19]MAIN[6][18]MAIN[7][17]MAIN[7][18]MAIN[7][13]MAIN[6][12]MAIN[7][16]MAIN[6][17]MAIN[6][15]MAIN[6][14]OMUX[3]
Source
0000000000off
0001000001OUT_FAN[0]
0001000010OUT_FAN[1]
0001000100OUT_FAN[2]
0001001000OUT_FAN[3]
0001010000OUT_FAN[4]
0001100000OUT_FAN[5]
0010000001OUT_HALF0[9]
0010000010OUT_HALF0[8]
0010000100OUT_FAN[7]
0010001000OUT_FAN[6]
0010010000OUT_HALF0[11]
0010100000OUT_HALF0[10]
0100000001OUT_SEC[15]
0100000100OUT_SEC[12]
0100001000OUT_SEC[13]
0100010000OUT_SEC[17]
0100100000OUT_SEC[16]
1000000001OUT_SEC[21]
1000000010OUT_SEC[20]
1000000100OUT_SEC[18]
1000001000OUT_SEC[19]
1000010000OUT_SEC[23]
1000100000OUT_SEC[22]
virtex2 INT_BRAM switchbox INT muxes OMUX[4]
BitsDestination
MAIN[7][20]MAIN[6][21]MAIN[7][22]MAIN[7][21]MAIN[6][23]MAIN[6][20]MAIN[6][26]MAIN[6][29]MAIN[7][25]MAIN[7][24]OMUX[4]
Source
0000000000off
0001000001OUT_FAN[0]
0001000010OUT_FAN[1]
0001000100OUT_FAN[2]
0001001000OUT_FAN[3]
0001010000OUT_FAN[4]
0001100000OUT_FAN[5]
0010000001OUT_HALF0[9]
0010000010OUT_HALF0[8]
0010000100OUT_FAN[7]
0010001000OUT_FAN[6]
0010010000OUT_HALF0[11]
0010100000OUT_HALF0[10]
0100000001OUT_SEC[15]
0100000100OUT_SEC[12]
0100001000OUT_SEC[13]
0100010000OUT_SEC[17]
0100100000OUT_SEC[16]
1000000001OUT_SEC[21]
1000000010OUT_SEC[20]
1000000100OUT_SEC[18]
1000001000OUT_SEC[19]
1000010000OUT_SEC[23]
1000100000OUT_SEC[22]
virtex2 INT_BRAM switchbox INT muxes OMUX[5]
BitsDestination
MAIN[7][29]MAIN[6][28]MAIN[7][27]MAIN[7][28]MAIN[7][23]MAIN[6][22]MAIN[7][26]MAIN[6][27]MAIN[6][25]MAIN[6][24]OMUX[5]
Source
0000000000off
0001000001OUT_FAN[0]
0001000010OUT_FAN[1]
0001000100OUT_FAN[2]
0001001000OUT_FAN[3]
0001010000OUT_FAN[4]
0001100000OUT_FAN[5]
0010000001OUT_HALF0[9]
0010000010OUT_HALF0[8]
0010000100OUT_FAN[7]
0010001000OUT_FAN[6]
0010010000OUT_HALF0[11]
0010100000OUT_HALF0[10]
0100000001OUT_SEC[15]
0100000100OUT_SEC[12]
0100001000OUT_SEC[13]
0100010000OUT_SEC[17]
0100100000OUT_SEC[16]
1000000001OUT_SEC[21]
1000000010OUT_SEC[20]
1000000100OUT_SEC[18]
1000001000OUT_SEC[19]
1000010000OUT_SEC[23]
1000100000OUT_SEC[22]
virtex2 INT_BRAM switchbox INT muxes OMUX[6]
BitsDestination
MAIN[7][30]MAIN[6][31]MAIN[7][32]MAIN[7][31]MAIN[6][33]MAIN[6][30]MAIN[6][36]MAIN[6][39]MAIN[7][35]MAIN[7][34]OMUX[6]
Source
0000000000off
0001000001OUT_FAN[0]
0001000010OUT_FAN[1]
0001000100OUT_FAN[2]
0001001000OUT_FAN[3]
0001010000OUT_FAN[4]
0001100000OUT_FAN[5]
0010000001OUT_HALF0[9]
0010000010OUT_HALF0[8]
0010000100OUT_FAN[7]
0010001000OUT_FAN[6]
0010010000OUT_HALF0[11]
0010100000OUT_HALF0[10]
0100000001OUT_SEC[15]
0100000100OUT_SEC[12]
0100001000OUT_SEC[13]
0100010000OUT_SEC[17]
0100100000OUT_SEC[16]
1000000001OUT_SEC[21]
1000000010OUT_SEC[20]
1000000100OUT_SEC[18]
1000001000OUT_SEC[19]
1000010000OUT_SEC[23]
1000100000OUT_SEC[22]
virtex2 INT_BRAM switchbox INT muxes OMUX[7]
BitsDestination
MAIN[7][39]MAIN[6][38]MAIN[7][37]MAIN[7][38]MAIN[7][33]MAIN[6][32]MAIN[7][36]MAIN[6][37]MAIN[6][35]MAIN[6][34]OMUX[7]
Source
0000000000off
0001000001OUT_FAN[0]
0001000010OUT_FAN[1]
0001000100OUT_FAN[2]
0001001000OUT_FAN[3]
0001010000OUT_FAN[4]
0001100000OUT_FAN[5]
0010000001OUT_HALF0[9]
0010000010OUT_HALF0[8]
0010000100OUT_FAN[7]
0010001000OUT_FAN[6]
0010010000OUT_HALF0[11]
0010100000OUT_HALF0[10]
0100000001OUT_SEC[15]
0100000100OUT_SEC[12]
0100001000OUT_SEC[13]
0100010000OUT_SEC[17]
0100100000OUT_SEC[16]
1000000001OUT_SEC[21]
1000000010OUT_SEC[20]
1000000100OUT_SEC[18]
1000001000OUT_SEC[19]
1000010000OUT_SEC[23]
1000100000OUT_SEC[22]
virtex2 INT_BRAM switchbox INT muxes OMUX[8]
BitsDestination
MAIN[7][40]MAIN[6][41]MAIN[7][42]MAIN[7][41]MAIN[6][43]MAIN[6][40]MAIN[6][46]MAIN[6][49]MAIN[7][45]MAIN[7][44]OMUX[8]
Source
0000000000off
0001000001OUT_FAN[0]
0001000010OUT_FAN[1]
0001000100OUT_FAN[2]
0001001000OUT_FAN[3]
0001010000OUT_FAN[4]
0001100000OUT_FAN[5]
0010000001OUT_HALF1[9]
0010000010OUT_HALF1[8]
0010000100OUT_FAN[7]
0010001000OUT_FAN[6]
0010010000OUT_HALF1[11]
0010100000OUT_HALF1[10]
0100000001OUT_SEC[15]
0100000100OUT_SEC[12]
0100001000OUT_SEC[13]
0100010000OUT_SEC[17]
0100100000OUT_SEC[16]
1000000001OUT_SEC[21]
1000000010OUT_SEC[20]
1000000100OUT_SEC[18]
1000001000OUT_SEC[19]
1000010000OUT_SEC[23]
1000100000OUT_SEC[22]
virtex2 INT_BRAM switchbox INT muxes OMUX[9]
BitsDestination
MAIN[7][49]MAIN[6][48]MAIN[7][47]MAIN[7][48]MAIN[7][43]MAIN[6][42]MAIN[7][46]MAIN[6][47]MAIN[6][45]MAIN[6][44]OMUX[9]
Source
0000000000off
0001000001OUT_FAN[0]
0001000010OUT_FAN[1]
0001000100OUT_FAN[2]
0001001000OUT_FAN[3]
0001010000OUT_FAN[4]
0001100000OUT_FAN[5]
0010000001OUT_HALF1[9]
0010000010OUT_HALF1[8]
0010000100OUT_FAN[7]
0010001000OUT_FAN[6]
0010010000OUT_HALF1[11]
0010100000OUT_HALF1[10]
0100000001OUT_SEC[15]
0100000100OUT_SEC[12]
0100001000OUT_SEC[13]
0100010000OUT_SEC[17]
0100100000OUT_SEC[16]
1000000001OUT_SEC[21]
1000000010OUT_SEC[20]
1000000100OUT_SEC[18]
1000001000OUT_SEC[19]
1000010000OUT_SEC[23]
1000100000OUT_SEC[22]
virtex2 INT_BRAM switchbox INT muxes OMUX[10]
BitsDestination
MAIN[7][50]MAIN[6][51]MAIN[7][52]MAIN[7][51]MAIN[6][53]MAIN[6][50]MAIN[6][56]MAIN[6][59]MAIN[7][55]MAIN[7][54]OMUX[10]
Source
0000000000off
0001000001OUT_FAN[0]
0001000010OUT_FAN[1]
0001000100OUT_FAN[2]
0001001000OUT_FAN[3]
0001010000OUT_FAN[4]
0001100000OUT_FAN[5]
0010000001OUT_HALF1[9]
0010000010OUT_HALF1[8]
0010000100OUT_FAN[7]
0010001000OUT_FAN[6]
0010010000OUT_HALF1[11]
0010100000OUT_HALF1[10]
0100000001OUT_SEC[15]
0100000100OUT_SEC[12]
0100001000OUT_SEC[13]
0100010000OUT_SEC[17]
0100100000OUT_SEC[16]
1000000001OUT_SEC[21]
1000000010OUT_SEC[20]
1000000100OUT_SEC[18]
1000001000OUT_SEC[19]
1000010000OUT_SEC[23]
1000100000OUT_SEC[22]
virtex2 INT_BRAM switchbox INT muxes OMUX[11]
BitsDestination
MAIN[7][59]MAIN[6][58]MAIN[7][57]MAIN[7][58]MAIN[7][53]MAIN[6][52]MAIN[7][56]MAIN[6][57]MAIN[6][55]MAIN[6][54]OMUX[11]
Source
0000000000off
0001000001OUT_FAN[0]
0001000010OUT_FAN[1]
0001000100OUT_FAN[2]
0001001000OUT_FAN[3]
0001010000OUT_FAN[4]
0001100000OUT_FAN[5]
0010000001OUT_HALF1[9]
0010000010OUT_HALF1[8]
0010000100OUT_FAN[7]
0010001000OUT_FAN[6]
0010010000OUT_HALF1[11]
0010100000OUT_HALF1[10]
0100000001OUT_SEC[15]
0100000100OUT_SEC[12]
0100001000OUT_SEC[13]
0100010000OUT_SEC[17]
0100100000OUT_SEC[16]
1000000001OUT_SEC[21]
1000000010OUT_SEC[20]
1000000100OUT_SEC[18]
1000001000OUT_SEC[19]
1000010000OUT_SEC[23]
1000100000OUT_SEC[22]
virtex2 INT_BRAM switchbox INT muxes OMUX[12]
BitsDestination
MAIN[7][60]MAIN[6][61]MAIN[7][62]MAIN[7][61]MAIN[6][63]MAIN[6][60]MAIN[6][66]MAIN[6][69]MAIN[7][65]MAIN[7][64]OMUX[12]
Source
0000000000off
0001000001OUT_FAN[0]
0001000010OUT_FAN[1]
0001000100OUT_FAN[2]
0001001000OUT_FAN[3]
0001010000OUT_FAN[4]
0001100000OUT_FAN[5]
0010000001OUT_HALF1[9]
0010000010OUT_HALF1[8]
0010000100OUT_FAN[7]
0010001000OUT_FAN[6]
0010010000OUT_HALF1[11]
0010100000OUT_HALF1[10]
0100000001OUT_SEC[15]
0100000100OUT_SEC[12]
0100001000OUT_SEC[13]
0100010000OUT_SEC[17]
0100100000OUT_SEC[16]
1000000001OUT_SEC[21]
1000000010OUT_SEC[20]
1000000100OUT_SEC[18]
1000001000OUT_SEC[19]
1000010000OUT_SEC[23]
1000100000OUT_SEC[22]
virtex2 INT_BRAM switchbox INT muxes OMUX[13]
BitsDestination
MAIN[7][69]MAIN[6][68]MAIN[7][67]MAIN[7][68]MAIN[7][63]MAIN[6][62]MAIN[7][66]MAIN[6][67]MAIN[6][65]MAIN[6][64]OMUX[13]
Source
0000000000off
0001000001OUT_FAN[0]
0001000010OUT_FAN[1]
0001000100OUT_FAN[2]
0001001000OUT_FAN[3]
0001010000OUT_FAN[4]
0001100000OUT_FAN[5]
0010000001OUT_HALF1[9]
0010000010OUT_HALF1[8]
0010000100OUT_FAN[7]
0010001000OUT_FAN[6]
0010010000OUT_HALF1[11]
0010100000OUT_HALF1[10]
0100000001OUT_SEC[15]
0100000100OUT_SEC[12]
0100001000OUT_SEC[13]
0100010000OUT_SEC[17]
0100100000OUT_SEC[16]
1000000001OUT_SEC[21]
1000000010OUT_SEC[20]
1000000100OUT_SEC[18]
1000001000OUT_SEC[19]
1000010000OUT_SEC[23]
1000100000OUT_SEC[22]
virtex2 INT_BRAM switchbox INT muxes OMUX[14]
BitsDestination
MAIN[7][70]MAIN[6][71]MAIN[7][72]MAIN[7][71]MAIN[6][73]MAIN[6][70]MAIN[6][76]MAIN[6][79]MAIN[7][75]MAIN[7][74]OMUX[14]
Source
0000000000off
0001000001OUT_FAN[0]
0001000010OUT_FAN[1]
0001000100OUT_FAN[2]
0001001000OUT_FAN[3]
0001010000OUT_FAN[4]
0001100000OUT_FAN[5]
0010000001OUT_HALF1[9]
0010000010OUT_HALF1[8]
0010000100OUT_FAN[7]
0010001000OUT_FAN[6]
0010010000OUT_HALF1[11]
0010100000OUT_HALF1[10]
0100000001OUT_SEC[15]
0100000100OUT_SEC[12]
0100001000OUT_SEC[13]
0100010000OUT_SEC[17]
0100100000OUT_SEC[16]
1000000001OUT_SEC[21]
1000000010OUT_SEC[20]
1000000100OUT_SEC[18]
1000001000OUT_SEC[19]
1000010000OUT_SEC[23]
1000100000OUT_SEC[22]
virtex2 INT_BRAM switchbox INT muxes OMUX[15]
BitsDestination
MAIN[7][79]MAIN[6][78]MAIN[7][77]MAIN[7][78]MAIN[7][73]MAIN[6][72]MAIN[7][76]MAIN[6][77]MAIN[6][75]MAIN[6][74]OMUX[15]
Source
0000000000off
0001000001OUT_FAN[0]
0001000010OUT_FAN[1]
0001000100OUT_FAN[2]
0001001000OUT_FAN[3]
0001010000OUT_FAN[4]
0001100000OUT_FAN[5]
0010000001OUT_HALF1[9]
0010000010OUT_HALF1[8]
0010000100OUT_FAN[7]
0010001000OUT_FAN[6]
0010010000OUT_HALF1[11]
0010100000OUT_HALF1[10]
0100000001OUT_SEC[15]
0100000100OUT_SEC[12]
0100001000OUT_SEC[13]
0100010000OUT_SEC[17]
0100100000OUT_SEC[16]
1000000001OUT_SEC[21]
1000000010OUT_SEC[20]
1000000100OUT_SEC[18]
1000001000OUT_SEC[19]
1000010000OUT_SEC[23]
1000100000OUT_SEC[22]
virtex2 INT_BRAM switchbox INT muxes DBL_W0[0]
BitsDestination
MAIN[16][5]MAIN[16][6]MAIN[17][6]MAIN[17][5]MAIN[15][7]MAIN[14][5]MAIN[14][4]MAIN[15][6]DBL_W0[0]
Source
00000000off
00010001OMUX_S0
00010010HEX_E6[0]
00010100OUT_FAN[3]
00011000HEX_N6[0]
00100001OMUX_NW10
00100010HEX_S6[1]
00100100OUT_FAN[4]
00101000HEX_W6[0]
01000001DBL_W2[0]
01000010HEX_N3[0]
01000100HEX_S3[0]
01001000DBL_N3[9]
10000001DBL_W2_N[8]
10000010DBL_S1[0]
10000100DBL_S2[2]
10001000DBL_N1[0]
virtex2 INT_BRAM switchbox INT muxes DBL_W0[1]
BitsDestination
MAIN[16][13]MAIN[16][14]MAIN[17][14]MAIN[17][13]MAIN[15][15]MAIN[14][13]MAIN[14][12]MAIN[15][14]DBL_W0[1]
Source
00000000off
00010001OMUX[2]
00010010HEX_E6[1]
00010100OUT_FAN[2]
00011000HEX_N6[1]
00100001OMUX_W1
00100010HEX_S6[2]
00100100OUT_FAN[5]
00101000HEX_W6[1]
01000001DBL_W2[1]
01000010HEX_N3[1]
01000100HEX_S3[1]
01001000DBL_N2[0]
10000001DBL_W2_N[9]
10000010DBL_S1[1]
10000100DBL_S2[3]
10001000DBL_N1[1]
virtex2 INT_BRAM switchbox INT muxes DBL_W0[2]
BitsDestination
MAIN[15][23]MAIN[14][20]MAIN[15][22]MAIN[14][21]MAIN[16][22]MAIN[16][21]MAIN[17][22]MAIN[17][21]DBL_W0[2]
Source
00000000off
00010001OMUX[4]
00010010OUT_FAN[3]
00010100DBL_S2[4]
00011000HEX_S3[2]
00100001OMUX[6]
00100010OMUX_WN14
00100100DBL_W2[0]
00101000DBL_W2[2]
01000001HEX_E6[2]
01000010HEX_S6[3]
01000100DBL_S1[2]
01001000HEX_N3[2]
10000001HEX_N6[2]
10000010HEX_W6[2]
10000100DBL_N1[2]
10001000DBL_N2[1]
virtex2 INT_BRAM switchbox INT muxes DBL_W0[3]
BitsDestination
MAIN[16][30]MAIN[16][29]MAIN[17][30]MAIN[17][29]MAIN[15][31]MAIN[14][29]MAIN[14][28]MAIN[15][30]DBL_W0[3]
Source
00000000off
00010001OMUX_W6
00010010HEX_E6[3]
00010100OUT_FAN[4]
00011000HEX_N6[3]
00100001OMUX_NW10
00100010HEX_S6[4]
00100100OUT_FAN[2]
00101000HEX_W6[3]
01000001DBL_W2[1]
01000010DBL_S1[3]
01000100DBL_S2[5]
01001000DBL_N1[3]
10000001DBL_W2[3]
10000010HEX_N3[3]
10000100HEX_S3[3]
10001000DBL_N2[2]
virtex2 INT_BRAM switchbox INT muxes DBL_W0[4]
BitsDestination
MAIN[16][38]MAIN[16][37]MAIN[17][38]MAIN[17][37]MAIN[15][39]MAIN[14][37]MAIN[14][36]MAIN[15][38]DBL_W0[4]
Source
00000000off
00010001OMUX_WS1
00010010HEX_E6[4]
00010100OUT_FAN[5]
00011000HEX_N6[4]
00100001OMUX_N12
00100010HEX_S6[5]
00100100OUT_FAN[6]
00101000HEX_W6[4]
01000001DBL_W2[2]
01000010DBL_S1[4]
01000100DBL_S2[6]
01001000DBL_N1[4]
10000001DBL_W2[4]
10000010HEX_N3[4]
10000100HEX_S3[4]
10001000DBL_N2[3]
virtex2 INT_BRAM switchbox INT muxes DBL_W0[5]
BitsDestination
MAIN[16][46]MAIN[16][45]MAIN[17][46]MAIN[17][45]MAIN[15][47]MAIN[14][45]MAIN[14][44]MAIN[15][46]DBL_W0[5]
Source
00000000off
00010001OMUX_S3
00010010HEX_E6[5]
00010100OUT_FAN[1]
00011000HEX_N6[5]
00100001OMUX_WN14
00100010HEX_S6[6]
00100100OUT_FAN[7]
00101000HEX_W6[5]
01000001DBL_W2[3]
01000010DBL_S1[5]
01000100DBL_S2[7]
01001000DBL_N1[5]
10000001DBL_W2[5]
10000010HEX_N3[5]
10000100HEX_S3[5]
10001000DBL_N2[4]
virtex2 INT_BRAM switchbox INT muxes DBL_W0[6]
BitsDestination
MAIN[15][55]MAIN[14][52]MAIN[15][54]MAIN[14][53]MAIN[16][54]MAIN[16][53]MAIN[17][53]MAIN[17][54]DBL_W0[6]
Source
00000000off
00010001OMUX[11]
00010010OUT_FAN[0]
00010100DBL_S2[8]
00011000HEX_S3[6]
00100001OMUX_W9
00100010OMUX_SW5
00100100DBL_W2[4]
00101000DBL_W2[6]
01000001HEX_S6[7]
01000010HEX_E6[6]
01000100DBL_S1[6]
01001000HEX_N3[6]
10000001HEX_W6[6]
10000010HEX_N6[6]
10000100DBL_N1[6]
10001000DBL_N2[5]
virtex2 INT_BRAM switchbox INT muxes DBL_W0[7]
BitsDestination
MAIN[16][62]MAIN[16][61]MAIN[17][61]MAIN[17][62]MAIN[15][63]MAIN[14][61]MAIN[14][60]MAIN[15][62]DBL_W0[7]
Source
00000000off
00010001OMUX[9]
00010010HEX_S6[8]
00010100OUT_FAN[1]
00011000HEX_W6[7]
00100001OMUX_WS1
00100010HEX_E6[7]
00100100OUT_FAN[6]
00101000HEX_N6[7]
01000001DBL_W2[5]
01000010DBL_S1[7]
01000100DBL_S2[9]
01001000DBL_N1[7]
10000001DBL_W2[7]
10000010HEX_N3[7]
10000100HEX_S3[7]
10001000DBL_N2[6]
virtex2 INT_BRAM switchbox INT muxes DBL_W0[8]
BitsDestination
MAIN[16][70]MAIN[16][69]MAIN[17][69]MAIN[17][70]MAIN[15][71]MAIN[14][69]MAIN[14][68]MAIN[15][70]DBL_W0[8]
Source
00000000off
00010001OMUX[13]
00010010HEX_S6[9]
00010100OUT_FAN[0]
00011000HEX_W6[8]
00100001OMUX_W14
00100010HEX_E6[8]
00100100OUT_FAN[7]
00101000HEX_N6[8]
01000001DBL_W2[6]
01000010DBL_S1[8]
01000100DBL_S3[0]
01001000DBL_N1[8]
10000001DBL_W2[8]
10000010HEX_N3[8]
10000100HEX_S3[8]
10001000DBL_N2[7]
virtex2 INT_BRAM switchbox INT muxes DBL_W0[9]
BitsDestination
MAIN[15][79]MAIN[14][76]MAIN[14][77]MAIN[15][78]MAIN[16][78]MAIN[16][77]MAIN[17][77]MAIN[17][78]DBL_W0[9]
Source
00000000off
00010001OMUX[13]
00010010OMUX_SW5
00010100DBL_W2[7]
00011000DBL_W2[9]
00100001OMUX_S0
00100010OMUX[15]
00100100DBL_S3[1]
00101000HEX_S3[9]
01000001HEX_S7[0]
01000010HEX_E6[9]
01000100DBL_S1[9]
01001000HEX_N3[9]
10000001HEX_W6[9]
10000010HEX_N6[9]
10000100DBL_N1[9]
10001000DBL_N2[8]
virtex2 INT_BRAM switchbox INT muxes DBL_E0[0]
BitsDestination
MAIN[17][7]MAIN[17][4]MAIN[16][4]MAIN[16][7]MAIN[15][5]MAIN[14][7]MAIN[15][4]MAIN[14][6]DBL_E0[0]
Source
00000000off
00010001OMUX_E2
00010010HEX_S6[1]
00010100OUT_FAN[4]
00011000HEX_W6[0]
00100001OMUX_EN8
00100010HEX_E6[0]
00100100OUT_FAN[3]
00101000HEX_N6[0]
01000001DBL_E2[0]
01000010DBL_S1[0]
01000100DBL_S2[2]
01001000DBL_N1[0]
10000001DBL_E2[2]
10000010HEX_N3[0]
10000100HEX_S3[0]
10001000DBL_N3[9]
virtex2 INT_BRAM switchbox INT muxes DBL_E0[1]
BitsDestination
MAIN[17][15]MAIN[17][12]MAIN[16][12]MAIN[16][15]MAIN[15][13]MAIN[14][15]MAIN[15][12]MAIN[14][14]DBL_E0[1]
Source
00000000off
00010001OMUX_S4
00010010HEX_S6[2]
00010100OUT_FAN[5]
00011000HEX_W6[1]
00100001OMUX_N10
00100010HEX_E6[1]
00100100OUT_FAN[2]
00101000HEX_N6[1]
01000001DBL_E2[1]
01000010DBL_S1[1]
01000100DBL_S2[3]
01001000DBL_N1[1]
10000001DBL_E2[3]
10000010HEX_N3[1]
10000100HEX_S3[1]
10001000DBL_N2[0]
virtex2 INT_BRAM switchbox INT muxes DBL_E0[2]
BitsDestination
MAIN[15][21]MAIN[15][20]MAIN[14][22]MAIN[14][23]MAIN[17][23]MAIN[17][20]MAIN[16][23]MAIN[16][20]DBL_E0[2]
Source
00000000off
00010001OMUX[4]
00010010OUT_FAN[3]
00010100DBL_S2[4]
00011000HEX_S3[2]
00100001OMUX_NE12
00100010OMUX[6]
00100100DBL_E2[2]
00101000DBL_E2[4]
01000001HEX_E6[2]
01000010HEX_S6[3]
01000100DBL_S1[2]
01001000HEX_N3[2]
10000001HEX_N6[2]
10000010HEX_W6[2]
10000100DBL_N1[2]
10001000DBL_N2[1]
virtex2 INT_BRAM switchbox INT muxes DBL_E0[3]
BitsDestination
MAIN[17][31]MAIN[17][28]MAIN[16][28]MAIN[16][31]MAIN[15][29]MAIN[14][31]MAIN[15][28]MAIN[14][30]DBL_E0[3]
Source
00000000off
00010001OMUX_SE3
00010010HEX_S6[4]
00010100OUT_FAN[2]
00011000HEX_W6[3]
00100001OMUX_EN8
00100010HEX_E6[3]
00100100OUT_FAN[4]
00101000HEX_N6[3]
01000001DBL_E2[3]
01000010DBL_S1[3]
01000100DBL_S2[5]
01001000DBL_N1[3]
10000001DBL_E2[5]
10000010HEX_N3[3]
10000100HEX_S3[3]
10001000DBL_N2[2]
virtex2 INT_BRAM switchbox INT muxes DBL_E0[4]
BitsDestination
MAIN[17][39]MAIN[17][36]MAIN[16][39]MAIN[16][36]MAIN[15][37]MAIN[14][39]MAIN[15][36]MAIN[14][38]DBL_E0[4]
Source
00000000off
00010001OMUX_E7
00010010HEX_E6[4]
00010100OUT_FAN[5]
00011000HEX_N6[4]
00100001OMUX_E8
00100010HEX_S6[5]
00100100OUT_FAN[6]
00101000HEX_W6[4]
01000001DBL_E2[4]
01000010DBL_S1[4]
01000100DBL_S2[6]
01001000DBL_N1[4]
10000001DBL_E2[6]
10000010HEX_N3[4]
10000100HEX_S3[4]
10001000DBL_N2[3]
virtex2 INT_BRAM switchbox INT muxes DBL_E0[5]
BitsDestination
MAIN[17][47]MAIN[17][44]MAIN[16][44]MAIN[16][47]MAIN[15][45]MAIN[14][47]MAIN[15][44]MAIN[14][46]DBL_E0[5]
Source
00000000off
00010001OMUX_ES7
00010010HEX_S6[6]
00010100OUT_FAN[7]
00011000HEX_W6[5]
00100001OMUX_NE12
00100010HEX_E6[5]
00100100OUT_FAN[1]
00101000HEX_N6[5]
01000001DBL_E2[5]
01000010DBL_S1[5]
01000100DBL_S2[7]
01001000DBL_N1[5]
10000001DBL_E2[7]
10000010HEX_N3[5]
10000100HEX_S3[5]
10001000DBL_N2[4]
virtex2 INT_BRAM switchbox INT muxes DBL_E0[6]
BitsDestination
MAIN[17][55]MAIN[17][52]MAIN[16][55]MAIN[16][52]MAIN[15][53]MAIN[15][52]MAIN[14][55]MAIN[14][54]DBL_E0[6]
Source
00000000off
00010001OMUX[9]
00010010OUT_FAN[0]
00010100HEX_E6[6]
00011000HEX_N6[6]
00100001OMUX_SE3
00100010OMUX[11]
00100100HEX_S6[7]
00101000HEX_W6[6]
01000001DBL_E2[6]
01000010DBL_S2[8]
01000100DBL_S1[6]
01001000DBL_N1[6]
10000001DBL_E2[8]
10000010HEX_S3[6]
10000100HEX_N3[6]
10001000DBL_N2[5]
virtex2 INT_BRAM switchbox INT muxes DBL_E0[7]
BitsDestination
MAIN[17][63]MAIN[17][60]MAIN[16][60]MAIN[16][63]MAIN[15][61]MAIN[14][63]MAIN[15][60]MAIN[14][62]DBL_E0[7]
Source
00000000off
00010001OMUX_S5
00010010HEX_S6[8]
00010100OUT_FAN[1]
00011000HEX_W6[7]
00100001OMUX_N11
00100010HEX_E6[7]
00100100OUT_FAN[6]
00101000HEX_N6[7]
01000001DBL_E2[7]
01000010DBL_S1[7]
01000100DBL_S2[9]
01001000DBL_N1[7]
10000001DBL_E2[9]
10000010HEX_N3[7]
10000100HEX_S3[7]
10001000DBL_N2[6]
virtex2 INT_BRAM switchbox INT muxes DBL_E0[8]
BitsDestination
MAIN[17][71]MAIN[17][68]MAIN[16][68]MAIN[16][71]MAIN[15][69]MAIN[14][71]MAIN[15][68]MAIN[14][70]DBL_E0[8]
Source
00000000off
00010001OMUX_ES7
00010010HEX_S6[9]
00010100OUT_FAN[0]
00011000HEX_W6[8]
00100001OMUX_E13
00100010HEX_E6[8]
00100100OUT_FAN[7]
00101000HEX_N6[8]
01000001DBL_E2[8]
01000010DBL_S1[8]
01000100DBL_S3[0]
01001000DBL_N1[8]
10000001DBL_E2_S[0]
10000010HEX_N3[8]
10000100HEX_S3[8]
10001000DBL_N2[7]
virtex2 INT_BRAM switchbox INT muxes DBL_E0[9]
BitsDestination
MAIN[17][79]MAIN[17][76]MAIN[16][79]MAIN[16][76]MAIN[15][77]MAIN[15][76]MAIN[14][78]MAIN[14][79]DBL_E0[9]
Source
00000000off
00010001OMUX[15]
00010010OMUX_N15
00010100HEX_E6[9]
00011000HEX_N6[9]
00100001OMUX_S0
00100010OMUX_S2
00100100HEX_S7[0]
00101000HEX_W6[9]
01000001DBL_S3[1]
01000010DBL_E2[9]
01000100DBL_S1[9]
01001000DBL_N1[9]
10000001HEX_S3[9]
10000010DBL_E2_S[1]
10000100HEX_N3[9]
10001000DBL_N2[8]
virtex2 INT_BRAM switchbox INT muxes DBL_S0[0]
BitsDestination
MAIN[15][0]MAIN[15][1]MAIN[14][2]MAIN[14][3]MAIN[17][3]MAIN[17][0]MAIN[16][3]MAIN[16][0]DBL_S0[0]
Source
00000000off
00010001OMUX[0]
00010010OUT_FAN[3]
00010100DBL_E2[1]
00011000HEX_E3[0]
00100001OMUX[2]
00100010OMUX_S0
00100100DBL_S2[0]
00101000DBL_S2[2]
01000001HEX_W6_N[9]
01000010HEX_N6[0]
01000100DBL_W1[0]
01001000DBL_W2_N[8]
10000001HEX_S6[0]
10000010HEX_E6[0]
10000100DBL_E1[0]
10001000HEX_W3[0]
virtex2 INT_BRAM switchbox INT muxes DBL_S0[1]
BitsDestination
MAIN[17][11]MAIN[17][8]MAIN[16][8]MAIN[16][11]MAIN[14][11]MAIN[15][8]MAIN[15][9]MAIN[14][10]DBL_S0[1]
Source
00000000off
00010001OMUX[2]
00010010HEX_N6[1]
00010100HEX_E6[1]
00011000OUT_FAN[2]
00100001OMUX_E2
00100010HEX_W6[0]
00100100HEX_S6[1]
00101000OUT_FAN[4]
01000001DBL_S2[1]
01000010DBL_W1[1]
01000100DBL_E1[1]
01001000DBL_E2[2]
10000001DBL_S2[3]
10000010DBL_W2_N[9]
10000100HEX_W3[1]
10001000HEX_E3[1]
virtex2 INT_BRAM switchbox INT muxes DBL_S0[2]
BitsDestination
MAIN[15][16]MAIN[15][17]MAIN[14][18]MAIN[14][19]MAIN[17][19]MAIN[17][16]MAIN[16][16]MAIN[16][19]DBL_S0[2]
Source
00000000off
00010001OMUX[4]
00010010OUT_FAN[5]
00010100DBL_E2[3]
00011000HEX_E3[2]
00100001OMUX[6]
00100010OMUX_S4
00100100DBL_S2[2]
00101000DBL_S2[4]
01000001HEX_N6[2]
01000010HEX_W6[1]
01000100DBL_W1[2]
01001000DBL_W2[0]
10000001HEX_E6[2]
10000010HEX_S6[2]
10000100DBL_E1[2]
10001000HEX_W3[2]
virtex2 INT_BRAM switchbox INT muxes DBL_S0[3]
BitsDestination
MAIN[17][27]MAIN[17][24]MAIN[16][27]MAIN[16][24]MAIN[14][27]MAIN[15][24]MAIN[15][25]MAIN[14][26]DBL_S0[3]
Source
00000000off
00010001OMUX[6]
00010010HEX_W6[2]
00010100HEX_S6[3]
00011000OUT_FAN[3]
00100001OMUX_W6
00100010HEX_N6[3]
00100100HEX_E6[3]
00101000OUT_FAN[4]
01000001DBL_S2[3]
01000010DBL_W1[3]
01000100DBL_E1[3]
01001000DBL_E2[4]
10000001DBL_S2[5]
10000010DBL_W2[1]
10000100HEX_W3[3]
10001000HEX_E3[3]
virtex2 INT_BRAM switchbox INT muxes DBL_S0[4]
BitsDestination
MAIN[17][35]MAIN[17][32]MAIN[16][32]MAIN[16][35]MAIN[14][35]MAIN[15][32]MAIN[15][33]MAIN[14][34]DBL_S0[4]
Source
00000000off
00010001OMUX_WS1
00010010HEX_N6[4]
00010100HEX_E6[4]
00011000OUT_FAN[5]
00100001OMUX_SE3
00100010HEX_W6[3]
00100100HEX_S6[4]
00101000OUT_FAN[2]
01000001DBL_S2[4]
01000010DBL_W1[4]
01000100DBL_E1[4]
01001000DBL_E2[5]
10000001DBL_S2[6]
10000010DBL_W2[2]
10000100HEX_W3[4]
10001000HEX_E3[4]
virtex2 INT_BRAM switchbox INT muxes DBL_S0[5]
BitsDestination
MAIN[17][43]MAIN[17][40]MAIN[16][40]MAIN[16][43]MAIN[14][43]MAIN[15][40]MAIN[15][41]MAIN[14][42]DBL_S0[5]
Source
00000000off
00010001OMUX_S3
00010010HEX_N6[5]
00010100HEX_E6[5]
00011000OUT_FAN[1]
00100001OMUX_E8
00100010HEX_W6[4]
00100100HEX_S6[5]
00101000OUT_FAN[6]
01000001DBL_S2[5]
01000010DBL_W1[5]
01000100DBL_E1[5]
01001000DBL_E2[6]
10000001DBL_S2[7]
10000010DBL_W2[3]
10000100HEX_W3[5]
10001000HEX_E3[5]
virtex2 INT_BRAM switchbox INT muxes DBL_S0[6]
BitsDestination
MAIN[17][51]MAIN[17][48]MAIN[16][48]MAIN[16][51]MAIN[14][51]MAIN[15][48]MAIN[15][49]MAIN[14][50]DBL_S0[6]
Source
00000000off
00010001OMUX_SW5
00010010HEX_N6[6]
00010100HEX_E6[6]
00011000OUT_FAN[0]
00100001OMUX_ES7
00100010HEX_W6[5]
00100100HEX_S6[6]
00101000OUT_FAN[7]
01000001DBL_S2[6]
01000010DBL_W1[6]
01000100DBL_E1[6]
01001000DBL_E2[7]
10000001DBL_S2[8]
10000010DBL_W2[4]
10000100HEX_W3[6]
10001000HEX_E3[6]
virtex2 INT_BRAM switchbox INT muxes DBL_S0[7]
BitsDestination
MAIN[15][56]MAIN[15][57]MAIN[14][58]MAIN[14][59]MAIN[17][59]MAIN[17][56]MAIN[16][59]MAIN[16][56]DBL_S0[7]
Source
00000000off
00010001OMUX[11]
00010010OUT_FAN[6]
00010100DBL_E2[8]
00011000HEX_E3[7]
00100001OMUX_SE3
00100010OMUX_WS1
00100100DBL_S2[7]
00101000DBL_S2[9]
01000001HEX_W6[6]
01000010HEX_N6[7]
01000100DBL_W1[7]
01001000DBL_W2[5]
10000001HEX_S6[7]
10000010HEX_E6[7]
10000100DBL_E1[7]
10001000HEX_W3[7]
virtex2 INT_BRAM switchbox INT muxes DBL_S0[8]
BitsDestination
MAIN[17][67]MAIN[17][64]MAIN[16][67]MAIN[16][64]MAIN[14][67]MAIN[15][64]MAIN[15][65]MAIN[14][66]DBL_S0[8]
Source
00000000off
00010001OMUX_S5
00010010HEX_W6[7]
00010100HEX_S6[8]
00011000OUT_FAN[1]
00100001OMUX_W14
00100010HEX_N6[8]
00100100HEX_E6[8]
00101000OUT_FAN[7]
01000001DBL_S2[8]
01000010DBL_W1[8]
01000100DBL_E1[8]
01001000DBL_E2[9]
10000001DBL_S3[0]
10000010DBL_W2[6]
10000100HEX_W3[8]
10001000HEX_E3[8]
virtex2 INT_BRAM switchbox INT muxes DBL_S0[9]
BitsDestination
MAIN[15][72]MAIN[15][73]MAIN[14][74]MAIN[14][75]MAIN[17][75]MAIN[17][72]MAIN[16][72]MAIN[16][75]DBL_S0[9]
Source
00000000off
00010001OMUX[15]
00010010OUT_FAN[0]
00010100DBL_E2_S[0]
00011000HEX_E3[9]
00100001OMUX_SW5
00100010OMUX_ES7
00100100DBL_S2[9]
00101000DBL_S3[1]
01000001HEX_N6[9]
01000010HEX_W6[8]
01000100DBL_W1[9]
01001000DBL_W2[7]
10000001HEX_E6[9]
10000010HEX_S6[9]
10000100DBL_E1[9]
10001000HEX_W3[9]
virtex2 INT_BRAM switchbox INT muxes DBL_N0[0]
BitsDestination
MAIN[14][0]MAIN[15][3]MAIN[15][2]MAIN[14][1]MAIN[16][2]MAIN[16][1]MAIN[17][2]MAIN[17][1]DBL_N0[0]
Source
00000000off
00010001OMUX[0]
00010010OUT_FAN[3]
00010100DBL_E2[1]
00011000HEX_E3[0]
00100001OMUX_N13
00100010OMUX_EN8
00100100DBL_N3[8]
00101000DBL_N2[0]
01000001HEX_W6_N[9]
01000010HEX_N6[0]
01000100DBL_W1[0]
01001000DBL_W2_N[8]
10000001HEX_S6[0]
10000010HEX_E6[0]
10000100DBL_E1[0]
10001000HEX_W3[0]
virtex2 INT_BRAM switchbox INT muxes DBL_N0[1]
BitsDestination
MAIN[16][10]MAIN[16][9]MAIN[17][9]MAIN[17][10]MAIN[14][9]MAIN[14][8]MAIN[15][11]MAIN[15][10]DBL_N0[1]
Source
00000000off
00010001OMUX_N10
00010010HEX_N6[1]
00010100HEX_E6[1]
00011000OUT_FAN[2]
00100001OMUX_NW10
00100010HEX_W6[0]
00100100HEX_S6[1]
00101000OUT_FAN[4]
01000001DBL_N3[9]
01000010DBL_W1[1]
01000100DBL_E1[1]
01001000DBL_E2[2]
10000001DBL_N2[1]
10000010DBL_W2_N[9]
10000100HEX_W3[1]
10001000HEX_E3[1]
virtex2 INT_BRAM switchbox INT muxes DBL_N0[2]
BitsDestination
MAIN[14][16]MAIN[15][19]MAIN[15][18]MAIN[14][17]MAIN[16][18]MAIN[16][17]MAIN[17][17]MAIN[17][18]DBL_N0[2]
Source
00000000off
00010001OMUX[4]
00010010OUT_FAN[5]
00010100DBL_E2[3]
00011000HEX_E3[2]
00100001OMUX_NE12
00100010OMUX_W1
00100100DBL_N2[0]
00101000DBL_N2[2]
01000001HEX_N6[2]
01000010HEX_W6[1]
01000100DBL_W1[2]
01001000DBL_W2[0]
10000001HEX_E6[2]
10000010HEX_S6[2]
10000100DBL_E1[2]
10001000HEX_W3[2]
virtex2 INT_BRAM switchbox INT muxes DBL_N0[3]
BitsDestination
MAIN[16][26]MAIN[16][25]MAIN[17][25]MAIN[17][26]MAIN[14][25]MAIN[14][24]MAIN[15][27]MAIN[15][26]DBL_N0[3]
Source
00000000off
00010001OMUX_EN8
00010010HEX_N6[3]
00010100HEX_E6[3]
00011000OUT_FAN[4]
00100001OMUX_WN14
00100010HEX_W6[2]
00100100HEX_S6[3]
00101000OUT_FAN[3]
01000001DBL_N2[1]
01000010DBL_W1[3]
01000100DBL_E1[3]
01001000DBL_E2[4]
10000001DBL_N2[3]
10000010DBL_W2[1]
10000100HEX_W3[3]
10001000HEX_E3[3]
virtex2 INT_BRAM switchbox INT muxes DBL_N0[4]
BitsDestination
MAIN[16][34]MAIN[16][33]MAIN[17][33]MAIN[17][34]MAIN[14][33]MAIN[14][32]MAIN[15][35]MAIN[15][34]DBL_N0[4]
Source
00000000off
00010001OMUX_E7
00010010HEX_N6[4]
00010100HEX_E6[4]
00011000OUT_FAN[5]
00100001OMUX_NW10
00100010HEX_W6[3]
00100100HEX_S6[4]
00101000OUT_FAN[2]
01000001DBL_N2[2]
01000010DBL_W1[4]
01000100DBL_E1[4]
01001000DBL_E2[5]
10000001DBL_N2[4]
10000010DBL_W2[2]
10000100HEX_W3[4]
10001000HEX_E3[4]
virtex2 INT_BRAM switchbox INT muxes DBL_N0[5]
BitsDestination
MAIN[16][42]MAIN[16][41]MAIN[17][42]MAIN[17][41]MAIN[14][41]MAIN[14][40]MAIN[15][43]MAIN[15][42]DBL_N0[5]
Source
00000000off
00010001OMUX_N12
00010010HEX_W6[4]
00010100HEX_S6[5]
00011000OUT_FAN[6]
00100001OMUX_NE12
00100010HEX_N6[5]
00100100HEX_E6[5]
00101000OUT_FAN[1]
01000001DBL_N2[3]
01000010DBL_W1[5]
01000100DBL_E1[5]
01001000DBL_E2[6]
10000001DBL_N2[5]
10000010DBL_W2[3]
10000100HEX_W3[5]
10001000HEX_E3[5]
virtex2 INT_BRAM switchbox INT muxes DBL_N0[6]
BitsDestination
MAIN[16][50]MAIN[16][49]MAIN[17][49]MAIN[17][50]MAIN[14][49]MAIN[14][48]MAIN[15][51]MAIN[15][50]DBL_N0[6]
Source
00000000off
00010001OMUX[9]
00010010HEX_N6[6]
00010100HEX_E6[6]
00011000OUT_FAN[0]
00100001OMUX_WN14
00100010HEX_W6[5]
00100100HEX_S6[6]
00101000OUT_FAN[7]
01000001DBL_N2[4]
01000010DBL_W1[6]
01000100DBL_E1[6]
01001000DBL_E2[7]
10000001DBL_N2[6]
10000010DBL_W2[4]
10000100HEX_W3[6]
10001000HEX_E3[6]
virtex2 INT_BRAM switchbox INT muxes DBL_N0[7]
BitsDestination
MAIN[14][56]MAIN[15][59]MAIN[15][58]MAIN[14][57]MAIN[16][58]MAIN[16][57]MAIN[17][58]MAIN[17][57]DBL_N0[7]
Source
00000000off
00010001OMUX[11]
00010010OUT_FAN[6]
00010100DBL_E2[8]
00011000HEX_E3[7]
00100001OMUX_W9
00100010OMUX_N11
00100100DBL_N2[5]
00101000DBL_N2[7]
01000001HEX_W6[6]
01000010HEX_N6[7]
01000100DBL_W1[7]
01001000DBL_W2[5]
10000001HEX_S6[7]
10000010HEX_E6[7]
10000100DBL_E1[7]
10001000HEX_W3[7]
virtex2 INT_BRAM switchbox INT muxes DBL_N0[8]
BitsDestination
MAIN[16][66]MAIN[16][65]MAIN[17][66]MAIN[17][65]MAIN[14][65]MAIN[14][64]MAIN[15][67]MAIN[15][66]DBL_N0[8]
Source
00000000off
00010001OMUX[9]
00010010HEX_W6[7]
00010100HEX_S6[8]
00011000OUT_FAN[1]
00100001OMUX_E13
00100010HEX_N6[8]
00100100HEX_E6[8]
00101000OUT_FAN[7]
01000001DBL_N2[6]
01000010DBL_W1[8]
01000100DBL_E1[8]
01001000DBL_E2[9]
10000001DBL_N2[8]
10000010DBL_W2[6]
10000100HEX_W3[8]
10001000HEX_E3[8]
virtex2 INT_BRAM switchbox INT muxes DBL_N0[9]
BitsDestination
MAIN[16][74]MAIN[16][73]MAIN[17][74]MAIN[17][73]MAIN[14][72]MAIN[15][75]MAIN[14][73]MAIN[15][74]DBL_N0[9]
Source
00000000off
00010001OMUX[13]
00010010OUT_FAN[0]
00010100HEX_W6[8]
00011000HEX_S6[9]
00100001OMUX_N15
00100010OMUX[15]
00100100HEX_N6[9]
00101000HEX_E6[9]
01000001DBL_N2[7]
01000010DBL_E2_S[0]
01000100DBL_W1[9]
01001000DBL_E1[9]
10000001DBL_N2[9]
10000010HEX_E3[9]
10000100DBL_W2[7]
10001000HEX_W3[9]
virtex2 INT_BRAM switchbox INT muxes HEX_W0[0]
BitsDestination
MAIN[20][4]MAIN[20][6]MAIN[20][5]MAIN[18][4]MAIN[19][6]MAIN[18][6]MAIN[19][4]HEX_W0[0]
Source
0000000off
0010001OMUX_S0
0010010HEX_S3[0]
0010100HEX_N3[0]
0011000LH[6]
0100001OUT_FAN[4]
0100010OMUX_NW10
0100100HEX_W6[0]
0101000HEX_W6_N[8]
1000001OUT_FAN[3]
1000010LH[18]
1000100HEX_N7[9]
1001000HEX_S6[2]
virtex2 INT_BRAM switchbox INT muxes HEX_W0[1]
BitsDestination
MAIN[21][12]MAIN[20][15]MAIN[21][14]MAIN[18][13]MAIN[19][15]MAIN[18][15]MAIN[19][13]HEX_W0[1]
Source
0000000off
0010001OMUX[2]
0010010OUT_FAN[5]
0010100HEX_W6[1]
0011000HEX_W6_N[9]
0100001LH[0]
0100010OMUX_W1
0100100HEX_S3[1]
0101000HEX_N3[1]
1000001OUT_FAN[2]
1000010LH[12]
1000100HEX_N6[0]
1001000HEX_S6[3]
virtex2 INT_BRAM switchbox INT muxes HEX_W0[2]
BitsDestination
MAIN[20][22]MAIN[20][21]MAIN[20][20]MAIN[19][22]MAIN[18][20]MAIN[18][22]MAIN[19][20]HEX_W0[2]
Source
0000000off
0010001OMUX[4]
0010010LH[18]
0010100HEX_S6[4]
0011000HEX_N6[1]
0100001OMUX[6]
0100010HEX_S3[2]
0100100LH[6]
0101000HEX_N3[2]
1000001OUT_FAN[3]
1000010OMUX_WN14
1000100HEX_W6[0]
1001000HEX_W6[2]
virtex2 INT_BRAM switchbox INT muxes HEX_W0[3]
BitsDestination
MAIN[21][28]MAIN[20][31]MAIN[21][30]MAIN[19][31]MAIN[18][29]MAIN[18][31]MAIN[19][29]HEX_W0[3]
Source
0000000off
0010001OMUX_W6
0010010OUT_FAN[2]
0010100HEX_W6[1]
0011000HEX_W6[3]
0100001LH[0]
0100010OMUX_NW10
0100100HEX_N3[3]
0101000HEX_S3[3]
1000001OUT_FAN[4]
1000010LH[12]
1000100HEX_S6[5]
1001000HEX_N6[2]
virtex2 INT_BRAM switchbox INT muxes HEX_W0[4]
BitsDestination
MAIN[20][36]MAIN[20][38]MAIN[20][37]MAIN[19][38]MAIN[18][36]MAIN[18][38]MAIN[19][36]HEX_W0[4]
Source
0000000off
0010001OMUX_WS1
0010010HEX_S3[4]
0010100LH[6]
0011000HEX_N3[4]
0100001OUT_FAN[6]
0100010OMUX_N12
0100100HEX_W6[2]
0101000HEX_W6[4]
1000001OUT_FAN[5]
1000010LH[18]
1000100HEX_S6[6]
1001000HEX_N6[3]
virtex2 INT_BRAM switchbox INT muxes HEX_W0[5]
BitsDestination
MAIN[21][44]MAIN[20][47]MAIN[21][46]MAIN[19][47]MAIN[18][45]MAIN[18][47]MAIN[19][45]HEX_W0[5]
Source
0000000off
0010001OMUX_S3
0010010OUT_FAN[7]
0010100HEX_W6[3]
0011000HEX_W6[5]
0100001LH[0]
0100010OMUX_WN14
0100100HEX_N3[5]
0101000HEX_S3[5]
1000001OUT_FAN[1]
1000010LH[12]
1000100HEX_S6[7]
1001000HEX_N6[4]
virtex2 INT_BRAM switchbox INT muxes HEX_W0[6]
BitsDestination
MAIN[20][52]MAIN[20][53]MAIN[20][54]MAIN[19][54]MAIN[18][52]MAIN[18][54]MAIN[19][52]HEX_W0[6]
Source
0000000off
0010001OMUX[11]
0010010OMUX_W9
0010100HEX_W6[4]
0011000HEX_W6[6]
0100001OMUX_SW5
0100010HEX_S3[6]
0100100LH[6]
0101000HEX_N3[6]
1000001OUT_FAN[0]
1000010LH[18]
1000100HEX_S6[8]
1001000HEX_N6[5]
virtex2 INT_BRAM switchbox INT muxes HEX_W0[7]
BitsDestination
MAIN[21][60]MAIN[21][62]MAIN[20][63]MAIN[19][63]MAIN[18][61]MAIN[19][61]MAIN[18][63]HEX_W0[7]
Source
0000000off
0010001OMUX[9]
0010010LH[0]
0010100HEX_N3[7]
0011000HEX_S3[7]
0100001OUT_FAN[1]
0100010OMUX_WS1
0100100HEX_W6[5]
0101000HEX_W6[7]
1000001LH[12]
1000010OUT_FAN[6]
1000100HEX_S6[9]
1001000HEX_N6[6]
virtex2 INT_BRAM switchbox INT muxes HEX_W0[8]
BitsDestination
MAIN[20][68]MAIN[20][69]MAIN[20][70]MAIN[19][70]MAIN[18][68]MAIN[19][68]MAIN[18][70]HEX_W0[8]
Source
0000000off
0010001OMUX[13]
0010010OUT_FAN[0]
0010100HEX_W6[6]
0011000HEX_W6[8]
0100001HEX_S3[8]
0100010OMUX_W14
0100100LH[6]
0101000HEX_N3[8]
1000001LH[18]
1000010OUT_FAN[7]
1000100HEX_S7[0]
1001000HEX_N6[7]
virtex2 INT_BRAM switchbox INT muxes HEX_W0[9]
BitsDestination
MAIN[21][78]MAIN[21][76]MAIN[20][79]MAIN[19][79]MAIN[18][77]MAIN[19][77]MAIN[18][79]HEX_W0[9]
Source
0000000off
0010001OMUX[13]
0010010LH[0]
0010100HEX_N3[9]
0011000HEX_S3[9]
0100001LH[12]
0100010OMUX[15]
0100100HEX_S7[1]
0101000HEX_N6[8]
1000001OMUX_S0
1000010OMUX_SW5
1000100HEX_W6[7]
1001000HEX_W6[9]
virtex2 INT_BRAM switchbox INT muxes HEX_E0[0]
BitsDestination
MAIN[21][4]MAIN[21][6]MAIN[20][7]MAIN[19][7]MAIN[18][5]MAIN[19][5]MAIN[18][7]HEX_E0[0]
Source
0000000off
0010001OMUX_E2
0010010LH[6]
0010100HEX_N3[0]
0011000HEX_S3[0]
0100001OUT_FAN[4]
0100010OMUX_EN8
0100100HEX_E6[0]
0101000HEX_E6[2]
1000001LH[18]
1000010OUT_FAN[3]
1000100HEX_S6[2]
1001000HEX_N7[9]
virtex2 INT_BRAM switchbox INT muxes HEX_E0[1]
BitsDestination
MAIN[20][12]MAIN[20][13]MAIN[20][14]MAIN[19][14]MAIN[18][12]MAIN[19][12]MAIN[18][14]HEX_E0[1]
Source
0000000off
0010001OMUX_S4
0010010OUT_FAN[5]
0010100HEX_E6[1]
0011000HEX_E6[3]
0100001HEX_S3[1]
0100010OMUX_N10
0100100LH[0]
0101000HEX_N3[1]
1000001LH[12]
1000010OUT_FAN[2]
1000100HEX_S6[3]
1001000HEX_N6[0]
virtex2 INT_BRAM switchbox INT muxes HEX_E0[2]
BitsDestination
MAIN[21][22]MAIN[20][23]MAIN[21][20]MAIN[19][23]MAIN[18][21]MAIN[18][23]MAIN[19][21]HEX_E0[2]
Source
0000000off
0010001OMUX[4]
0010010LH[18]
0010100HEX_S6[4]
0011000HEX_N6[1]
0100001LH[6]
0100010OMUX[6]
0100100HEX_N3[2]
0101000HEX_S3[2]
1000001OMUX_NE12
1000010OUT_FAN[3]
1000100HEX_E6[2]
1001000HEX_E6[4]
virtex2 INT_BRAM switchbox INT muxes HEX_E0[3]
BitsDestination
MAIN[20][28]MAIN[20][29]MAIN[20][30]MAIN[19][30]MAIN[18][28]MAIN[19][28]MAIN[18][30]HEX_E0[3]
Source
0000000off
0010001OMUX_SE3
0010010OUT_FAN[2]
0010100HEX_E6[3]
0011000HEX_E6[5]
0100001HEX_S3[3]
0100010OMUX_EN8
0100100LH[0]
0101000HEX_N3[3]
1000001LH[12]
1000010OUT_FAN[4]
1000100HEX_S6[5]
1001000HEX_N6[2]
virtex2 INT_BRAM switchbox INT muxes HEX_E0[4]
BitsDestination
MAIN[21][36]MAIN[20][39]MAIN[21][38]MAIN[19][39]MAIN[18][37]MAIN[18][39]MAIN[19][37]HEX_E0[4]
Source
0000000off
0010001OMUX_E7
0010010OUT_FAN[6]
0010100HEX_E6[4]
0011000HEX_E6[6]
0100001LH[6]
0100010OMUX_E8
0100100HEX_N3[4]
0101000HEX_S3[4]
1000001OUT_FAN[5]
1000010LH[18]
1000100HEX_S6[6]
1001000HEX_N6[3]
virtex2 INT_BRAM switchbox INT muxes HEX_E0[5]
BitsDestination
MAIN[20][44]MAIN[20][45]MAIN[20][46]MAIN[19][46]MAIN[18][44]MAIN[19][44]MAIN[18][46]HEX_E0[5]
Source
0000000off
0010001OMUX_ES7
0010010OUT_FAN[7]
0010100HEX_E6[5]
0011000HEX_E6[7]
0100001HEX_S3[5]
0100010OMUX_NE12
0100100LH[0]
0101000HEX_N3[5]
1000001LH[12]
1000010OUT_FAN[1]
1000100HEX_S6[7]
1001000HEX_N6[4]
virtex2 INT_BRAM switchbox INT muxes HEX_E0[6]
BitsDestination
MAIN[21][52]MAIN[20][55]MAIN[21][54]MAIN[19][55]MAIN[18][53]MAIN[18][55]MAIN[19][53]HEX_E0[6]
Source
0000000off
0010001OMUX[9]
0010010OMUX[11]
0010100HEX_E6[6]
0011000HEX_E6[8]
0100001LH[6]
0100010OMUX_SE3
0100100HEX_N3[6]
0101000HEX_S3[6]
1000001OUT_FAN[0]
1000010LH[18]
1000100HEX_S6[8]
1001000HEX_N6[5]
virtex2 INT_BRAM switchbox INT muxes HEX_E0[7]
BitsDestination
MAIN[20][60]MAIN[20][61]MAIN[20][62]MAIN[19][62]MAIN[18][60]MAIN[19][60]MAIN[18][62]HEX_E0[7]
Source
0000000off
0010001OMUX_S5
0010010OUT_FAN[1]
0010100HEX_E6[7]
0011000HEX_E6[9]
0100001HEX_S3[7]
0100010OMUX_N11
0100100LH[0]
0101000HEX_N3[7]
1000001LH[12]
1000010OUT_FAN[6]
1000100HEX_S6[9]
1001000HEX_N6[6]
virtex2 INT_BRAM switchbox INT muxes HEX_E0[8]
BitsDestination
MAIN[21][68]MAIN[21][70]MAIN[20][71]MAIN[19][71]MAIN[18][69]MAIN[19][69]MAIN[18][71]HEX_E0[8]
Source
0000000off
0010001OMUX_ES7
0010010LH[6]
0010100HEX_N3[8]
0011000HEX_S3[8]
0100001OUT_FAN[0]
0100010OMUX_E13
0100100HEX_E6[8]
0101000HEX_E6_S[0]
1000001LH[18]
1000010OUT_FAN[7]
1000100HEX_S7[0]
1001000HEX_N6[7]
virtex2 INT_BRAM switchbox INT muxes HEX_E0[9]
BitsDestination
MAIN[20][77]MAIN[20][78]MAIN[20][76]MAIN[19][78]MAIN[18][76]MAIN[18][78]MAIN[19][76]HEX_E0[9]
Source
0000000off
0010001OMUX[15]
0010010LH[12]
0010100HEX_S7[1]
0011000HEX_N6[8]
0100001OMUX_S0
0100010OMUX_S2
0100100HEX_E6[9]
0101000HEX_E6_S[1]
1000001OMUX_N15
1000010HEX_S3[9]
1000100LH[0]
1001000HEX_N3[9]
virtex2 INT_BRAM switchbox INT muxes HEX_S0[0]
BitsDestination
MAIN[20][3]MAIN[21][2]MAIN[21][0]MAIN[19][3]MAIN[18][1]MAIN[18][3]MAIN[19][1]HEX_S0[0]
Source
0000000off
0010001OMUX[0]
0010010LV[0]
0010100HEX_E6[1]
0011000HEX_W6_N[8]
0100001OMUX[2]
0100010OUT_FAN[3]
0100100HEX_S6[0]
0101000HEX_S6[2]
1000001LV[12]
1000010OMUX_S0
1000100HEX_W3[0]
1001000HEX_E3[0]
virtex2 INT_BRAM switchbox INT muxes HEX_S0[1]
BitsDestination
MAIN[20][8]MAIN[20][9]MAIN[20][10]MAIN[18][8]MAIN[19][10]MAIN[19][8]MAIN[18][10]HEX_S0[1]
Source
0000000off
0010001OMUX[2]
0010010OUT_FAN[2]
0010100HEX_S6[3]
0011000HEX_S6[1]
0100001HEX_E3[1]
0100010OMUX_E2
0100100HEX_W3[1]
0101000LV[18]
1000001LV[6]
1000010OUT_FAN[4]
1000100HEX_W6_N[9]
1001000HEX_E6[2]
virtex2 INT_BRAM switchbox INT muxes HEX_S0[2]
BitsDestination
MAIN[21][16]MAIN[20][19]MAIN[21][18]MAIN[19][19]MAIN[18][17]MAIN[19][17]MAIN[18][19]HEX_S0[2]
Source
0000000off
0010001OMUX[4]
0010010OMUX_S4
0010100HEX_S6[2]
0011000HEX_S6[4]
0100001OMUX[6]
0100010LV[12]
0100100HEX_W3[2]
0101000HEX_E3[2]
1000001LV[0]
1000010OUT_FAN[5]
1000100HEX_E6[3]
1001000HEX_W6[0]
virtex2 INT_BRAM switchbox INT muxes HEX_S0[3]
BitsDestination
MAIN[20][24]MAIN[20][26]MAIN[20][25]MAIN[18][24]MAIN[19][26]MAIN[18][26]MAIN[19][24]HEX_S0[3]
Source
0000000off
0010001OMUX[6]
0010010HEX_E3[3]
0010100HEX_W3[3]
0011000LV[18]
0100001OUT_FAN[4]
0100010OMUX_W6
0100100HEX_S6[5]
0101000HEX_S6[3]
1000001OUT_FAN[3]
1000010LV[6]
1000100HEX_W6[1]
1001000HEX_E6[4]
virtex2 INT_BRAM switchbox INT muxes HEX_S0[4]
BitsDestination
MAIN[21][32]MAIN[21][34]MAIN[20][35]MAIN[19][35]MAIN[18][33]MAIN[19][33]MAIN[18][35]HEX_S0[4]
Source
0000000off
0010001OMUX_WS1
0010010LV[12]
0010100HEX_W3[4]
0011000HEX_E3[4]
0100001OUT_FAN[5]
0100010OMUX_SE3
0100100HEX_S6[4]
0101000HEX_S6[6]
1000001LV[0]
1000010OUT_FAN[2]
1000100HEX_E6[5]
1001000HEX_W6[2]
virtex2 INT_BRAM switchbox INT muxes HEX_S0[5]
BitsDestination
MAIN[20][40]MAIN[20][41]MAIN[20][42]MAIN[18][40]MAIN[19][42]MAIN[19][40]MAIN[18][42]HEX_S0[5]
Source
0000000off
0010001OMUX_S3
0010010OUT_FAN[1]
0010100HEX_S6[7]
0011000HEX_S6[5]
0100001HEX_E3[5]
0100010OMUX_E8
0100100HEX_W3[5]
0101000LV[18]
1000001LV[6]
1000010OUT_FAN[6]
1000100HEX_W6[3]
1001000HEX_E6[6]
virtex2 INT_BRAM switchbox INT muxes HEX_S0[6]
BitsDestination
MAIN[21][48]MAIN[21][50]MAIN[20][51]MAIN[19][51]MAIN[18][49]MAIN[19][49]MAIN[18][51]HEX_S0[6]
Source
0000000off
0010001OMUX_SW5
0010010LV[12]
0010100HEX_W3[6]
0011000HEX_E3[6]
0100001OUT_FAN[0]
0100010OMUX_ES7
0100100HEX_S6[6]
0101000HEX_S6[8]
1000001LV[0]
1000010OUT_FAN[7]
1000100HEX_E6[7]
1001000HEX_W6[4]
virtex2 INT_BRAM switchbox INT muxes HEX_S0[7]
BitsDestination
MAIN[20][57]MAIN[20][58]MAIN[20][56]MAIN[18][56]MAIN[19][58]MAIN[18][58]MAIN[19][56]HEX_S0[7]
Source
0000000off
0010001OMUX[11]
0010010LV[6]
0010100HEX_W6[5]
0011000HEX_E6[8]
0100001OUT_FAN[6]
0100010OMUX_WS1
0100100HEX_S6[9]
0101000HEX_S6[7]
1000001OMUX_SE3
1000010HEX_E3[7]
1000100HEX_W3[7]
1001000LV[18]
virtex2 INT_BRAM switchbox INT muxes HEX_S0[8]
BitsDestination
MAIN[21][64]MAIN[20][67]MAIN[21][66]MAIN[19][67]MAIN[18][65]MAIN[18][67]MAIN[19][65]HEX_S0[8]
Source
0000000off
0010001OMUX_S5
0010010OUT_FAN[7]
0010100HEX_S6[8]
0011000HEX_S7[0]
0100001LV[12]
0100010OMUX_W14
0100100HEX_W3[8]
0101000HEX_E3[8]
1000001OUT_FAN[1]
1000010LV[0]
1000100HEX_E6[9]
1001000HEX_W6[6]
virtex2 INT_BRAM switchbox INT muxes HEX_S0[9]
BitsDestination
MAIN[20][72]MAIN[20][73]MAIN[20][74]MAIN[18][72]MAIN[19][74]MAIN[18][74]MAIN[19][72]HEX_S0[9]
Source
0000000off
0010001OMUX[15]
0010010OMUX_SW5
0010100HEX_S7[1]
0011000HEX_S6[9]
0100001OMUX_ES7
0100010HEX_E3[9]
0100100HEX_W3[9]
0101000LV[18]
1000001OUT_FAN[0]
1000010LV[6]
1000100HEX_W6[7]
1001000HEX_E6_S[0]
virtex2 INT_BRAM switchbox INT muxes HEX_N0[0]
BitsDestination
MAIN[20][1]MAIN[20][2]MAIN[20][0]MAIN[18][0]MAIN[19][2]MAIN[18][2]MAIN[19][0]HEX_N0[0]
Source
0000000off
0010001OMUX[0]
0010010LV[0]
0010100HEX_W6_N[8]
0011000HEX_E6[1]
0100001OUT_FAN[3]
0100010OMUX_EN8
0100100HEX_N6[0]
0101000HEX_N7[8]
1000001OMUX_N13
1000010HEX_E3[0]
1000100HEX_W3[0]
1001000LV[12]
virtex2 INT_BRAM switchbox INT muxes HEX_N0[1]
BitsDestination
MAIN[21][8]MAIN[21][10]MAIN[20][11]MAIN[19][11]MAIN[18][9]MAIN[19][9]MAIN[18][11]HEX_N0[1]
Source
0000000off
0010001OMUX_N10
0010010LV[18]
0010100HEX_W3[1]
0011000HEX_E3[1]
0100001OUT_FAN[2]
0100010OMUX_NW10
0100100HEX_N7[9]
0101000HEX_N6[1]
1000001LV[6]
1000010OUT_FAN[4]
1000100HEX_E6[2]
1001000HEX_W6_N[9]
virtex2 INT_BRAM switchbox INT muxes HEX_N0[2]
BitsDestination
MAIN[20][16]MAIN[20][17]MAIN[20][18]MAIN[18][16]MAIN[19][18]MAIN[18][18]MAIN[19][16]HEX_N0[2]
Source
0000000off
0010001OMUX[4]
0010010OMUX_NE12
0010100HEX_N6[2]
0011000HEX_N6[0]
0100001OMUX_W1
0100010HEX_E3[2]
0100100HEX_W3[2]
0101000LV[12]
1000001OUT_FAN[5]
1000010LV[0]
1000100HEX_W6[0]
1001000HEX_E6[3]
virtex2 INT_BRAM switchbox INT muxes HEX_N0[3]
BitsDestination
MAIN[21][24]MAIN[21][26]MAIN[20][27]MAIN[19][27]MAIN[18][25]MAIN[19][25]MAIN[18][27]HEX_N0[3]
Source
0000000off
0010001OMUX_EN8
0010010LV[18]
0010100HEX_W3[3]
0011000HEX_E3[3]
0100001OUT_FAN[4]
0100010OMUX_WN14
0100100HEX_N6[1]
0101000HEX_N6[3]
1000001LV[6]
1000010OUT_FAN[3]
1000100HEX_E6[4]
1001000HEX_W6[1]
virtex2 INT_BRAM switchbox INT muxes HEX_N0[4]
BitsDestination
MAIN[20][32]MAIN[20][33]MAIN[20][34]MAIN[18][32]MAIN[19][34]MAIN[19][32]MAIN[18][34]HEX_N0[4]
Source
0000000off
0010001OMUX_E7
0010010OUT_FAN[5]
0010100HEX_N6[4]
0011000HEX_N6[2]
0100001HEX_E3[4]
0100010OMUX_NW10
0100100HEX_W3[4]
0101000LV[12]
1000001LV[0]
1000010OUT_FAN[2]
1000100HEX_W6[2]
1001000HEX_E6[5]
virtex2 INT_BRAM switchbox INT muxes HEX_N0[5]
BitsDestination
MAIN[21][40]MAIN[20][43]MAIN[21][42]MAIN[19][43]MAIN[18][41]MAIN[18][43]MAIN[19][41]HEX_N0[5]
Source
0000000off
0010001OMUX_N12
0010010OUT_FAN[1]
0010100HEX_N6[3]
0011000HEX_N6[5]
0100001LV[18]
0100010OMUX_NE12
0100100HEX_W3[5]
0101000HEX_E3[5]
1000001OUT_FAN[6]
1000010LV[6]
1000100HEX_E6[6]
1001000HEX_W6[3]
virtex2 INT_BRAM switchbox INT muxes HEX_N0[6]
BitsDestination
MAIN[20][48]MAIN[20][49]MAIN[20][50]MAIN[18][48]MAIN[19][50]MAIN[19][48]MAIN[18][50]HEX_N0[6]
Source
0000000off
0010001OMUX[9]
0010010OUT_FAN[0]
0010100HEX_N6[6]
0011000HEX_N6[4]
0100001HEX_E3[6]
0100010OMUX_WN14
0100100HEX_W3[6]
0101000LV[12]
1000001LV[0]
1000010OUT_FAN[7]
1000100HEX_W6[4]
1001000HEX_E6[7]
virtex2 INT_BRAM switchbox INT muxes HEX_N0[7]
BitsDestination
MAIN[20][59]MAIN[21][58]MAIN[21][56]MAIN[19][59]MAIN[18][57]MAIN[18][59]MAIN[19][57]HEX_N0[7]
Source
0000000off
0010001OMUX[11]
0010010LV[6]
0010100HEX_E6[8]
0011000HEX_W6[5]
0100001OMUX_W9
0100010OUT_FAN[6]
0100100HEX_N6[5]
0101000HEX_N6[7]
1000001LV[18]
1000010OMUX_N11
1000100HEX_W3[7]
1001000HEX_E3[7]
virtex2 INT_BRAM switchbox INT muxes HEX_N0[8]
BitsDestination
MAIN[20][64]MAIN[20][66]MAIN[20][65]MAIN[18][64]MAIN[19][66]MAIN[18][66]MAIN[19][64]HEX_N0[8]
Source
0000000off
0010001OMUX[9]
0010010HEX_E3[8]
0010100HEX_W3[8]
0011000LV[12]
0100001OUT_FAN[7]
0100010OMUX_E13
0100100HEX_N6[8]
0101000HEX_N6[6]
1000001OUT_FAN[1]
1000010LV[0]
1000100HEX_W6[6]
1001000HEX_E6[9]
virtex2 INT_BRAM switchbox INT muxes HEX_N0[9]
BitsDestination
MAIN[21][72]MAIN[20][75]MAIN[21][74]MAIN[19][75]MAIN[18][73]MAIN[18][75]MAIN[19][73]HEX_N0[9]
Source
0000000off
0010001OMUX[13]
0010010OMUX[15]
0010100HEX_N6[7]
0011000HEX_N6[9]
0100001LV[18]
0100010OMUX_N15
0100100HEX_W3[9]
0101000HEX_E3[9]
1000001OUT_FAN[0]
1000010LV[6]
1000100HEX_E6_S[0]
1001000HEX_W6[7]
virtex2 INT_BRAM switchbox INT muxes LH[0]
BitsDestination
MAIN[21][47]MAIN[21][49]MAIN[21][51]LH[0]
Source
000off
001DBL_W1[5]
011OMUX_S4
101DBL_E1[6]
111OMUX[11]
virtex2 INT_BRAM switchbox INT muxes LH[6]
BitsDestination
MAIN[21][31]MAIN[21][33]MAIN[21][29]LH[6]
Source
000off
001OMUX[4]
011OMUX_N15
101DBL_E1[4]
111DBL_W1[3]
virtex2 INT_BRAM switchbox INT muxes LH[12]
BitsDestination
MAIN[21][41]MAIN[21][45]MAIN[21][43]LH[12]
Source
000off
001DBL_W1[5]
011OMUX_S4
101DBL_E1[6]
111OMUX[11]
virtex2 INT_BRAM switchbox INT muxes LH[18]
BitsDestination
MAIN[21][39]MAIN[21][37]MAIN[21][35]LH[18]
Source
000off
001OMUX[4]
011OMUX_N15
101DBL_E1[4]
111DBL_W1[3]
virtex2 INT_BRAM switchbox INT muxes LV[0]
BitsDestination
MAIN[21][7]MAIN[21][9]MAIN[21][19]MAIN[21][25]MAIN[21][21]MAIN[21][11]MAIN[21][5]LV[0]
Source
0000000off
0000011HEX_E1[1]
0000101OMUX_E2
0001001DBL_W1[1]
0010001HEX_E6[1]
0100001HEX_E4[1]
1000011OMUX[0]
1000101HEX_E2[1]
1001001HEX_E5[1]
1010001DBL_E1[2]
1100001HEX_E3[1]
virtex2 INT_BRAM switchbox INT muxes LV[6]
BitsDestination
MAIN[21][73]MAIN[21][61]MAIN[21][55]MAIN[21][69]MAIN[21][71]MAIN[21][65]MAIN[21][75]LV[6]
Source
0000000off
0000011OMUX_W9
0000101DBL_W1[7]
0001001HEX_W5[7]
0010001HEX_W3[7]
0100001HEX_W4[7]
1000011OMUX[15]
1000101HEX_W2[7]
1001001DBL_E1[8]
1010001HEX_W0[7]
1100001HEX_W1[7]
virtex2 INT_BRAM switchbox INT muxes LV[12]
BitsDestination
MAIN[21][13]MAIN[21][1]MAIN[21][27]MAIN[21][23]MAIN[21][17]MAIN[21][3]MAIN[21][15]LV[12]
Source
0000000off
0000011HEX_E1[1]
0000101OMUX_E2
0001001DBL_W1[1]
0010001HEX_E6[1]
0100001HEX_E4[1]
1000011OMUX[0]
1000101HEX_E2[1]
1001001HEX_E5[1]
1010001DBL_E1[2]
1100001HEX_E3[1]
virtex2 INT_BRAM switchbox INT muxes LV[18]
BitsDestination
MAIN[21][67]MAIN[21][53]MAIN[21][57]MAIN[21][77]MAIN[21][59]MAIN[21][79]MAIN[21][63]LV[18]
Source
0000000off
0000011OMUX_W9
0000101DBL_W1[7]
0001001HEX_W5[7]
0010001HEX_W3[7]
0100001HEX_W4[7]
1000011OMUX[15]
1000101HEX_W2[7]
1001001DBL_E1[8]
1010001HEX_W0[7]
1100001HEX_W1[7]
virtex2 INT_BRAM switchbox INT muxes IMUX_CLK[1]
BitsDestination
MAIN[5][47]MAIN[5][48]MAIN[5][50]MAIN[4][48]MAIN[4][50]MAIN[4][46]MAIN[4][44]MAIN[5][46]MAIN[5][44]MAIN[4][40]IMUX_CLK[1]
Source
0000000000PULLUP
0001000001GCLK[0]
0001000010GCLK[1]
0001000100GCLK[2]
0001001000HEX_N0[6]
0001010000HEX_N3[6]
0001100000HEX_S4[6]
0010000001GCLK[3]
0010000010HEX_S3[6]
0010000100GCLK[4]
0010001000HEX_S6[6]
0010010000HEX_N1[6]
0010100000HEX_N4[6]
0100000001GCLK[5]
0100000010HEX_N2[6]
0100000100HEX_N5[6]
0100001000GCLK[6]
0100010000HEX_S5[6]
0100100000HEX_S2[6]
1000000001GCLK[7]
1000000010DBL_W1[5]
1000000100DBL_E0[5]
1000001000DBL_E1[5]
1000010000DBL_W2[5]
1000100000HEX_S1[6]
virtex2 INT_BRAM switchbox INT muxes IMUX_CLK[2]
BitsDestination
MAIN[5][54]MAIN[5][53]MAIN[5][51]MAIN[4][53]MAIN[4][51]MAIN[4][55]MAIN[4][57]MAIN[5][55]MAIN[5][57]MAIN[4][61]IMUX_CLK[2]
Source
0000000000PULLUP
0001000001GCLK[0]
0001000010GCLK[1]
0001000100GCLK[2]
0001001000HEX_N0[6]
0001010000HEX_N3[6]
0001100000HEX_S4[6]
0010000001GCLK[3]
0010000010HEX_S3[6]
0010000100GCLK[4]
0010001000HEX_S6[6]
0010010000HEX_N1[6]
0010100000HEX_N4[6]
0100000001GCLK[5]
0100000010HEX_N2[6]
0100000100HEX_N5[6]
0100001000GCLK[6]
0100010000HEX_S5[6]
0100100000HEX_S2[6]
1000000001GCLK[7]
1000000010DBL_W2[6]
1000000100DBL_E0[6]
1000001000DBL_E1[6]
1000010000DBL_W1[6]
1000100000HEX_S1[6]
virtex2 INT_BRAM switchbox INT muxes IMUX_CLK[3]
BitsDestination
MAIN[5][60]MAIN[5][59]MAIN[5][61]MAIN[4][59]MAIN[5][52]MAIN[4][54]MAIN[4][58]MAIN[5][56]MAIN[4][56]MAIN[5][58]IMUX_CLK[3]
Source
0000000000PULLUP
0001000001GCLK[0]
0001000010GCLK[1]
0001000100GCLK[2]
0001001000HEX_N0[6]
0001010000HEX_N3[6]
0001100000HEX_S4[6]
0010000001GCLK[3]
0010000010HEX_S3[6]
0010000100GCLK[4]
0010001000HEX_S6[6]
0010010000HEX_N1[6]
0010100000HEX_N4[6]
0100000001GCLK[5]
0100000010HEX_N2[6]
0100000100HEX_N5[6]
0100001000GCLK[6]
0100010000HEX_S5[6]
0100100000HEX_S2[6]
1000000001GCLK[7]
1000000010DBL_W2[6]
1000000100DBL_E0[6]
1000001000DBL_E1[6]
1000010000DBL_W1[6]
1000100000HEX_S1[6]
virtex2 INT_BRAM switchbox INT muxes IMUX_SR[0]
BitsDestination
MAIN[5][3]MAIN[4][3]MAIN[5][5]MAIN[4][5]MAIN[5][1]MAIN[5][2]MAIN[4][2]MAIN[5][0]IMUX_SR[0]
Source
00000000PULLUP
00010001DBL_W1[0]
00010010HEX_N1[0]
00010100HEX_N5[0]
00011000HEX_S4[0]
00100001DBL_W2[0]
00100010HEX_S5[0]
00100100HEX_S1[0]
00101000HEX_N3[0]
01000001HEX_N2[0]
01000010DBL_E0[0]
01000100HEX_S2[0]
01001000HEX_N0[0]
10000001HEX_S3[0]
10000010DBL_E1[0]
10000100HEX_N4[0]
10001000HEX_S6[0]
virtex2 INT_BRAM switchbox INT muxes IMUX_SR[1]
BitsDestination
MAIN[4][12]MAIN[5][12]MAIN[5][14]MAIN[4][14]MAIN[5][16]MAIN[5][15]MAIN[5][17]MAIN[4][15]IMUX_SR[1]
Source
00000000PULLUP
00010001DBL_W1[1]
00010010HEX_N2[0]
00010100HEX_S2[0]
00011000HEX_N0[0]
00100001DBL_W2[1]
00100010HEX_S3[0]
00100100HEX_N4[0]
00101000HEX_S6[0]
01000001HEX_S5[0]
01000010DBL_E0[1]
01000100HEX_S1[0]
01001000HEX_N3[0]
10000001HEX_N1[0]
10000010DBL_E1[1]
10000100HEX_N5[0]
10001000HEX_S4[0]
virtex2 INT_BRAM switchbox INT muxes IMUX_SR[2]
BitsDestination
MAIN[4][0]MAIN[4][4]MAIN[4][8]MAIN[5][4]MAIN[5][7]MAIN[5][8]MAIN[4][6]MAIN[5][6]IMUX_SR[2]
Source
00000000PULLUP
00010001DBL_W1[0]
00010010HEX_N1[0]
00010100HEX_N5[0]
00011000HEX_S4[0]
00100001DBL_W2[0]
00100010HEX_S5[0]
00100100HEX_S1[0]
00101000HEX_N3[0]
01000001HEX_N2[0]
01000010DBL_E0[0]
01000100HEX_S2[0]
01001000HEX_N0[0]
10000001HEX_S3[0]
10000010DBL_E1[0]
10000100HEX_N4[0]
10001000HEX_S6[0]
virtex2 INT_BRAM switchbox INT muxes IMUX_CE[1]
BitsDestination
MAIN[4][62]MAIN[4][66]MAIN[4][70]MAIN[5][66]MAIN[5][69]MAIN[5][70]MAIN[4][68]MAIN[5][68]IMUX_CE[1]
Source
00000000PULLUP
00010001DBL_W1[8]
00010010HEX_N0[9]
00010100HEX_N2[9]
00011000HEX_N3[9]
00100001DBL_W2[8]
00100010HEX_S6[9]
00100100HEX_S4[9]
00101000HEX_S3[9]
01000001HEX_S1[9]
01000010DBL_E0[8]
01000100HEX_S2[9]
01001000HEX_S5[9]
10000001HEX_N5[9]
10000010DBL_E1[8]
10000100HEX_N4[9]
10001000HEX_N1[9]
virtex2 INT_BRAM switchbox INT muxes IMUX_CE[2]
BitsDestination
MAIN[5][75]MAIN[4][71]MAIN[4][79]MAIN[4][75]MAIN[5][72]MAIN[5][71]MAIN[5][73]MAIN[4][73]IMUX_CE[2]
Source
00000000PULLUP
00010001DBL_W1[9]
00010010HEX_S1[9]
00010100HEX_S2[9]
00011000HEX_S5[9]
00100001DBL_W2[9]
00100010HEX_N5[9]
00100100HEX_N4[9]
00101000HEX_N1[9]
01000001HEX_S6[9]
01000010DBL_E0[9]
01000100HEX_S4[9]
01001000HEX_S3[9]
10000001HEX_N0[9]
10000010DBL_E1[9]
10000100HEX_N2[9]
10001000HEX_N3[9]
virtex2 INT_BRAM switchbox INT muxes IMUX_CE[3]
BitsDestination
MAIN[4][74]MAIN[5][74]MAIN[5][76]MAIN[4][76]MAIN[5][78]MAIN[5][77]MAIN[5][79]MAIN[4][77]IMUX_CE[3]
Source
00000000PULLUP
00010001DBL_W1[9]
00010010HEX_S1[9]
00010100HEX_S2[9]
00011000HEX_S5[9]
00100001DBL_W2[9]
00100010HEX_N5[9]
00100100HEX_N4[9]
00101000HEX_N1[9]
01000001HEX_S6[9]
01000010DBL_E0[9]
01000100HEX_S4[9]
01001000HEX_S3[9]
10000001HEX_N0[9]
10000010DBL_E1[9]
10000100HEX_N2[9]
10001000HEX_N3[9]
virtex2 INT_BRAM switchbox INT muxes IMUX_TS[0]
BitsDestination
MAIN[4][37]MAIN[5][39]MAIN[5][37]MAIN[5][38]MAIN[5][30]MAIN[4][32]MAIN[5][34]MAIN[4][34]MAIN[4][36]IMUX_TS[0]
Source
000000000PULLUP
000100001DBL_W1[4]
000100010HEX_N2[3]
000100100DBL_E0[4]
000101000DBL_E1[4]
000110000HEX_S1[3]
001000010DBL_W2[4]
001000100HEX_N5[3]
001001000HEX_S5[3]
001010000HEX_S2[3]
010000001HEX_S6[3]
010000010HEX_S3[3]
010001000HEX_N1[3]
010010000HEX_N4[3]
100000001HEX_N0[3]
100001000HEX_N3[3]
100010000HEX_S4[3]
virtex2 INT_BRAM switchbox INT muxes IMUX_TS[1]
BitsDestination
MAIN[4][31]MAIN[5][29]MAIN[5][31]MAIN[5][32]MAIN[4][29]MAIN[4][33]MAIN[5][33]MAIN[5][35]MAIN[4][35]IMUX_TS[1]
Source
000000000PULLUP
000100001DBL_W1[4]
000100010HEX_N2[3]
000100100DBL_E0[4]
000101000DBL_E1[4]
000110000HEX_S1[3]
001000010DBL_W2[4]
001000100HEX_N5[3]
001001000HEX_S5[3]
001010000HEX_S2[3]
010000001HEX_S6[3]
010000010HEX_S3[3]
010001000HEX_N1[3]
010010000HEX_N4[3]
100000001HEX_N0[3]
100001000HEX_N3[3]
100010000HEX_S4[3]
virtex2 INT_BRAM switchbox INT muxes IMUX_G0_FAN[0]
BitsDestination
MAIN[9][16]MAIN[9][19]MAIN[8][19]MAIN[8][16]MAIN[10][17]MAIN[10][19]MAIN[11][19]MAIN[11][17]MAIN[13][17]MAIN[12][19]MAIN[13][19]MAIN[12][17]IMUX_G0_FAN[0]
Source
000000000000off
000100000001OMUX_W1
000100000010OMUX_E2
000100000100OMUX_NW10
000100001000OMUX_N10
000100010000DBL_S1[0]
000100100000IMUX_G1_FAN[0]
000101000000DBL_N2[0]
000110000000IMUX_G2_FAN[0]
001000000001DBL_E0[1]
001000000010DBL_S0[0]
001000000100OMUX_EN8
001000001000DBL_W0[0]
001000010000DBL_N1[1]
001000100000DBL_S1[2]
001001000000DBL_W2[1]
001010000000DBL_S1[1]
010000000001DBL_E2[1]
010000000010DBL_S0[2]
010000000100DBL_E2[0]
010000001000DBL_E2[2]
010000010000DBL_W1[0]
010000100000OUT_FAN[2]
010001000000DBL_E1[1]
010010000000OUT_FAN[5]
100000000001DBL_S2[0]
100000000010DBL_S2[2]
100000000100DBL_N0[1]
100000001000DBL_S2[1]
100000010000DBL_E1[0]
100000100000DBL_W1[1]
100001000000DBL_W2[0]
100010000000DBL_N1[0]
virtex2 INT_BRAM switchbox INT muxes IMUX_G0_FAN[1]
BitsDestination
MAIN[9][17]MAIN[9][18]MAIN[8][18]MAIN[8][17]MAIN[10][16]MAIN[10][18]MAIN[11][18]MAIN[11][16]MAIN[13][16]MAIN[12][18]MAIN[13][18]MAIN[12][16]IMUX_G0_FAN[1]
Source
000000000000off
000100000001OMUX_W1
000100000010OMUX_E2
000100000100OMUX_NW10
000100001000OMUX_N10
000100010000DBL_S1[0]
000100100000IMUX_G1_FAN[0]
000101000000DBL_N2[0]
000110000000IMUX_G2_FAN[0]
001000000001DBL_E0[1]
001000000010DBL_S0[0]
001000000100OMUX_EN8
001000001000DBL_W0[0]
001000010000DBL_N1[1]
001000100000DBL_S1[2]
001001000000DBL_W2[1]
001010000000DBL_S1[1]
010000000001DBL_E2[1]
010000000010DBL_S0[2]
010000000100DBL_E2[0]
010000001000DBL_E2[2]
010000010000DBL_W1[0]
010000100000OUT_FAN[2]
010001000000DBL_E1[1]
010010000000OUT_FAN[5]
100000000001DBL_S2[0]
100000000010DBL_S2[2]
100000000100DBL_N0[1]
100000001000DBL_S2[1]
100000010000DBL_E1[0]
100000100000DBL_W1[1]
100001000000DBL_W2[0]
100010000000DBL_N1[0]
virtex2 INT_BRAM switchbox INT muxes IMUX_G0_DATA[2]
BitsDestination
MAIN[9][7]MAIN[9][4]MAIN[8][4]MAIN[8][7]MAIN[10][6]MAIN[10][4]MAIN[11][4]MAIN[11][6]MAIN[13][6]MAIN[12][4]MAIN[13][4]MAIN[12][6]IMUX_G0_DATA[2]
Source
000000000000PULLUP
000100000001OMUX_W1
000100000010OMUX_E2
000100000100OMUX_NW10
000100001000OMUX_N10
000100010000DBL_S1[0]
000100100000IMUX_G1_FAN[0]
000101000000DBL_N2[0]
000110000000IMUX_G2_FAN[0]
001000000001DBL_E0[1]
001000000010DBL_S0[0]
001000000100OMUX_EN8
001000001000DBL_W0[0]
001000010000DBL_N1[1]
001000100000DBL_S1[2]
001001000000DBL_W2[1]
001010000000DBL_S1[1]
010000000001DBL_E2[1]
010000000010DBL_S0[2]
010000000100DBL_E2[0]
010000001000DBL_E2[2]
010000010000DBL_W1[0]
010000100000OUT_FAN[2]
010001000000DBL_E1[1]
010010000000OUT_FAN[5]
100000000001DBL_S2[0]
100000000010DBL_S2[2]
100000000100DBL_N0[1]
100000001000DBL_S2[1]
100000010000DBL_E1[0]
100000100000DBL_W1[1]
100001000000DBL_W2[0]
100010000000DBL_N1[0]
virtex2 INT_BRAM switchbox INT muxes IMUX_G0_DATA[3]
BitsDestination
MAIN[9][6]MAIN[9][5]MAIN[8][5]MAIN[8][6]MAIN[10][7]MAIN[10][5]MAIN[11][5]MAIN[11][7]MAIN[13][7]MAIN[12][5]MAIN[13][5]MAIN[12][7]IMUX_G0_DATA[3]
Source
000000000000PULLUP
000100000001OMUX_W1
000100000010OMUX_E2
000100000100OMUX_NW10
000100001000OMUX_N10
000100010000DBL_S1[0]
000100100000IMUX_G1_FAN[0]
000101000000DBL_N2[0]
000110000000IMUX_G2_FAN[0]
001000000001DBL_E0[1]
001000000010DBL_S0[0]
001000000100OMUX_EN8
001000001000DBL_W0[0]
001000010000DBL_N1[1]
001000100000DBL_S1[2]
001001000000DBL_W2[1]
001010000000DBL_S1[1]
010000000001DBL_E2[1]
010000000010DBL_S0[2]
010000000100DBL_E2[0]
010000001000DBL_E2[2]
010000010000DBL_W1[0]
010000100000OUT_FAN[2]
010001000000DBL_E1[1]
010010000000OUT_FAN[5]
100000000001DBL_S2[0]
100000000010DBL_S2[2]
100000000100DBL_N0[1]
100000001000DBL_S2[1]
100000010000DBL_E1[0]
100000100000DBL_W1[1]
100001000000DBL_W2[0]
100010000000DBL_N1[0]
virtex2 INT_BRAM switchbox INT muxes IMUX_G0_DATA[4]
BitsDestination
MAIN[9][8]MAIN[9][11]MAIN[8][11]MAIN[8][8]MAIN[10][9]MAIN[10][11]MAIN[11][11]MAIN[11][9]MAIN[13][9]MAIN[12][11]MAIN[13][11]MAIN[12][9]IMUX_G0_DATA[4]
Source
000000000000PULLUP
000100000001OMUX_W1
000100000010OMUX_E2
000100000100OMUX_NW10
000100001000OMUX_N10
000100010000DBL_S1[0]
000100100000IMUX_G1_FAN[0]
000101000000DBL_N2[0]
000110000000IMUX_G2_FAN[0]
001000000001DBL_E0[1]
001000000010DBL_S0[0]
001000000100OMUX_EN8
001000001000DBL_W0[0]
001000010000DBL_N1[1]
001000100000DBL_S1[2]
001001000000DBL_W2[1]
001010000000DBL_S1[1]
010000000001DBL_E2[1]
010000000010DBL_S0[2]
010000000100DBL_E2[0]
010000001000DBL_E2[2]
010000010000DBL_W1[0]
010000100000OUT_FAN[2]
010001000000DBL_E1[1]
010010000000OUT_FAN[5]
100000000001DBL_S2[0]
100000000010DBL_S2[2]
100000000100DBL_N0[1]
100000001000DBL_S2[1]
100000010000DBL_E1[0]
100000100000DBL_W1[1]
100001000000DBL_W2[0]
100010000000DBL_N1[0]
virtex2 INT_BRAM switchbox INT muxes IMUX_G0_DATA[5]
BitsDestination
MAIN[9][9]MAIN[9][10]MAIN[8][10]MAIN[8][9]MAIN[10][8]MAIN[10][10]MAIN[11][10]MAIN[11][8]MAIN[13][8]MAIN[12][10]MAIN[13][10]MAIN[12][8]IMUX_G0_DATA[5]
Source
000000000000PULLUP
000100000001OMUX_W1
000100000010OMUX_E2
000100000100OMUX_NW10
000100001000OMUX_N10
000100010000DBL_S1[0]
000100100000IMUX_G1_FAN[0]
000101000000DBL_N2[0]
000110000000IMUX_G2_FAN[0]
001000000001DBL_E0[1]
001000000010DBL_S0[0]
001000000100OMUX_EN8
001000001000DBL_W0[0]
001000010000DBL_N1[1]
001000100000DBL_S1[2]
001001000000DBL_W2[1]
001010000000DBL_S1[1]
010000000001DBL_E2[1]
010000000010DBL_S0[2]
010000000100DBL_E2[0]
010000001000DBL_E2[2]
010000010000DBL_W1[0]
010000100000OUT_FAN[2]
010001000000DBL_E1[1]
010010000000OUT_FAN[5]
100000000001DBL_S2[0]
100000000010DBL_S2[2]
100000000100DBL_N0[1]
100000001000DBL_S2[1]
100000010000DBL_E1[0]
100000100000DBL_W1[1]
100001000000DBL_W2[0]
100010000000DBL_N1[0]
virtex2 INT_BRAM switchbox INT muxes IMUX_G0_DATA[6]
BitsDestination
MAIN[9][15]MAIN[9][12]MAIN[8][12]MAIN[8][15]MAIN[10][14]MAIN[10][12]MAIN[11][12]MAIN[11][14]MAIN[13][14]MAIN[12][12]MAIN[13][12]MAIN[12][14]IMUX_G0_DATA[6]
Source
000000000000PULLUP
000100000001OMUX_W1
000100000010OMUX_E2
000100000100OMUX_NW10
000100001000OMUX_N10
000100010000DBL_S1[0]
000100100000IMUX_G1_FAN[0]
000101000000DBL_N2[0]
000110000000IMUX_G2_FAN[0]
001000000001DBL_E0[1]
001000000010DBL_S0[0]
001000000100OMUX_EN8
001000001000DBL_W0[0]
001000010000DBL_N1[1]
001000100000DBL_S1[2]
001001000000DBL_W2[1]
001010000000DBL_S1[1]
010000000001DBL_E2[1]
010000000010DBL_S0[2]
010000000100DBL_E2[0]
010000001000DBL_E2[2]
010000010000DBL_W1[0]
010000100000OUT_FAN[2]
010001000000DBL_E1[1]
010010000000OUT_FAN[5]
100000000001DBL_S2[0]
100000000010DBL_S2[2]
100000000100DBL_N0[1]
100000001000DBL_S2[1]
100000010000DBL_E1[0]
100000100000DBL_W1[1]
100001000000DBL_W2[0]
100010000000DBL_N1[0]
virtex2 INT_BRAM switchbox INT muxes IMUX_G0_DATA[7]
BitsDestination
MAIN[9][14]MAIN[9][13]MAIN[8][13]MAIN[8][14]MAIN[10][15]MAIN[10][13]MAIN[11][13]MAIN[11][15]MAIN[13][15]MAIN[12][13]MAIN[13][13]MAIN[12][15]IMUX_G0_DATA[7]
Source
000000000000PULLUP
000100000001OMUX_W1
000100000010OMUX_E2
000100000100OMUX_NW10
000100001000OMUX_N10
000100010000DBL_S1[0]
000100100000IMUX_G1_FAN[0]
000101000000DBL_N2[0]
000110000000IMUX_G2_FAN[0]
001000000001DBL_E0[1]
001000000010DBL_S0[0]
001000000100OMUX_EN8
001000001000DBL_W0[0]
001000010000DBL_N1[1]
001000100000DBL_S1[2]
001001000000DBL_W2[1]
001010000000DBL_S1[1]
010000000001DBL_E2[1]
010000000010DBL_S0[2]
010000000100DBL_E2[0]
010000001000DBL_E2[2]
010000010000DBL_W1[0]
010000100000OUT_FAN[2]
010001000000DBL_E1[1]
010010000000OUT_FAN[5]
100000000001DBL_S2[0]
100000000010DBL_S2[2]
100000000100DBL_N0[1]
100000001000DBL_S2[1]
100000010000DBL_E1[0]
100000100000DBL_W1[1]
100001000000DBL_W2[0]
100010000000DBL_N1[0]
virtex2 INT_BRAM switchbox INT muxes IMUX_G1_FAN[0]
BitsDestination
MAIN[9][23]MAIN[9][20]MAIN[8][23]MAIN[8][20]MAIN[10][22]MAIN[10][20]MAIN[11][22]MAIN[11][20]MAIN[13][20]MAIN[13][22]MAIN[12][22]MAIN[12][20]IMUX_G1_FAN[0]
Source
000000000000off
000100000001OMUX_W6
000100000010DBL_S0[4]
000100000100DBL_W0[4]
000100001000DBL_E0[3]
000100010000DBL_W1[2]
000100100000DBL_N1[4]
000101000000DBL_W2[4]
000110000000DBL_N2[4]
001000000001OMUX_N12
001000000010OMUX_E7
001000000100OMUX_NE12
001000001000OMUX_WN14
001000010000IMUX_G3_FAN[1]
001000100000DBL_S1[3]
001001000000DBL_E1[4]
001010000000IMUX_G0_FAN[1]
010000000001DBL_E2[4]
010000000010DBL_E2[3]
010000000100DBL_W2[3]
010000001000DBL_W0[2]
010000010000OUT_FAN[3]
010000100000DBL_W1[3]
010001000000DBL_W1[4]
010010000000OUT_FAN[4]
100000000001DBL_N0[3]
100000000010DBL_S2[4]
100000000100DBL_S2[3]
100000001000DBL_W2[2]
100000010000DBL_S1[4]
100000100000DBL_E1[3]
100001000000DBL_N2[2]
100010000000DBL_N1[3]
virtex2 INT_BRAM switchbox INT muxes IMUX_G1_FAN[1]
BitsDestination
MAIN[9][22]MAIN[9][21]MAIN[8][22]MAIN[8][21]MAIN[10][23]MAIN[10][21]MAIN[11][23]MAIN[11][21]MAIN[13][21]MAIN[13][23]MAIN[12][23]MAIN[12][21]IMUX_G1_FAN[1]
Source
000000000000off
000100000001OMUX_W6
000100000010DBL_S0[4]
000100000100DBL_W0[4]
000100001000DBL_E0[3]
000100010000DBL_W1[2]
000100100000DBL_N1[4]
000101000000DBL_W2[4]
000110000000DBL_N2[4]
001000000001OMUX_N12
001000000010OMUX_E7
001000000100OMUX_NE12
001000001000OMUX_WN14
001000010000IMUX_G3_FAN[1]
001000100000DBL_S1[3]
001001000000DBL_E1[4]
001010000000IMUX_G0_FAN[1]
010000000001DBL_E2[4]
010000000010DBL_E2[3]
010000000100DBL_W2[3]
010000001000DBL_W0[2]
010000010000OUT_FAN[3]
010000100000DBL_W1[3]
010001000000DBL_W1[4]
010010000000OUT_FAN[4]
100000000001DBL_N0[3]
100000000010DBL_S2[4]
100000000100DBL_S2[3]
100000001000DBL_W2[2]
100000010000DBL_S1[4]
100000100000DBL_E1[3]
100001000000DBL_N2[2]
100010000000DBL_N1[3]
virtex2 INT_BRAM switchbox INT muxes IMUX_G1_DATA[4]
BitsDestination
MAIN[9][31]MAIN[9][28]MAIN[8][31]MAIN[8][28]MAIN[10][30]MAIN[10][28]MAIN[11][30]MAIN[11][28]MAIN[13][28]MAIN[13][30]MAIN[12][30]MAIN[12][28]IMUX_G1_DATA[4]
Source
000000000000PULLUP
000100000001OMUX_W6
000100000010DBL_S0[4]
000100000100DBL_W0[4]
000100001000DBL_E0[3]
000100010000DBL_W1[2]
000100100000DBL_N1[4]
000101000000DBL_W2[4]
000110000000DBL_N2[4]
001000000001OMUX_N12
001000000010OMUX_E7
001000000100OMUX_NE12
001000001000OMUX_WN14
001000010000IMUX_G3_FAN[1]
001000100000DBL_S1[3]
001001000000DBL_E1[4]
001010000000IMUX_G0_FAN[1]
010000000001DBL_E2[4]
010000000010DBL_E2[3]
010000000100DBL_W2[3]
010000001000DBL_W0[2]
010000010000OUT_FAN[3]
010000100000DBL_W1[3]
010001000000DBL_W1[4]
010010000000OUT_FAN[4]
100000000001DBL_N0[3]
100000000010DBL_S2[4]
100000000100DBL_S2[3]
100000001000DBL_W2[2]
100000010000DBL_S1[4]
100000100000DBL_E1[3]
100001000000DBL_N2[2]
100010000000DBL_N1[3]
virtex2 INT_BRAM switchbox INT muxes IMUX_G1_DATA[5]
BitsDestination
MAIN[9][30]MAIN[9][29]MAIN[8][30]MAIN[8][29]MAIN[10][31]MAIN[10][29]MAIN[11][31]MAIN[11][29]MAIN[13][29]MAIN[13][31]MAIN[12][31]MAIN[12][29]IMUX_G1_DATA[5]
Source
000000000000PULLUP
000100000001OMUX_W6
000100000010DBL_S0[4]
000100000100DBL_W0[4]
000100001000DBL_E0[3]
000100010000DBL_W1[2]
000100100000DBL_N1[4]
000101000000DBL_W2[4]
000110000000DBL_N2[4]
001000000001OMUX_N12
001000000010OMUX_E7
001000000100OMUX_NE12
001000001000OMUX_WN14
001000010000IMUX_G3_FAN[1]
001000100000DBL_S1[3]
001001000000DBL_E1[4]
001010000000IMUX_G0_FAN[1]
010000000001DBL_E2[4]
010000000010DBL_E2[3]
010000000100DBL_W2[3]
010000001000DBL_W0[2]
010000010000OUT_FAN[3]
010000100000DBL_W1[3]
010001000000DBL_W1[4]
010010000000OUT_FAN[4]
100000000001DBL_N0[3]
100000000010DBL_S2[4]
100000000100DBL_S2[3]
100000001000DBL_W2[2]
100000010000DBL_S1[4]
100000100000DBL_E1[3]
100001000000DBL_N2[2]
100010000000DBL_N1[3]
virtex2 INT_BRAM switchbox INT muxes IMUX_G1_DATA[6]
BitsDestination
MAIN[9][24]MAIN[9][27]MAIN[8][24]MAIN[8][27]MAIN[10][25]MAIN[10][27]MAIN[11][25]MAIN[11][27]MAIN[13][27]MAIN[13][25]MAIN[12][25]MAIN[12][27]IMUX_G1_DATA[6]
Source
000000000000PULLUP
000100000001OMUX_W6
000100000010DBL_S0[4]
000100000100DBL_W0[4]
000100001000DBL_E0[3]
000100010000DBL_W1[2]
000100100000DBL_N1[4]
000101000000DBL_W2[4]
000110000000DBL_N2[4]
001000000001OMUX_N12
001000000010OMUX_E7
001000000100OMUX_NE12
001000001000OMUX_WN14
001000010000IMUX_G3_FAN[1]
001000100000DBL_S1[3]
001001000000DBL_E1[4]
001010000000IMUX_G0_FAN[1]
010000000001DBL_E2[4]
010000000010DBL_E2[3]
010000000100DBL_W2[3]
010000001000DBL_W0[2]
010000010000OUT_FAN[3]
010000100000DBL_W1[3]
010001000000DBL_W1[4]
010010000000OUT_FAN[4]
100000000001DBL_N0[3]
100000000010DBL_S2[4]
100000000100DBL_S2[3]
100000001000DBL_W2[2]
100000010000DBL_S1[4]
100000100000DBL_E1[3]
100001000000DBL_N2[2]
100010000000DBL_N1[3]
virtex2 INT_BRAM switchbox INT muxes IMUX_G1_DATA[7]
BitsDestination
MAIN[9][25]MAIN[9][26]MAIN[8][25]MAIN[8][26]MAIN[10][24]MAIN[10][26]MAIN[11][24]MAIN[11][26]MAIN[13][26]MAIN[13][24]MAIN[12][24]MAIN[12][26]IMUX_G1_DATA[7]
Source
000000000000PULLUP
000100000001OMUX_W6
000100000010DBL_S0[4]
000100000100DBL_W0[4]
000100001000DBL_E0[3]
000100010000DBL_W1[2]
000100100000DBL_N1[4]
000101000000DBL_W2[4]
000110000000DBL_N2[4]
001000000001OMUX_N12
001000000010OMUX_E7
001000000100OMUX_NE12
001000001000OMUX_WN14
001000010000IMUX_G3_FAN[1]
001000100000DBL_S1[3]
001001000000DBL_E1[4]
001010000000IMUX_G0_FAN[1]
010000000001DBL_E2[4]
010000000010DBL_E2[3]
010000000100DBL_W2[3]
010000001000DBL_W0[2]
010000010000OUT_FAN[3]
010000100000DBL_W1[3]
010001000000DBL_W1[4]
010010000000OUT_FAN[4]
100000000001DBL_N0[3]
100000000010DBL_S2[4]
100000000100DBL_S2[3]
100000001000DBL_W2[2]
100000010000DBL_S1[4]
100000100000DBL_E1[3]
100001000000DBL_N2[2]
100010000000DBL_N1[3]
virtex2 INT_BRAM switchbox INT muxes IMUX_G2_FAN[0]
BitsDestination
MAIN[9][56]MAIN[9][59]MAIN[8][59]MAIN[8][56]MAIN[10][57]MAIN[10][59]MAIN[11][59]MAIN[11][57]MAIN[13][59]MAIN[13][57]MAIN[12][59]MAIN[12][57]IMUX_G2_FAN[0]
Source
000000000000off
000100000001OMUX_WS1
000100000010OMUX_E8
000100000100OMUX_SE3
000100001000OMUX_W9
000100010000DBL_S1[5]
000100100000IMUX_G3_FAN[0]
000101000000DBL_N2[5]
000110000000IMUX_G0_FAN[0]
001000000001DBL_E0[5]
001000000010OMUX_S3
001000000100DBL_W0[6]
001000001000DBL_S0[6]
001000010000DBL_N1[6]
001000100000DBL_S1[7]
001001000000DBL_W2[6]
001010000000DBL_S1[6]
010000000001DBL_E2[6]
010000000010DBL_E2[5]
010000000100DBL_E2[7]
010000001000DBL_E0[7]
010000010000DBL_W1[5]
010000100000OUT_FAN[0]
010001000000DBL_E1[6]
010010000000OUT_FAN[7]
100000000001DBL_S2[5]
100000000010DBL_N0[5]
100000000100DBL_S2[6]
100000001000DBL_S2[7]
100000010000DBL_E1[5]
100000100000DBL_W1[6]
100001000000DBL_W2[5]
100010000000DBL_N1[5]
virtex2 INT_BRAM switchbox INT muxes IMUX_G2_FAN[1]
BitsDestination
MAIN[9][57]MAIN[9][58]MAIN[8][58]MAIN[8][57]MAIN[10][56]MAIN[10][58]MAIN[11][58]MAIN[11][56]MAIN[13][58]MAIN[13][56]MAIN[12][58]MAIN[12][56]IMUX_G2_FAN[1]
Source
000000000000off
000100000001OMUX_WS1
000100000010OMUX_E8
000100000100OMUX_SE3
000100001000OMUX_W9
000100010000DBL_S1[5]
000100100000IMUX_G3_FAN[0]
000101000000DBL_N2[5]
000110000000IMUX_G0_FAN[0]
001000000001DBL_E0[5]
001000000010OMUX_S3
001000000100DBL_W0[6]
001000001000DBL_S0[6]
001000010000DBL_N1[6]
001000100000DBL_S1[7]
001001000000DBL_W2[6]
001010000000DBL_S1[6]
010000000001DBL_E2[6]
010000000010DBL_E2[5]
010000000100DBL_E2[7]
010000001000DBL_E0[7]
010000010000DBL_W1[5]
010000100000OUT_FAN[0]
010001000000DBL_E1[6]
010010000000OUT_FAN[7]
100000000001DBL_S2[5]
100000000010DBL_N0[5]
100000000100DBL_S2[6]
100000001000DBL_S2[7]
100000010000DBL_E1[5]
100000100000DBL_W1[6]
100001000000DBL_W2[5]
100010000000DBL_N1[5]
virtex2 INT_BRAM switchbox INT muxes IMUX_G2_DATA[2]
BitsDestination
MAIN[9][47]MAIN[9][44]MAIN[8][44]MAIN[8][47]MAIN[10][46]MAIN[10][44]MAIN[11][44]MAIN[11][46]MAIN[13][44]MAIN[13][46]MAIN[12][44]MAIN[12][46]IMUX_G2_DATA[2]
Source
000000000000PULLUP
000100000001OMUX_WS1
000100000010OMUX_E8
000100000100OMUX_SE3
000100001000OMUX_W9
000100010000DBL_S1[5]
000100100000IMUX_G3_FAN[0]
000101000000DBL_N2[5]
000110000000IMUX_G0_FAN[0]
001000000001DBL_E0[5]
001000000010OMUX_S3
001000000100DBL_W0[6]
001000001000DBL_S0[6]
001000010000DBL_N1[6]
001000100000DBL_S1[7]
001001000000DBL_W2[6]
001010000000DBL_S1[6]
010000000001DBL_E2[6]
010000000010DBL_E2[5]
010000000100DBL_E2[7]
010000001000DBL_E0[7]
010000010000DBL_W1[5]
010000100000OUT_FAN[0]
010001000000DBL_E1[6]
010010000000OUT_FAN[7]
100000000001DBL_S2[5]
100000000010DBL_N0[5]
100000000100DBL_S2[6]
100000001000DBL_S2[7]
100000010000DBL_E1[5]
100000100000DBL_W1[6]
100001000000DBL_W2[5]
100010000000DBL_N1[5]
virtex2 INT_BRAM switchbox INT muxes IMUX_G2_DATA[3]
BitsDestination
MAIN[9][46]MAIN[9][45]MAIN[8][45]MAIN[8][46]MAIN[10][47]MAIN[10][45]MAIN[11][45]MAIN[11][47]MAIN[13][45]MAIN[13][47]MAIN[12][45]MAIN[12][47]IMUX_G2_DATA[3]
Source
000000000000PULLUP
000100000001OMUX_WS1
000100000010OMUX_E8
000100000100OMUX_SE3
000100001000OMUX_W9
000100010000DBL_S1[5]
000100100000IMUX_G3_FAN[0]
000101000000DBL_N2[5]
000110000000IMUX_G0_FAN[0]
001000000001DBL_E0[5]
001000000010OMUX_S3
001000000100DBL_W0[6]
001000001000DBL_S0[6]
001000010000DBL_N1[6]
001000100000DBL_S1[7]
001001000000DBL_W2[6]
001010000000DBL_S1[6]
010000000001DBL_E2[6]
010000000010DBL_E2[5]
010000000100DBL_E2[7]
010000001000DBL_E0[7]
010000010000DBL_W1[5]
010000100000OUT_FAN[0]
010001000000DBL_E1[6]
010010000000OUT_FAN[7]
100000000001DBL_S2[5]
100000000010DBL_N0[5]
100000000100DBL_S2[6]
100000001000DBL_S2[7]
100000010000DBL_E1[5]
100000100000DBL_W1[6]
100001000000DBL_W2[5]
100010000000DBL_N1[5]
virtex2 INT_BRAM switchbox INT muxes IMUX_G2_DATA[4]
BitsDestination
MAIN[9][48]MAIN[9][51]MAIN[8][51]MAIN[8][48]MAIN[10][49]MAIN[10][51]MAIN[11][51]MAIN[11][49]MAIN[13][51]MAIN[13][49]MAIN[12][51]MAIN[12][49]IMUX_G2_DATA[4]
Source
000000000000PULLUP
000100000001OMUX_WS1
000100000010OMUX_E8
000100000100OMUX_SE3
000100001000OMUX_W9
000100010000DBL_S1[5]
000100100000IMUX_G3_FAN[0]
000101000000DBL_N2[5]
000110000000IMUX_G0_FAN[0]
001000000001DBL_E0[5]
001000000010OMUX_S3
001000000100DBL_W0[6]
001000001000DBL_S0[6]
001000010000DBL_N1[6]
001000100000DBL_S1[7]
001001000000DBL_W2[6]
001010000000DBL_S1[6]
010000000001DBL_E2[6]
010000000010DBL_E2[5]
010000000100DBL_E2[7]
010000001000DBL_E0[7]
010000010000DBL_W1[5]
010000100000OUT_FAN[0]
010001000000DBL_E1[6]
010010000000OUT_FAN[7]
100000000001DBL_S2[5]
100000000010DBL_N0[5]
100000000100DBL_S2[6]
100000001000DBL_S2[7]
100000010000DBL_E1[5]
100000100000DBL_W1[6]
100001000000DBL_W2[5]
100010000000DBL_N1[5]
virtex2 INT_BRAM switchbox INT muxes IMUX_G2_DATA[5]
BitsDestination
MAIN[9][49]MAIN[9][50]MAIN[8][50]MAIN[8][49]MAIN[10][48]MAIN[10][50]MAIN[11][50]MAIN[11][48]MAIN[13][50]MAIN[13][48]MAIN[12][50]MAIN[12][48]IMUX_G2_DATA[5]
Source
000000000000PULLUP
000100000001OMUX_WS1
000100000010OMUX_E8
000100000100OMUX_SE3
000100001000OMUX_W9
000100010000DBL_S1[5]
000100100000IMUX_G3_FAN[0]
000101000000DBL_N2[5]
000110000000IMUX_G0_FAN[0]
001000000001DBL_E0[5]
001000000010OMUX_S3
001000000100DBL_W0[6]
001000001000DBL_S0[6]
001000010000DBL_N1[6]
001000100000DBL_S1[7]
001001000000DBL_W2[6]
001010000000DBL_S1[6]
010000000001DBL_E2[6]
010000000010DBL_E2[5]
010000000100DBL_E2[7]
010000001000DBL_E0[7]
010000010000DBL_W1[5]
010000100000OUT_FAN[0]
010001000000DBL_E1[6]
010010000000OUT_FAN[7]
100000000001DBL_S2[5]
100000000010DBL_N0[5]
100000000100DBL_S2[6]
100000001000DBL_S2[7]
100000010000DBL_E1[5]
100000100000DBL_W1[6]
100001000000DBL_W2[5]
100010000000DBL_N1[5]
virtex2 INT_BRAM switchbox INT muxes IMUX_G2_DATA[6]
BitsDestination
MAIN[9][55]MAIN[9][52]MAIN[8][52]MAIN[8][55]MAIN[10][54]MAIN[10][52]MAIN[11][52]MAIN[11][54]MAIN[13][52]MAIN[13][54]MAIN[12][52]MAIN[12][54]IMUX_G2_DATA[6]
Source
000000000000PULLUP
000100000001OMUX_WS1
000100000010OMUX_E8
000100000100OMUX_SE3
000100001000OMUX_W9
000100010000DBL_S1[5]
000100100000IMUX_G3_FAN[0]
000101000000DBL_N2[5]
000110000000IMUX_G0_FAN[0]
001000000001DBL_E0[5]
001000000010OMUX_S3
001000000100DBL_W0[6]
001000001000DBL_S0[6]
001000010000DBL_N1[6]
001000100000DBL_S1[7]
001001000000DBL_W2[6]
001010000000DBL_S1[6]
010000000001DBL_E2[6]
010000000010DBL_E2[5]
010000000100DBL_E2[7]
010000001000DBL_E0[7]
010000010000DBL_W1[5]
010000100000OUT_FAN[0]
010001000000DBL_E1[6]
010010000000OUT_FAN[7]
100000000001DBL_S2[5]
100000000010DBL_N0[5]
100000000100DBL_S2[6]
100000001000DBL_S2[7]
100000010000DBL_E1[5]
100000100000DBL_W1[6]
100001000000DBL_W2[5]
100010000000DBL_N1[5]
virtex2 INT_BRAM switchbox INT muxes IMUX_G2_DATA[7]
BitsDestination
MAIN[9][54]MAIN[9][53]MAIN[8][53]MAIN[8][54]MAIN[10][55]MAIN[10][53]MAIN[11][53]MAIN[11][55]MAIN[13][53]MAIN[13][55]MAIN[12][53]MAIN[12][55]IMUX_G2_DATA[7]
Source
000000000000PULLUP
000100000001OMUX_WS1
000100000010OMUX_E8
000100000100OMUX_SE3
000100001000OMUX_W9
000100010000DBL_S1[5]
000100100000IMUX_G3_FAN[0]
000101000000DBL_N2[5]
000110000000IMUX_G0_FAN[0]
001000000001DBL_E0[5]
001000000010OMUX_S3
001000000100DBL_W0[6]
001000001000DBL_S0[6]
001000010000DBL_N1[6]
001000100000DBL_S1[7]
001001000000DBL_W2[6]
001010000000DBL_S1[6]
010000000001DBL_E2[6]
010000000010DBL_E2[5]
010000000100DBL_E2[7]
010000001000DBL_E0[7]
010000010000DBL_W1[5]
010000100000OUT_FAN[0]
010001000000DBL_E1[6]
010010000000OUT_FAN[7]
100000000001DBL_S2[5]
100000000010DBL_N0[5]
100000000100DBL_S2[6]
100000001000DBL_S2[7]
100000010000DBL_E1[5]
100000100000DBL_W1[6]
100001000000DBL_W2[5]
100010000000DBL_N1[5]
virtex2 INT_BRAM switchbox INT muxes IMUX_G3_FAN[0]
BitsDestination
MAIN[9][63]MAIN[9][60]MAIN[8][60]MAIN[8][63]MAIN[10][62]MAIN[10][60]MAIN[11][62]MAIN[11][60]MAIN[13][62]MAIN[12][62]MAIN[12][60]MAIN[13][60]IMUX_G3_FAN[0]
Source
000000000000off
000100000001OMUX_S5
000100000010OMUX_W14
000100000100OMUX_ES7
000100001000OMUX_E13
000100010000IMUX_G1_FAN[1]
000100100000DBL_S1[8]
000101000000DBL_E1[9]
000110000000IMUX_G2_FAN[1]
001000000001DBL_W0[8]
001000000010OMUX_SW5
001000000100DBL_S0[8]
001000001000DBL_E0[9]
001000010000DBL_W1[7]
001000100000DBL_N1[9]
001001000000DBL_W2[9]
001010000000DBL_N2[9]
010000000001DBL_N0[7]
010000000010DBL_E2[9]
010000000100DBL_E2[8]
010000001000DBL_W2[8]
010000010000OUT_FAN[1]
010000100000DBL_W1[8]
010001000000DBL_W1[9]
010010000000OUT_FAN[6]
100000000001DBL_W2[7]
100000000010DBL_N0[9]
100000000100DBL_S2[9]
100000001000DBL_S2[8]
100000010000DBL_S1[9]
100000100000DBL_E1[8]
100001000000DBL_N2[7]
100010000000DBL_N1[8]
virtex2 INT_BRAM switchbox INT muxes IMUX_G3_FAN[1]
BitsDestination
MAIN[9][62]MAIN[9][61]MAIN[8][61]MAIN[8][62]MAIN[10][63]MAIN[10][61]MAIN[11][63]MAIN[11][61]MAIN[13][63]MAIN[12][63]MAIN[12][61]MAIN[13][61]IMUX_G3_FAN[1]
Source
000000000000off
000100000001OMUX_S5
000100000010OMUX_W14
000100000100OMUX_ES7
000100001000OMUX_E13
000100010000IMUX_G1_FAN[1]
000100100000DBL_S1[8]
000101000000DBL_E1[9]
000110000000IMUX_G2_FAN[1]
001000000001DBL_W0[8]
001000000010OMUX_SW5
001000000100DBL_S0[8]
001000001000DBL_E0[9]
001000010000DBL_W1[7]
001000100000DBL_N1[9]
001001000000DBL_W2[9]
001010000000DBL_N2[9]
010000000001DBL_N0[7]
010000000010DBL_E2[9]
010000000100DBL_E2[8]
010000001000DBL_W2[8]
010000010000OUT_FAN[1]
010000100000DBL_W1[8]
010001000000DBL_W1[9]
010010000000OUT_FAN[6]
100000000001DBL_W2[7]
100000000010DBL_N0[9]
100000000100DBL_S2[9]
100000001000DBL_S2[8]
100000010000DBL_S1[9]
100000100000DBL_E1[8]
100001000000DBL_N2[7]
100010000000DBL_N1[8]
virtex2 INT_BRAM switchbox INT muxes IMUX_G3_DATA[2]
BitsDestination
MAIN[9][72]MAIN[9][75]MAIN[8][75]MAIN[8][72]MAIN[10][73]MAIN[10][75]MAIN[11][73]MAIN[11][75]MAIN[13][73]MAIN[12][73]MAIN[12][75]MAIN[13][75]IMUX_G3_DATA[2]
Source
000000000000PULLUP
000100000001OMUX_S5
000100000010OMUX_W14
000100000100OMUX_ES7
000100001000OMUX_E13
000100010000IMUX_G1_FAN[1]
000100100000DBL_S1[8]
000101000000DBL_E1[9]
000110000000IMUX_G2_FAN[1]
001000000001DBL_W0[8]
001000000010OMUX_SW5
001000000100DBL_S0[8]
001000001000DBL_E0[9]
001000010000DBL_W1[7]
001000100000DBL_N1[9]
001001000000DBL_W2[9]
001010000000DBL_N2[9]
010000000001DBL_N0[7]
010000000010DBL_E2[9]
010000000100DBL_E2[8]
010000001000DBL_W2[8]
010000010000OUT_FAN[1]
010000100000DBL_W1[8]
010001000000DBL_W1[9]
010010000000OUT_FAN[6]
100000000001DBL_W2[7]
100000000010DBL_N0[9]
100000000100DBL_S2[9]
100000001000DBL_S2[8]
100000010000DBL_S1[9]
100000100000DBL_E1[8]
100001000000DBL_N2[7]
100010000000DBL_N1[8]
virtex2 INT_BRAM switchbox INT muxes IMUX_G3_DATA[3]
BitsDestination
MAIN[9][73]MAIN[9][74]MAIN[8][74]MAIN[8][73]MAIN[10][72]MAIN[10][74]MAIN[11][72]MAIN[11][74]MAIN[13][72]MAIN[12][72]MAIN[12][74]MAIN[13][74]IMUX_G3_DATA[3]
Source
000000000000PULLUP
000100000001OMUX_S5
000100000010OMUX_W14
000100000100OMUX_ES7
000100001000OMUX_E13
000100010000IMUX_G1_FAN[1]
000100100000DBL_S1[8]
000101000000DBL_E1[9]
000110000000IMUX_G2_FAN[1]
001000000001DBL_W0[8]
001000000010OMUX_SW5
001000000100DBL_S0[8]
001000001000DBL_E0[9]
001000010000DBL_W1[7]
001000100000DBL_N1[9]
001001000000DBL_W2[9]
001010000000DBL_N2[9]
010000000001DBL_N0[7]
010000000010DBL_E2[9]
010000000100DBL_E2[8]
010000001000DBL_W2[8]
010000010000OUT_FAN[1]
010000100000DBL_W1[8]
010001000000DBL_W1[9]
010010000000OUT_FAN[6]
100000000001DBL_W2[7]
100000000010DBL_N0[9]
100000000100DBL_S2[9]
100000001000DBL_S2[8]
100000010000DBL_S1[9]
100000100000DBL_E1[8]
100001000000DBL_N2[7]
100010000000DBL_N1[8]
virtex2 INT_BRAM switchbox INT muxes IMUX_G3_DATA[4]
BitsDestination
MAIN[9][71]MAIN[9][68]MAIN[8][68]MAIN[8][71]MAIN[10][70]MAIN[10][68]MAIN[11][70]MAIN[11][68]MAIN[13][70]MAIN[12][70]MAIN[12][68]MAIN[13][68]IMUX_G3_DATA[4]
Source
000000000000PULLUP
000100000001OMUX_S5
000100000010OMUX_W14
000100000100OMUX_ES7
000100001000OMUX_E13
000100010000IMUX_G1_FAN[1]
000100100000DBL_S1[8]
000101000000DBL_E1[9]
000110000000IMUX_G2_FAN[1]
001000000001DBL_W0[8]
001000000010OMUX_SW5
001000000100DBL_S0[8]
001000001000DBL_E0[9]
001000010000DBL_W1[7]
001000100000DBL_N1[9]
001001000000DBL_W2[9]
001010000000DBL_N2[9]
010000000001DBL_N0[7]
010000000010DBL_E2[9]
010000000100DBL_E2[8]
010000001000DBL_W2[8]
010000010000OUT_FAN[1]
010000100000DBL_W1[8]
010001000000DBL_W1[9]
010010000000OUT_FAN[6]
100000000001DBL_W2[7]
100000000010DBL_N0[9]
100000000100DBL_S2[9]
100000001000DBL_S2[8]
100000010000DBL_S1[9]
100000100000DBL_E1[8]
100001000000DBL_N2[7]
100010000000DBL_N1[8]
virtex2 INT_BRAM switchbox INT muxes IMUX_G3_DATA[5]
BitsDestination
MAIN[9][70]MAIN[9][69]MAIN[8][69]MAIN[8][70]MAIN[10][71]MAIN[10][69]MAIN[11][71]MAIN[11][69]MAIN[13][71]MAIN[12][71]MAIN[12][69]MAIN[13][69]IMUX_G3_DATA[5]
Source
000000000000PULLUP
000100000001OMUX_S5
000100000010OMUX_W14
000100000100OMUX_ES7
000100001000OMUX_E13
000100010000IMUX_G1_FAN[1]
000100100000DBL_S1[8]
000101000000DBL_E1[9]
000110000000IMUX_G2_FAN[1]
001000000001DBL_W0[8]
001000000010OMUX_SW5
001000000100DBL_S0[8]
001000001000DBL_E0[9]
001000010000DBL_W1[7]
001000100000DBL_N1[9]
001001000000DBL_W2[9]
001010000000DBL_N2[9]
010000000001DBL_N0[7]
010000000010DBL_E2[9]
010000000100DBL_E2[8]
010000001000DBL_W2[8]
010000010000OUT_FAN[1]
010000100000DBL_W1[8]
010001000000DBL_W1[9]
010010000000OUT_FAN[6]
100000000001DBL_W2[7]
100000000010DBL_N0[9]
100000000100DBL_S2[9]
100000001000DBL_S2[8]
100000010000DBL_S1[9]
100000100000DBL_E1[8]
100001000000DBL_N2[7]
100010000000DBL_N1[8]
virtex2 INT_BRAM switchbox INT muxes IMUX_G3_DATA[6]
BitsDestination
MAIN[9][64]MAIN[9][67]MAIN[8][67]MAIN[8][64]MAIN[10][65]MAIN[10][67]MAIN[11][65]MAIN[11][67]MAIN[13][65]MAIN[12][65]MAIN[12][67]MAIN[13][67]IMUX_G3_DATA[6]
Source
000000000000PULLUP
000100000001OMUX_S5
000100000010OMUX_W14
000100000100OMUX_ES7
000100001000OMUX_E13
000100010000IMUX_G1_FAN[1]
000100100000DBL_S1[8]
000101000000DBL_E1[9]
000110000000IMUX_G2_FAN[1]
001000000001DBL_W0[8]
001000000010OMUX_SW5
001000000100DBL_S0[8]
001000001000DBL_E0[9]
001000010000DBL_W1[7]
001000100000DBL_N1[9]
001001000000DBL_W2[9]
001010000000DBL_N2[9]
010000000001DBL_N0[7]
010000000010DBL_E2[9]
010000000100DBL_E2[8]
010000001000DBL_W2[8]
010000010000OUT_FAN[1]
010000100000DBL_W1[8]
010001000000DBL_W1[9]
010010000000OUT_FAN[6]
100000000001DBL_W2[7]
100000000010DBL_N0[9]
100000000100DBL_S2[9]
100000001000DBL_S2[8]
100000010000DBL_S1[9]
100000100000DBL_E1[8]
100001000000DBL_N2[7]
100010000000DBL_N1[8]
virtex2 INT_BRAM switchbox INT muxes IMUX_G3_DATA[7]
BitsDestination
MAIN[9][65]MAIN[9][66]MAIN[8][66]MAIN[8][65]MAIN[10][64]MAIN[10][66]MAIN[11][64]MAIN[11][66]MAIN[13][64]MAIN[12][64]MAIN[12][66]MAIN[13][66]IMUX_G3_DATA[7]
Source
000000000000PULLUP
000100000001OMUX_S5
000100000010OMUX_W14
000100000100OMUX_ES7
000100001000OMUX_E13
000100010000IMUX_G1_FAN[1]
000100100000DBL_S1[8]
000101000000DBL_E1[9]
000110000000IMUX_G2_FAN[1]
001000000001DBL_W0[8]
001000000010OMUX_SW5
001000000100DBL_S0[8]
001000001000DBL_E0[9]
001000010000DBL_W1[7]
001000100000DBL_N1[9]
001001000000DBL_W2[9]
001010000000DBL_N2[9]
010000000001DBL_N0[7]
010000000010DBL_E2[9]
010000000100DBL_E2[8]
010000001000DBL_W2[8]
010000010000OUT_FAN[1]
010000100000DBL_W1[8]
010001000000DBL_W1[9]
010010000000OUT_FAN[6]
100000000001DBL_W2[7]
100000000010DBL_N0[9]
100000000100DBL_S2[9]
100000001000DBL_S2[8]
100000010000DBL_S1[9]
100000100000DBL_E1[8]
100001000000DBL_N2[7]
100010000000DBL_N1[8]
virtex2 INT_BRAM switchbox INT muxes IMUX_BRAM_ADDRA[0]
BitsDestination
MAIN[9][1]MAIN[9][2]MAIN[8][2]MAIN[8][1]MAIN[10][0]MAIN[10][2]MAIN[11][2]MAIN[11][0]MAIN[12][2]MAIN[13][0]MAIN[13][2]MAIN[12][0]IMUX_BRAM_ADDRA[0]
Source
000000000000PULLUP
000100000001OMUX_W1
000100000010OMUX_E2
000100000100OMUX_N10
000100001000OMUX_NW10
000100010000DBL_S1[0]
000100100000IMUX_G1_FAN[0]
000101000000DBL_N2[0]
000110000000IMUX_G2_FAN[0]
001000000001DBL_E0[1]
001000000010DBL_S0[0]
001000000100DBL_W0[0]
001000001000IMUX_BRAM_ADDRB_N4[0]
001000010000DBL_N1[1]
001000100000DBL_S1[2]
001001000000DBL_W2[1]
001010000000DBL_S1[1]
010000000001DBL_E2[1]
010000000010DBL_S0[2]
010000000100DBL_E2[2]
010000001000DBL_E2[0]
010000010000DBL_W1[0]
010000100000IMUX_BRAM_ADDRA_N4[0]
010001000000DBL_E1[1]
010010000000IMUX_BRAM_ADDRB_S4[0]
100000000001DBL_S2[0]
100000000010DBL_S2[2]
100000000100DBL_S2[1]
100000001000DBL_N0[1]
100000010000DBL_E1[0]
100000100000DBL_W1[1]
100001000000IMUX_BRAM_ADDRA_S4[0]
100010000000DBL_N1[0]
virtex2 INT_BRAM switchbox INT muxes IMUX_BRAM_ADDRA[1]
BitsDestination
MAIN[9][38]MAIN[8][37]MAIN[9][37]MAIN[8][38]MAIN[10][39]MAIN[10][37]MAIN[11][39]MAIN[11][37]MAIN[13][37]MAIN[13][39]MAIN[12][37]MAIN[12][39]IMUX_BRAM_ADDRA[1]
Source
000000000000PULLUP
000100000001OMUX_E7
000100000010OMUX_N12
000100000100OMUX_NE12
000100001000OMUX_WN14
000100010000IMUX_G3_FAN[1]
000100100000DBL_S1[3]
000101000000DBL_E1[4]
000110000000IMUX_G0_FAN[1]
001000000001DBL_E2[3]
001000000010DBL_E2[4]
001000000100DBL_W2[3]
001000001000DBL_W0[2]
001000010000IMUX_BRAM_ADDRA_N4[1]
001000100000DBL_W1[3]
001001000000DBL_W1[4]
001010000000IMUX_BRAM_ADDRB_S4[1]
010000000001DBL_S0[4]
010000000010IMUX_BRAM_ADDRB_N4[1]
010000000100DBL_W0[4]
010000001000DBL_E0[3]
010000010000DBL_W1[2]
010000100000DBL_N1[4]
010001000000DBL_W2[4]
010010000000DBL_N2[4]
100000000001DBL_S2[4]
100000000010DBL_N0[3]
100000000100DBL_S2[3]
100000001000DBL_W2[2]
100000010000DBL_S1[4]
100000100000DBL_E1[3]
100001000000IMUX_BRAM_ADDRA_S4[1]
100010000000DBL_N1[3]
virtex2 INT_BRAM switchbox INT muxes IMUX_BRAM_ADDRA[2]
BitsDestination
MAIN[9][41]MAIN[9][42]MAIN[8][42]MAIN[8][41]MAIN[10][40]MAIN[10][42]MAIN[11][42]MAIN[11][40]MAIN[13][42]MAIN[12][42]MAIN[13][40]MAIN[12][40]IMUX_BRAM_ADDRA[2]
Source
000000000000PULLUP
000100000001OMUX_WS1
000100000010OMUX_SE3
000100000100OMUX_E8
000100001000OMUX_W9
000100010000DBL_S1[5]
000100100000IMUX_G3_FAN[0]
000101000000DBL_N2[5]
000110000000IMUX_G0_FAN[0]
001000000001DBL_E0[5]
001000000010DBL_W0[6]
001000000100IMUX_BRAM_ADDRB_N4[2]
001000001000DBL_S0[6]
001000010000DBL_N1[6]
001000100000DBL_S1[7]
001001000000DBL_W2[6]
001010000000DBL_S1[6]
010000000001DBL_E2[6]
010000000010DBL_E2[7]
010000000100DBL_E2[5]
010000001000DBL_E0[7]
010000010000DBL_W1[5]
010000100000IMUX_BRAM_ADDRA_N4[2]
010001000000DBL_E1[6]
010010000000IMUX_BRAM_ADDRB_S4[2]
100000000001DBL_S2[5]
100000000010DBL_S2[6]
100000000100DBL_N0[5]
100000001000DBL_S2[7]
100000010000DBL_E1[5]
100000100000DBL_W1[6]
100001000000IMUX_BRAM_ADDRA_S4[2]
100010000000DBL_N1[5]
virtex2 INT_BRAM switchbox INT muxes IMUX_BRAM_ADDRA[3]
BitsDestination
MAIN[9][78]MAIN[9][77]MAIN[8][77]MAIN[8][78]MAIN[10][79]MAIN[10][77]MAIN[11][79]MAIN[11][77]MAIN[12][77]MAIN[13][79]MAIN[12][79]MAIN[13][77]IMUX_BRAM_ADDRA[3]
Source
000000000000PULLUP
000100000001OMUX_S5
000100000010OMUX_ES7
000100000100OMUX_E13
000100001000OMUX_W14
000100010000IMUX_G1_FAN[1]
000100100000DBL_S1[8]
000101000000DBL_E1[9]
000110000000IMUX_G2_FAN[1]
001000000001DBL_W0[8]
001000000010DBL_S0[8]
001000000100DBL_E0[9]
001000001000IMUX_BRAM_ADDRB_N4[3]
001000010000DBL_W1[7]
001000100000DBL_N1[9]
001001000000DBL_W2[9]
001010000000DBL_N2[9]
010000000001DBL_N0[7]
010000000010DBL_E2[8]
010000000100DBL_W2[8]
010000001000DBL_E2[9]
010000010000IMUX_BRAM_ADDRA_N4[3]
010000100000DBL_W1[8]
010001000000DBL_W1[9]
010010000000IMUX_BRAM_ADDRB_S4[3]
100000000001DBL_W2[7]
100000000010DBL_S2[9]
100000000100DBL_S2[8]
100000001000DBL_N0[9]
100000010000DBL_S1[9]
100000100000DBL_E1[8]
100001000000IMUX_BRAM_ADDRA_S4[3]
100010000000DBL_N1[8]
virtex2 INT_BRAM switchbox INT muxes IMUX_BRAM_ADDRB[0]
BitsDestination
MAIN[9][0]MAIN[9][3]MAIN[8][3]MAIN[8][0]MAIN[10][1]MAIN[10][3]MAIN[11][3]MAIN[11][1]MAIN[12][3]MAIN[13][1]MAIN[13][3]MAIN[12][1]IMUX_BRAM_ADDRB[0]
Source
000000000000PULLUP
000100000001OMUX_W1
000100000010OMUX_E2
000100000100OMUX_N10
000100001000OMUX_NW10
000100010000DBL_S1[0]
000100100000IMUX_G1_FAN[0]
000101000000DBL_N2[0]
000110000000IMUX_G2_FAN[0]
001000000001DBL_E0[1]
001000000010DBL_S0[0]
001000000100DBL_W0[0]
001000001000IMUX_BRAM_ADDRB_N4[0]
001000010000DBL_N1[1]
001000100000DBL_S1[2]
001001000000DBL_W2[1]
001010000000DBL_S1[1]
010000000001DBL_E2[1]
010000000010DBL_S0[2]
010000000100DBL_E2[2]
010000001000DBL_E2[0]
010000010000DBL_W1[0]
010000100000IMUX_BRAM_ADDRA_N4[0]
010001000000DBL_E1[1]
010010000000IMUX_BRAM_ADDRB_S4[0]
100000000001DBL_S2[0]
100000000010DBL_S2[2]
100000000100DBL_S2[1]
100000001000DBL_N0[1]
100000010000DBL_E1[0]
100000100000DBL_W1[1]
100001000000IMUX_BRAM_ADDRA_S4[0]
100010000000DBL_N1[0]
virtex2 INT_BRAM switchbox INT muxes IMUX_BRAM_ADDRB[1]
BitsDestination
MAIN[9][39]MAIN[8][36]MAIN[9][36]MAIN[8][39]MAIN[10][38]MAIN[10][36]MAIN[11][38]MAIN[11][36]MAIN[13][36]MAIN[13][38]MAIN[12][36]MAIN[12][38]IMUX_BRAM_ADDRB[1]
Source
000000000000PULLUP
000100000001OMUX_E7
000100000010OMUX_N12
000100000100OMUX_NE12
000100001000OMUX_WN14
000100010000IMUX_G3_FAN[1]
000100100000DBL_S1[3]
000101000000DBL_E1[4]
000110000000IMUX_G0_FAN[1]
001000000001DBL_E2[3]
001000000010DBL_E2[4]
001000000100DBL_W2[3]
001000001000DBL_W0[2]
001000010000IMUX_BRAM_ADDRA_N4[1]
001000100000DBL_W1[3]
001001000000DBL_W1[4]
001010000000IMUX_BRAM_ADDRB_S4[1]
010000000001DBL_S0[4]
010000000010IMUX_BRAM_ADDRB_N4[1]
010000000100DBL_W0[4]
010000001000DBL_E0[3]
010000010000DBL_W1[2]
010000100000DBL_N1[4]
010001000000DBL_W2[4]
010010000000DBL_N2[4]
100000000001DBL_S2[4]
100000000010DBL_N0[3]
100000000100DBL_S2[3]
100000001000DBL_W2[2]
100000010000DBL_S1[4]
100000100000DBL_E1[3]
100001000000IMUX_BRAM_ADDRA_S4[1]
100010000000DBL_N1[3]
virtex2 INT_BRAM switchbox INT muxes IMUX_BRAM_ADDRB[2]
BitsDestination
MAIN[9][40]MAIN[9][43]MAIN[8][43]MAIN[8][40]MAIN[10][41]MAIN[10][43]MAIN[11][43]MAIN[11][41]MAIN[13][43]MAIN[12][43]MAIN[13][41]MAIN[12][41]IMUX_BRAM_ADDRB[2]
Source
000000000000PULLUP
000100000001OMUX_WS1
000100000010OMUX_SE3
000100000100OMUX_E8
000100001000OMUX_W9
000100010000DBL_S1[5]
000100100000IMUX_G3_FAN[0]
000101000000DBL_N2[5]
000110000000IMUX_G0_FAN[0]
001000000001DBL_E0[5]
001000000010DBL_W0[6]
001000000100IMUX_BRAM_ADDRB_N4[2]
001000001000DBL_S0[6]
001000010000DBL_N1[6]
001000100000DBL_S1[7]
001001000000DBL_W2[6]
001010000000DBL_S1[6]
010000000001DBL_E2[6]
010000000010DBL_E2[7]
010000000100DBL_E2[5]
010000001000DBL_E0[7]
010000010000DBL_W1[5]
010000100000IMUX_BRAM_ADDRA_N4[2]
010001000000DBL_E1[6]
010010000000IMUX_BRAM_ADDRB_S4[2]
100000000001DBL_S2[5]
100000000010DBL_S2[6]
100000000100DBL_N0[5]
100000001000DBL_S2[7]
100000010000DBL_E1[5]
100000100000DBL_W1[6]
100001000000IMUX_BRAM_ADDRA_S4[2]
100010000000DBL_N1[5]
virtex2 INT_BRAM switchbox INT muxes IMUX_BRAM_ADDRB[3]
BitsDestination
MAIN[9][79]MAIN[9][76]MAIN[8][76]MAIN[8][79]MAIN[10][78]MAIN[10][76]MAIN[11][78]MAIN[11][76]MAIN[12][76]MAIN[13][78]MAIN[12][78]MAIN[13][76]IMUX_BRAM_ADDRB[3]
Source
000000000000PULLUP
000100000001OMUX_S5
000100000010OMUX_ES7
000100000100OMUX_E13
000100001000OMUX_W14
000100010000IMUX_G1_FAN[1]
000100100000DBL_S1[8]
000101000000DBL_E1[9]
000110000000IMUX_G2_FAN[1]
001000000001DBL_W0[8]
001000000010DBL_S0[8]
001000000100DBL_E0[9]
001000001000IMUX_BRAM_ADDRB_N4[3]
001000010000DBL_W1[7]
001000100000DBL_N1[9]
001001000000DBL_W2[9]
001010000000DBL_N2[9]
010000000001DBL_N0[7]
010000000010DBL_E2[8]
010000000100DBL_W2[8]
010000001000DBL_E2[9]
010000010000IMUX_BRAM_ADDRA_N4[3]
010000100000DBL_W1[8]
010001000000DBL_W1[9]
010010000000IMUX_BRAM_ADDRB_S4[3]
100000000001DBL_W2[7]
100000000010DBL_S2[9]
100000000100DBL_S2[8]
100000001000DBL_N0[9]
100000010000DBL_S1[9]
100000100000DBL_E1[8]
100001000000IMUX_BRAM_ADDRA_S4[3]
100010000000DBL_N1[8]

Bitstream

virtex2 INT_BRAM rect MAIN
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21
B79 - - - - INT: mux IMUX_CE[2] bit 5 INT: mux IMUX_CE[3] bit 1 INT: mux OMUX[14] bit 2 INT: mux OMUX[15] bit 9 INT: mux IMUX_BRAM_ADDRB[3] bit 8 INT: mux IMUX_BRAM_ADDRB[3] bit 11 INT: mux IMUX_BRAM_ADDRA[3] bit 7 INT: mux IMUX_BRAM_ADDRA[3] bit 5 INT: mux IMUX_BRAM_ADDRA[3] bit 1 INT: mux IMUX_BRAM_ADDRA[3] bit 2 INT: mux DBL_E0[9] bit 0 INT: mux DBL_W0[9] bit 7 INT: mux DBL_E0[9] bit 5 INT: mux DBL_E0[9] bit 7 INT: mux HEX_W0[9] bit 0 INT: mux HEX_W0[9] bit 3 INT: mux HEX_W0[9] bit 4 INT: mux LV[18] bit 1
B78 - - - - INT: !invert IMUX_CE_OPTINV[3] ← IMUX_CE[3] INT: mux IMUX_CE[3] bit 3 INT: mux OMUX[15] bit 8 INT: mux OMUX[15] bit 6 INT: mux IMUX_BRAM_ADDRA[3] bit 8 INT: mux IMUX_BRAM_ADDRA[3] bit 11 INT: mux IMUX_BRAM_ADDRB[3] bit 7 INT: mux IMUX_BRAM_ADDRB[3] bit 5 INT: mux IMUX_BRAM_ADDRB[3] bit 1 INT: mux IMUX_BRAM_ADDRB[3] bit 2 INT: mux DBL_E0[9] bit 1 INT: mux DBL_W0[9] bit 4 INT: mux DBL_W0[9] bit 3 INT: mux DBL_W0[9] bit 0 INT: mux HEX_E0[9] bit 1 INT: mux HEX_E0[9] bit 3 INT: mux HEX_E0[9] bit 5 INT: mux HEX_W0[9] bit 6
B77 - - - - INT: mux IMUX_CE[3] bit 0 INT: mux IMUX_CE[3] bit 2 INT: mux OMUX[15] bit 2 INT: mux OMUX[15] bit 7 INT: mux IMUX_BRAM_ADDRA[3] bit 9 INT: mux IMUX_BRAM_ADDRA[3] bit 10 INT: mux IMUX_BRAM_ADDRA[3] bit 6 INT: mux IMUX_BRAM_ADDRA[3] bit 4 INT: mux IMUX_BRAM_ADDRA[3] bit 3 INT: mux IMUX_BRAM_ADDRA[3] bit 0 INT: mux DBL_W0[9] bit 5 INT: mux DBL_E0[9] bit 3 INT: mux DBL_W0[9] bit 2 INT: mux DBL_W0[9] bit 1 INT: mux HEX_W0[9] bit 2 INT: mux HEX_W0[9] bit 1 INT: mux HEX_E0[9] bit 6 INT: mux LV[18] bit 3
B76 - - - - INT: mux IMUX_CE[3] bit 4 INT: mux IMUX_CE[3] bit 5 INT: mux OMUX[14] bit 3 INT: mux OMUX[15] bit 3 INT: mux IMUX_BRAM_ADDRB[3] bit 9 INT: mux IMUX_BRAM_ADDRB[3] bit 10 INT: mux IMUX_BRAM_ADDRB[3] bit 6 INT: mux IMUX_BRAM_ADDRB[3] bit 4 INT: mux IMUX_BRAM_ADDRB[3] bit 3 INT: mux IMUX_BRAM_ADDRB[3] bit 0 INT: mux DBL_W0[9] bit 6 INT: mux DBL_E0[9] bit 2 INT: mux DBL_E0[9] bit 4 INT: mux DBL_E0[9] bit 6 INT: mux HEX_E0[9] bit 2 INT: mux HEX_E0[9] bit 0 INT: mux HEX_E0[9] bit 4 INT: mux HEX_W0[9] bit 5
B75 - - - - INT: mux IMUX_CE[2] bit 4 INT: mux IMUX_CE[2] bit 7 INT: mux OMUX[15] bit 1 INT: mux OMUX[14] bit 1 INT: mux IMUX_G3_DATA[2] bit 9 INT: mux IMUX_G3_DATA[2] bit 10 INT: mux IMUX_G3_DATA[2] bit 6 INT: mux IMUX_G3_DATA[2] bit 4 INT: mux IMUX_G3_DATA[2] bit 1 INT: mux IMUX_G3_DATA[2] bit 0 INT: mux DBL_S0[9] bit 4 INT: mux DBL_N0[9] bit 2 INT: mux DBL_S0[9] bit 0 INT: mux DBL_S0[9] bit 3 INT: mux HEX_N0[9] bit 1 INT: mux HEX_N0[9] bit 3 INT: mux HEX_N0[9] bit 5 INT: mux LV[6] bit 0
B74 - - - - INT: mux IMUX_CE[3] bit 7 INT: mux IMUX_CE[3] bit 6 INT: mux OMUX[15] bit 0 INT: mux OMUX[14] bit 0 INT: mux IMUX_G3_DATA[3] bit 9 INT: mux IMUX_G3_DATA[3] bit 10 INT: mux IMUX_G3_DATA[3] bit 6 INT: mux IMUX_G3_DATA[3] bit 4 INT: mux IMUX_G3_DATA[3] bit 1 INT: mux IMUX_G3_DATA[3] bit 0 INT: mux DBL_S0[9] bit 5 INT: mux DBL_N0[9] bit 0 INT: mux DBL_N0[9] bit 7 INT: mux DBL_N0[9] bit 5 INT: mux HEX_S0[9] bit 1 INT: mux HEX_S0[9] bit 2 INT: mux HEX_S0[9] bit 4 INT: mux HEX_N0[9] bit 4
B73 - - - - INT: mux IMUX_CE[2] bit 0 INT: mux IMUX_CE[2] bit 1 INT: mux OMUX[14] bit 5 INT: mux OMUX[15] bit 5 INT: mux IMUX_G3_DATA[3] bit 8 INT: mux IMUX_G3_DATA[3] bit 11 INT: mux IMUX_G3_DATA[2] bit 7 INT: mux IMUX_G3_DATA[2] bit 5 INT: mux IMUX_G3_DATA[2] bit 2 INT: mux IMUX_G3_DATA[2] bit 3 INT: mux DBL_N0[9] bit 1 INT: mux DBL_S0[9] bit 6 INT: mux DBL_N0[9] bit 6 INT: mux DBL_N0[9] bit 4 INT: mux HEX_N0[9] bit 2 INT: mux HEX_N0[9] bit 0 INT: mux HEX_S0[9] bit 5 INT: mux LV[6] bit 6
B72 - - - - INT: !invert IMUX_CE_OPTINV[2] ← IMUX_CE[2] INT: mux IMUX_CE[2] bit 3 INT: mux OMUX[15] bit 4 INT: mux OMUX[14] bit 7 INT: mux IMUX_G3_DATA[2] bit 8 INT: mux IMUX_G3_DATA[2] bit 11 INT: mux IMUX_G3_DATA[3] bit 7 INT: mux IMUX_G3_DATA[3] bit 5 INT: mux IMUX_G3_DATA[3] bit 2 INT: mux IMUX_G3_DATA[3] bit 3 INT: mux DBL_N0[9] bit 3 INT: mux DBL_S0[9] bit 7 INT: mux DBL_S0[9] bit 1 INT: mux DBL_S0[9] bit 2 INT: mux HEX_S0[9] bit 3 INT: mux HEX_S0[9] bit 0 INT: mux HEX_S0[9] bit 6 INT: mux HEX_N0[9] bit 6
B71 - - - - INT: mux IMUX_CE[2] bit 6 INT: mux IMUX_CE[2] bit 2 INT: mux OMUX[14] bit 8 INT: mux OMUX[14] bit 6 INT: mux IMUX_G3_DATA[4] bit 8 INT: mux IMUX_G3_DATA[4] bit 11 INT: mux IMUX_G3_DATA[5] bit 7 INT: mux IMUX_G3_DATA[5] bit 5 INT: mux IMUX_G3_DATA[5] bit 2 INT: mux IMUX_G3_DATA[5] bit 3 INT: mux DBL_E0[8] bit 2 INT: mux DBL_W0[8] bit 3 INT: mux DBL_E0[8] bit 4 INT: mux DBL_E0[8] bit 7 INT: mux HEX_E0[8] bit 0 INT: mux HEX_E0[8] bit 3 INT: mux HEX_E0[8] bit 4 INT: mux LV[6] bit 2
B70 - - - - INT: mux IMUX_CE[1] bit 5 INT: mux IMUX_CE[1] bit 2 INT: mux OMUX[14] bit 4 INT: mux OMUX[14] bit 9 INT: mux IMUX_G3_DATA[5] bit 8 INT: mux IMUX_G3_DATA[5] bit 11 INT: mux IMUX_G3_DATA[4] bit 7 INT: mux IMUX_G3_DATA[4] bit 5 INT: mux IMUX_G3_DATA[4] bit 2 INT: mux IMUX_G3_DATA[4] bit 3 INT: mux DBL_E0[8] bit 0 INT: mux DBL_W0[8] bit 0 INT: mux DBL_W0[8] bit 7 INT: mux DBL_W0[8] bit 4 INT: mux HEX_W0[8] bit 0 INT: mux HEX_W0[8] bit 3 INT: mux HEX_W0[8] bit 4 INT: mux HEX_E0[8] bit 5
B69 - - - - INT: !invert IMUX_CE_OPTINV[1] ← IMUX_CE[1] INT: mux IMUX_CE[1] bit 3 INT: mux OMUX[12] bit 2 INT: mux OMUX[13] bit 9 INT: mux IMUX_G3_DATA[5] bit 9 INT: mux IMUX_G3_DATA[5] bit 10 INT: mux IMUX_G3_DATA[5] bit 6 INT: mux IMUX_G3_DATA[5] bit 4 INT: mux IMUX_G3_DATA[5] bit 1 INT: mux IMUX_G3_DATA[5] bit 0 INT: mux DBL_W0[8] bit 2 INT: mux DBL_E0[8] bit 3 INT: mux DBL_W0[8] bit 6 INT: mux DBL_W0[8] bit 5 INT: mux HEX_E0[8] bit 2 INT: mux HEX_E0[8] bit 1 INT: mux HEX_W0[8] bit 5 INT: mux LV[6] bit 3
B68 - - - - INT: mux IMUX_CE[1] bit 1 INT: mux IMUX_CE[1] bit 0 INT: mux OMUX[13] bit 8 INT: mux OMUX[13] bit 6 INT: mux IMUX_G3_DATA[4] bit 9 INT: mux IMUX_G3_DATA[4] bit 10 INT: mux IMUX_G3_DATA[4] bit 6 INT: mux IMUX_G3_DATA[4] bit 4 INT: mux IMUX_G3_DATA[4] bit 1 INT: mux IMUX_G3_DATA[4] bit 0 INT: mux DBL_W0[8] bit 1 INT: mux DBL_E0[8] bit 1 INT: mux DBL_E0[8] bit 5 INT: mux DBL_E0[8] bit 6 INT: mux HEX_W0[8] bit 2 INT: mux HEX_W0[8] bit 1 INT: mux HEX_W0[8] bit 6 INT: mux HEX_E0[8] bit 6
B67 - - - - - - INT: mux OMUX[13] bit 2 INT: mux OMUX[13] bit 7 INT: mux IMUX_G3_DATA[6] bit 9 INT: mux IMUX_G3_DATA[6] bit 10 INT: mux IMUX_G3_DATA[6] bit 6 INT: mux IMUX_G3_DATA[6] bit 4 INT: mux IMUX_G3_DATA[6] bit 1 INT: mux IMUX_G3_DATA[6] bit 0 INT: mux DBL_S0[8] bit 3 INT: mux DBL_N0[8] bit 1 INT: mux DBL_S0[8] bit 5 INT: mux DBL_S0[8] bit 7 INT: mux HEX_S0[8] bit 1 INT: mux HEX_S0[8] bit 3 INT: mux HEX_S0[8] bit 5 INT: mux LV[18] bit 6
B66 - - - - INT: mux IMUX_CE[1] bit 6 INT: mux IMUX_CE[1] bit 4 INT: mux OMUX[12] bit 3 INT: mux OMUX[13] bit 3 INT: mux IMUX_G3_DATA[7] bit 9 INT: mux IMUX_G3_DATA[7] bit 10 INT: mux IMUX_G3_DATA[7] bit 6 INT: mux IMUX_G3_DATA[7] bit 4 INT: mux IMUX_G3_DATA[7] bit 1 INT: mux IMUX_G3_DATA[7] bit 0 INT: mux DBL_S0[8] bit 0 INT: mux DBL_N0[8] bit 0 INT: mux DBL_N0[8] bit 7 INT: mux DBL_N0[8] bit 5 INT: mux HEX_N0[8] bit 1 INT: mux HEX_N0[8] bit 2 INT: mux HEX_N0[8] bit 5 INT: mux HEX_S0[8] bit 4
B65 - - - - - - INT: mux OMUX[13] bit 1 INT: mux OMUX[12] bit 1 INT: mux IMUX_G3_DATA[7] bit 8 INT: mux IMUX_G3_DATA[7] bit 11 INT: mux IMUX_G3_DATA[6] bit 7 INT: mux IMUX_G3_DATA[6] bit 5 INT: mux IMUX_G3_DATA[6] bit 2 INT: mux IMUX_G3_DATA[6] bit 3 INT: mux DBL_N0[8] bit 3 INT: mux DBL_S0[8] bit 1 INT: mux DBL_N0[8] bit 6 INT: mux DBL_N0[8] bit 4 INT: mux HEX_S0[8] bit 2 INT: mux HEX_S0[8] bit 0 INT: mux HEX_N0[8] bit 4 INT: mux LV[6] bit 1
B64 - - - - - - INT: mux OMUX[13] bit 0 INT: mux OMUX[12] bit 0 INT: mux IMUX_G3_DATA[6] bit 8 INT: mux IMUX_G3_DATA[6] bit 11 INT: mux IMUX_G3_DATA[7] bit 7 INT: mux IMUX_G3_DATA[7] bit 5 INT: mux IMUX_G3_DATA[7] bit 2 INT: mux IMUX_G3_DATA[7] bit 3 INT: mux DBL_N0[8] bit 2 INT: mux DBL_S0[8] bit 2 INT: mux DBL_S0[8] bit 4 INT: mux DBL_S0[8] bit 6 INT: mux HEX_N0[8] bit 3 INT: mux HEX_N0[8] bit 0 INT: mux HEX_N0[8] bit 6 INT: mux HEX_S0[8] bit 6
B63 - - - - - - INT: mux OMUX[12] bit 5 INT: mux OMUX[13] bit 5 INT: mux IMUX_G3_FAN[0] bit 8 INT: mux IMUX_G3_FAN[0] bit 11 INT: mux IMUX_G3_FAN[1] bit 7 INT: mux IMUX_G3_FAN[1] bit 5 INT: mux IMUX_G3_FAN[1] bit 2 INT: mux IMUX_G3_FAN[1] bit 3 INT: mux DBL_E0[7] bit 2 INT: mux DBL_W0[7] bit 3 INT: mux DBL_E0[7] bit 4 INT: mux DBL_E0[7] bit 7 INT: mux HEX_W0[7] bit 0 INT: mux HEX_W0[7] bit 3 INT: mux HEX_W0[7] bit 4 INT: mux LV[18] bit 0
B62 - - - - INT: mux IMUX_CE[1] bit 7 - INT: mux OMUX[13] bit 4 INT: mux OMUX[12] bit 7 INT: mux IMUX_G3_FAN[1] bit 8 INT: mux IMUX_G3_FAN[1] bit 11 INT: mux IMUX_G3_FAN[0] bit 7 INT: mux IMUX_G3_FAN[0] bit 5 INT: mux IMUX_G3_FAN[0] bit 2 INT: mux IMUX_G3_FAN[0] bit 3 INT: mux DBL_E0[7] bit 0 INT: mux DBL_W0[7] bit 0 INT: mux DBL_W0[7] bit 7 INT: mux DBL_W0[7] bit 4 INT: mux HEX_E0[7] bit 0 INT: mux HEX_E0[7] bit 3 INT: mux HEX_E0[7] bit 4 INT: mux HEX_W0[7] bit 5
B61 - - - - INT: mux IMUX_CLK[2] bit 0 INT: mux IMUX_CLK[3] bit 7 INT: mux OMUX[12] bit 8 INT: mux OMUX[12] bit 6 INT: mux IMUX_G3_FAN[1] bit 9 INT: mux IMUX_G3_FAN[1] bit 10 INT: mux IMUX_G3_FAN[1] bit 6 INT: mux IMUX_G3_FAN[1] bit 4 INT: mux IMUX_G3_FAN[1] bit 1 INT: mux IMUX_G3_FAN[1] bit 0 INT: mux DBL_W0[7] bit 2 INT: mux DBL_E0[7] bit 3 INT: mux DBL_W0[7] bit 6 INT: mux DBL_W0[7] bit 5 INT: mux HEX_W0[7] bit 2 INT: mux HEX_W0[7] bit 1 INT: mux HEX_E0[7] bit 5 INT: mux LV[6] bit 5
B60 - - - - INT: invert IMUX_CLK_OPTINV[3] ← IMUX_CLK[3] INT: mux IMUX_CLK[3] bit 9 INT: mux OMUX[12] bit 4 INT: mux OMUX[12] bit 9 INT: mux IMUX_G3_FAN[0] bit 9 INT: mux IMUX_G3_FAN[0] bit 10 INT: mux IMUX_G3_FAN[0] bit 6 INT: mux IMUX_G3_FAN[0] bit 4 INT: mux IMUX_G3_FAN[0] bit 1 INT: mux IMUX_G3_FAN[0] bit 0 INT: mux DBL_W0[7] bit 1 INT: mux DBL_E0[7] bit 1 INT: mux DBL_E0[7] bit 5 INT: mux DBL_E0[7] bit 6 INT: mux HEX_E0[7] bit 2 INT: mux HEX_E0[7] bit 1 INT: mux HEX_E0[7] bit 6 INT: mux HEX_W0[7] bit 6
B59 - - - - INT: mux IMUX_CLK[3] bit 6 INT: mux IMUX_CLK[3] bit 8 INT: mux OMUX[10] bit 2 INT: mux OMUX[11] bit 9 INT: mux IMUX_G2_FAN[0] bit 9 INT: mux IMUX_G2_FAN[0] bit 10 INT: mux IMUX_G2_FAN[0] bit 6 INT: mux IMUX_G2_FAN[0] bit 5 INT: mux IMUX_G2_FAN[0] bit 1 INT: mux IMUX_G2_FAN[0] bit 3 INT: mux DBL_S0[7] bit 4 INT: mux DBL_N0[7] bit 6 INT: mux DBL_S0[7] bit 1 INT: mux DBL_S0[7] bit 3 INT: mux HEX_N0[7] bit 1 INT: mux HEX_N0[7] bit 3 INT: mux HEX_N0[7] bit 6 INT: mux LV[18] bit 2
B58 - - - - INT: mux IMUX_CLK[3] bit 3 INT: mux IMUX_CLK[3] bit 0 INT: mux OMUX[11] bit 8 INT: mux OMUX[11] bit 6 INT: mux IMUX_G2_FAN[1] bit 9 INT: mux IMUX_G2_FAN[1] bit 10 INT: mux IMUX_G2_FAN[1] bit 6 INT: mux IMUX_G2_FAN[1] bit 5 INT: mux IMUX_G2_FAN[1] bit 1 INT: mux IMUX_G2_FAN[1] bit 3 INT: mux DBL_S0[7] bit 5 INT: mux DBL_N0[7] bit 5 INT: mux DBL_N0[7] bit 3 INT: mux DBL_N0[7] bit 1 INT: mux HEX_S0[7] bit 1 INT: mux HEX_S0[7] bit 2 INT: mux HEX_S0[7] bit 5 INT: mux HEX_N0[7] bit 5
B57 - - - - INT: mux IMUX_CLK[2] bit 3 INT: mux IMUX_CLK[2] bit 1 INT: mux OMUX[11] bit 2 INT: mux OMUX[11] bit 7 INT: mux IMUX_G2_FAN[1] bit 8 INT: mux IMUX_G2_FAN[1] bit 11 INT: mux IMUX_G2_FAN[0] bit 7 INT: mux IMUX_G2_FAN[0] bit 4 INT: mux IMUX_G2_FAN[0] bit 0 INT: mux IMUX_G2_FAN[0] bit 2 INT: mux DBL_N0[7] bit 4 INT: mux DBL_S0[7] bit 6 INT: mux DBL_N0[7] bit 2 INT: mux DBL_N0[7] bit 0 INT: mux HEX_N0[7] bit 2 INT: mux HEX_N0[7] bit 0 INT: mux HEX_S0[7] bit 6 INT: mux LV[18] bit 4
B56 - - - - INT: mux IMUX_CLK[3] bit 1 INT: mux IMUX_CLK[3] bit 2 INT: mux OMUX[10] bit 3 INT: mux OMUX[11] bit 3 INT: mux IMUX_G2_FAN[0] bit 8 INT: mux IMUX_G2_FAN[0] bit 11 INT: mux IMUX_G2_FAN[1] bit 7 INT: mux IMUX_G2_FAN[1] bit 4 INT: mux IMUX_G2_FAN[1] bit 0 INT: mux IMUX_G2_FAN[1] bit 2 INT: mux DBL_N0[7] bit 7 INT: mux DBL_S0[7] bit 7 INT: mux DBL_S0[7] bit 0 INT: mux DBL_S0[7] bit 2 INT: mux HEX_S0[7] bit 3 INT: mux HEX_S0[7] bit 0 INT: mux HEX_S0[7] bit 4 INT: mux HEX_N0[7] bit 4
B55 - - - - INT: mux IMUX_CLK[2] bit 4 INT: mux IMUX_CLK[2] bit 2 INT: mux OMUX[11] bit 1 INT: mux OMUX[10] bit 1 INT: mux IMUX_G2_DATA[6] bit 8 INT: mux IMUX_G2_DATA[6] bit 11 INT: mux IMUX_G2_DATA[7] bit 7 INT: mux IMUX_G2_DATA[7] bit 4 INT: mux IMUX_G2_DATA[7] bit 0 INT: mux IMUX_G2_DATA[7] bit 2 INT: mux DBL_E0[6] bit 1 INT: mux DBL_W0[6] bit 7 INT: mux DBL_E0[6] bit 5 INT: mux DBL_E0[6] bit 7 INT: mux HEX_E0[6] bit 1 INT: mux HEX_E0[6] bit 3 INT: mux HEX_E0[6] bit 5 INT: mux LV[6] bit 4
B54 - - - - INT: mux IMUX_CLK[3] bit 4 INT: mux IMUX_CLK[2] bit 9 INT: mux OMUX[11] bit 0 INT: mux OMUX[10] bit 0 INT: mux IMUX_G2_DATA[7] bit 8 INT: mux IMUX_G2_DATA[7] bit 11 INT: mux IMUX_G2_DATA[6] bit 7 INT: mux IMUX_G2_DATA[6] bit 4 INT: mux IMUX_G2_DATA[6] bit 0 INT: mux IMUX_G2_DATA[6] bit 2 INT: mux DBL_E0[6] bit 0 INT: mux DBL_W0[6] bit 5 INT: mux DBL_W0[6] bit 3 INT: mux DBL_W0[6] bit 0 INT: mux HEX_W0[6] bit 1 INT: mux HEX_W0[6] bit 3 INT: mux HEX_W0[6] bit 4 INT: mux HEX_E0[6] bit 4
B53 - - - - INT: mux IMUX_CLK[2] bit 6 INT: mux IMUX_CLK[2] bit 8 INT: mux OMUX[10] bit 5 INT: mux OMUX[11] bit 5 INT: mux IMUX_G2_DATA[7] bit 9 INT: mux IMUX_G2_DATA[7] bit 10 INT: mux IMUX_G2_DATA[7] bit 6 INT: mux IMUX_G2_DATA[7] bit 5 INT: mux IMUX_G2_DATA[7] bit 1 INT: mux IMUX_G2_DATA[7] bit 3 INT: mux DBL_W0[6] bit 4 INT: mux DBL_E0[6] bit 3 INT: mux DBL_W0[6] bit 2 INT: mux DBL_W0[6] bit 1 INT: mux HEX_E0[6] bit 2 INT: mux HEX_E0[6] bit 0 INT: mux HEX_W0[6] bit 5 INT: mux LV[18] bit 5
B52 - - - - INT: invert IMUX_CLK_OPTINV[2] ← IMUX_CLK[2] INT: mux IMUX_CLK[3] bit 5 INT: mux OMUX[11] bit 4 INT: mux OMUX[10] bit 7 INT: mux IMUX_G2_DATA[6] bit 9 INT: mux IMUX_G2_DATA[6] bit 10 INT: mux IMUX_G2_DATA[6] bit 6 INT: mux IMUX_G2_DATA[6] bit 5 INT: mux IMUX_G2_DATA[6] bit 1 INT: mux IMUX_G2_DATA[6] bit 3 INT: mux DBL_W0[6] bit 6 INT: mux DBL_E0[6] bit 2 INT: mux DBL_E0[6] bit 4 INT: mux DBL_E0[6] bit 6 INT: mux HEX_W0[6] bit 2 INT: mux HEX_W0[6] bit 0 INT: mux HEX_W0[6] bit 6 INT: mux HEX_E0[6] bit 6
B51 - - - - INT: mux IMUX_CLK[2] bit 5 INT: mux IMUX_CLK[2] bit 7 INT: mux OMUX[10] bit 8 INT: mux OMUX[10] bit 6 INT: mux IMUX_G2_DATA[4] bit 9 INT: mux IMUX_G2_DATA[4] bit 10 INT: mux IMUX_G2_DATA[4] bit 6 INT: mux IMUX_G2_DATA[4] bit 5 INT: mux IMUX_G2_DATA[4] bit 1 INT: mux IMUX_G2_DATA[4] bit 3 INT: mux DBL_S0[6] bit 3 INT: mux DBL_N0[6] bit 1 INT: mux DBL_S0[6] bit 4 INT: mux DBL_S0[6] bit 7 INT: mux HEX_S0[6] bit 0 INT: mux HEX_S0[6] bit 3 INT: mux HEX_S0[6] bit 4 INT: mux LH[0] bit 0
B50 - - - - INT: mux IMUX_CLK[1] bit 5 INT: mux IMUX_CLK[1] bit 7 INT: mux OMUX[10] bit 4 INT: mux OMUX[10] bit 9 INT: mux IMUX_G2_DATA[5] bit 9 INT: mux IMUX_G2_DATA[5] bit 10 INT: mux IMUX_G2_DATA[5] bit 6 INT: mux IMUX_G2_DATA[5] bit 5 INT: mux IMUX_G2_DATA[5] bit 1 INT: mux IMUX_G2_DATA[5] bit 3 INT: mux DBL_S0[6] bit 0 INT: mux DBL_N0[6] bit 0 INT: mux DBL_N0[6] bit 7 INT: mux DBL_N0[6] bit 4 INT: mux HEX_N0[6] bit 0 INT: mux HEX_N0[6] bit 2 INT: mux HEX_N0[6] bit 4 INT: mux HEX_S0[6] bit 5
B49 - - - - INT: invert IMUX_CLK_OPTINV[1] ← IMUX_CLK[1] - INT: mux OMUX[8] bit 2 INT: mux OMUX[9] bit 9 INT: mux IMUX_G2_DATA[5] bit 8 INT: mux IMUX_G2_DATA[5] bit 11 INT: mux IMUX_G2_DATA[4] bit 7 INT: mux IMUX_G2_DATA[4] bit 4 INT: mux IMUX_G2_DATA[4] bit 0 INT: mux IMUX_G2_DATA[4] bit 2 INT: mux DBL_N0[6] bit 3 INT: mux DBL_S0[6] bit 1 INT: mux DBL_N0[6] bit 6 INT: mux DBL_N0[6] bit 5 INT: mux HEX_S0[6] bit 2 INT: mux HEX_S0[6] bit 1 INT: mux HEX_N0[6] bit 5 INT: mux LH[0] bit 1
B48 - - - - INT: mux IMUX_CLK[1] bit 6 INT: mux IMUX_CLK[1] bit 8 INT: mux OMUX[9] bit 8 INT: mux OMUX[9] bit 6 INT: mux IMUX_G2_DATA[4] bit 8 INT: mux IMUX_G2_DATA[4] bit 11 INT: mux IMUX_G2_DATA[5] bit 7 INT: mux IMUX_G2_DATA[5] bit 4 INT: mux IMUX_G2_DATA[5] bit 0 INT: mux IMUX_G2_DATA[5] bit 2 INT: mux DBL_N0[6] bit 2 INT: mux DBL_S0[6] bit 2 INT: mux DBL_S0[6] bit 5 INT: mux DBL_S0[6] bit 6 INT: mux HEX_N0[6] bit 3 INT: mux HEX_N0[6] bit 1 INT: mux HEX_N0[6] bit 6 INT: mux HEX_S0[6] bit 6
B47 - - - - - INT: mux IMUX_CLK[1] bit 9 INT: mux OMUX[9] bit 2 INT: mux OMUX[9] bit 7 INT: mux IMUX_G2_DATA[2] bit 8 INT: mux IMUX_G2_DATA[2] bit 11 INT: mux IMUX_G2_DATA[3] bit 7 INT: mux IMUX_G2_DATA[3] bit 4 INT: mux IMUX_G2_DATA[3] bit 0 INT: mux IMUX_G2_DATA[3] bit 2 INT: mux DBL_E0[5] bit 2 INT: mux DBL_W0[5] bit 3 INT: mux DBL_E0[5] bit 4 INT: mux DBL_E0[5] bit 7 INT: mux HEX_W0[5] bit 1 INT: mux HEX_W0[5] bit 3 INT: mux HEX_W0[5] bit 5 INT: mux LH[0] bit 2
B46 - - - - INT: mux IMUX_CLK[1] bit 4 INT: mux IMUX_CLK[1] bit 2 INT: mux OMUX[8] bit 3 INT: mux OMUX[9] bit 3 INT: mux IMUX_G2_DATA[3] bit 8 INT: mux IMUX_G2_DATA[3] bit 11 INT: mux IMUX_G2_DATA[2] bit 7 INT: mux IMUX_G2_DATA[2] bit 4 INT: mux IMUX_G2_DATA[2] bit 0 INT: mux IMUX_G2_DATA[2] bit 2 INT: mux DBL_E0[5] bit 0 INT: mux DBL_W0[5] bit 0 INT: mux DBL_W0[5] bit 7 INT: mux DBL_W0[5] bit 5 INT: mux HEX_E0[5] bit 0 INT: mux HEX_E0[5] bit 3 INT: mux HEX_E0[5] bit 4 INT: mux HEX_W0[5] bit 4
B45 - - - - - - INT: mux OMUX[9] bit 1 INT: mux OMUX[8] bit 1 INT: mux IMUX_G2_DATA[3] bit 9 INT: mux IMUX_G2_DATA[3] bit 10 INT: mux IMUX_G2_DATA[3] bit 6 INT: mux IMUX_G2_DATA[3] bit 5 INT: mux IMUX_G2_DATA[3] bit 1 INT: mux IMUX_G2_DATA[3] bit 3 INT: mux DBL_W0[5] bit 2 INT: mux DBL_E0[5] bit 3 INT: mux DBL_W0[5] bit 6 INT: mux DBL_W0[5] bit 4 INT: mux HEX_W0[5] bit 2 INT: mux HEX_W0[5] bit 0 INT: mux HEX_E0[5] bit 5 INT: mux LH[12] bit 1
B44 - - - - INT: mux IMUX_CLK[1] bit 3 INT: mux IMUX_CLK[1] bit 1 INT: mux OMUX[9] bit 0 INT: mux OMUX[8] bit 0 INT: mux IMUX_G2_DATA[2] bit 9 INT: mux IMUX_G2_DATA[2] bit 10 INT: mux IMUX_G2_DATA[2] bit 6 INT: mux IMUX_G2_DATA[2] bit 5 INT: mux IMUX_G2_DATA[2] bit 1 INT: mux IMUX_G2_DATA[2] bit 3 INT: mux DBL_W0[5] bit 1 INT: mux DBL_E0[5] bit 1 INT: mux DBL_E0[5] bit 5 INT: mux DBL_E0[5] bit 6 INT: mux HEX_E0[5] bit 2 INT: mux HEX_E0[5] bit 1 INT: mux HEX_E0[5] bit 6 INT: mux HEX_W0[5] bit 6
B43 - - - - - - INT: mux OMUX[8] bit 5 INT: mux OMUX[9] bit 5 INT: mux IMUX_BRAM_ADDRB[2] bit 9 INT: mux IMUX_BRAM_ADDRB[2] bit 10 INT: mux IMUX_BRAM_ADDRB[2] bit 6 INT: mux IMUX_BRAM_ADDRB[2] bit 5 INT: mux IMUX_BRAM_ADDRB[2] bit 2 INT: mux IMUX_BRAM_ADDRB[2] bit 3 INT: mux DBL_S0[5] bit 3 INT: mux DBL_N0[5] bit 1 INT: mux DBL_S0[5] bit 4 INT: mux DBL_S0[5] bit 7 INT: mux HEX_N0[5] bit 1 INT: mux HEX_N0[5] bit 3 INT: mux HEX_N0[5] bit 5 INT: mux LH[12] bit 0
B42 - - - - - - INT: mux OMUX[9] bit 4 INT: mux OMUX[8] bit 7 INT: mux IMUX_BRAM_ADDRA[2] bit 9 INT: mux IMUX_BRAM_ADDRA[2] bit 10 INT: mux IMUX_BRAM_ADDRA[2] bit 6 INT: mux IMUX_BRAM_ADDRA[2] bit 5 INT: mux IMUX_BRAM_ADDRA[2] bit 2 INT: mux IMUX_BRAM_ADDRA[2] bit 3 INT: mux DBL_S0[5] bit 0 INT: mux DBL_N0[5] bit 0 INT: mux DBL_N0[5] bit 7 INT: mux DBL_N0[5] bit 5 INT: mux HEX_S0[5] bit 0 INT: mux HEX_S0[5] bit 2 INT: mux HEX_S0[5] bit 4 INT: mux HEX_N0[5] bit 4
B41 - - - - - - INT: mux OMUX[8] bit 8 INT: mux OMUX[8] bit 6 INT: mux IMUX_BRAM_ADDRA[2] bit 8 INT: mux IMUX_BRAM_ADDRA[2] bit 11 INT: mux IMUX_BRAM_ADDRB[2] bit 7 INT: mux IMUX_BRAM_ADDRB[2] bit 4 INT: mux IMUX_BRAM_ADDRB[2] bit 0 INT: mux IMUX_BRAM_ADDRB[2] bit 1 INT: mux DBL_N0[5] bit 3 INT: mux DBL_S0[5] bit 1 INT: mux DBL_N0[5] bit 6 INT: mux DBL_N0[5] bit 4 INT: mux HEX_N0[5] bit 2 INT: mux HEX_N0[5] bit 0 INT: mux HEX_S0[5] bit 5 INT: mux LH[12] bit 2
B40 - - - - INT: mux IMUX_CLK[1] bit 0 - INT: mux OMUX[8] bit 4 INT: mux OMUX[8] bit 9 INT: mux IMUX_BRAM_ADDRB[2] bit 8 INT: mux IMUX_BRAM_ADDRB[2] bit 11 INT: mux IMUX_BRAM_ADDRA[2] bit 7 INT: mux IMUX_BRAM_ADDRA[2] bit 4 INT: mux IMUX_BRAM_ADDRA[2] bit 0 INT: mux IMUX_BRAM_ADDRA[2] bit 1 INT: mux DBL_N0[5] bit 2 INT: mux DBL_S0[5] bit 2 INT: mux DBL_S0[5] bit 5 INT: mux DBL_S0[5] bit 6 INT: mux HEX_S0[5] bit 3 INT: mux HEX_S0[5] bit 1 INT: mux HEX_S0[5] bit 6 INT: mux HEX_N0[5] bit 6
B39 - - - - - INT: mux IMUX_TS[0] bit 7 INT: mux OMUX[6] bit 2 INT: mux OMUX[7] bit 9 INT: mux IMUX_BRAM_ADDRB[1] bit 8 INT: mux IMUX_BRAM_ADDRB[1] bit 11 INT: mux IMUX_BRAM_ADDRA[1] bit 7 INT: mux IMUX_BRAM_ADDRA[1] bit 5 INT: mux IMUX_BRAM_ADDRA[1] bit 0 INT: mux IMUX_BRAM_ADDRA[1] bit 2 INT: mux DBL_E0[4] bit 2 INT: mux DBL_W0[4] bit 3 INT: mux DBL_E0[4] bit 5 INT: mux DBL_E0[4] bit 7 INT: mux HEX_E0[4] bit 1 INT: mux HEX_E0[4] bit 3 INT: mux HEX_E0[4] bit 5 INT: mux LH[18] bit 2
B38 - - - - INT: invert IMUX_TS_OPTINV[0] ← IMUX_TS[0] INT: mux IMUX_TS[0] bit 5 INT: mux OMUX[7] bit 8 INT: mux OMUX[7] bit 6 INT: mux IMUX_BRAM_ADDRA[1] bit 8 INT: mux IMUX_BRAM_ADDRA[1] bit 11 INT: mux IMUX_BRAM_ADDRB[1] bit 7 INT: mux IMUX_BRAM_ADDRB[1] bit 5 INT: mux IMUX_BRAM_ADDRB[1] bit 0 INT: mux IMUX_BRAM_ADDRB[1] bit 2 INT: mux DBL_E0[4] bit 0 INT: mux DBL_W0[4] bit 0 INT: mux DBL_W0[4] bit 7 INT: mux DBL_W0[4] bit 5 INT: mux HEX_W0[4] bit 1 INT: mux HEX_W0[4] bit 3 INT: mux HEX_W0[4] bit 5 INT: mux HEX_E0[4] bit 4
B37 - - - - INT: mux IMUX_TS[0] bit 8 INT: mux IMUX_TS[0] bit 6 INT: mux OMUX[7] bit 2 INT: mux OMUX[7] bit 7 INT: mux IMUX_BRAM_ADDRA[1] bit 10 INT: mux IMUX_BRAM_ADDRA[1] bit 9 INT: mux IMUX_BRAM_ADDRA[1] bit 6 INT: mux IMUX_BRAM_ADDRA[1] bit 4 INT: mux IMUX_BRAM_ADDRA[1] bit 1 INT: mux IMUX_BRAM_ADDRA[1] bit 3 INT: mux DBL_W0[4] bit 2 INT: mux DBL_E0[4] bit 3 INT: mux DBL_W0[4] bit 6 INT: mux DBL_W0[4] bit 4 INT: mux HEX_E0[4] bit 2 INT: mux HEX_E0[4] bit 0 INT: mux HEX_W0[4] bit 4 INT: mux LH[18] bit 1
B36 - - - - INT: mux IMUX_TS[0] bit 0 - INT: mux OMUX[6] bit 3 INT: mux OMUX[7] bit 3 INT: mux IMUX_BRAM_ADDRB[1] bit 10 INT: mux IMUX_BRAM_ADDRB[1] bit 9 INT: mux IMUX_BRAM_ADDRB[1] bit 6 INT: mux IMUX_BRAM_ADDRB[1] bit 4 INT: mux IMUX_BRAM_ADDRB[1] bit 1 INT: mux IMUX_BRAM_ADDRB[1] bit 3 INT: mux DBL_W0[4] bit 1 INT: mux DBL_E0[4] bit 1 INT: mux DBL_E0[4] bit 4 INT: mux DBL_E0[4] bit 6 INT: mux HEX_W0[4] bit 2 INT: mux HEX_W0[4] bit 0 INT: mux HEX_W0[4] bit 6 INT: mux HEX_E0[4] bit 6
B35 - - - - INT: mux IMUX_TS[1] bit 0 INT: mux IMUX_TS[1] bit 1 INT: mux OMUX[7] bit 1 INT: mux OMUX[6] bit 1 - - - - - - INT: mux DBL_S0[4] bit 3 INT: mux DBL_N0[4] bit 1 INT: mux DBL_S0[4] bit 4 INT: mux DBL_S0[4] bit 7 INT: mux HEX_S0[4] bit 0 INT: mux HEX_S0[4] bit 3 INT: mux HEX_S0[4] bit 4 INT: mux LH[18] bit 0
B34 - - - - INT: mux IMUX_TS[0] bit 1 INT: mux IMUX_TS[0] bit 2 INT: mux OMUX[7] bit 0 INT: mux OMUX[6] bit 0 - - - - - - INT: mux DBL_S0[4] bit 0 INT: mux DBL_N0[4] bit 0 INT: mux DBL_N0[4] bit 7 INT: mux DBL_N0[4] bit 4 INT: mux HEX_N0[4] bit 0 INT: mux HEX_N0[4] bit 2 INT: mux HEX_N0[4] bit 4 INT: mux HEX_S0[4] bit 5
B33 - - - - INT: mux IMUX_TS[1] bit 3 INT: mux IMUX_TS[1] bit 2 INT: mux OMUX[6] bit 5 INT: mux OMUX[7] bit 5 - - - - - - INT: mux DBL_N0[4] bit 3 INT: mux DBL_S0[4] bit 1 INT: mux DBL_N0[4] bit 6 INT: mux DBL_N0[4] bit 5 INT: mux HEX_S0[4] bit 2 INT: mux HEX_S0[4] bit 1 INT: mux HEX_N0[4] bit 5 INT: mux LH[6] bit 1
B32 - - - - INT: mux IMUX_TS[0] bit 3 INT: mux IMUX_TS[1] bit 5 INT: mux OMUX[7] bit 4 INT: mux OMUX[6] bit 7 - - - - - - INT: mux DBL_N0[4] bit 2 INT: mux DBL_S0[4] bit 2 INT: mux DBL_S0[4] bit 5 INT: mux DBL_S0[4] bit 6 INT: mux HEX_N0[4] bit 3 INT: mux HEX_N0[4] bit 1 INT: mux HEX_N0[4] bit 6 INT: mux HEX_S0[4] bit 6
B31 - - - - INT: mux IMUX_TS[1] bit 8 INT: mux IMUX_TS[1] bit 6 INT: mux OMUX[6] bit 8 INT: mux OMUX[6] bit 6 INT: mux IMUX_G1_DATA[4] bit 9 INT: mux IMUX_G1_DATA[4] bit 11 INT: mux IMUX_G1_DATA[5] bit 7 INT: mux IMUX_G1_DATA[5] bit 5 INT: mux IMUX_G1_DATA[5] bit 1 INT: mux IMUX_G1_DATA[5] bit 2 INT: mux DBL_E0[3] bit 2 INT: mux DBL_W0[3] bit 3 INT: mux DBL_E0[3] bit 4 INT: mux DBL_E0[3] bit 7 INT: mux HEX_W0[3] bit 1 INT: mux HEX_W0[3] bit 3 INT: mux HEX_W0[3] bit 5 INT: mux LH[6] bit 2
B30 - - - - INT: invert IMUX_TS_OPTINV[1] ← IMUX_TS[1] INT: mux IMUX_TS[0] bit 4 INT: mux OMUX[6] bit 4 INT: mux OMUX[6] bit 9 INT: mux IMUX_G1_DATA[5] bit 9 INT: mux IMUX_G1_DATA[5] bit 11 INT: mux IMUX_G1_DATA[4] bit 7 INT: mux IMUX_G1_DATA[4] bit 5 INT: mux IMUX_G1_DATA[4] bit 1 INT: mux IMUX_G1_DATA[4] bit 2 INT: mux DBL_E0[3] bit 0 INT: mux DBL_W0[3] bit 0 INT: mux DBL_W0[3] bit 7 INT: mux DBL_W0[3] bit 5 INT: mux HEX_E0[3] bit 0 INT: mux HEX_E0[3] bit 3 INT: mux HEX_E0[3] bit 4 INT: mux HEX_W0[3] bit 4
B29 - - - - INT: mux IMUX_TS[1] bit 4 INT: mux IMUX_TS[1] bit 7 INT: mux OMUX[4] bit 2 INT: mux OMUX[5] bit 9 INT: mux IMUX_G1_DATA[5] bit 8 INT: mux IMUX_G1_DATA[5] bit 10 INT: mux IMUX_G1_DATA[5] bit 6 INT: mux IMUX_G1_DATA[5] bit 4 INT: mux IMUX_G1_DATA[5] bit 0 INT: mux IMUX_G1_DATA[5] bit 3 INT: mux DBL_W0[3] bit 2 INT: mux DBL_E0[3] bit 3 INT: mux DBL_W0[3] bit 6 INT: mux DBL_W0[3] bit 4 INT: mux HEX_W0[3] bit 2 INT: mux HEX_W0[3] bit 0 INT: mux HEX_E0[3] bit 5 INT: mux LH[6] bit 0
B28 - - - - - - INT: mux OMUX[5] bit 8 INT: mux OMUX[5] bit 6 INT: mux IMUX_G1_DATA[4] bit 8 INT: mux IMUX_G1_DATA[4] bit 10 INT: mux IMUX_G1_DATA[4] bit 6 INT: mux IMUX_G1_DATA[4] bit 4 INT: mux IMUX_G1_DATA[4] bit 0 INT: mux IMUX_G1_DATA[4] bit 3 INT: mux DBL_W0[3] bit 1 INT: mux DBL_E0[3] bit 1 INT: mux DBL_E0[3] bit 5 INT: mux DBL_E0[3] bit 6 INT: mux HEX_E0[3] bit 2 INT: mux HEX_E0[3] bit 1 INT: mux HEX_E0[3] bit 6 INT: mux HEX_W0[3] bit 6
B27 - - - - - - INT: mux OMUX[5] bit 2 INT: mux OMUX[5] bit 7 INT: mux IMUX_G1_DATA[6] bit 8 INT: mux IMUX_G1_DATA[6] bit 10 INT: mux IMUX_G1_DATA[6] bit 6 INT: mux IMUX_G1_DATA[6] bit 4 INT: mux IMUX_G1_DATA[6] bit 0 INT: mux IMUX_G1_DATA[6] bit 3 INT: mux DBL_S0[3] bit 3 INT: mux DBL_N0[3] bit 1 INT: mux DBL_S0[3] bit 5 INT: mux DBL_S0[3] bit 7 INT: mux HEX_N0[3] bit 0 INT: mux HEX_N0[3] bit 3 INT: mux HEX_N0[3] bit 4 INT: mux LV[12] bit 4
B26 - - - - - - INT: mux OMUX[4] bit 3 INT: mux OMUX[5] bit 3 INT: mux IMUX_G1_DATA[7] bit 8 INT: mux IMUX_G1_DATA[7] bit 10 INT: mux IMUX_G1_DATA[7] bit 6 INT: mux IMUX_G1_DATA[7] bit 4 INT: mux IMUX_G1_DATA[7] bit 0 INT: mux IMUX_G1_DATA[7] bit 3 INT: mux DBL_S0[3] bit 0 INT: mux DBL_N0[3] bit 0 INT: mux DBL_N0[3] bit 7 INT: mux DBL_N0[3] bit 4 INT: mux HEX_S0[3] bit 1 INT: mux HEX_S0[3] bit 2 INT: mux HEX_S0[3] bit 5 INT: mux HEX_N0[3] bit 5
B25 - - - - - - INT: mux OMUX[5] bit 1 INT: mux OMUX[4] bit 1 INT: mux IMUX_G1_DATA[7] bit 9 INT: mux IMUX_G1_DATA[7] bit 11 INT: mux IMUX_G1_DATA[6] bit 7 INT: mux IMUX_G1_DATA[6] bit 5 INT: mux IMUX_G1_DATA[6] bit 1 INT: mux IMUX_G1_DATA[6] bit 2 INT: mux DBL_N0[3] bit 3 INT: mux DBL_S0[3] bit 1 INT: mux DBL_N0[3] bit 6 INT: mux DBL_N0[3] bit 5 INT: mux HEX_N0[3] bit 2 INT: mux HEX_N0[3] bit 1 INT: mux HEX_S0[3] bit 4 INT: mux LV[0] bit 3
B24 - - - - - - INT: mux OMUX[5] bit 0 INT: mux OMUX[4] bit 0 INT: mux IMUX_G1_DATA[6] bit 9 INT: mux IMUX_G1_DATA[6] bit 11 INT: mux IMUX_G1_DATA[7] bit 7 INT: mux IMUX_G1_DATA[7] bit 5 INT: mux IMUX_G1_DATA[7] bit 1 INT: mux IMUX_G1_DATA[7] bit 2 INT: mux DBL_N0[3] bit 2 INT: mux DBL_S0[3] bit 2 INT: mux DBL_S0[3] bit 4 INT: mux DBL_S0[3] bit 6 INT: mux HEX_S0[3] bit 3 INT: mux HEX_S0[3] bit 0 INT: mux HEX_S0[3] bit 6 INT: mux HEX_N0[3] bit 6
B23 - - - - - - INT: mux OMUX[4] bit 5 INT: mux OMUX[5] bit 5 INT: mux IMUX_G1_FAN[0] bit 9 INT: mux IMUX_G1_FAN[0] bit 11 INT: mux IMUX_G1_FAN[1] bit 7 INT: mux IMUX_G1_FAN[1] bit 5 INT: mux IMUX_G1_FAN[1] bit 1 INT: mux IMUX_G1_FAN[1] bit 2 INT: mux DBL_E0[2] bit 4 INT: mux DBL_W0[2] bit 7 INT: mux DBL_E0[2] bit 1 INT: mux DBL_E0[2] bit 3 INT: mux HEX_E0[2] bit 1 INT: mux HEX_E0[2] bit 3 INT: mux HEX_E0[2] bit 5 INT: mux LV[12] bit 3
B22 - - - - - - INT: mux OMUX[5] bit 4 INT: mux OMUX[4] bit 7 INT: mux IMUX_G1_FAN[1] bit 9 INT: mux IMUX_G1_FAN[1] bit 11 INT: mux IMUX_G1_FAN[0] bit 7 INT: mux IMUX_G1_FAN[0] bit 5 INT: mux IMUX_G1_FAN[0] bit 1 INT: mux IMUX_G1_FAN[0] bit 2 INT: mux DBL_E0[2] bit 5 INT: mux DBL_W0[2] bit 5 INT: mux DBL_W0[2] bit 3 INT: mux DBL_W0[2] bit 1 INT: mux HEX_W0[2] bit 1 INT: mux HEX_W0[2] bit 3 INT: mux HEX_W0[2] bit 6 INT: mux HEX_E0[2] bit 6
B21 - - - - - - INT: mux OMUX[4] bit 8 INT: mux OMUX[4] bit 6 INT: mux IMUX_G1_FAN[1] bit 8 INT: mux IMUX_G1_FAN[1] bit 10 INT: mux IMUX_G1_FAN[1] bit 6 INT: mux IMUX_G1_FAN[1] bit 4 INT: mux IMUX_G1_FAN[1] bit 0 INT: mux IMUX_G1_FAN[1] bit 3 INT: mux DBL_W0[2] bit 4 INT: mux DBL_E0[2] bit 7 INT: mux DBL_W0[2] bit 2 INT: mux DBL_W0[2] bit 0 INT: mux HEX_E0[2] bit 2 INT: mux HEX_E0[2] bit 0 INT: mux HEX_W0[2] bit 5 INT: mux LV[0] bit 2
B20 - - - - - - INT: mux OMUX[4] bit 4 INT: mux OMUX[4] bit 9 INT: mux IMUX_G1_FAN[0] bit 8 INT: mux IMUX_G1_FAN[0] bit 10 INT: mux IMUX_G1_FAN[0] bit 6 INT: mux IMUX_G1_FAN[0] bit 4 INT: mux IMUX_G1_FAN[0] bit 0 INT: mux IMUX_G1_FAN[0] bit 3 INT: mux DBL_W0[2] bit 6 INT: mux DBL_E0[2] bit 6 INT: mux DBL_E0[2] bit 0 INT: mux DBL_E0[2] bit 2 INT: mux HEX_W0[2] bit 2 INT: mux HEX_W0[2] bit 0 INT: mux HEX_W0[2] bit 4 INT: mux HEX_E0[2] bit 4
B19 - - - - - - INT: mux OMUX[2] bit 2 INT: mux OMUX[3] bit 9 INT: mux IMUX_G0_FAN[0] bit 9 INT: mux IMUX_G0_FAN[0] bit 10 INT: mux IMUX_G0_FAN[0] bit 6 INT: mux IMUX_G0_FAN[0] bit 5 INT: mux IMUX_G0_FAN[0] bit 2 INT: mux IMUX_G0_FAN[0] bit 1 INT: mux DBL_S0[2] bit 4 INT: mux DBL_N0[2] bit 6 INT: mux DBL_S0[2] bit 0 INT: mux DBL_S0[2] bit 3 INT: mux HEX_S0[2] bit 0 INT: mux HEX_S0[2] bit 3 INT: mux HEX_S0[2] bit 5 INT: mux LV[0] bit 4
B18 - - - - - - INT: mux OMUX[3] bit 8 INT: mux OMUX[3] bit 6 INT: mux IMUX_G0_FAN[1] bit 9 INT: mux IMUX_G0_FAN[1] bit 10 INT: mux IMUX_G0_FAN[1] bit 6 INT: mux IMUX_G0_FAN[1] bit 5 INT: mux IMUX_G0_FAN[1] bit 2 INT: mux IMUX_G0_FAN[1] bit 1 INT: mux DBL_S0[2] bit 5 INT: mux DBL_N0[2] bit 5 INT: mux DBL_N0[2] bit 3 INT: mux DBL_N0[2] bit 0 INT: mux HEX_N0[2] bit 1 INT: mux HEX_N0[2] bit 2 INT: mux HEX_N0[2] bit 4 INT: mux HEX_S0[2] bit 4
B17 - - - - - INT: mux IMUX_SR[1] bit 1 INT: mux OMUX[3] bit 2 INT: mux OMUX[3] bit 7 INT: mux IMUX_G0_FAN[1] bit 8 INT: mux IMUX_G0_FAN[1] bit 11 INT: mux IMUX_G0_FAN[0] bit 7 INT: mux IMUX_G0_FAN[0] bit 4 INT: mux IMUX_G0_FAN[0] bit 0 INT: mux IMUX_G0_FAN[0] bit 3 INT: mux DBL_N0[2] bit 4 INT: mux DBL_S0[2] bit 6 INT: mux DBL_N0[2] bit 2 INT: mux DBL_N0[2] bit 1 INT: mux HEX_S0[2] bit 2 INT: mux HEX_S0[2] bit 1 INT: mux HEX_N0[2] bit 5 INT: mux LV[12] bit 2
B16 - - - - INT: !invert IMUX_SR_OPTINV[1] ← IMUX_SR[1] INT: mux IMUX_SR[1] bit 3 INT: mux OMUX[2] bit 3 INT: mux OMUX[3] bit 3 INT: mux IMUX_G0_FAN[0] bit 8 INT: mux IMUX_G0_FAN[0] bit 11 INT: mux IMUX_G0_FAN[1] bit 7 INT: mux IMUX_G0_FAN[1] bit 4 INT: mux IMUX_G0_FAN[1] bit 0 INT: mux IMUX_G0_FAN[1] bit 3 INT: mux DBL_N0[2] bit 7 INT: mux DBL_S0[2] bit 7 INT: mux DBL_S0[2] bit 1 INT: mux DBL_S0[2] bit 2 INT: mux HEX_N0[2] bit 3 INT: mux HEX_N0[2] bit 0 INT: mux HEX_N0[2] bit 6 INT: mux HEX_S0[2] bit 6
B15 - - - - INT: mux IMUX_SR[1] bit 0 INT: mux IMUX_SR[1] bit 2 INT: mux OMUX[3] bit 1 INT: mux OMUX[2] bit 1 INT: mux IMUX_G0_DATA[6] bit 8 INT: mux IMUX_G0_DATA[6] bit 11 INT: mux IMUX_G0_DATA[7] bit 7 INT: mux IMUX_G0_DATA[7] bit 4 INT: mux IMUX_G0_DATA[7] bit 0 INT: mux IMUX_G0_DATA[7] bit 3 INT: mux DBL_E0[1] bit 2 INT: mux DBL_W0[1] bit 3 INT: mux DBL_E0[1] bit 4 INT: mux DBL_E0[1] bit 7 INT: mux HEX_W0[1] bit 1 INT: mux HEX_W0[1] bit 2 INT: mux HEX_W0[1] bit 5 INT: mux LV[12] bit 0
B14 - - - - INT: mux IMUX_SR[1] bit 4 INT: mux IMUX_SR[1] bit 5 INT: mux OMUX[3] bit 0 INT: mux OMUX[2] bit 0 INT: mux IMUX_G0_DATA[7] bit 8 INT: mux IMUX_G0_DATA[7] bit 11 INT: mux IMUX_G0_DATA[6] bit 7 INT: mux IMUX_G0_DATA[6] bit 4 INT: mux IMUX_G0_DATA[6] bit 0 INT: mux IMUX_G0_DATA[6] bit 3 INT: mux DBL_E0[1] bit 0 INT: mux DBL_W0[1] bit 0 INT: mux DBL_W0[1] bit 6 INT: mux DBL_W0[1] bit 5 INT: mux HEX_E0[1] bit 0 INT: mux HEX_E0[1] bit 3 INT: mux HEX_E0[1] bit 4 INT: mux HEX_W0[1] bit 4
B13 - - - - - - INT: mux OMUX[2] bit 5 INT: mux OMUX[3] bit 5 INT: mux IMUX_G0_DATA[7] bit 9 INT: mux IMUX_G0_DATA[7] bit 10 INT: mux IMUX_G0_DATA[7] bit 6 INT: mux IMUX_G0_DATA[7] bit 5 INT: mux IMUX_G0_DATA[7] bit 2 INT: mux IMUX_G0_DATA[7] bit 1 INT: mux DBL_W0[1] bit 2 INT: mux DBL_E0[1] bit 3 INT: mux DBL_W0[1] bit 7 INT: mux DBL_W0[1] bit 4 INT: mux HEX_W0[1] bit 3 INT: mux HEX_W0[1] bit 0 INT: mux HEX_E0[1] bit 5 INT: mux LV[12] bit 6
B12 - - - - INT: mux IMUX_SR[1] bit 7 INT: mux IMUX_SR[1] bit 6 INT: mux OMUX[3] bit 4 INT: mux OMUX[2] bit 7 INT: mux IMUX_G0_DATA[6] bit 9 INT: mux IMUX_G0_DATA[6] bit 10 INT: mux IMUX_G0_DATA[6] bit 6 INT: mux IMUX_G0_DATA[6] bit 5 INT: mux IMUX_G0_DATA[6] bit 2 INT: mux IMUX_G0_DATA[6] bit 1 INT: mux DBL_W0[1] bit 1 INT: mux DBL_E0[1] bit 1 INT: mux DBL_E0[1] bit 5 INT: mux DBL_E0[1] bit 6 INT: mux HEX_E0[1] bit 2 INT: mux HEX_E0[1] bit 1 INT: mux HEX_E0[1] bit 6 INT: mux HEX_W0[1] bit 6
B11 - - - - - - INT: mux OMUX[2] bit 8 INT: mux OMUX[2] bit 6 INT: mux IMUX_G0_DATA[4] bit 9 INT: mux IMUX_G0_DATA[4] bit 10 INT: mux IMUX_G0_DATA[4] bit 6 INT: mux IMUX_G0_DATA[4] bit 5 INT: mux IMUX_G0_DATA[4] bit 2 INT: mux IMUX_G0_DATA[4] bit 1 INT: mux DBL_S0[1] bit 3 INT: mux DBL_N0[1] bit 1 INT: mux DBL_S0[1] bit 4 INT: mux DBL_S0[1] bit 7 INT: mux HEX_N0[1] bit 0 INT: mux HEX_N0[1] bit 3 INT: mux HEX_N0[1] bit 4 INT: mux LV[0] bit 1
B10 - - - - - - INT: mux OMUX[2] bit 4 INT: mux OMUX[2] bit 9 INT: mux IMUX_G0_DATA[5] bit 9 INT: mux IMUX_G0_DATA[5] bit 10 INT: mux IMUX_G0_DATA[5] bit 6 INT: mux IMUX_G0_DATA[5] bit 5 INT: mux IMUX_G0_DATA[5] bit 2 INT: mux IMUX_G0_DATA[5] bit 1 INT: mux DBL_S0[1] bit 0 INT: mux DBL_N0[1] bit 0 INT: mux DBL_N0[1] bit 7 INT: mux DBL_N0[1] bit 4 INT: mux HEX_S0[1] bit 0 INT: mux HEX_S0[1] bit 2 INT: mux HEX_S0[1] bit 4 INT: mux HEX_N0[1] bit 5
B9 - - - - - - INT: mux OMUX[0] bit 2 INT: mux OMUX[1] bit 9 INT: mux IMUX_G0_DATA[5] bit 8 INT: mux IMUX_G0_DATA[5] bit 11 INT: mux IMUX_G0_DATA[4] bit 7 INT: mux IMUX_G0_DATA[4] bit 4 INT: mux IMUX_G0_DATA[4] bit 0 INT: mux IMUX_G0_DATA[4] bit 3 INT: mux DBL_N0[1] bit 3 INT: mux DBL_S0[1] bit 1 INT: mux DBL_N0[1] bit 6 INT: mux DBL_N0[1] bit 5 INT: mux HEX_N0[1] bit 2 INT: mux HEX_N0[1] bit 1 INT: mux HEX_S0[1] bit 5 INT: mux LV[0] bit 5
B8 - - - - INT: mux IMUX_SR[2] bit 5 INT: mux IMUX_SR[2] bit 2 INT: mux OMUX[1] bit 8 INT: mux OMUX[1] bit 6 INT: mux IMUX_G0_DATA[4] bit 8 INT: mux IMUX_G0_DATA[4] bit 11 INT: mux IMUX_G0_DATA[5] bit 7 INT: mux IMUX_G0_DATA[5] bit 4 INT: mux IMUX_G0_DATA[5] bit 0 INT: mux IMUX_G0_DATA[5] bit 3 INT: mux DBL_N0[1] bit 2 INT: mux DBL_S0[1] bit 2 INT: mux DBL_S0[1] bit 5 INT: mux DBL_S0[1] bit 6 INT: mux HEX_S0[1] bit 3 INT: mux HEX_S0[1] bit 1 INT: mux HEX_S0[1] bit 6 INT: mux HEX_N0[1] bit 6
B7 - - - - INT: !invert IMUX_SR_OPTINV[2] ← IMUX_SR[2] INT: mux IMUX_SR[2] bit 3 INT: mux OMUX[1] bit 2 INT: mux OMUX[1] bit 7 INT: mux IMUX_G0_DATA[2] bit 8 INT: mux IMUX_G0_DATA[2] bit 11 INT: mux IMUX_G0_DATA[3] bit 7 INT: mux IMUX_G0_DATA[3] bit 4 INT: mux IMUX_G0_DATA[3] bit 0 INT: mux IMUX_G0_DATA[3] bit 3 INT: mux DBL_E0[0] bit 2 INT: mux DBL_W0[0] bit 3 INT: mux DBL_E0[0] bit 4 INT: mux DBL_E0[0] bit 7 INT: mux HEX_E0[0] bit 0 INT: mux HEX_E0[0] bit 3 INT: mux HEX_E0[0] bit 4 INT: mux LV[0] bit 6
B6 - - - - INT: mux IMUX_SR[2] bit 1 INT: mux IMUX_SR[2] bit 0 INT: mux OMUX[0] bit 3 INT: mux OMUX[1] bit 3 INT: mux IMUX_G0_DATA[3] bit 8 INT: mux IMUX_G0_DATA[3] bit 11 INT: mux IMUX_G0_DATA[2] bit 7 INT: mux IMUX_G0_DATA[2] bit 4 INT: mux IMUX_G0_DATA[2] bit 0 INT: mux IMUX_G0_DATA[2] bit 3 INT: mux DBL_E0[0] bit 0 INT: mux DBL_W0[0] bit 0 INT: mux DBL_W0[0] bit 6 INT: mux DBL_W0[0] bit 5 INT: mux HEX_W0[0] bit 1 INT: mux HEX_W0[0] bit 2 INT: mux HEX_W0[0] bit 5 INT: mux HEX_E0[0] bit 5
B5 - - - - INT: mux IMUX_SR[0] bit 4 INT: mux IMUX_SR[0] bit 5 INT: mux OMUX[1] bit 1 INT: mux OMUX[0] bit 1 INT: mux IMUX_G0_DATA[3] bit 9 INT: mux IMUX_G0_DATA[3] bit 10 INT: mux IMUX_G0_DATA[3] bit 6 INT: mux IMUX_G0_DATA[3] bit 5 INT: mux IMUX_G0_DATA[3] bit 2 INT: mux IMUX_G0_DATA[3] bit 1 INT: mux DBL_W0[0] bit 2 INT: mux DBL_E0[0] bit 3 INT: mux DBL_W0[0] bit 7 INT: mux DBL_W0[0] bit 4 INT: mux HEX_E0[0] bit 2 INT: mux HEX_E0[0] bit 1 INT: mux HEX_W0[0] bit 4 INT: mux LV[0] bit 0
B4 - - - - INT: mux IMUX_SR[2] bit 6 INT: mux IMUX_SR[2] bit 4 INT: mux OMUX[1] bit 0 INT: mux OMUX[0] bit 0 INT: mux IMUX_G0_DATA[2] bit 9 INT: mux IMUX_G0_DATA[2] bit 10 INT: mux IMUX_G0_DATA[2] bit 6 INT: mux IMUX_G0_DATA[2] bit 5 INT: mux IMUX_G0_DATA[2] bit 2 INT: mux IMUX_G0_DATA[2] bit 1 INT: mux DBL_W0[0] bit 1 INT: mux DBL_E0[0] bit 1 INT: mux DBL_E0[0] bit 5 INT: mux DBL_E0[0] bit 6 INT: mux HEX_W0[0] bit 3 INT: mux HEX_W0[0] bit 0 INT: mux HEX_W0[0] bit 6 INT: mux HEX_E0[0] bit 6
B3 - - - - INT: mux IMUX_SR[0] bit 6 INT: mux IMUX_SR[0] bit 7 INT: mux OMUX[0] bit 5 INT: mux OMUX[1] bit 5 INT: mux IMUX_BRAM_ADDRB[0] bit 9 INT: mux IMUX_BRAM_ADDRB[0] bit 10 INT: mux IMUX_BRAM_ADDRB[0] bit 6 INT: mux IMUX_BRAM_ADDRB[0] bit 5 INT: mux IMUX_BRAM_ADDRB[0] bit 3 INT: mux IMUX_BRAM_ADDRB[0] bit 1 INT: mux DBL_S0[0] bit 4 INT: mux DBL_N0[0] bit 6 INT: mux DBL_S0[0] bit 1 INT: mux DBL_S0[0] bit 3 INT: mux HEX_S0[0] bit 1 INT: mux HEX_S0[0] bit 3 INT: mux HEX_S0[0] bit 6 INT: mux LV[12] bit 1
B2 - - - - INT: mux IMUX_SR[0] bit 1 INT: mux IMUX_SR[0] bit 2 INT: mux OMUX[1] bit 4 INT: mux OMUX[0] bit 7 INT: mux IMUX_BRAM_ADDRA[0] bit 9 INT: mux IMUX_BRAM_ADDRA[0] bit 10 INT: mux IMUX_BRAM_ADDRA[0] bit 6 INT: mux IMUX_BRAM_ADDRA[0] bit 5 INT: mux IMUX_BRAM_ADDRA[0] bit 3 INT: mux IMUX_BRAM_ADDRA[0] bit 1 INT: mux DBL_S0[0] bit 5 INT: mux DBL_N0[0] bit 5 INT: mux DBL_N0[0] bit 3 INT: mux DBL_N0[0] bit 1 INT: mux HEX_N0[0] bit 1 INT: mux HEX_N0[0] bit 2 INT: mux HEX_N0[0] bit 5 INT: mux HEX_S0[0] bit 5
B1 - - - - INT: !invert IMUX_SR_OPTINV[0] ← IMUX_SR[0] INT: mux IMUX_SR[0] bit 3 INT: mux OMUX[0] bit 8 INT: mux OMUX[0] bit 6 INT: mux IMUX_BRAM_ADDRA[0] bit 8 INT: mux IMUX_BRAM_ADDRA[0] bit 11 INT: mux IMUX_BRAM_ADDRB[0] bit 7 INT: mux IMUX_BRAM_ADDRB[0] bit 4 INT: mux IMUX_BRAM_ADDRB[0] bit 0 INT: mux IMUX_BRAM_ADDRB[0] bit 2 INT: mux DBL_N0[0] bit 4 INT: mux DBL_S0[0] bit 6 INT: mux DBL_N0[0] bit 2 INT: mux DBL_N0[0] bit 0 INT: mux HEX_S0[0] bit 2 INT: mux HEX_S0[0] bit 0 INT: mux HEX_N0[0] bit 6 INT: mux LV[12] bit 5
B0 - - - - INT: mux IMUX_SR[2] bit 7 INT: mux IMUX_SR[0] bit 0 INT: mux OMUX[0] bit 4 INT: mux OMUX[0] bit 9 INT: mux IMUX_BRAM_ADDRB[0] bit 8 INT: mux IMUX_BRAM_ADDRB[0] bit 11 INT: mux IMUX_BRAM_ADDRA[0] bit 7 INT: mux IMUX_BRAM_ADDRA[0] bit 4 INT: mux IMUX_BRAM_ADDRA[0] bit 0 INT: mux IMUX_BRAM_ADDRA[0] bit 2 INT: mux DBL_N0[0] bit 7 INT: mux DBL_S0[0] bit 7 INT: mux DBL_S0[0] bit 0 INT: mux DBL_S0[0] bit 2 INT: mux HEX_N0[0] bit 3 INT: mux HEX_N0[0] bit 0 INT: mux HEX_N0[0] bit 4 INT: mux HEX_S0[0] bit 4

INT_IOI

Used with IOI tiles.

Tile INT_IOI

Cells: 1

Switchbox INT

virtex2 INT_IOI switchbox INT programmable inverters
DestinationSourceBit
IMUX_CLK_OPTINV[0]IMUX_CLK[0]MAIN[4][41]
IMUX_CLK_OPTINV[1]IMUX_CLK[1]MAIN[4][49]
IMUX_CLK_OPTINV[2]IMUX_CLK[2]MAIN[4][52]
IMUX_CLK_OPTINV[3]IMUX_CLK[3]MAIN[4][60]
IMUX_SR_OPTINV[0]IMUX_SR[0]!MAIN[4][1]
IMUX_SR_OPTINV[1]IMUX_SR[1]!MAIN[4][16]
IMUX_SR_OPTINV[2]IMUX_SR[2]!MAIN[4][7]
IMUX_SR_OPTINV[3]IMUX_SR[3]!MAIN[4][10]
IMUX_CE_OPTINV[0]IMUX_CE[0]!MAIN[4][63]
IMUX_CE_OPTINV[1]IMUX_CE[1]!MAIN[4][69]
IMUX_CE_OPTINV[2]IMUX_CE[2]!MAIN[4][72]
IMUX_CE_OPTINV[3]IMUX_CE[3]!MAIN[4][78]
virtex2 INT_IOI switchbox INT muxes OMUX[0]
BitsDestination
MAIN[7][0]MAIN[6][1]MAIN[7][2]MAIN[7][1]MAIN[6][0]MAIN[6][3]MAIN[7][5]MAIN[7][4]MAIN[6][6]MAIN[6][9]OMUX[0]
Source
0000000000off
0001000001OUT_FAN[0]
0001000010OUT_FAN[1]
0001000100OUT_FAN[2]
0001001000OUT_FAN[3]
0010000100OUT_SEC[9]
0010010000OUT_SEC[10]
0100000001OUT_SEC[12]
0100000010OUT_SEC[13]
0100000100OUT_SEC[15]
0100001000OUT_SEC[14]
0100100000OUT_SEC[17]
1000000001OUT_SEC[18]
1000000100OUT_SEC[21]
1000001000OUT_SEC[20]
1000010000OUT_SEC[22]
1000100000OUT_SEC[23]
virtex2 INT_IOI switchbox INT muxes OMUX[1]
BitsDestination
MAIN[7][9]MAIN[6][8]MAIN[7][7]MAIN[7][8]MAIN[6][2]MAIN[7][3]MAIN[6][5]MAIN[6][4]MAIN[7][6]MAIN[6][7]OMUX[1]
Source
0000000000off
0001000001OUT_FAN[0]
0001000010OUT_FAN[1]
0001000100OUT_FAN[2]
0001001000OUT_FAN[3]
0010000100OUT_SEC[9]
0010010000OUT_SEC[10]
0100000001OUT_SEC[12]
0100000010OUT_SEC[13]
0100000100OUT_SEC[15]
0100001000OUT_SEC[14]
0100100000OUT_SEC[17]
1000000001OUT_SEC[18]
1000000100OUT_SEC[21]
1000001000OUT_SEC[20]
1000010000OUT_SEC[22]
1000100000OUT_SEC[23]
virtex2 INT_IOI switchbox INT muxes OMUX[2]
BitsDestination
MAIN[7][10]MAIN[6][11]MAIN[7][12]MAIN[7][11]MAIN[6][10]MAIN[6][13]MAIN[7][15]MAIN[7][14]MAIN[6][16]MAIN[6][19]OMUX[2]
Source
0000000000off
0001000001OUT_FAN[0]
0001000010OUT_FAN[1]
0001000100OUT_FAN[2]
0001001000OUT_FAN[3]
0010000100OUT_SEC[9]
0010010000OUT_SEC[10]
0100000001OUT_SEC[12]
0100000010OUT_SEC[13]
0100000100OUT_SEC[15]
0100001000OUT_SEC[14]
0100100000OUT_SEC[17]
1000000001OUT_SEC[18]
1000000100OUT_SEC[21]
1000001000OUT_SEC[20]
1000010000OUT_SEC[22]
1000100000OUT_SEC[23]
virtex2 INT_IOI switchbox INT muxes OMUX[3]
BitsDestination
MAIN[7][19]MAIN[6][18]MAIN[7][17]MAIN[7][18]MAIN[6][12]MAIN[7][13]MAIN[6][15]MAIN[6][14]MAIN[7][16]MAIN[6][17]OMUX[3]
Source
0000000000off
0001000001OUT_FAN[0]
0001000010OUT_FAN[1]
0001000100OUT_FAN[2]
0001001000OUT_FAN[3]
0010000100OUT_SEC[9]
0010010000OUT_SEC[10]
0100000001OUT_SEC[12]
0100000010OUT_SEC[13]
0100000100OUT_SEC[15]
0100001000OUT_SEC[14]
0100100000OUT_SEC[17]
1000000001OUT_SEC[18]
1000000100OUT_SEC[21]
1000001000OUT_SEC[20]
1000010000OUT_SEC[22]
1000100000OUT_SEC[23]
virtex2 INT_IOI switchbox INT muxes OMUX[4]
BitsDestination
MAIN[7][20]MAIN[6][21]MAIN[7][22]MAIN[7][21]MAIN[6][20]MAIN[6][23]MAIN[7][25]MAIN[7][24]MAIN[6][26]MAIN[6][29]OMUX[4]
Source
0000000000off
0001000001OUT_FAN[0]
0001000010OUT_FAN[1]
0001000100OUT_FAN[2]
0001001000OUT_FAN[3]
0010000100OUT_SEC[9]
0010010000OUT_SEC[10]
0100000001OUT_SEC[12]
0100000010OUT_SEC[13]
0100000100OUT_SEC[15]
0100001000OUT_SEC[14]
0100100000OUT_SEC[17]
1000000001OUT_SEC[18]
1000000100OUT_SEC[21]
1000001000OUT_SEC[20]
1000010000OUT_SEC[22]
1000100000OUT_SEC[23]
virtex2 INT_IOI switchbox INT muxes OMUX[5]
BitsDestination
MAIN[7][29]MAIN[6][28]MAIN[7][27]MAIN[7][28]MAIN[6][22]MAIN[7][23]MAIN[6][25]MAIN[6][24]MAIN[7][26]MAIN[6][27]OMUX[5]
Source
0000000000off
0001000001OUT_FAN[0]
0001000010OUT_FAN[1]
0001000100OUT_FAN[2]
0001001000OUT_FAN[3]
0010000100OUT_SEC[9]
0010010000OUT_SEC[10]
0100000001OUT_SEC[12]
0100000010OUT_SEC[13]
0100000100OUT_SEC[15]
0100001000OUT_SEC[14]
0100100000OUT_SEC[17]
1000000001OUT_SEC[18]
1000000100OUT_SEC[21]
1000001000OUT_SEC[20]
1000010000OUT_SEC[22]
1000100000OUT_SEC[23]
virtex2 INT_IOI switchbox INT muxes OMUX[6]
BitsDestination
MAIN[7][30]MAIN[6][31]MAIN[7][32]MAIN[7][31]MAIN[6][30]MAIN[6][33]MAIN[7][35]MAIN[7][34]MAIN[6][36]MAIN[6][39]OMUX[6]
Source
0000000000off
0001000001OUT_FAN[0]
0001000010OUT_FAN[1]
0001000100OUT_FAN[2]
0001001000OUT_FAN[3]
0010000100OUT_SEC[9]
0010010000OUT_SEC[10]
0100000001OUT_SEC[12]
0100000010OUT_SEC[13]
0100000100OUT_SEC[15]
0100001000OUT_SEC[14]
0100100000OUT_SEC[17]
1000000001OUT_SEC[18]
1000000100OUT_SEC[21]
1000001000OUT_SEC[20]
1000010000OUT_SEC[22]
1000100000OUT_SEC[23]
virtex2 INT_IOI switchbox INT muxes OMUX[7]
BitsDestination
MAIN[7][39]MAIN[6][38]MAIN[7][37]MAIN[7][38]MAIN[6][32]MAIN[7][33]MAIN[6][35]MAIN[6][34]MAIN[7][36]MAIN[6][37]OMUX[7]
Source
0000000000off
0001000001OUT_FAN[0]
0001000010OUT_FAN[1]
0001000100OUT_FAN[2]
0001001000OUT_FAN[3]
0010000100OUT_SEC[9]
0010010000OUT_SEC[10]
0100000001OUT_SEC[12]
0100000010OUT_SEC[13]
0100000100OUT_SEC[15]
0100001000OUT_SEC[14]
0100100000OUT_SEC[17]
1000000001OUT_SEC[18]
1000000100OUT_SEC[21]
1000001000OUT_SEC[20]
1000010000OUT_SEC[22]
1000100000OUT_SEC[23]
virtex2 INT_IOI switchbox INT muxes OMUX[8]
BitsDestination
MAIN[7][40]MAIN[6][41]MAIN[7][42]MAIN[7][41]MAIN[6][40]MAIN[6][43]MAIN[7][45]MAIN[7][44]MAIN[6][46]MAIN[6][49]OMUX[8]
Source
0000000000off
0001000001OUT_FAN[0]
0001000010OUT_FAN[1]
0001000100OUT_FAN[2]
0001001000OUT_FAN[3]
0010000100OUT_SEC[9]
0010010000OUT_SEC[10]
0100000001OUT_SEC[12]
0100000010OUT_SEC[13]
0100000100OUT_SEC[15]
0100001000OUT_SEC[14]
0100100000OUT_SEC[17]
1000000001OUT_SEC[18]
1000000100OUT_SEC[21]
1000001000OUT_SEC[20]
1000010000OUT_SEC[22]
1000100000OUT_SEC[23]
virtex2 INT_IOI switchbox INT muxes OMUX[9]
BitsDestination
MAIN[7][49]MAIN[6][48]MAIN[7][47]MAIN[7][48]MAIN[6][42]MAIN[7][43]MAIN[6][45]MAIN[6][44]MAIN[7][46]MAIN[6][47]OMUX[9]
Source
0000000000off
0001000001OUT_FAN[0]
0001000010OUT_FAN[1]
0001000100OUT_FAN[2]
0001001000OUT_FAN[3]
0010000100OUT_SEC[9]
0010010000OUT_SEC[10]
0100000001OUT_SEC[12]
0100000010OUT_SEC[13]
0100000100OUT_SEC[15]
0100001000OUT_SEC[14]
0100100000OUT_SEC[17]
1000000001OUT_SEC[18]
1000000100OUT_SEC[21]
1000001000OUT_SEC[20]
1000010000OUT_SEC[22]
1000100000OUT_SEC[23]
virtex2 INT_IOI switchbox INT muxes OMUX[10]
BitsDestination
MAIN[7][50]MAIN[6][51]MAIN[7][52]MAIN[7][51]MAIN[6][50]MAIN[6][53]MAIN[7][55]MAIN[7][54]MAIN[6][56]MAIN[6][59]OMUX[10]
Source
0000000000off
0001000001OUT_FAN[0]
0001000010OUT_FAN[1]
0001000100OUT_FAN[2]
0001001000OUT_FAN[3]
0010000100OUT_SEC[9]
0010010000OUT_SEC[10]
0100000001OUT_SEC[12]
0100000010OUT_SEC[13]
0100000100OUT_SEC[15]
0100001000OUT_SEC[14]
0100100000OUT_SEC[17]
1000000001OUT_SEC[18]
1000000100OUT_SEC[21]
1000001000OUT_SEC[20]
1000010000OUT_SEC[22]
1000100000OUT_SEC[23]
virtex2 INT_IOI switchbox INT muxes OMUX[11]
BitsDestination
MAIN[7][59]MAIN[6][58]MAIN[7][57]MAIN[7][58]MAIN[6][52]MAIN[7][53]MAIN[6][55]MAIN[6][54]MAIN[7][56]MAIN[6][57]OMUX[11]
Source
0000000000off
0001000001OUT_FAN[0]
0001000010OUT_FAN[1]
0001000100OUT_FAN[2]
0001001000OUT_FAN[3]
0010000100OUT_SEC[9]
0010010000OUT_SEC[10]
0100000001OUT_SEC[12]
0100000010OUT_SEC[13]
0100000100OUT_SEC[15]
0100001000OUT_SEC[14]
0100100000OUT_SEC[17]
1000000001OUT_SEC[18]
1000000100OUT_SEC[21]
1000001000OUT_SEC[20]
1000010000OUT_SEC[22]
1000100000OUT_SEC[23]
virtex2 INT_IOI switchbox INT muxes OMUX[12]
BitsDestination
MAIN[7][60]MAIN[6][61]MAIN[7][62]MAIN[7][61]MAIN[6][60]MAIN[6][63]MAIN[7][65]MAIN[7][64]MAIN[6][66]MAIN[6][69]OMUX[12]
Source
0000000000off
0001000001OUT_FAN[0]
0001000010OUT_FAN[1]
0001000100OUT_FAN[2]
0001001000OUT_FAN[3]
0010000100OUT_SEC[9]
0010010000OUT_SEC[10]
0100000001OUT_SEC[12]
0100000010OUT_SEC[13]
0100000100OUT_SEC[15]
0100001000OUT_SEC[14]
0100100000OUT_SEC[17]
1000000001OUT_SEC[18]
1000000100OUT_SEC[21]
1000001000OUT_SEC[20]
1000010000OUT_SEC[22]
1000100000OUT_SEC[23]
virtex2 INT_IOI switchbox INT muxes OMUX[13]
BitsDestination
MAIN[7][69]MAIN[6][68]MAIN[7][67]MAIN[7][68]MAIN[6][62]MAIN[7][63]MAIN[6][65]MAIN[6][64]MAIN[7][66]MAIN[6][67]OMUX[13]
Source
0000000000off
0001000001OUT_FAN[0]
0001000010OUT_FAN[1]
0001000100OUT_FAN[2]
0001001000OUT_FAN[3]
0010000100OUT_SEC[9]
0010010000OUT_SEC[10]
0100000001OUT_SEC[12]
0100000010OUT_SEC[13]
0100000100OUT_SEC[15]
0100001000OUT_SEC[14]
0100100000OUT_SEC[17]
1000000001OUT_SEC[18]
1000000100OUT_SEC[21]
1000001000OUT_SEC[20]
1000010000OUT_SEC[22]
1000100000OUT_SEC[23]
virtex2 INT_IOI switchbox INT muxes OMUX[14]
BitsDestination
MAIN[7][70]MAIN[6][71]MAIN[7][72]MAIN[7][71]MAIN[6][70]MAIN[6][73]MAIN[7][75]MAIN[7][74]MAIN[6][76]MAIN[6][79]OMUX[14]
Source
0000000000off
0001000001OUT_FAN[0]
0001000010OUT_FAN[1]
0001000100OUT_FAN[2]
0001001000OUT_FAN[3]
0010000100OUT_SEC[9]
0010010000OUT_SEC[10]
0100000001OUT_SEC[12]
0100000010OUT_SEC[13]
0100000100OUT_SEC[15]
0100001000OUT_SEC[14]
0100100000OUT_SEC[17]
1000000001OUT_SEC[18]
1000000100OUT_SEC[21]
1000001000OUT_SEC[20]
1000010000OUT_SEC[22]
1000100000OUT_SEC[23]
virtex2 INT_IOI switchbox INT muxes OMUX[15]
BitsDestination
MAIN[7][79]MAIN[6][78]MAIN[7][77]MAIN[7][78]MAIN[6][72]MAIN[7][73]MAIN[6][75]MAIN[6][74]MAIN[7][76]MAIN[6][77]OMUX[15]
Source
0000000000off
0001000001OUT_FAN[0]
0001000010OUT_FAN[1]
0001000100OUT_FAN[2]
0001001000OUT_FAN[3]
0010000100OUT_SEC[9]
0010010000OUT_SEC[10]
0100000001OUT_SEC[12]
0100000010OUT_SEC[13]
0100000100OUT_SEC[15]
0100001000OUT_SEC[14]
0100100000OUT_SEC[17]
1000000001OUT_SEC[18]
1000000100OUT_SEC[21]
1000001000OUT_SEC[20]
1000010000OUT_SEC[22]
1000100000OUT_SEC[23]
virtex2 INT_IOI switchbox INT muxes DBL_W0[0]
BitsDestination
MAIN[16][5]MAIN[16][6]MAIN[17][6]MAIN[17][5]MAIN[15][7]MAIN[14][5]MAIN[14][4]MAIN[15][6]DBL_W0[0]
Source
00000000off
00010001OMUX_S0
00010010HEX_E6[0]
00010100OUT_FAN[3]
00011000HEX_N6[0]
00100001OMUX_NW10
00100010HEX_S6[1]
00101000HEX_W6[0]
01000001DBL_W2[0]
01000010HEX_N3[0]
01000100HEX_S3[0]
01001000DBL_N3[9]
10000001DBL_W2_N[8]
10000010DBL_S1[0]
10000100DBL_S2[2]
10001000DBL_N1[0]
virtex2 INT_IOI switchbox INT muxes DBL_W0[1]
BitsDestination
MAIN[16][13]MAIN[16][14]MAIN[17][14]MAIN[17][13]MAIN[15][15]MAIN[14][13]MAIN[14][12]MAIN[15][14]DBL_W0[1]
Source
00000000off
00010001OMUX[2]
00010010HEX_E6[1]
00010100OUT_FAN[2]
00011000HEX_N6[1]
00100001OMUX_W1
00100010HEX_S6[2]
00101000HEX_W6[1]
01000001DBL_W2[1]
01000010HEX_N3[1]
01000100HEX_S3[1]
01001000DBL_N2[0]
10000001DBL_W2_N[9]
10000010DBL_S1[1]
10000100DBL_S2[3]
10001000DBL_N1[1]
virtex2 INT_IOI switchbox INT muxes DBL_W0[2]
BitsDestination
MAIN[15][23]MAIN[14][20]MAIN[15][22]MAIN[14][21]MAIN[16][22]MAIN[16][21]MAIN[17][22]MAIN[17][21]DBL_W0[2]
Source
00000000off
00010001OMUX[4]
00010010OUT_FAN[3]
00010100DBL_S2[4]
00011000HEX_S3[2]
00100001OMUX[6]
00100010OMUX_WN14
00100100DBL_W2[0]
00101000DBL_W2[2]
01000001HEX_E6[2]
01000010HEX_S6[3]
01000100DBL_S1[2]
01001000HEX_N3[2]
10000001HEX_N6[2]
10000010HEX_W6[2]
10000100DBL_N1[2]
10001000DBL_N2[1]
virtex2 INT_IOI switchbox INT muxes DBL_W0[3]
BitsDestination
MAIN[16][30]MAIN[16][29]MAIN[17][30]MAIN[17][29]MAIN[15][31]MAIN[14][29]MAIN[14][28]MAIN[15][30]DBL_W0[3]
Source
00000000off
00010001OMUX_W6
00010010HEX_E6[3]
00011000HEX_N6[3]
00100001OMUX_NW10
00100010HEX_S6[4]
00100100OUT_FAN[2]
00101000HEX_W6[3]
01000001DBL_W2[1]
01000010DBL_S1[3]
01000100DBL_S2[5]
01001000DBL_N1[3]
10000001DBL_W2[3]
10000010HEX_N3[3]
10000100HEX_S3[3]
10001000DBL_N2[2]
virtex2 INT_IOI switchbox INT muxes DBL_W0[4]
BitsDestination
MAIN[16][38]MAIN[16][37]MAIN[17][38]MAIN[17][37]MAIN[15][39]MAIN[14][37]MAIN[14][36]MAIN[15][38]DBL_W0[4]
Source
00000000off
00010001OMUX_WS1
00010010HEX_E6[4]
00011000HEX_N6[4]
00100001OMUX_N12
00100010HEX_S6[5]
00101000HEX_W6[4]
01000001DBL_W2[2]
01000010DBL_S1[4]
01000100DBL_S2[6]
01001000DBL_N1[4]
10000001DBL_W2[4]
10000010HEX_N3[4]
10000100HEX_S3[4]
10001000DBL_N2[3]
virtex2 INT_IOI switchbox INT muxes DBL_W0[5]
BitsDestination
MAIN[16][46]MAIN[16][45]MAIN[17][46]MAIN[17][45]MAIN[15][47]MAIN[14][45]MAIN[14][44]MAIN[15][46]DBL_W0[5]
Source
00000000off
00010001OMUX_S3
00010010HEX_E6[5]
00010100OUT_FAN[1]
00011000HEX_N6[5]
00100001OMUX_WN14
00100010HEX_S6[6]
00101000HEX_W6[5]
01000001DBL_W2[3]
01000010DBL_S1[5]
01000100DBL_S2[7]
01001000DBL_N1[5]
10000001DBL_W2[5]
10000010HEX_N3[5]
10000100HEX_S3[5]
10001000DBL_N2[4]
virtex2 INT_IOI switchbox INT muxes DBL_W0[6]
BitsDestination
MAIN[15][55]MAIN[14][52]MAIN[15][54]MAIN[14][53]MAIN[16][54]MAIN[16][53]MAIN[17][53]MAIN[17][54]DBL_W0[6]
Source
00000000off
00010001OMUX[11]
00010010OUT_FAN[0]
00010100DBL_S2[8]
00011000HEX_S3[6]
00100001OMUX_W9
00100010OMUX_SW5
00100100DBL_W2[4]
00101000DBL_W2[6]
01000001HEX_S6[7]
01000010HEX_E6[6]
01000100DBL_S1[6]
01001000HEX_N3[6]
10000001HEX_W6[6]
10000010HEX_N6[6]
10000100DBL_N1[6]
10001000DBL_N2[5]
virtex2 INT_IOI switchbox INT muxes DBL_W0[7]
BitsDestination
MAIN[16][62]MAIN[16][61]MAIN[17][61]MAIN[17][62]MAIN[15][63]MAIN[14][61]MAIN[14][60]MAIN[15][62]DBL_W0[7]
Source
00000000off
00010001OMUX[9]
00010010HEX_S6[8]
00010100OUT_FAN[1]
00011000HEX_W6[7]
00100001OMUX_WS1
00100010HEX_E6[7]
00101000HEX_N6[7]
01000001DBL_W2[5]
01000010DBL_S1[7]
01000100DBL_S2[9]
01001000DBL_N1[7]
10000001DBL_W2[7]
10000010HEX_N3[7]
10000100HEX_S3[7]
10001000DBL_N2[6]
virtex2 INT_IOI switchbox INT muxes DBL_W0[8]
BitsDestination
MAIN[16][70]MAIN[16][69]MAIN[17][69]MAIN[17][70]MAIN[15][71]MAIN[14][69]MAIN[14][68]MAIN[15][70]DBL_W0[8]
Source
00000000off
00010001OMUX[13]
00010010HEX_S6[9]
00010100OUT_FAN[0]
00011000HEX_W6[8]
00100001OMUX_W14
00100010HEX_E6[8]
00101000HEX_N6[8]
01000001DBL_W2[6]
01000010DBL_S1[8]
01000100DBL_S3[0]
01001000DBL_N1[8]
10000001DBL_W2[8]
10000010HEX_N3[8]
10000100HEX_S3[8]
10001000DBL_N2[7]
virtex2 INT_IOI switchbox INT muxes DBL_W0[9]
BitsDestination
MAIN[15][79]MAIN[14][76]MAIN[14][77]MAIN[15][78]MAIN[16][78]MAIN[16][77]MAIN[17][77]MAIN[17][78]DBL_W0[9]
Source
00000000off
00010001OMUX[13]
00010010OMUX_SW5
00010100DBL_W2[7]
00011000DBL_W2[9]
00100001OMUX_S0
00100010OMUX[15]
00100100DBL_S3[1]
00101000HEX_S3[9]
01000001HEX_S7[0]
01000010HEX_E6[9]
01000100DBL_S1[9]
01001000HEX_N3[9]
10000001HEX_W6[9]
10000010HEX_N6[9]
10000100DBL_N1[9]
10001000DBL_N2[8]
virtex2 INT_IOI switchbox INT muxes DBL_E0[0]
BitsDestination
MAIN[17][7]MAIN[17][4]MAIN[16][4]MAIN[16][7]MAIN[15][5]MAIN[14][7]MAIN[15][4]MAIN[14][6]DBL_E0[0]
Source
00000000off
00010001OMUX_E2
00010010HEX_S6[1]
00011000HEX_W6[0]
00100001OMUX_EN8
00100010HEX_E6[0]
00100100OUT_FAN[3]
00101000HEX_N6[0]
01000001DBL_E2[0]
01000010DBL_S1[0]
01000100DBL_S2[2]
01001000DBL_N1[0]
10000001DBL_E2[2]
10000010HEX_N3[0]
10000100HEX_S3[0]
10001000DBL_N3[9]
virtex2 INT_IOI switchbox INT muxes DBL_E0[1]
BitsDestination
MAIN[17][15]MAIN[17][12]MAIN[16][12]MAIN[16][15]MAIN[15][13]MAIN[14][15]MAIN[15][12]MAIN[14][14]DBL_E0[1]
Source
00000000off
00010001OMUX_S4
00010010HEX_S6[2]
00011000HEX_W6[1]
00100001OMUX_N10
00100010HEX_E6[1]
00100100OUT_FAN[2]
00101000HEX_N6[1]
01000001DBL_E2[1]
01000010DBL_S1[1]
01000100DBL_S2[3]
01001000DBL_N1[1]
10000001DBL_E2[3]
10000010HEX_N3[1]
10000100HEX_S3[1]
10001000DBL_N2[0]
virtex2 INT_IOI switchbox INT muxes DBL_E0[2]
BitsDestination
MAIN[15][21]MAIN[15][20]MAIN[14][22]MAIN[14][23]MAIN[17][23]MAIN[17][20]MAIN[16][23]MAIN[16][20]DBL_E0[2]
Source
00000000off
00010001OMUX[4]
00010010OUT_FAN[3]
00010100DBL_S2[4]
00011000HEX_S3[2]
00100001OMUX_NE12
00100010OMUX[6]
00100100DBL_E2[2]
00101000DBL_E2[4]
01000001HEX_E6[2]
01000010HEX_S6[3]
01000100DBL_S1[2]
01001000HEX_N3[2]
10000001HEX_N6[2]
10000010HEX_W6[2]
10000100DBL_N1[2]
10001000DBL_N2[1]
virtex2 INT_IOI switchbox INT muxes DBL_E0[3]
BitsDestination
MAIN[17][31]MAIN[17][28]MAIN[16][28]MAIN[16][31]MAIN[15][29]MAIN[14][31]MAIN[15][28]MAIN[14][30]DBL_E0[3]
Source
00000000off
00010001OMUX_SE3
00010010HEX_S6[4]
00010100OUT_FAN[2]
00011000HEX_W6[3]
00100001OMUX_EN8
00100010HEX_E6[3]
00101000HEX_N6[3]
01000001DBL_E2[3]
01000010DBL_S1[3]
01000100DBL_S2[5]
01001000DBL_N1[3]
10000001DBL_E2[5]
10000010HEX_N3[3]
10000100HEX_S3[3]
10001000DBL_N2[2]
virtex2 INT_IOI switchbox INT muxes DBL_E0[4]
BitsDestination
MAIN[17][39]MAIN[17][36]MAIN[16][39]MAIN[16][36]MAIN[15][37]MAIN[14][39]MAIN[15][36]MAIN[14][38]DBL_E0[4]
Source
00000000off
00010001OMUX_E7
00010010HEX_E6[4]
00011000HEX_N6[4]
00100001OMUX_E8
00100010HEX_S6[5]
00101000HEX_W6[4]
01000001DBL_E2[4]
01000010DBL_S1[4]
01000100DBL_S2[6]
01001000DBL_N1[4]
10000001DBL_E2[6]
10000010HEX_N3[4]
10000100HEX_S3[4]
10001000DBL_N2[3]
virtex2 INT_IOI switchbox INT muxes DBL_E0[5]
BitsDestination
MAIN[17][47]MAIN[17][44]MAIN[16][44]MAIN[16][47]MAIN[15][45]MAIN[14][47]MAIN[15][44]MAIN[14][46]DBL_E0[5]
Source
00000000off
00010001OMUX_ES7
00010010HEX_S6[6]
00011000HEX_W6[5]
00100001OMUX_NE12
00100010HEX_E6[5]
00100100OUT_FAN[1]
00101000HEX_N6[5]
01000001DBL_E2[5]
01000010DBL_S1[5]
01000100DBL_S2[7]
01001000DBL_N1[5]
10000001DBL_E2[7]
10000010HEX_N3[5]
10000100HEX_S3[5]
10001000DBL_N2[4]
virtex2 INT_IOI switchbox INT muxes DBL_E0[6]
BitsDestination
MAIN[17][55]MAIN[17][52]MAIN[16][55]MAIN[16][52]MAIN[15][53]MAIN[15][52]MAIN[14][55]MAIN[14][54]DBL_E0[6]
Source
00000000off
00010001OMUX[9]
00010010OUT_FAN[0]
00010100HEX_E6[6]
00011000HEX_N6[6]
00100001OMUX_SE3
00100010OMUX[11]
00100100HEX_S6[7]
00101000HEX_W6[6]
01000001DBL_E2[6]
01000010DBL_S2[8]
01000100DBL_S1[6]
01001000DBL_N1[6]
10000001DBL_E2[8]
10000010HEX_S3[6]
10000100HEX_N3[6]
10001000DBL_N2[5]
virtex2 INT_IOI switchbox INT muxes DBL_E0[7]
BitsDestination
MAIN[17][63]MAIN[17][60]MAIN[16][60]MAIN[16][63]MAIN[15][61]MAIN[14][63]MAIN[15][60]MAIN[14][62]DBL_E0[7]
Source
00000000off
00010001OMUX_S5
00010010HEX_S6[8]
00010100OUT_FAN[1]
00011000HEX_W6[7]
00100001OMUX_N11
00100010HEX_E6[7]
00101000HEX_N6[7]
01000001DBL_E2[7]
01000010DBL_S1[7]
01000100DBL_S2[9]
01001000DBL_N1[7]
10000001DBL_E2[9]
10000010HEX_N3[7]
10000100HEX_S3[7]
10001000DBL_N2[6]
virtex2 INT_IOI switchbox INT muxes DBL_E0[8]
BitsDestination
MAIN[17][71]MAIN[17][68]MAIN[16][68]MAIN[16][71]MAIN[15][69]MAIN[14][71]MAIN[15][68]MAIN[14][70]DBL_E0[8]
Source
00000000off
00010001OMUX_ES7
00010010HEX_S6[9]
00010100OUT_FAN[0]
00011000HEX_W6[8]
00100001OMUX_E13
00100010HEX_E6[8]
00101000HEX_N6[8]
01000001DBL_E2[8]
01000010DBL_S1[8]
01000100DBL_S3[0]
01001000DBL_N1[8]
10000001DBL_E2_S[0]
10000010HEX_N3[8]
10000100HEX_S3[8]
10001000DBL_N2[7]
virtex2 INT_IOI switchbox INT muxes DBL_E0[9]
BitsDestination
MAIN[17][79]MAIN[17][76]MAIN[16][79]MAIN[16][76]MAIN[15][77]MAIN[15][76]MAIN[14][78]MAIN[14][79]DBL_E0[9]
Source
00000000off
00010001OMUX[15]
00010010OMUX_N15
00010100HEX_E6[9]
00011000HEX_N6[9]
00100001OMUX_S0
00100010OMUX_S2
00100100HEX_S7[0]
00101000HEX_W6[9]
01000001DBL_S3[1]
01000010DBL_E2[9]
01000100DBL_S1[9]
01001000DBL_N1[9]
10000001HEX_S3[9]
10000010DBL_E2_S[1]
10000100HEX_N3[9]
10001000DBL_N2[8]
virtex2 INT_IOI switchbox INT muxes DBL_S0[0]
BitsDestination
MAIN[15][0]MAIN[15][1]MAIN[14][2]MAIN[14][3]MAIN[17][3]MAIN[17][0]MAIN[16][3]MAIN[16][0]DBL_S0[0]
Source
00000000off
00010001OMUX[0]
00010010OUT_FAN[3]
00010100DBL_E2[1]
00011000HEX_E3[0]
00100001OMUX[2]
00100010OMUX_S0
00100100DBL_S2[0]
00101000DBL_S2[2]
01000001HEX_W6_N[9]
01000010HEX_N6[0]
01000100DBL_W1[0]
01001000DBL_W2_N[8]
10000001HEX_S6[0]
10000010HEX_E6[0]
10000100DBL_E1[0]
10001000HEX_W3[0]
virtex2 INT_IOI switchbox INT muxes DBL_S0[1]
BitsDestination
MAIN[17][11]MAIN[17][8]MAIN[16][8]MAIN[16][11]MAIN[14][11]MAIN[15][8]MAIN[15][9]MAIN[14][10]DBL_S0[1]
Source
00000000off
00010001OMUX[2]
00010010HEX_N6[1]
00010100HEX_E6[1]
00011000OUT_FAN[2]
00100001OMUX_E2
00100010HEX_W6[0]
00100100HEX_S6[1]
01000001DBL_S2[1]
01000010DBL_W1[1]
01000100DBL_E1[1]
01001000DBL_E2[2]
10000001DBL_S2[3]
10000010DBL_W2_N[9]
10000100HEX_W3[1]
10001000HEX_E3[1]
virtex2 INT_IOI switchbox INT muxes DBL_S0[2]
BitsDestination
MAIN[15][16]MAIN[15][17]MAIN[14][18]MAIN[14][19]MAIN[17][19]MAIN[17][16]MAIN[16][16]MAIN[16][19]DBL_S0[2]
Source
00000000off
00010001OMUX[4]
00010100DBL_E2[3]
00011000HEX_E3[2]
00100001OMUX[6]
00100010OMUX_S4
00100100DBL_S2[2]
00101000DBL_S2[4]
01000001HEX_N6[2]
01000010HEX_W6[1]
01000100DBL_W1[2]
01001000DBL_W2[0]
10000001HEX_E6[2]
10000010HEX_S6[2]
10000100DBL_E1[2]
10001000HEX_W3[2]
virtex2 INT_IOI switchbox INT muxes DBL_S0[3]
BitsDestination
MAIN[17][27]MAIN[17][24]MAIN[16][27]MAIN[16][24]MAIN[14][27]MAIN[15][24]MAIN[15][25]MAIN[14][26]DBL_S0[3]
Source
00000000off
00010001OMUX[6]
00010010HEX_W6[2]
00010100HEX_S6[3]
00011000OUT_FAN[3]
00100001OMUX_W6
00100010HEX_N6[3]
00100100HEX_E6[3]
01000001DBL_S2[3]
01000010DBL_W1[3]
01000100DBL_E1[3]
01001000DBL_E2[4]
10000001DBL_S2[5]
10000010DBL_W2[1]
10000100HEX_W3[3]
10001000HEX_E3[3]
virtex2 INT_IOI switchbox INT muxes DBL_S0[4]
BitsDestination
MAIN[17][35]MAIN[17][32]MAIN[16][32]MAIN[16][35]MAIN[14][35]MAIN[15][32]MAIN[15][33]MAIN[14][34]DBL_S0[4]
Source
00000000off
00010001OMUX_WS1
00010010HEX_N6[4]
00010100HEX_E6[4]
00100001OMUX_SE3
00100010HEX_W6[3]
00100100HEX_S6[4]
00101000OUT_FAN[2]
01000001DBL_S2[4]
01000010DBL_W1[4]
01000100DBL_E1[4]
01001000DBL_E2[5]
10000001DBL_S2[6]
10000010DBL_W2[2]
10000100HEX_W3[4]
10001000HEX_E3[4]
virtex2 INT_IOI switchbox INT muxes DBL_S0[5]
BitsDestination
MAIN[17][43]MAIN[17][40]MAIN[16][40]MAIN[16][43]MAIN[14][43]MAIN[15][40]MAIN[15][41]MAIN[14][42]DBL_S0[5]
Source
00000000off
00010001OMUX_S3
00010010HEX_N6[5]
00010100HEX_E6[5]
00011000OUT_FAN[1]
00100001OMUX_E8
00100010HEX_W6[4]
00100100HEX_S6[5]
01000001DBL_S2[5]
01000010DBL_W1[5]
01000100DBL_E1[5]
01001000DBL_E2[6]
10000001DBL_S2[7]
10000010DBL_W2[3]
10000100HEX_W3[5]
10001000HEX_E3[5]
virtex2 INT_IOI switchbox INT muxes DBL_S0[6]
BitsDestination
MAIN[17][51]MAIN[17][48]MAIN[16][48]MAIN[16][51]MAIN[14][51]MAIN[15][48]MAIN[15][49]MAIN[14][50]DBL_S0[6]
Source
00000000off
00010001OMUX_SW5
00010010HEX_N6[6]
00010100HEX_E6[6]
00011000OUT_FAN[0]
00100001OMUX_ES7
00100010HEX_W6[5]
00100100HEX_S6[6]
01000001DBL_S2[6]
01000010DBL_W1[6]
01000100DBL_E1[6]
01001000DBL_E2[7]
10000001DBL_S2[8]
10000010DBL_W2[4]
10000100HEX_W3[6]
10001000HEX_E3[6]
virtex2 INT_IOI switchbox INT muxes DBL_S0[7]
BitsDestination
MAIN[15][56]MAIN[15][57]MAIN[14][58]MAIN[14][59]MAIN[17][59]MAIN[17][56]MAIN[16][59]MAIN[16][56]DBL_S0[7]
Source
00000000off
00010001OMUX[11]
00010100DBL_E2[8]
00011000HEX_E3[7]
00100001OMUX_SE3
00100010OMUX_WS1
00100100DBL_S2[7]
00101000DBL_S2[9]
01000001HEX_W6[6]
01000010HEX_N6[7]
01000100DBL_W1[7]
01001000DBL_W2[5]
10000001HEX_S6[7]
10000010HEX_E6[7]
10000100DBL_E1[7]
10001000HEX_W3[7]
virtex2 INT_IOI switchbox INT muxes DBL_S0[8]
BitsDestination
MAIN[17][67]MAIN[17][64]MAIN[16][67]MAIN[16][64]MAIN[14][67]MAIN[15][64]MAIN[15][65]MAIN[14][66]DBL_S0[8]
Source
00000000off
00010001OMUX_S5
00010010HEX_W6[7]
00010100HEX_S6[8]
00011000OUT_FAN[1]
00100001OMUX_W14
00100010HEX_N6[8]
00100100HEX_E6[8]
01000001DBL_S2[8]
01000010DBL_W1[8]
01000100DBL_E1[8]
01001000DBL_E2[9]
10000001DBL_S3[0]
10000010DBL_W2[6]
10000100HEX_W3[8]
10001000HEX_E3[8]
virtex2 INT_IOI switchbox INT muxes DBL_S0[9]
BitsDestination
MAIN[15][72]MAIN[15][73]MAIN[14][74]MAIN[14][75]MAIN[17][75]MAIN[17][72]MAIN[16][72]MAIN[16][75]DBL_S0[9]
Source
00000000off
00010001OMUX[15]
00010010OUT_FAN[0]
00010100DBL_E2_S[0]
00011000HEX_E3[9]
00100001OMUX_SW5
00100010OMUX_ES7
00100100DBL_S2[9]
00101000DBL_S3[1]
01000001HEX_N6[9]
01000010HEX_W6[8]
01000100DBL_W1[9]
01001000DBL_W2[7]
10000001HEX_E6[9]
10000010HEX_S6[9]
10000100DBL_E1[9]
10001000HEX_W3[9]
virtex2 INT_IOI switchbox INT muxes DBL_N0[0]
BitsDestination
MAIN[14][0]MAIN[15][3]MAIN[15][2]MAIN[14][1]MAIN[16][2]MAIN[16][1]MAIN[17][2]MAIN[17][1]DBL_N0[0]
Source
00000000off
00010001OMUX[0]
00010010OUT_FAN[3]
00010100DBL_E2[1]
00011000HEX_E3[0]
00100001OMUX_N13
00100010OMUX_EN8
00100100DBL_N3[8]
00101000DBL_N2[0]
01000001HEX_W6_N[9]
01000010HEX_N6[0]
01000100DBL_W1[0]
01001000DBL_W2_N[8]
10000001HEX_S6[0]
10000010HEX_E6[0]
10000100DBL_E1[0]
10001000HEX_W3[0]
virtex2 INT_IOI switchbox INT muxes DBL_N0[1]
BitsDestination
MAIN[16][10]MAIN[16][9]MAIN[17][9]MAIN[17][10]MAIN[14][9]MAIN[14][8]MAIN[15][11]MAIN[15][10]DBL_N0[1]
Source
00000000off
00010001OMUX_N10
00010010HEX_N6[1]
00010100HEX_E6[1]
00011000OUT_FAN[2]
00100001OMUX_NW10
00100010HEX_W6[0]
00100100HEX_S6[1]
01000001DBL_N3[9]
01000010DBL_W1[1]
01000100DBL_E1[1]
01001000DBL_E2[2]
10000001DBL_N2[1]
10000010DBL_W2_N[9]
10000100HEX_W3[1]
10001000HEX_E3[1]
virtex2 INT_IOI switchbox INT muxes DBL_N0[2]
BitsDestination
MAIN[14][16]MAIN[15][19]MAIN[15][18]MAIN[14][17]MAIN[16][18]MAIN[16][17]MAIN[17][17]MAIN[17][18]DBL_N0[2]
Source
00000000off
00010001OMUX[4]
00010100DBL_E2[3]
00011000HEX_E3[2]
00100001OMUX_NE12
00100010OMUX_W1
00100100DBL_N2[0]
00101000DBL_N2[2]
01000001HEX_N6[2]
01000010HEX_W6[1]
01000100DBL_W1[2]
01001000DBL_W2[0]
10000001HEX_E6[2]
10000010HEX_S6[2]
10000100DBL_E1[2]
10001000HEX_W3[2]
virtex2 INT_IOI switchbox INT muxes DBL_N0[3]
BitsDestination
MAIN[16][26]MAIN[16][25]MAIN[17][25]MAIN[17][26]MAIN[14][25]MAIN[14][24]MAIN[15][27]MAIN[15][26]DBL_N0[3]
Source
00000000off
00010001OMUX_EN8
00010010HEX_N6[3]
00010100HEX_E6[3]
00100001OMUX_WN14
00100010HEX_W6[2]
00100100HEX_S6[3]
00101000OUT_FAN[3]
01000001DBL_N2[1]
01000010DBL_W1[3]
01000100DBL_E1[3]
01001000DBL_E2[4]
10000001DBL_N2[3]
10000010DBL_W2[1]
10000100HEX_W3[3]
10001000HEX_E3[3]
virtex2 INT_IOI switchbox INT muxes DBL_N0[4]
BitsDestination
MAIN[16][34]MAIN[16][33]MAIN[17][33]MAIN[17][34]MAIN[14][33]MAIN[14][32]MAIN[15][35]MAIN[15][34]DBL_N0[4]
Source
00000000off
00010001OMUX_E7
00010010HEX_N6[4]
00010100HEX_E6[4]
00100001OMUX_NW10
00100010HEX_W6[3]
00100100HEX_S6[4]
00101000OUT_FAN[2]
01000001DBL_N2[2]
01000010DBL_W1[4]
01000100DBL_E1[4]
01001000DBL_E2[5]
10000001DBL_N2[4]
10000010DBL_W2[2]
10000100HEX_W3[4]
10001000HEX_E3[4]
virtex2 INT_IOI switchbox INT muxes DBL_N0[5]
BitsDestination
MAIN[16][42]MAIN[16][41]MAIN[17][42]MAIN[17][41]MAIN[14][41]MAIN[14][40]MAIN[15][43]MAIN[15][42]DBL_N0[5]
Source
00000000off
00010001OMUX_N12
00010010HEX_W6[4]
00010100HEX_S6[5]
00100001OMUX_NE12
00100010HEX_N6[5]
00100100HEX_E6[5]
00101000OUT_FAN[1]
01000001DBL_N2[3]
01000010DBL_W1[5]
01000100DBL_E1[5]
01001000DBL_E2[6]
10000001DBL_N2[5]
10000010DBL_W2[3]
10000100HEX_W3[5]
10001000HEX_E3[5]
virtex2 INT_IOI switchbox INT muxes DBL_N0[6]
BitsDestination
MAIN[16][50]MAIN[16][49]MAIN[17][49]MAIN[17][50]MAIN[14][49]MAIN[14][48]MAIN[15][51]MAIN[15][50]DBL_N0[6]
Source
00000000off
00010001OMUX[9]
00010010HEX_N6[6]
00010100HEX_E6[6]
00011000OUT_FAN[0]
00100001OMUX_WN14
00100010HEX_W6[5]
00100100HEX_S6[6]
01000001DBL_N2[4]
01000010DBL_W1[6]
01000100DBL_E1[6]
01001000DBL_E2[7]
10000001DBL_N2[6]
10000010DBL_W2[4]
10000100HEX_W3[6]
10001000HEX_E3[6]
virtex2 INT_IOI switchbox INT muxes DBL_N0[7]
BitsDestination
MAIN[14][56]MAIN[15][59]MAIN[15][58]MAIN[14][57]MAIN[16][58]MAIN[16][57]MAIN[17][58]MAIN[17][57]DBL_N0[7]
Source
00000000off
00010001OMUX[11]
00010100DBL_E2[8]
00011000HEX_E3[7]
00100001OMUX_W9
00100010OMUX_N11
00100100DBL_N2[5]
00101000DBL_N2[7]
01000001HEX_W6[6]
01000010HEX_N6[7]
01000100DBL_W1[7]
01001000DBL_W2[5]
10000001HEX_S6[7]
10000010HEX_E6[7]
10000100DBL_E1[7]
10001000HEX_W3[7]
virtex2 INT_IOI switchbox INT muxes DBL_N0[8]
BitsDestination
MAIN[16][66]MAIN[16][65]MAIN[17][66]MAIN[17][65]MAIN[14][65]MAIN[14][64]MAIN[15][67]MAIN[15][66]DBL_N0[8]
Source
00000000off
00010001OMUX[9]
00010010HEX_W6[7]
00010100HEX_S6[8]
00011000OUT_FAN[1]
00100001OMUX_E13
00100010HEX_N6[8]
00100100HEX_E6[8]
01000001DBL_N2[6]
01000010DBL_W1[8]
01000100DBL_E1[8]
01001000DBL_E2[9]
10000001DBL_N2[8]
10000010DBL_W2[6]
10000100HEX_W3[8]
10001000HEX_E3[8]
virtex2 INT_IOI switchbox INT muxes DBL_N0[9]
BitsDestination
MAIN[16][74]MAIN[16][73]MAIN[17][74]MAIN[17][73]MAIN[14][72]MAIN[15][75]MAIN[14][73]MAIN[15][74]DBL_N0[9]
Source
00000000off
00010001OMUX[13]
00010010OUT_FAN[0]
00010100HEX_W6[8]
00011000HEX_S6[9]
00100001OMUX_N15
00100010OMUX[15]
00100100HEX_N6[9]
00101000HEX_E6[9]
01000001DBL_N2[7]
01000010DBL_E2_S[0]
01000100DBL_W1[9]
01001000DBL_E1[9]
10000001DBL_N2[9]
10000010HEX_E3[9]
10000100DBL_W2[7]
10001000HEX_W3[9]
virtex2 INT_IOI switchbox INT muxes HEX_W0[0]
BitsDestination
MAIN[20][4]MAIN[20][6]MAIN[20][5]MAIN[18][4]MAIN[19][6]MAIN[18][6]MAIN[19][4]HEX_W0[0]
Source
0000000off
0010001OMUX_S0
0010010HEX_S3[0]
0010100HEX_N3[0]
0011000LH[6]
0100010OMUX_NW10
0100100HEX_W6[0]
0101000HEX_W6_N[8]
1000001OUT_FAN[3]
1000010LH[18]
1000100HEX_N7[9]
1001000HEX_S6[2]
virtex2 INT_IOI switchbox INT muxes HEX_W0[1]
BitsDestination
MAIN[21][12]MAIN[20][15]MAIN[21][14]MAIN[18][13]MAIN[19][15]MAIN[18][15]MAIN[19][13]HEX_W0[1]
Source
0000000off
0010001OMUX[2]
0010100HEX_W6[1]
0011000HEX_W6_N[9]
0100001LH[0]
0100010OMUX_W1
0100100HEX_S3[1]
0101000HEX_N3[1]
1000001OUT_FAN[2]
1000010LH[12]
1000100HEX_N6[0]
1001000HEX_S6[3]
virtex2 INT_IOI switchbox INT muxes HEX_W0[2]
BitsDestination
MAIN[20][22]MAIN[20][21]MAIN[20][20]MAIN[19][22]MAIN[18][20]MAIN[18][22]MAIN[19][20]HEX_W0[2]
Source
0000000off
0010001OMUX[4]
0010010LH[18]
0010100HEX_S6[4]
0011000HEX_N6[1]
0100001OMUX[6]
0100010HEX_S3[2]
0100100LH[6]
0101000HEX_N3[2]
1000001OUT_FAN[3]
1000010OMUX_WN14
1000100HEX_W6[0]
1001000HEX_W6[2]
virtex2 INT_IOI switchbox INT muxes HEX_W0[3]
BitsDestination
MAIN[21][28]MAIN[20][31]MAIN[21][30]MAIN[19][31]MAIN[18][29]MAIN[18][31]MAIN[19][29]HEX_W0[3]
Source
0000000off
0010001OMUX_W6
0010010OUT_FAN[2]
0010100HEX_W6[1]
0011000HEX_W6[3]
0100001LH[0]
0100010OMUX_NW10
0100100HEX_N3[3]
0101000HEX_S3[3]
1000010LH[12]
1000100HEX_S6[5]
1001000HEX_N6[2]
virtex2 INT_IOI switchbox INT muxes HEX_W0[4]
BitsDestination
MAIN[20][36]MAIN[20][38]MAIN[20][37]MAIN[19][38]MAIN[18][36]MAIN[18][38]MAIN[19][36]HEX_W0[4]
Source
0000000off
0010001OMUX_WS1
0010010HEX_S3[4]
0010100LH[6]
0011000HEX_N3[4]
0100010OMUX_N12
0100100HEX_W6[2]
0101000HEX_W6[4]
1000010LH[18]
1000100HEX_S6[6]
1001000HEX_N6[3]
virtex2 INT_IOI switchbox INT muxes HEX_W0[5]
BitsDestination
MAIN[21][44]MAIN[20][47]MAIN[21][46]MAIN[19][47]MAIN[18][45]MAIN[18][47]MAIN[19][45]HEX_W0[5]
Source
0000000off
0010001OMUX_S3
0010100HEX_W6[3]
0011000HEX_W6[5]
0100001LH[0]
0100010OMUX_WN14
0100100HEX_N3[5]
0101000HEX_S3[5]
1000001OUT_FAN[1]
1000010LH[12]
1000100HEX_S6[7]
1001000HEX_N6[4]
virtex2 INT_IOI switchbox INT muxes HEX_W0[6]
BitsDestination
MAIN[20][52]MAIN[20][53]MAIN[20][54]MAIN[19][54]MAIN[18][52]MAIN[18][54]MAIN[19][52]HEX_W0[6]
Source
0000000off
0010001OMUX[11]
0010010OMUX_W9
0010100HEX_W6[4]
0011000HEX_W6[6]
0100001OMUX_SW5
0100010HEX_S3[6]
0100100LH[6]
0101000HEX_N3[6]
1000001OUT_FAN[0]
1000010LH[18]
1000100HEX_S6[8]
1001000HEX_N6[5]
virtex2 INT_IOI switchbox INT muxes HEX_W0[7]
BitsDestination
MAIN[21][60]MAIN[21][62]MAIN[20][63]MAIN[19][63]MAIN[18][61]MAIN[19][61]MAIN[18][63]HEX_W0[7]
Source
0000000off
0010001OMUX[9]
0010010LH[0]
0010100HEX_N3[7]
0011000HEX_S3[7]
0100001OUT_FAN[1]
0100010OMUX_WS1
0100100HEX_W6[5]
0101000HEX_W6[7]
1000001LH[12]
1000100HEX_S6[9]
1001000HEX_N6[6]
virtex2 INT_IOI switchbox INT muxes HEX_W0[8]
BitsDestination
MAIN[20][68]MAIN[20][69]MAIN[20][70]MAIN[19][70]MAIN[18][68]MAIN[19][68]MAIN[18][70]HEX_W0[8]
Source
0000000off
0010001OMUX[13]
0010010OUT_FAN[0]
0010100HEX_W6[6]
0011000HEX_W6[8]
0100001HEX_S3[8]
0100010OMUX_W14
0100100LH[6]
0101000HEX_N3[8]
1000001LH[18]
1000100HEX_S7[0]
1001000HEX_N6[7]
virtex2 INT_IOI switchbox INT muxes HEX_W0[9]
BitsDestination
MAIN[21][78]MAIN[21][76]MAIN[20][79]MAIN[19][79]MAIN[18][77]MAIN[19][77]MAIN[18][79]HEX_W0[9]
Source
0000000off
0010001OMUX[13]
0010010LH[0]
0010100HEX_N3[9]
0011000HEX_S3[9]
0100001LH[12]
0100010OMUX[15]
0100100HEX_S7[1]
0101000HEX_N6[8]
1000001OMUX_S0
1000010OMUX_SW5
1000100HEX_W6[7]
1001000HEX_W6[9]
virtex2 INT_IOI switchbox INT muxes HEX_E0[0]
BitsDestination
MAIN[21][4]MAIN[21][6]MAIN[20][7]MAIN[19][7]MAIN[18][5]MAIN[19][5]MAIN[18][7]HEX_E0[0]
Source
0000000off
0010001OMUX_E2
0010010LH[6]
0010100HEX_N3[0]
0011000HEX_S3[0]
0100010OMUX_EN8
0100100HEX_E6[0]
0101000HEX_E6[2]
1000001LH[18]
1000010OUT_FAN[3]
1000100HEX_S6[2]
1001000HEX_N7[9]
virtex2 INT_IOI switchbox INT muxes HEX_E0[1]
BitsDestination
MAIN[20][12]MAIN[20][13]MAIN[20][14]MAIN[19][14]MAIN[18][12]MAIN[19][12]MAIN[18][14]HEX_E0[1]
Source
0000000off
0010001OMUX_S4
0010100HEX_E6[1]
0011000HEX_E6[3]
0100001HEX_S3[1]
0100010OMUX_N10
0100100LH[0]
0101000HEX_N3[1]
1000001LH[12]
1000010OUT_FAN[2]
1000100HEX_S6[3]
1001000HEX_N6[0]
virtex2 INT_IOI switchbox INT muxes HEX_E0[2]
BitsDestination
MAIN[21][22]MAIN[20][23]MAIN[21][20]MAIN[19][23]MAIN[18][21]MAIN[18][23]MAIN[19][21]HEX_E0[2]
Source
0000000off
0010001OMUX[4]
0010010LH[18]
0010100HEX_S6[4]
0011000HEX_N6[1]
0100001LH[6]
0100010OMUX[6]
0100100HEX_N3[2]
0101000HEX_S3[2]
1000001OMUX_NE12
1000010OUT_FAN[3]
1000100HEX_E6[2]
1001000HEX_E6[4]
virtex2 INT_IOI switchbox INT muxes HEX_E0[3]
BitsDestination
MAIN[20][28]MAIN[20][29]MAIN[20][30]MAIN[19][30]MAIN[18][28]MAIN[19][28]MAIN[18][30]HEX_E0[3]
Source
0000000off
0010001OMUX_SE3
0010010OUT_FAN[2]
0010100HEX_E6[3]
0011000HEX_E6[5]
0100001HEX_S3[3]
0100010OMUX_EN8
0100100LH[0]
0101000HEX_N3[3]
1000001LH[12]
1000100HEX_S6[5]
1001000HEX_N6[2]
virtex2 INT_IOI switchbox INT muxes HEX_E0[4]
BitsDestination
MAIN[21][36]MAIN[20][39]MAIN[21][38]MAIN[19][39]MAIN[18][37]MAIN[18][39]MAIN[19][37]HEX_E0[4]
Source
0000000off
0010001OMUX_E7
0010100HEX_E6[4]
0011000HEX_E6[6]
0100001LH[6]
0100010OMUX_E8
0100100HEX_N3[4]
0101000HEX_S3[4]
1000010LH[18]
1000100HEX_S6[6]
1001000HEX_N6[3]
virtex2 INT_IOI switchbox INT muxes HEX_E0[5]
BitsDestination
MAIN[20][44]MAIN[20][45]MAIN[20][46]MAIN[19][46]MAIN[18][44]MAIN[19][44]MAIN[18][46]HEX_E0[5]
Source
0000000off
0010001OMUX_ES7
0010100HEX_E6[5]
0011000HEX_E6[7]
0100001HEX_S3[5]
0100010OMUX_NE12
0100100LH[0]
0101000HEX_N3[5]
1000001LH[12]
1000010OUT_FAN[1]
1000100HEX_S6[7]
1001000HEX_N6[4]
virtex2 INT_IOI switchbox INT muxes HEX_E0[6]
BitsDestination
MAIN[21][52]MAIN[20][55]MAIN[21][54]MAIN[19][55]MAIN[18][53]MAIN[18][55]MAIN[19][53]HEX_E0[6]
Source
0000000off
0010001OMUX[9]
0010010OMUX[11]
0010100HEX_E6[6]
0011000HEX_E6[8]
0100001LH[6]
0100010OMUX_SE3
0100100HEX_N3[6]
0101000HEX_S3[6]
1000001OUT_FAN[0]
1000010LH[18]
1000100HEX_S6[8]
1001000HEX_N6[5]
virtex2 INT_IOI switchbox INT muxes HEX_E0[7]
BitsDestination
MAIN[20][60]MAIN[20][61]MAIN[20][62]MAIN[19][62]MAIN[18][60]MAIN[19][60]MAIN[18][62]HEX_E0[7]
Source
0000000off
0010001OMUX_S5
0010010OUT_FAN[1]
0010100HEX_E6[7]
0011000HEX_E6[9]
0100001HEX_S3[7]
0100010OMUX_N11
0100100LH[0]
0101000HEX_N3[7]
1000001LH[12]
1000100HEX_S6[9]
1001000HEX_N6[6]
virtex2 INT_IOI switchbox INT muxes HEX_E0[8]
BitsDestination
MAIN[21][68]MAIN[21][70]MAIN[20][71]MAIN[19][71]MAIN[18][69]MAIN[19][69]MAIN[18][71]HEX_E0[8]
Source
0000000off
0010001OMUX_ES7
0010010LH[6]
0010100HEX_N3[8]
0011000HEX_S3[8]
0100001OUT_FAN[0]
0100010OMUX_E13
0100100HEX_E6[8]
0101000HEX_E6_S[0]
1000001LH[18]
1000100HEX_S7[0]
1001000HEX_N6[7]
virtex2 INT_IOI switchbox INT muxes HEX_E0[9]
BitsDestination
MAIN[20][77]MAIN[20][78]MAIN[20][76]MAIN[19][78]MAIN[18][76]MAIN[18][78]MAIN[19][76]HEX_E0[9]
Source
0000000off
0010001OMUX[15]
0010010LH[12]
0010100HEX_S7[1]
0011000HEX_N6[8]
0100001OMUX_S0
0100010OMUX_S2
0100100HEX_E6[9]
0101000HEX_E6_S[1]
1000001OMUX_N15
1000010HEX_S3[9]
1000100LH[0]
1001000HEX_N3[9]
virtex2 INT_IOI switchbox INT muxes HEX_S0[0]
BitsDestination
MAIN[20][3]MAIN[21][2]MAIN[21][0]MAIN[19][3]MAIN[18][1]MAIN[18][3]MAIN[19][1]HEX_S0[0]
Source
0000000off
0010001OMUX[0]
0010010LV[0]
0010100HEX_E6[1]
0011000HEX_W6_N[8]
0100001OMUX[2]
0100010OUT_FAN[3]
0100100HEX_S6[0]
0101000HEX_S6[2]
1000001LV[12]
1000010OMUX_S0
1000100HEX_W3[0]
1001000HEX_E3[0]
virtex2 INT_IOI switchbox INT muxes HEX_S0[1]
BitsDestination
MAIN[20][8]MAIN[20][9]MAIN[20][10]MAIN[18][8]MAIN[19][10]MAIN[19][8]MAIN[18][10]HEX_S0[1]
Source
0000000off
0010001OMUX[2]
0010010OUT_FAN[2]
0010100HEX_S6[3]
0011000HEX_S6[1]
0100001HEX_E3[1]
0100010OMUX_E2
0100100HEX_W3[1]
0101000LV[18]
1000001LV[6]
1000100HEX_W6_N[9]
1001000HEX_E6[2]
virtex2 INT_IOI switchbox INT muxes HEX_S0[2]
BitsDestination
MAIN[21][16]MAIN[20][19]MAIN[21][18]MAIN[19][19]MAIN[18][17]MAIN[19][17]MAIN[18][19]HEX_S0[2]
Source
0000000off
0010001OMUX[4]
0010010OMUX_S4
0010100HEX_S6[2]
0011000HEX_S6[4]
0100001OMUX[6]
0100010LV[12]
0100100HEX_W3[2]
0101000HEX_E3[2]
1000001LV[0]
1000100HEX_E6[3]
1001000HEX_W6[0]
virtex2 INT_IOI switchbox INT muxes HEX_S0[3]
BitsDestination
MAIN[20][24]MAIN[20][26]MAIN[20][25]MAIN[18][24]MAIN[19][26]MAIN[18][26]MAIN[19][24]HEX_S0[3]
Source
0000000off
0010001OMUX[6]
0010010HEX_E3[3]
0010100HEX_W3[3]
0011000LV[18]
0100010OMUX_W6
0100100HEX_S6[5]
0101000HEX_S6[3]
1000001OUT_FAN[3]
1000010LV[6]
1000100HEX_W6[1]
1001000HEX_E6[4]
virtex2 INT_IOI switchbox INT muxes HEX_S0[4]
BitsDestination
MAIN[21][32]MAIN[21][34]MAIN[20][35]MAIN[19][35]MAIN[18][33]MAIN[19][33]MAIN[18][35]HEX_S0[4]
Source
0000000off
0010001OMUX_WS1
0010010LV[12]
0010100HEX_W3[4]
0011000HEX_E3[4]
0100010OMUX_SE3
0100100HEX_S6[4]
0101000HEX_S6[6]
1000001LV[0]
1000010OUT_FAN[2]
1000100HEX_E6[5]
1001000HEX_W6[2]
virtex2 INT_IOI switchbox INT muxes HEX_S0[5]
BitsDestination
MAIN[20][40]MAIN[20][41]MAIN[20][42]MAIN[18][40]MAIN[19][42]MAIN[19][40]MAIN[18][42]HEX_S0[5]
Source
0000000off
0010001OMUX_S3
0010010OUT_FAN[1]
0010100HEX_S6[7]
0011000HEX_S6[5]
0100001HEX_E3[5]
0100010OMUX_E8
0100100HEX_W3[5]
0101000LV[18]
1000001LV[6]
1000100HEX_W6[3]
1001000HEX_E6[6]
virtex2 INT_IOI switchbox INT muxes HEX_S0[6]
BitsDestination
MAIN[21][48]MAIN[21][50]MAIN[20][51]MAIN[19][51]MAIN[18][49]MAIN[19][49]MAIN[18][51]HEX_S0[6]
Source
0000000off
0010001OMUX_SW5
0010010LV[12]
0010100HEX_W3[6]
0011000HEX_E3[6]
0100001OUT_FAN[0]
0100010OMUX_ES7
0100100HEX_S6[6]
0101000HEX_S6[8]
1000001LV[0]
1000100HEX_E6[7]
1001000HEX_W6[4]
virtex2 INT_IOI switchbox INT muxes HEX_S0[7]
BitsDestination
MAIN[20][57]MAIN[20][58]MAIN[20][56]MAIN[18][56]MAIN[19][58]MAIN[18][58]MAIN[19][56]HEX_S0[7]
Source
0000000off
0010001OMUX[11]
0010010LV[6]
0010100HEX_W6[5]
0011000HEX_E6[8]
0100010OMUX_WS1
0100100HEX_S6[9]
0101000HEX_S6[7]
1000001OMUX_SE3
1000010HEX_E3[7]
1000100HEX_W3[7]
1001000LV[18]
virtex2 INT_IOI switchbox INT muxes HEX_S0[8]
BitsDestination
MAIN[21][64]MAIN[20][67]MAIN[21][66]MAIN[19][67]MAIN[18][65]MAIN[18][67]MAIN[19][65]HEX_S0[8]
Source
0000000off
0010001OMUX_S5
0010100HEX_S6[8]
0011000HEX_S7[0]
0100001LV[12]
0100010OMUX_W14
0100100HEX_W3[8]
0101000HEX_E3[8]
1000001OUT_FAN[1]
1000010LV[0]
1000100HEX_E6[9]
1001000HEX_W6[6]
virtex2 INT_IOI switchbox INT muxes HEX_S0[9]
BitsDestination
MAIN[20][72]MAIN[20][73]MAIN[20][74]MAIN[18][72]MAIN[19][74]MAIN[18][74]MAIN[19][72]HEX_S0[9]
Source
0000000off
0010001OMUX[15]
0010010OMUX_SW5
0010100HEX_S7[1]
0011000HEX_S6[9]
0100001OMUX_ES7
0100010HEX_E3[9]
0100100HEX_W3[9]
0101000LV[18]
1000001OUT_FAN[0]
1000010LV[6]
1000100HEX_W6[7]
1001000HEX_E6_S[0]
virtex2 INT_IOI switchbox INT muxes HEX_N0[0]
BitsDestination
MAIN[20][1]MAIN[20][2]MAIN[20][0]MAIN[18][0]MAIN[19][2]MAIN[18][2]MAIN[19][0]HEX_N0[0]
Source
0000000off
0010001OMUX[0]
0010010LV[0]
0010100HEX_W6_N[8]
0011000HEX_E6[1]
0100001OUT_FAN[3]
0100010OMUX_EN8
0100100HEX_N6[0]
0101000HEX_N7[8]
1000001OMUX_N13
1000010HEX_E3[0]
1000100HEX_W3[0]
1001000LV[12]
virtex2 INT_IOI switchbox INT muxes HEX_N0[1]
BitsDestination
MAIN[21][8]MAIN[21][10]MAIN[20][11]MAIN[19][11]MAIN[18][9]MAIN[19][9]MAIN[18][11]HEX_N0[1]
Source
0000000off
0010001OMUX_N10
0010010LV[18]
0010100HEX_W3[1]
0011000HEX_E3[1]
0100001OUT_FAN[2]
0100010OMUX_NW10
0100100HEX_N7[9]
0101000HEX_N6[1]
1000001LV[6]
1000100HEX_E6[2]
1001000HEX_W6_N[9]
virtex2 INT_IOI switchbox INT muxes HEX_N0[2]
BitsDestination
MAIN[20][16]MAIN[20][17]MAIN[20][18]MAIN[18][16]MAIN[19][18]MAIN[18][18]MAIN[19][16]HEX_N0[2]
Source
0000000off
0010001OMUX[4]
0010010OMUX_NE12
0010100HEX_N6[2]
0011000HEX_N6[0]
0100001OMUX_W1
0100010HEX_E3[2]
0100100HEX_W3[2]
0101000LV[12]
1000010LV[0]
1000100HEX_W6[0]
1001000HEX_E6[3]
virtex2 INT_IOI switchbox INT muxes HEX_N0[3]
BitsDestination
MAIN[21][24]MAIN[21][26]MAIN[20][27]MAIN[19][27]MAIN[18][25]MAIN[19][25]MAIN[18][27]HEX_N0[3]
Source
0000000off
0010001OMUX_EN8
0010010LV[18]
0010100HEX_W3[3]
0011000HEX_E3[3]
0100010OMUX_WN14
0100100HEX_N6[1]
0101000HEX_N6[3]
1000001LV[6]
1000010OUT_FAN[3]
1000100HEX_E6[4]
1001000HEX_W6[1]
virtex2 INT_IOI switchbox INT muxes HEX_N0[4]
BitsDestination
MAIN[20][32]MAIN[20][33]MAIN[20][34]MAIN[18][32]MAIN[19][34]MAIN[19][32]MAIN[18][34]HEX_N0[4]
Source
0000000off
0010001OMUX_E7
0010100HEX_N6[4]
0011000HEX_N6[2]
0100001HEX_E3[4]
0100010OMUX_NW10
0100100HEX_W3[4]
0101000LV[12]
1000001LV[0]
1000010OUT_FAN[2]
1000100HEX_W6[2]
1001000HEX_E6[5]
virtex2 INT_IOI switchbox INT muxes HEX_N0[5]
BitsDestination
MAIN[21][40]MAIN[20][43]MAIN[21][42]MAIN[19][43]MAIN[18][41]MAIN[18][43]MAIN[19][41]HEX_N0[5]
Source
0000000off
0010001OMUX_N12
0010010OUT_FAN[1]
0010100HEX_N6[3]
0011000HEX_N6[5]
0100001LV[18]
0100010OMUX_NE12
0100100HEX_W3[5]
0101000HEX_E3[5]
1000010LV[6]
1000100HEX_E6[6]
1001000HEX_W6[3]
virtex2 INT_IOI switchbox INT muxes HEX_N0[6]
BitsDestination
MAIN[20][48]MAIN[20][49]MAIN[20][50]MAIN[18][48]MAIN[19][50]MAIN[19][48]MAIN[18][50]HEX_N0[6]
Source
0000000off
0010001OMUX[9]
0010010OUT_FAN[0]
0010100HEX_N6[6]
0011000HEX_N6[4]
0100001HEX_E3[6]
0100010OMUX_WN14
0100100HEX_W3[6]
0101000LV[12]
1000001LV[0]
1000100HEX_W6[4]
1001000HEX_E6[7]
virtex2 INT_IOI switchbox INT muxes HEX_N0[7]
BitsDestination
MAIN[20][59]MAIN[21][58]MAIN[21][56]MAIN[19][59]MAIN[18][57]MAIN[18][59]MAIN[19][57]HEX_N0[7]
Source
0000000off
0010001OMUX[11]
0010010LV[6]
0010100HEX_E6[8]
0011000HEX_W6[5]
0100001OMUX_W9
0100100HEX_N6[5]
0101000HEX_N6[7]
1000001LV[18]
1000010OMUX_N11
1000100HEX_W3[7]
1001000HEX_E3[7]
virtex2 INT_IOI switchbox INT muxes HEX_N0[8]
BitsDestination
MAIN[20][64]MAIN[20][66]MAIN[20][65]MAIN[18][64]MAIN[19][66]MAIN[18][66]MAIN[19][64]HEX_N0[8]
Source
0000000off
0010001OMUX[9]
0010010HEX_E3[8]
0010100HEX_W3[8]
0011000LV[12]
0100010OMUX_E13
0100100HEX_N6[8]
0101000HEX_N6[6]
1000001OUT_FAN[1]
1000010LV[0]
1000100HEX_W6[6]
1001000HEX_E6[9]
virtex2 INT_IOI switchbox INT muxes HEX_N0[9]
BitsDestination
MAIN[21][72]MAIN[20][75]MAIN[21][74]MAIN[19][75]MAIN[18][73]MAIN[18][75]MAIN[19][73]HEX_N0[9]
Source
0000000off
0010001OMUX[13]
0010010OMUX[15]
0010100HEX_N6[7]
0011000HEX_N6[9]
0100001LV[18]
0100010OMUX_N15
0100100HEX_W3[9]
0101000HEX_E3[9]
1000001OUT_FAN[0]
1000010LV[6]
1000100HEX_E6_S[0]
1001000HEX_W6[7]
virtex2 INT_IOI switchbox INT muxes LH[0]
BitsDestination
MAIN[21][47]MAIN[21][49]MAIN[21][51]LH[0]
Source
000off
001DBL_W1[5]
011OMUX_S4
101DBL_E1[6]
111OMUX[11]
virtex2 INT_IOI switchbox INT muxes LH[6]
BitsDestination
MAIN[21][31]MAIN[21][33]MAIN[21][29]LH[6]
Source
000off
001OMUX[4]
011OMUX_N15
101DBL_E1[4]
111DBL_W1[3]
virtex2 INT_IOI switchbox INT muxes LH[12]
BitsDestination
MAIN[21][41]MAIN[21][45]MAIN[21][43]LH[12]
Source
000off
001DBL_W1[5]
011OMUX_S4
101DBL_E1[6]
111OMUX[11]
virtex2 INT_IOI switchbox INT muxes LH[18]
BitsDestination
MAIN[21][39]MAIN[21][37]MAIN[21][35]LH[18]
Source
000off
001OMUX[4]
011OMUX_N15
101DBL_E1[4]
111DBL_W1[3]
virtex2 INT_IOI switchbox INT muxes LV[0]
BitsDestination
MAIN[21][7]MAIN[21][9]MAIN[21][19]MAIN[21][25]MAIN[21][21]MAIN[21][11]MAIN[21][5]LV[0]
Source
0000000off
0000011HEX_E1[1]
0000101OMUX_E2
0001001DBL_W1[1]
0010001HEX_E6[1]
0100001HEX_E4[1]
1000011OMUX[0]
1000101HEX_E2[1]
1001001HEX_E5[1]
1010001DBL_E1[2]
1100001HEX_E3[1]
virtex2 INT_IOI switchbox INT muxes LV[6]
BitsDestination
MAIN[21][73]MAIN[21][61]MAIN[21][55]MAIN[21][69]MAIN[21][71]MAIN[21][65]MAIN[21][75]LV[6]
Source
0000000off
0000011OMUX_W9
0000101DBL_W1[7]
0001001HEX_W5[7]
0010001HEX_W3[7]
0100001HEX_W4[7]
1000011OMUX[15]
1000101HEX_W2[7]
1001001DBL_E1[8]
1010001HEX_W0[7]
1100001HEX_W1[7]
virtex2 INT_IOI switchbox INT muxes LV[12]
BitsDestination
MAIN[21][13]MAIN[21][1]MAIN[21][27]MAIN[21][23]MAIN[21][17]MAIN[21][3]MAIN[21][15]LV[12]
Source
0000000off
0000011HEX_E1[1]
0000101OMUX_E2
0001001DBL_W1[1]
0010001HEX_E6[1]
0100001HEX_E4[1]
1000011OMUX[0]
1000101HEX_E2[1]
1001001HEX_E5[1]
1010001DBL_E1[2]
1100001HEX_E3[1]
virtex2 INT_IOI switchbox INT muxes LV[18]
BitsDestination
MAIN[21][67]MAIN[21][53]MAIN[21][57]MAIN[21][77]MAIN[21][59]MAIN[21][79]MAIN[21][63]LV[18]
Source
0000000off
0000011OMUX_W9
0000101DBL_W1[7]
0001001HEX_W5[7]
0010001HEX_W3[7]
0100001HEX_W4[7]
1000011OMUX[15]
1000101HEX_W2[7]
1001001DBL_E1[8]
1010001HEX_W0[7]
1100001HEX_W1[7]
virtex2 INT_IOI switchbox INT muxes IMUX_CLK[0]
BitsDestination
MAIN[5][41]MAIN[5][42]MAIN[5][40]MAIN[4][42]MAIN[5][49]MAIN[4][47]MAIN[4][43]MAIN[5][45]MAIN[4][45]MAIN[5][43]IMUX_CLK[0]
Source
0000000000off
0001000001GCLK[0]
0001000010GCLK[1]
0001000100GCLK[2]
0001001000HEX_N0[6]
0001010000HEX_N3[6]
0001100000HEX_S4[6]
0010000001GCLK[3]
0010000010HEX_S3[6]
0010000100GCLK[4]
0010001000HEX_S6[6]
0010010000HEX_N1[6]
0010100000HEX_N4[6]
0100000001GCLK[5]
0100000010HEX_N2[6]
0100000100HEX_N5[6]
0100001000GCLK[6]
0100010000HEX_S5[6]
0100100000HEX_S2[6]
1000000001GCLK[7]
1000000010DBL_W1[5]
1000000100DBL_E0[5]
1000001000DBL_E1[5]
1000010000DBL_W2[5]
1000100000HEX_S1[6]
virtex2 INT_IOI switchbox INT muxes IMUX_CLK[1]
BitsDestination
MAIN[5][47]MAIN[5][48]MAIN[5][50]MAIN[4][48]MAIN[4][50]MAIN[4][46]MAIN[4][44]MAIN[5][46]MAIN[5][44]MAIN[4][40]IMUX_CLK[1]
Source
0000000000off
0001000001GCLK[0]
0001000010GCLK[1]
0001000100GCLK[2]
0001001000HEX_N0[6]
0001010000HEX_N3[6]
0001100000HEX_S4[6]
0010000001GCLK[3]
0010000010HEX_S3[6]
0010000100GCLK[4]
0010001000HEX_S6[6]
0010010000HEX_N1[6]
0010100000HEX_N4[6]
0100000001GCLK[5]
0100000010HEX_N2[6]
0100000100HEX_N5[6]
0100001000GCLK[6]
0100010000HEX_S5[6]
0100100000HEX_S2[6]
1000000001GCLK[7]
1000000010DBL_W1[5]
1000000100DBL_E0[5]
1000001000DBL_E1[5]
1000010000DBL_W2[5]
1000100000HEX_S1[6]
virtex2 INT_IOI switchbox INT muxes IMUX_CLK[2]
BitsDestination
MAIN[5][54]MAIN[5][53]MAIN[5][51]MAIN[4][53]MAIN[4][51]MAIN[4][55]MAIN[4][57]MAIN[5][55]MAIN[5][57]MAIN[4][61]IMUX_CLK[2]
Source
0000000000off
0001000001GCLK[0]
0001000010GCLK[1]
0001000100GCLK[2]
0001001000HEX_N0[6]
0001010000HEX_N3[6]
0001100000HEX_S4[6]
0010000001GCLK[3]
0010000010HEX_S3[6]
0010000100GCLK[4]
0010001000HEX_S6[6]
0010010000HEX_N1[6]
0010100000HEX_N4[6]
0100000001GCLK[5]
0100000010HEX_N2[6]
0100000100HEX_N5[6]
0100001000GCLK[6]
0100010000HEX_S5[6]
0100100000HEX_S2[6]
1000000001GCLK[7]
1000000010DBL_W2[6]
1000000100DBL_E0[6]
1000001000DBL_E1[6]
1000010000DBL_W1[6]
1000100000HEX_S1[6]
virtex2 INT_IOI switchbox INT muxes IMUX_CLK[3]
BitsDestination
MAIN[5][60]MAIN[5][59]MAIN[5][61]MAIN[4][59]MAIN[5][52]MAIN[4][54]MAIN[4][58]MAIN[5][56]MAIN[4][56]MAIN[5][58]IMUX_CLK[3]
Source
0000000000off
0001000001GCLK[0]
0001000010GCLK[1]
0001000100GCLK[2]
0001001000HEX_N0[6]
0001010000HEX_N3[6]
0001100000HEX_S4[6]
0010000001GCLK[3]
0010000010HEX_S3[6]
0010000100GCLK[4]
0010001000HEX_S6[6]
0010010000HEX_N1[6]
0010100000HEX_N4[6]
0100000001GCLK[5]
0100000010HEX_N2[6]
0100000100HEX_N5[6]
0100001000GCLK[6]
0100010000HEX_S5[6]
0100100000HEX_S2[6]
1000000001GCLK[7]
1000000010DBL_W2[6]
1000000100DBL_E0[6]
1000001000DBL_E1[6]
1000010000DBL_W1[6]
1000100000HEX_S1[6]
virtex2 INT_IOI switchbox INT muxes IMUX_SR[0]
BitsDestination
MAIN[5][3]MAIN[4][3]MAIN[5][5]MAIN[4][5]MAIN[5][1]MAIN[5][2]MAIN[4][2]MAIN[5][0]IMUX_SR[0]
Source
00000000PULLUP
00010001DBL_W1[0]
00010010HEX_N1[0]
00010100HEX_N5[0]
00011000HEX_S4[0]
00100001DBL_W2[0]
00100010HEX_S5[0]
00100100HEX_S1[0]
00101000HEX_N3[0]
01000001HEX_N2[0]
01000010DBL_E0[0]
01000100HEX_S2[0]
01001000HEX_N0[0]
10000001HEX_S3[0]
10000010DBL_E1[0]
10000100HEX_N4[0]
10001000HEX_S6[0]
virtex2 INT_IOI switchbox INT muxes IMUX_SR[1]
BitsDestination
MAIN[4][12]MAIN[5][12]MAIN[5][14]MAIN[4][14]MAIN[5][16]MAIN[5][15]MAIN[5][17]MAIN[4][15]IMUX_SR[1]
Source
00000000PULLUP
00010001DBL_W1[1]
00010010HEX_N2[0]
00010100HEX_S2[0]
00011000HEX_N0[0]
00100001DBL_W2[1]
00100010HEX_S3[0]
00100100HEX_N4[0]
00101000HEX_S6[0]
01000001HEX_S5[0]
01000010DBL_E0[1]
01000100HEX_S1[0]
01001000HEX_N3[0]
10000001HEX_N1[0]
10000010DBL_E1[1]
10000100HEX_N5[0]
10001000HEX_S4[0]
virtex2 INT_IOI switchbox INT muxes IMUX_SR[2]
BitsDestination
MAIN[4][0]MAIN[4][4]MAIN[4][8]MAIN[5][4]MAIN[5][7]MAIN[5][8]MAIN[4][6]MAIN[5][6]IMUX_SR[2]
Source
00000000PULLUP
00010001DBL_W1[0]
00010010HEX_N1[0]
00010100HEX_N5[0]
00011000HEX_S4[0]
00100001DBL_W2[0]
00100010HEX_S5[0]
00100100HEX_S1[0]
00101000HEX_N3[0]
01000001HEX_N2[0]
01000010DBL_E0[0]
01000100HEX_S2[0]
01001000HEX_N0[0]
10000001HEX_S3[0]
10000010DBL_E1[0]
10000100HEX_N4[0]
10001000HEX_S6[0]
virtex2 INT_IOI switchbox INT muxes IMUX_SR[3]
BitsDestination
MAIN[5][13]MAIN[4][9]MAIN[4][17]MAIN[4][13]MAIN[5][10]MAIN[5][9]MAIN[5][11]MAIN[4][11]IMUX_SR[3]
Source
00000000PULLUP
00010001DBL_W1[1]
00010010HEX_N2[0]
00010100HEX_S2[0]
00011000HEX_N0[0]
00100001DBL_W2[1]
00100010HEX_S3[0]
00100100HEX_N4[0]
00101000HEX_S6[0]
01000001HEX_S5[0]
01000010DBL_E0[1]
01000100HEX_S1[0]
01001000HEX_N3[0]
10000001HEX_N1[0]
10000010DBL_E1[1]
10000100HEX_N5[0]
10001000HEX_S4[0]
virtex2 INT_IOI switchbox INT muxes IMUX_CE[0]
BitsDestination
MAIN[5][65]MAIN[4][65]MAIN[5][67]MAIN[4][67]MAIN[5][63]MAIN[5][64]MAIN[4][64]MAIN[5][62]IMUX_CE[0]
Source
00000000PULLUP
00010001DBL_W1[8]
00010010HEX_N0[9]
00010100HEX_N2[9]
00011000HEX_N3[9]
00100001DBL_W2[8]
00100010HEX_S6[9]
00100100HEX_S4[9]
00101000HEX_S3[9]
01000001HEX_S1[9]
01000010DBL_E0[8]
01000100HEX_S2[9]
01001000HEX_S5[9]
10000001HEX_N5[9]
10000010DBL_E1[8]
10000100HEX_N4[9]
10001000HEX_N1[9]
virtex2 INT_IOI switchbox INT muxes IMUX_CE[1]
BitsDestination
MAIN[4][62]MAIN[4][66]MAIN[4][70]MAIN[5][66]MAIN[5][69]MAIN[5][70]MAIN[4][68]MAIN[5][68]IMUX_CE[1]
Source
00000000PULLUP
00010001DBL_W1[8]
00010010HEX_N0[9]
00010100HEX_N2[9]
00011000HEX_N3[9]
00100001DBL_W2[8]
00100010HEX_S6[9]
00100100HEX_S4[9]
00101000HEX_S3[9]
01000001HEX_S1[9]
01000010DBL_E0[8]
01000100HEX_S2[9]
01001000HEX_S5[9]
10000001HEX_N5[9]
10000010DBL_E1[8]
10000100HEX_N4[9]
10001000HEX_N1[9]
virtex2 INT_IOI switchbox INT muxes IMUX_CE[2]
BitsDestination
MAIN[5][75]MAIN[4][71]MAIN[4][79]MAIN[4][75]MAIN[5][72]MAIN[5][71]MAIN[5][73]MAIN[4][73]IMUX_CE[2]
Source
00000000PULLUP
00010001DBL_W1[9]
00010010HEX_S1[9]
00010100HEX_S2[9]
00011000HEX_S5[9]
00100001DBL_W2[9]
00100010HEX_N5[9]
00100100HEX_N4[9]
00101000HEX_N1[9]
01000001HEX_S6[9]
01000010DBL_E0[9]
01000100HEX_S4[9]
01001000HEX_S3[9]
10000001HEX_N0[9]
10000010DBL_E1[9]
10000100HEX_N2[9]
10001000HEX_N3[9]
virtex2 INT_IOI switchbox INT muxes IMUX_CE[3]
BitsDestination
MAIN[4][74]MAIN[5][74]MAIN[5][76]MAIN[4][76]MAIN[5][78]MAIN[5][77]MAIN[5][79]MAIN[4][77]IMUX_CE[3]
Source
00000000PULLUP
00010001DBL_W1[9]
00010010HEX_S1[9]
00010100HEX_S2[9]
00011000HEX_S5[9]
00100001DBL_W2[9]
00100010HEX_N5[9]
00100100HEX_N4[9]
00101000HEX_N1[9]
01000001HEX_S6[9]
01000010DBL_E0[9]
01000100HEX_S4[9]
01001000HEX_S3[9]
10000001HEX_N0[9]
10000010DBL_E1[9]
10000100HEX_N2[9]
10001000HEX_N3[9]
virtex2 INT_IOI switchbox INT muxes IMUX_G0_FAN[0]
BitsDestination
MAIN[9][16]MAIN[9][19]MAIN[8][19]MAIN[8][16]MAIN[10][17]MAIN[10][19]MAIN[11][19]MAIN[11][17]MAIN[13][17]MAIN[12][19]MAIN[13][19]MAIN[12][17]IMUX_G0_FAN[0]
Source
000000000000PULLUP
000100000001OMUX_W1
000100000010OMUX_E2
000100000100OMUX_NW10
000100001000OMUX_N10
000100010000DBL_S1[0]
000100100000IMUX_G1_FAN[0]
000101000000DBL_N2[0]
000110000000IMUX_G2_FAN[0]
001000000001DBL_E0[1]
001000000010DBL_S0[0]
001000000100OMUX_EN8
001000001000DBL_W0[0]
001000010000DBL_N1[1]
001000100000DBL_S1[2]
001001000000DBL_W2[1]
001010000000DBL_S1[1]
010000000001DBL_E2[1]
010000000010DBL_S0[2]
010000000100DBL_E2[0]
010000001000DBL_E2[2]
010000010000DBL_W1[0]
010000100000DBL_E1[2]
010001000000DBL_E1[1]
010010000000DBL_N2[1]
100000000001DBL_S2[0]
100000000010DBL_S2[2]
100000000100DBL_N0[1]
100000001000DBL_S2[1]
100000010000DBL_E1[0]
100000100000DBL_W1[1]
100001000000DBL_W2[0]
100010000000DBL_N1[0]
virtex2 INT_IOI switchbox INT muxes IMUX_G0_FAN[1]
BitsDestination
MAIN[9][17]MAIN[9][18]MAIN[8][18]MAIN[8][17]MAIN[10][16]MAIN[10][18]MAIN[11][18]MAIN[11][16]MAIN[13][16]MAIN[12][18]MAIN[13][18]MAIN[12][16]IMUX_G0_FAN[1]
Source
000000000000PULLUP
000100000001OMUX_W1
000100000010OMUX_E2
000100000100OMUX_NW10
000100001000OMUX_N10
000100010000DBL_S1[0]
000100100000IMUX_G1_FAN[0]
000101000000DBL_N2[0]
000110000000IMUX_G2_FAN[0]
001000000001DBL_E0[1]
001000000010DBL_S0[0]
001000000100OMUX_EN8
001000001000DBL_W0[0]
001000010000DBL_N1[1]
001000100000DBL_S1[2]
001001000000DBL_W2[1]
001010000000DBL_S1[1]
010000000001DBL_E2[1]
010000000010DBL_S0[2]
010000000100DBL_E2[0]
010000001000DBL_E2[2]
010000010000DBL_W1[0]
010000100000DBL_E1[2]
010001000000DBL_E1[1]
010010000000DBL_N2[1]
100000000001DBL_S2[0]
100000000010DBL_S2[2]
100000000100DBL_N0[1]
100000001000DBL_S2[1]
100000010000DBL_E1[0]
100000100000DBL_W1[1]
100001000000DBL_W2[0]
100010000000DBL_N1[0]
virtex2 INT_IOI switchbox INT muxes IMUX_G0_DATA[5]
BitsDestination
MAIN[9][9]MAIN[9][10]MAIN[8][10]MAIN[8][9]MAIN[10][8]MAIN[10][10]MAIN[11][10]MAIN[11][8]MAIN[13][8]MAIN[12][10]MAIN[13][10]MAIN[12][8]IMUX_G0_DATA[5]
Source
000000000000PULLUP
000100000001OMUX_W1
000100000010OMUX_E2
000100000100OMUX_NW10
000100001000OMUX_N10
000100010000DBL_S1[0]
000100100000IMUX_G1_FAN[0]
000101000000DBL_N2[0]
000110000000IMUX_G2_FAN[0]
001000000001DBL_E0[1]
001000000010DBL_S0[0]
001000000100OMUX_EN8
001000001000DBL_W0[0]
001000010000DBL_N1[1]
001000100000DBL_S1[2]
001001000000DBL_W2[1]
001010000000DBL_S1[1]
010000000001DBL_E2[1]
010000000010DBL_S0[2]
010000000100DBL_E2[0]
010000001000DBL_E2[2]
010000010000DBL_W1[0]
010000100000DBL_E1[2]
010001000000DBL_E1[1]
010010000000DBL_N2[1]
100000000001DBL_S2[0]
100000000010DBL_S2[2]
100000000100DBL_N0[1]
100000001000DBL_S2[1]
100000010000DBL_E1[0]
100000100000DBL_W1[1]
100001000000DBL_W2[0]
100010000000DBL_N1[0]
virtex2 INT_IOI switchbox INT muxes IMUX_G0_DATA[6]
BitsDestination
MAIN[9][15]MAIN[9][12]MAIN[8][12]MAIN[8][15]MAIN[10][14]MAIN[10][12]MAIN[11][12]MAIN[11][14]MAIN[13][14]MAIN[12][12]MAIN[13][12]MAIN[12][14]IMUX_G0_DATA[6]
Source
000000000000PULLUP
000100000001OMUX_W1
000100000010OMUX_E2
000100000100OMUX_NW10
000100001000OMUX_N10
000100010000DBL_S1[0]
000100100000IMUX_G1_FAN[0]
000101000000DBL_N2[0]
000110000000IMUX_G2_FAN[0]
001000000001DBL_E0[1]
001000000010DBL_S0[0]
001000000100OMUX_EN8
001000001000DBL_W0[0]
001000010000DBL_N1[1]
001000100000DBL_S1[2]
001001000000DBL_W2[1]
001010000000DBL_S1[1]
010000000001DBL_E2[1]
010000000010DBL_S0[2]
010000000100DBL_E2[0]
010000001000DBL_E2[2]
010000010000DBL_W1[0]
010000100000DBL_E1[2]
010001000000DBL_E1[1]
010010000000DBL_N2[1]
100000000001DBL_S2[0]
100000000010DBL_S2[2]
100000000100DBL_N0[1]
100000001000DBL_S2[1]
100000010000DBL_E1[0]
100000100000DBL_W1[1]
100001000000DBL_W2[0]
100010000000DBL_N1[0]
virtex2 INT_IOI switchbox INT muxes IMUX_G0_DATA[7]
BitsDestination
MAIN[9][14]MAIN[9][13]MAIN[8][13]MAIN[8][14]MAIN[10][15]MAIN[10][13]MAIN[11][13]MAIN[11][15]MAIN[13][15]MAIN[12][13]MAIN[13][13]MAIN[12][15]IMUX_G0_DATA[7]
Source
000000000000PULLUP
000100000001OMUX_W1
000100000010OMUX_E2
000100000100OMUX_NW10
000100001000OMUX_N10
000100010000DBL_S1[0]
000100100000IMUX_G1_FAN[0]
000101000000DBL_N2[0]
000110000000IMUX_G2_FAN[0]
001000000001DBL_E0[1]
001000000010DBL_S0[0]
001000000100OMUX_EN8
001000001000DBL_W0[0]
001000010000DBL_N1[1]
001000100000DBL_S1[2]
001001000000DBL_W2[1]
001010000000DBL_S1[1]
010000000001DBL_E2[1]
010000000010DBL_S0[2]
010000000100DBL_E2[0]
010000001000DBL_E2[2]
010000010000DBL_W1[0]
010000100000DBL_E1[2]
010001000000DBL_E1[1]
010010000000DBL_N2[1]
100000000001DBL_S2[0]
100000000010DBL_S2[2]
100000000100DBL_N0[1]
100000001000DBL_S2[1]
100000010000DBL_E1[0]
100000100000DBL_W1[1]
100001000000DBL_W2[0]
100010000000DBL_N1[0]
virtex2 INT_IOI switchbox INT muxes IMUX_G1_FAN[0]
BitsDestination
MAIN[9][23]MAIN[9][20]MAIN[8][23]MAIN[8][20]MAIN[10][22]MAIN[10][20]MAIN[11][22]MAIN[11][20]MAIN[13][20]MAIN[13][22]MAIN[12][22]MAIN[12][20]IMUX_G1_FAN[0]
Source
000000000000PULLUP
000100000001OMUX_W6
000100000010DBL_S0[4]
000100000100DBL_W0[4]
000100001000DBL_E0[3]
000100010000DBL_W1[2]
000100100000DBL_N1[4]
000101000000DBL_W2[4]
000110000000DBL_N2[4]
001000000001OMUX_N12
001000000010OMUX_E7
001000000100OMUX_NE12
001000001000OMUX_WN14
001000010000IMUX_G3_FAN[1]
001000100000DBL_S1[3]
001001000000DBL_E1[4]
001010000000IMUX_G0_FAN[1]
010000000001DBL_E2[4]
010000000010DBL_E2[3]
010000000100DBL_W2[3]
010000001000DBL_W0[2]
010000010000DBL_N1[2]
010000100000DBL_W1[3]
010001000000DBL_W1[4]
010010000000DBL_N2[3]
100000000001DBL_N0[3]
100000000010DBL_S2[4]
100000000100DBL_S2[3]
100000001000DBL_W2[2]
100000010000DBL_S1[4]
100000100000DBL_E1[3]
100001000000DBL_N2[2]
100010000000DBL_N1[3]
virtex2 INT_IOI switchbox INT muxes IMUX_G1_FAN[1]
BitsDestination
MAIN[9][22]MAIN[9][21]MAIN[8][22]MAIN[8][21]MAIN[10][23]MAIN[10][21]MAIN[11][23]MAIN[11][21]MAIN[13][21]MAIN[13][23]MAIN[12][23]MAIN[12][21]IMUX_G1_FAN[1]
Source
000000000000PULLUP
000100000001OMUX_W6
000100000010DBL_S0[4]
000100000100DBL_W0[4]
000100001000DBL_E0[3]
000100010000DBL_W1[2]
000100100000DBL_N1[4]
000101000000DBL_W2[4]
000110000000DBL_N2[4]
001000000001OMUX_N12
001000000010OMUX_E7
001000000100OMUX_NE12
001000001000OMUX_WN14
001000010000IMUX_G3_FAN[1]
001000100000DBL_S1[3]
001001000000DBL_E1[4]
001010000000IMUX_G0_FAN[1]
010000000001DBL_E2[4]
010000000010DBL_E2[3]
010000000100DBL_W2[3]
010000001000DBL_W0[2]
010000010000DBL_N1[2]
010000100000DBL_W1[3]
010001000000DBL_W1[4]
010010000000DBL_N2[3]
100000000001DBL_N0[3]
100000000010DBL_S2[4]
100000000100DBL_S2[3]
100000001000DBL_W2[2]
100000010000DBL_S1[4]
100000100000DBL_E1[3]
100001000000DBL_N2[2]
100010000000DBL_N1[3]
virtex2 INT_IOI switchbox INT muxes IMUX_G1_DATA[5]
BitsDestination
MAIN[9][30]MAIN[9][29]MAIN[8][30]MAIN[8][29]MAIN[10][31]MAIN[10][29]MAIN[11][31]MAIN[11][29]MAIN[13][29]MAIN[13][31]MAIN[12][31]MAIN[12][29]IMUX_G1_DATA[5]
Source
000000000000PULLUP
000100000001OMUX_W6
000100000010DBL_S0[4]
000100000100DBL_W0[4]
000100001000DBL_E0[3]
000100010000DBL_W1[2]
000100100000DBL_N1[4]
000101000000DBL_W2[4]
000110000000DBL_N2[4]
001000000001OMUX_N12
001000000010OMUX_E7
001000000100OMUX_NE12
001000001000OMUX_WN14
001000010000IMUX_G3_FAN[1]
001000100000DBL_S1[3]
001001000000DBL_E1[4]
001010000000IMUX_G0_FAN[1]
010000000001DBL_E2[4]
010000000010DBL_E2[3]
010000000100DBL_W2[3]
010000001000DBL_W0[2]
010000010000DBL_N1[2]
010000100000DBL_W1[3]
010001000000DBL_W1[4]
010010000000DBL_N2[3]
100000000001DBL_N0[3]
100000000010DBL_S2[4]
100000000100DBL_S2[3]
100000001000DBL_W2[2]
100000010000DBL_S1[4]
100000100000DBL_E1[3]
100001000000DBL_N2[2]
100010000000DBL_N1[3]
virtex2 INT_IOI switchbox INT muxes IMUX_G1_DATA[6]
BitsDestination
MAIN[9][24]MAIN[9][27]MAIN[8][24]MAIN[8][27]MAIN[10][25]MAIN[10][27]MAIN[11][25]MAIN[11][27]MAIN[13][27]MAIN[13][25]MAIN[12][25]MAIN[12][27]IMUX_G1_DATA[6]
Source
000000000000PULLUP
000100000001OMUX_W6
000100000010DBL_S0[4]
000100000100DBL_W0[4]
000100001000DBL_E0[3]
000100010000DBL_W1[2]
000100100000DBL_N1[4]
000101000000DBL_W2[4]
000110000000DBL_N2[4]
001000000001OMUX_N12
001000000010OMUX_E7
001000000100OMUX_NE12
001000001000OMUX_WN14
001000010000IMUX_G3_FAN[1]
001000100000DBL_S1[3]
001001000000DBL_E1[4]
001010000000IMUX_G0_FAN[1]
010000000001DBL_E2[4]
010000000010DBL_E2[3]
010000000100DBL_W2[3]
010000001000DBL_W0[2]
010000010000DBL_N1[2]
010000100000DBL_W1[3]
010001000000DBL_W1[4]
010010000000DBL_N2[3]
100000000001DBL_N0[3]
100000000010DBL_S2[4]
100000000100DBL_S2[3]
100000001000DBL_W2[2]
100000010000DBL_S1[4]
100000100000DBL_E1[3]
100001000000DBL_N2[2]
100010000000DBL_N1[3]
virtex2 INT_IOI switchbox INT muxes IMUX_G1_DATA[7]
BitsDestination
MAIN[9][25]MAIN[9][26]MAIN[8][25]MAIN[8][26]MAIN[10][24]MAIN[10][26]MAIN[11][24]MAIN[11][26]MAIN[13][26]MAIN[13][24]MAIN[12][24]MAIN[12][26]IMUX_G1_DATA[7]
Source
000000000000PULLUP
000100000001OMUX_W6
000100000010DBL_S0[4]
000100000100DBL_W0[4]
000100001000DBL_E0[3]
000100010000DBL_W1[2]
000100100000DBL_N1[4]
000101000000DBL_W2[4]
000110000000DBL_N2[4]
001000000001OMUX_N12
001000000010OMUX_E7
001000000100OMUX_NE12
001000001000OMUX_WN14
001000010000IMUX_G3_FAN[1]
001000100000DBL_S1[3]
001001000000DBL_E1[4]
001010000000IMUX_G0_FAN[1]
010000000001DBL_E2[4]
010000000010DBL_E2[3]
010000000100DBL_W2[3]
010000001000DBL_W0[2]
010000010000DBL_N1[2]
010000100000DBL_W1[3]
010001000000DBL_W1[4]
010010000000DBL_N2[3]
100000000001DBL_N0[3]
100000000010DBL_S2[4]
100000000100DBL_S2[3]
100000001000DBL_W2[2]
100000010000DBL_S1[4]
100000100000DBL_E1[3]
100001000000DBL_N2[2]
100010000000DBL_N1[3]
virtex2 INT_IOI switchbox INT muxes IMUX_G2_FAN[0]
BitsDestination
MAIN[9][56]MAIN[9][59]MAIN[8][59]MAIN[8][56]MAIN[10][57]MAIN[10][59]MAIN[11][59]MAIN[11][57]MAIN[13][59]MAIN[13][57]MAIN[12][59]MAIN[12][57]IMUX_G2_FAN[0]
Source
000000000000PULLUP
000100000001OMUX_WS1
000100000010OMUX_E8
000100000100OMUX_SE3
000100001000OMUX_W9
000100010000DBL_S1[5]
000100100000IMUX_G3_FAN[0]
000101000000DBL_N2[5]
000110000000IMUX_G0_FAN[0]
001000000001DBL_E0[5]
001000000010OMUX_S3
001000000100DBL_W0[6]
001000001000DBL_S0[6]
001000010000DBL_N1[6]
001000100000DBL_S1[7]
001001000000DBL_W2[6]
001010000000DBL_S1[6]
010000000001DBL_E2[6]
010000000010DBL_E2[5]
010000000100DBL_E2[7]
010000001000DBL_E0[7]
010000010000DBL_W1[5]
010000100000DBL_E1[7]
010001000000DBL_E1[6]
010010000000DBL_N2[6]
100000000001DBL_S2[5]
100000000010DBL_N0[5]
100000000100DBL_S2[6]
100000001000DBL_S2[7]
100000010000DBL_E1[5]
100000100000DBL_W1[6]
100001000000DBL_W2[5]
100010000000DBL_N1[5]
virtex2 INT_IOI switchbox INT muxes IMUX_G2_FAN[1]
BitsDestination
MAIN[9][57]MAIN[9][58]MAIN[8][58]MAIN[8][57]MAIN[10][56]MAIN[10][58]MAIN[11][58]MAIN[11][56]MAIN[13][58]MAIN[13][56]MAIN[12][58]MAIN[12][56]IMUX_G2_FAN[1]
Source
000000000000PULLUP
000100000001OMUX_WS1
000100000010OMUX_E8
000100000100OMUX_SE3
000100001000OMUX_W9
000100010000DBL_S1[5]
000100100000IMUX_G3_FAN[0]
000101000000DBL_N2[5]
000110000000IMUX_G0_FAN[0]
001000000001DBL_E0[5]
001000000010OMUX_S3
001000000100DBL_W0[6]
001000001000DBL_S0[6]
001000010000DBL_N1[6]
001000100000DBL_S1[7]
001001000000DBL_W2[6]
001010000000DBL_S1[6]
010000000001DBL_E2[6]
010000000010DBL_E2[5]
010000000100DBL_E2[7]
010000001000DBL_E0[7]
010000010000DBL_W1[5]
010000100000DBL_E1[7]
010001000000DBL_E1[6]
010010000000DBL_N2[6]
100000000001DBL_S2[5]
100000000010DBL_N0[5]
100000000100DBL_S2[6]
100000001000DBL_S2[7]
100000010000DBL_E1[5]
100000100000DBL_W1[6]
100001000000DBL_W2[5]
100010000000DBL_N1[5]
virtex2 INT_IOI switchbox INT muxes IMUX_G2_DATA[5]
BitsDestination
MAIN[9][49]MAIN[9][50]MAIN[8][50]MAIN[8][49]MAIN[10][48]MAIN[10][50]MAIN[11][50]MAIN[11][48]MAIN[13][50]MAIN[13][48]MAIN[12][50]MAIN[12][48]IMUX_G2_DATA[5]
Source
000000000000PULLUP
000100000001OMUX_WS1
000100000010OMUX_E8
000100000100OMUX_SE3
000100001000OMUX_W9
000100010000DBL_S1[5]
000100100000IMUX_G3_FAN[0]
000101000000DBL_N2[5]
000110000000IMUX_G0_FAN[0]
001000000001DBL_E0[5]
001000000010OMUX_S3
001000000100DBL_W0[6]
001000001000DBL_S0[6]
001000010000DBL_N1[6]
001000100000DBL_S1[7]
001001000000DBL_W2[6]
001010000000DBL_S1[6]
010000000001DBL_E2[6]
010000000010DBL_E2[5]
010000000100DBL_E2[7]
010000001000DBL_E0[7]
010000010000DBL_W1[5]
010000100000DBL_E1[7]
010001000000DBL_E1[6]
010010000000DBL_N2[6]
100000000001DBL_S2[5]
100000000010DBL_N0[5]
100000000100DBL_S2[6]
100000001000DBL_S2[7]
100000010000DBL_E1[5]
100000100000DBL_W1[6]
100001000000DBL_W2[5]
100010000000DBL_N1[5]
virtex2 INT_IOI switchbox INT muxes IMUX_G2_DATA[6]
BitsDestination
MAIN[9][55]MAIN[9][52]MAIN[8][52]MAIN[8][55]MAIN[10][54]MAIN[10][52]MAIN[11][52]MAIN[11][54]MAIN[13][52]MAIN[13][54]MAIN[12][52]MAIN[12][54]IMUX_G2_DATA[6]
Source
000000000000PULLUP
000100000001OMUX_WS1
000100000010OMUX_E8
000100000100OMUX_SE3
000100001000OMUX_W9
000100010000DBL_S1[5]
000100100000IMUX_G3_FAN[0]
000101000000DBL_N2[5]
000110000000IMUX_G0_FAN[0]
001000000001DBL_E0[5]
001000000010OMUX_S3
001000000100DBL_W0[6]
001000001000DBL_S0[6]
001000010000DBL_N1[6]
001000100000DBL_S1[7]
001001000000DBL_W2[6]
001010000000DBL_S1[6]
010000000001DBL_E2[6]
010000000010DBL_E2[5]
010000000100DBL_E2[7]
010000001000DBL_E0[7]
010000010000DBL_W1[5]
010000100000DBL_E1[7]
010001000000DBL_E1[6]
010010000000DBL_N2[6]
100000000001DBL_S2[5]
100000000010DBL_N0[5]
100000000100DBL_S2[6]
100000001000DBL_S2[7]
100000010000DBL_E1[5]
100000100000DBL_W1[6]
100001000000DBL_W2[5]
100010000000DBL_N1[5]
virtex2 INT_IOI switchbox INT muxes IMUX_G2_DATA[7]
BitsDestination
MAIN[9][54]MAIN[9][53]MAIN[8][53]MAIN[8][54]MAIN[10][55]MAIN[10][53]MAIN[11][53]MAIN[11][55]MAIN[13][53]MAIN[13][55]MAIN[12][53]MAIN[12][55]IMUX_G2_DATA[7]
Source
000000000000PULLUP
000100000001OMUX_WS1
000100000010OMUX_E8
000100000100OMUX_SE3
000100001000OMUX_W9
000100010000DBL_S1[5]
000100100000IMUX_G3_FAN[0]
000101000000DBL_N2[5]
000110000000IMUX_G0_FAN[0]
001000000001DBL_E0[5]
001000000010OMUX_S3
001000000100DBL_W0[6]
001000001000DBL_S0[6]
001000010000DBL_N1[6]
001000100000DBL_S1[7]
001001000000DBL_W2[6]
001010000000DBL_S1[6]
010000000001DBL_E2[6]
010000000010DBL_E2[5]
010000000100DBL_E2[7]
010000001000DBL_E0[7]
010000010000DBL_W1[5]
010000100000DBL_E1[7]
010001000000DBL_E1[6]
010010000000DBL_N2[6]
100000000001DBL_S2[5]
100000000010DBL_N0[5]
100000000100DBL_S2[6]
100000001000DBL_S2[7]
100000010000DBL_E1[5]
100000100000DBL_W1[6]
100001000000DBL_W2[5]
100010000000DBL_N1[5]
virtex2 INT_IOI switchbox INT muxes IMUX_G3_FAN[0]
BitsDestination
MAIN[9][63]MAIN[9][60]MAIN[8][60]MAIN[8][63]MAIN[10][62]MAIN[10][60]MAIN[11][62]MAIN[11][60]MAIN[13][62]MAIN[12][62]MAIN[12][60]MAIN[13][60]IMUX_G3_FAN[0]
Source
000000000000PULLUP
000100000001OMUX_S5
000100000010OMUX_W14
000100000100OMUX_ES7
000100001000OMUX_E13
000100010000IMUX_G1_FAN[1]
000100100000DBL_S1[8]
000101000000DBL_E1[9]
000110000000IMUX_G2_FAN[1]
001000000001DBL_W0[8]
001000000010OMUX_SW5
001000000100DBL_S0[8]
001000001000DBL_E0[9]
001000010000DBL_W1[7]
001000100000DBL_N1[9]
001001000000DBL_W2[9]
001010000000DBL_N2[9]
010000000001DBL_N0[7]
010000000010DBL_E2[9]
010000000100DBL_E2[8]
010000001000DBL_W2[8]
010000010000DBL_N1[7]
010000100000DBL_W1[8]
010001000000DBL_W1[9]
010010000000DBL_N2[8]
100000000001DBL_W2[7]
100000000010DBL_N0[9]
100000000100DBL_S2[9]
100000001000DBL_S2[8]
100000010000DBL_S1[9]
100000100000DBL_E1[8]
100001000000DBL_N2[7]
100010000000DBL_N1[8]
virtex2 INT_IOI switchbox INT muxes IMUX_G3_FAN[1]
BitsDestination
MAIN[9][62]MAIN[9][61]MAIN[8][61]MAIN[8][62]MAIN[10][63]MAIN[10][61]MAIN[11][63]MAIN[11][61]MAIN[13][63]MAIN[12][63]MAIN[12][61]MAIN[13][61]IMUX_G3_FAN[1]
Source
000000000000PULLUP
000100000001OMUX_S5
000100000010OMUX_W14
000100000100OMUX_ES7
000100001000OMUX_E13
000100010000IMUX_G1_FAN[1]
000100100000DBL_S1[8]
000101000000DBL_E1[9]
000110000000IMUX_G2_FAN[1]
001000000001DBL_W0[8]
001000000010OMUX_SW5
001000000100DBL_S0[8]
001000001000DBL_E0[9]
001000010000DBL_W1[7]
001000100000DBL_N1[9]
001001000000DBL_W2[9]
001010000000DBL_N2[9]
010000000001DBL_N0[7]
010000000010DBL_E2[9]
010000000100DBL_E2[8]
010000001000DBL_W2[8]
010000010000DBL_N1[7]
010000100000DBL_W1[8]
010001000000DBL_W1[9]
010010000000DBL_N2[8]
100000000001DBL_W2[7]
100000000010DBL_N0[9]
100000000100DBL_S2[9]
100000001000DBL_S2[8]
100000010000DBL_S1[9]
100000100000DBL_E1[8]
100001000000DBL_N2[7]
100010000000DBL_N1[8]
virtex2 INT_IOI switchbox INT muxes IMUX_G3_DATA[5]
BitsDestination
MAIN[9][70]MAIN[9][69]MAIN[8][69]MAIN[8][70]MAIN[10][71]MAIN[10][69]MAIN[11][71]MAIN[11][69]MAIN[13][71]MAIN[12][71]MAIN[12][69]MAIN[13][69]IMUX_G3_DATA[5]
Source
000000000000PULLUP
000100000001OMUX_S5
000100000010OMUX_W14
000100000100OMUX_ES7
000100001000OMUX_E13
000100010000IMUX_G1_FAN[1]
000100100000DBL_S1[8]
000101000000DBL_E1[9]
000110000000IMUX_G2_FAN[1]
001000000001DBL_W0[8]
001000000010OMUX_SW5
001000000100DBL_S0[8]
001000001000DBL_E0[9]
001000010000DBL_W1[7]
001000100000DBL_N1[9]
001001000000DBL_W2[9]
001010000000DBL_N2[9]
010000000001DBL_N0[7]
010000000010DBL_E2[9]
010000000100DBL_E2[8]
010000001000DBL_W2[8]
010000010000DBL_N1[7]
010000100000DBL_W1[8]
010001000000DBL_W1[9]
010010000000DBL_N2[8]
100000000001DBL_W2[7]
100000000010DBL_N0[9]
100000000100DBL_S2[9]
100000001000DBL_S2[8]
100000010000DBL_S1[9]
100000100000DBL_E1[8]
100001000000DBL_N2[7]
100010000000DBL_N1[8]
virtex2 INT_IOI switchbox INT muxes IMUX_G3_DATA[6]
BitsDestination
MAIN[9][64]MAIN[9][67]MAIN[8][67]MAIN[8][64]MAIN[10][65]MAIN[10][67]MAIN[11][65]MAIN[11][67]MAIN[13][65]MAIN[12][65]MAIN[12][67]MAIN[13][67]IMUX_G3_DATA[6]
Source
000000000000PULLUP
000100000001OMUX_S5
000100000010OMUX_W14
000100000100OMUX_ES7
000100001000OMUX_E13
000100010000IMUX_G1_FAN[1]
000100100000DBL_S1[8]
000101000000DBL_E1[9]
000110000000IMUX_G2_FAN[1]
001000000001DBL_W0[8]
001000000010OMUX_SW5
001000000100DBL_S0[8]
001000001000DBL_E0[9]
001000010000DBL_W1[7]
001000100000DBL_N1[9]
001001000000DBL_W2[9]
001010000000DBL_N2[9]
010000000001DBL_N0[7]
010000000010DBL_E2[9]
010000000100DBL_E2[8]
010000001000DBL_W2[8]
010000010000DBL_N1[7]
010000100000DBL_W1[8]
010001000000DBL_W1[9]
010010000000DBL_N2[8]
100000000001DBL_W2[7]
100000000010DBL_N0[9]
100000000100DBL_S2[9]
100000001000DBL_S2[8]
100000010000DBL_S1[9]
100000100000DBL_E1[8]
100001000000DBL_N2[7]
100010000000DBL_N1[8]
virtex2 INT_IOI switchbox INT muxes IMUX_G3_DATA[7]
BitsDestination
MAIN[9][65]MAIN[9][66]MAIN[8][66]MAIN[8][65]MAIN[10][64]MAIN[10][66]MAIN[11][64]MAIN[11][66]MAIN[13][64]MAIN[12][64]MAIN[12][66]MAIN[13][66]IMUX_G3_DATA[7]
Source
000000000000PULLUP
000100000001OMUX_S5
000100000010OMUX_W14
000100000100OMUX_ES7
000100001000OMUX_E13
000100010000IMUX_G1_FAN[1]
000100100000DBL_S1[8]
000101000000DBL_E1[9]
000110000000IMUX_G2_FAN[1]
001000000001DBL_W0[8]
001000000010OMUX_SW5
001000000100DBL_S0[8]
001000001000DBL_E0[9]
001000010000DBL_W1[7]
001000100000DBL_N1[9]
001001000000DBL_W2[9]
001010000000DBL_N2[9]
010000000001DBL_N0[7]
010000000010DBL_E2[9]
010000000100DBL_E2[8]
010000001000DBL_W2[8]
010000010000DBL_N1[7]
010000100000DBL_W1[8]
010001000000DBL_W1[9]
010010000000DBL_N2[8]
100000000001DBL_W2[7]
100000000010DBL_N0[9]
100000000100DBL_S2[9]
100000001000DBL_S2[8]
100000010000DBL_S1[9]
100000100000DBL_E1[8]
100001000000DBL_N2[7]
100010000000DBL_N1[8]
virtex2 INT_IOI switchbox INT muxes IMUX_IOI_ICLK[0]
BitsDestination
MAIN[5][19]MAIN[5][20]MAIN[5][18]MAIN[4][20]MAIN[5][27]MAIN[4][25]MAIN[4][21]MAIN[5][23]MAIN[4][23]MAIN[5][21]IMUX_IOI_ICLK[0]
Source
0000000000off
0001000001GCLK[0]
0001000010GCLK[1]
0001000100GCLK[2]
0001001000HEX_N0[3]
0001010000HEX_N3[3]
0001100000HEX_S4[3]
0010000001GCLK[3]
0010000010HEX_S3[3]
0010000100GCLK[4]
0010001000HEX_S6[3]
0010010000HEX_N1[3]
0010100000HEX_N4[3]
0100000001GCLK[5]
0100000010HEX_N2[3]
0100000100HEX_N5[3]
0100001000GCLK[6]
0100010000HEX_S5[3]
0100100000HEX_S2[3]
1000000001GCLK[7]
1000000010DBL_E1[3]
1000000100DBL_W1[3]
1000001000DBL_W2[3]
1000010000DBL_E0[3]
1000100000HEX_S1[3]
virtex2 INT_IOI switchbox INT muxes IMUX_IOI_ICLK[1]
BitsDestination
MAIN[5][25]MAIN[5][26]MAIN[5][28]MAIN[4][26]MAIN[4][28]MAIN[4][24]MAIN[4][22]MAIN[5][24]MAIN[5][22]MAIN[4][18]IMUX_IOI_ICLK[1]
Source
0000000000off
0001000001GCLK[0]
0001000010GCLK[1]
0001000100GCLK[2]
0001001000HEX_N0[3]
0001010000HEX_N3[3]
0001100000HEX_S4[3]
0010000001GCLK[3]
0010000010HEX_S3[3]
0010000100GCLK[4]
0010001000HEX_S6[3]
0010010000HEX_N1[3]
0010100000HEX_N4[3]
0100000001GCLK[5]
0100000010HEX_N2[3]
0100000100HEX_N5[3]
0100001000GCLK[6]
0100010000HEX_S5[3]
0100100000HEX_S2[3]
1000000001GCLK[7]
1000000010DBL_E1[3]
1000000100DBL_W1[3]
1000001000DBL_W2[3]
1000010000DBL_E0[3]
1000100000HEX_S1[3]
virtex2 INT_IOI switchbox INT muxes IMUX_IOI_ICLK[2]
BitsDestination
MAIN[5][32]MAIN[5][31]MAIN[5][29]MAIN[4][31]MAIN[4][29]MAIN[4][33]MAIN[4][35]MAIN[5][33]MAIN[5][35]MAIN[4][39]IMUX_IOI_ICLK[2]
Source
0000000000off
0001000001GCLK[0]
0001000010GCLK[1]
0001000100GCLK[2]
0001001000HEX_N0[3]
0001010000HEX_N3[3]
0001100000HEX_S4[3]
0010000001GCLK[3]
0010000010HEX_S3[3]
0010000100GCLK[4]
0010001000HEX_S6[3]
0010010000HEX_N1[3]
0010100000HEX_N4[3]
0100000001GCLK[5]
0100000010DBL_W2[4]
0100000100HEX_N5[3]
0100001000GCLK[6]
0100010000HEX_S5[3]
0100100000HEX_S2[3]
1000000001GCLK[7]
1000000010HEX_N2[3]
1000000100DBL_E0[4]
1000001000DBL_W1[4]
1000010000DBL_E1[4]
1000100000HEX_S1[3]
virtex2 INT_IOI switchbox INT muxes IMUX_IOI_ICLK[3]
BitsDestination
MAIN[5][38]MAIN[5][37]MAIN[5][39]MAIN[4][37]MAIN[5][30]MAIN[4][32]MAIN[4][36]MAIN[5][34]MAIN[4][34]MAIN[5][36]IMUX_IOI_ICLK[3]
Source
0000000000off
0001000001GCLK[0]
0001000010GCLK[1]
0001000100GCLK[2]
0001001000HEX_N0[3]
0001010000HEX_N3[3]
0001100000HEX_S4[3]
0010000001GCLK[3]
0010000010HEX_S3[3]
0010000100GCLK[4]
0010001000HEX_S6[3]
0010010000HEX_N1[3]
0010100000HEX_N4[3]
0100000001GCLK[5]
0100000010DBL_W2[4]
0100000100HEX_N5[3]
0100001000GCLK[6]
0100010000HEX_S5[3]
0100100000HEX_S2[3]
1000000001GCLK[7]
1000000010HEX_N2[3]
1000000100DBL_E0[4]
1000001000DBL_W1[4]
1000010000DBL_E1[4]
1000100000HEX_S1[3]
virtex2 INT_IOI switchbox INT muxes IMUX_IOI_TS1[0]
BitsDestination
MAIN[9][6]MAIN[9][5]MAIN[8][5]MAIN[8][6]MAIN[10][7]MAIN[13][5]MAIN[12][7]MAIN[10][5]MAIN[11][5]MAIN[11][7]MAIN[13][7]MAIN[12][5]IMUX_IOI_TS1[0]
Source
000000000000PULLUP
000100000001OMUX_NW10
000100000010HEX_N4[1]
000100000100DBL_S1[0]
000100001000IMUX_G1_FAN[0]
000100010000DBL_N2[0]
000100100000HEX_N2[1]
000101000000HEX_S2[1]
000110000000IMUX_G2_FAN[0]
001000000001HEX_N0[1]
001000000010DBL_W0[0]
001000000100DBL_N1[1]
001000001000DBL_S1[2]
001000010000DBL_W2[1]
001000100000DBL_E0[1]
001001000000DBL_S0[0]
001010000000DBL_S1[1]
010000000001DBL_E2[0]
010000000010HEX_S6[1]
010000000100DBL_W1[0]
010000001000HEX_S5[1]
010000010000DBL_E1[1]
010000100000HEX_S4[1]
010001000000HEX_S1[1]
010010000000HEX_N3[1]
100000000001DBL_N0[1]
100000000010HEX_N1[1]
100000000100DBL_E1[0]
100000001000DBL_W1[1]
100000010000HEX_S3[1]
100000100000DBL_S2[0]
100001000000HEX_N5[1]
100010000000DBL_N1[0]
virtex2 INT_IOI switchbox INT muxes IMUX_IOI_TS1[1]
BitsDestination
MAIN[9][7]MAIN[9][4]MAIN[8][4]MAIN[8][7]MAIN[10][6]MAIN[13][4]MAIN[12][6]MAIN[10][4]MAIN[11][4]MAIN[11][6]MAIN[13][6]MAIN[12][4]IMUX_IOI_TS1[1]
Source
000000000000PULLUP
000100000001OMUX_NW10
000100000010HEX_N4[1]
000100000100DBL_S1[0]
000100001000IMUX_G1_FAN[0]
000100010000DBL_N2[0]
000100100000HEX_N2[1]
000101000000HEX_S2[1]
000110000000IMUX_G2_FAN[0]
001000000001HEX_N0[1]
001000000010DBL_W0[0]
001000000100DBL_N1[1]
001000001000DBL_S1[2]
001000010000DBL_W2[1]
001000100000DBL_E0[1]
001001000000DBL_S0[0]
001010000000DBL_S1[1]
010000000001DBL_E2[0]
010000000010HEX_S6[1]
010000000100DBL_W1[0]
010000001000HEX_S5[1]
010000010000DBL_E1[1]
010000100000HEX_S4[1]
010001000000HEX_S1[1]
010010000000HEX_N3[1]
100000000001DBL_N0[1]
100000000010HEX_N1[1]
100000000100DBL_E1[0]
100000001000DBL_W1[1]
100000010000HEX_S3[1]
100000100000DBL_S2[0]
100001000000HEX_N5[1]
100010000000DBL_N1[0]
virtex2 INT_IOI switchbox INT muxes IMUX_IOI_TS1[2]
BitsDestination
MAIN[9][1]MAIN[9][2]MAIN[8][2]MAIN[8][1]MAIN[10][0]MAIN[13][2]MAIN[12][0]MAIN[10][2]MAIN[11][2]MAIN[11][0]MAIN[13][0]MAIN[12][2]IMUX_IOI_TS1[2]
Source
000000000000PULLUP
000100000001OMUX_NW10
000100000010HEX_N4[1]
000100000100DBL_S1[0]
000100001000IMUX_G1_FAN[0]
000100010000DBL_N2[0]
000100100000HEX_N2[1]
000101000000HEX_S2[1]
000110000000IMUX_G2_FAN[0]
001000000001HEX_N0[1]
001000000010DBL_W0[0]
001000000100DBL_N1[1]
001000001000DBL_S1[2]
001000010000DBL_W2[1]
001000100000DBL_E0[1]
001001000000DBL_S0[0]
001010000000DBL_S1[1]
010000000001DBL_E2[0]
010000000010HEX_S6[1]
010000000100DBL_W1[0]
010000001000HEX_S5[1]
010000010000DBL_E1[1]
010000100000HEX_S4[1]
010001000000HEX_S1[1]
010010000000HEX_N3[1]
100000000001DBL_N0[1]
100000000010HEX_N1[1]
100000000100DBL_E1[0]
100000001000DBL_W1[1]
100000010000HEX_S3[1]
100000100000DBL_S2[0]
100001000000HEX_N5[1]
100010000000DBL_N1[0]
virtex2 INT_IOI switchbox INT muxes IMUX_IOI_TS1[3]
BitsDestination
MAIN[9][0]MAIN[9][3]MAIN[8][3]MAIN[8][0]MAIN[10][1]MAIN[13][3]MAIN[12][1]MAIN[10][3]MAIN[11][3]MAIN[11][1]MAIN[13][1]MAIN[12][3]IMUX_IOI_TS1[3]
Source
000000000000PULLUP
000100000001OMUX_NW10
000100000010HEX_N4[1]
000100000100DBL_S1[0]
000100001000IMUX_G1_FAN[0]
000100010000DBL_N2[0]
000100100000HEX_N2[1]
000101000000HEX_S2[1]
000110000000IMUX_G2_FAN[0]
001000000001HEX_N0[1]
001000000010DBL_W0[0]
001000000100DBL_N1[1]
001000001000DBL_S1[2]
001000010000DBL_W2[1]
001000100000DBL_E0[1]
001001000000DBL_S0[0]
001010000000DBL_S1[1]
010000000001DBL_E2[0]
010000000010HEX_S6[1]
010000000100DBL_W1[0]
010000001000HEX_S5[1]
010000010000DBL_E1[1]
010000100000HEX_S4[1]
010001000000HEX_S1[1]
010010000000HEX_N3[1]
100000000001DBL_N0[1]
100000000010HEX_N1[1]
100000000100DBL_E1[0]
100000001000DBL_W1[1]
100000010000HEX_S3[1]
100000100000DBL_S2[0]
100001000000HEX_N5[1]
100010000000DBL_N1[0]
virtex2 INT_IOI switchbox INT muxes IMUX_IOI_TS2[0]
BitsDestination
MAIN[9][33]MAIN[9][34]MAIN[8][34]MAIN[8][33]MAIN[10][32]MAIN[12][32]MAIN[13][34]MAIN[10][34]MAIN[11][32]MAIN[11][34]MAIN[13][32]MAIN[12][34]IMUX_IOI_TS2[0]
Source
000000000000PULLUP
000100000001OMUX_N12
000100000010HEX_S2[4]
000100000100IMUX_G3_FAN[1]
000100001000DBL_S1[3]
000100010000DBL_E1[4]
000100100000HEX_N5[4]
000101000000HEX_N3[4]
000110000000IMUX_G0_FAN[1]
001000000001HEX_N4[4]
001000000010DBL_W0[4]
001000000100DBL_W1[2]
001000001000DBL_N1[4]
001000010000DBL_W2[4]
001000100000DBL_E0[3]
001001000000DBL_S0[4]
001010000000DBL_N2[4]
010000000001DBL_E2[4]
010000000010HEX_S4[4]
010000000100HEX_S5[4]
010000001000DBL_W1[3]
010000010000DBL_W1[4]
010000100000HEX_N1[4]
010001000000HEX_S3[4]
010010000000HEX_N0[4]
100000000001DBL_N0[3]
100000000010HEX_N2[4]
100000000100DBL_S1[4]
100000001000DBL_E1[3]
100000010000HEX_S6[4]
100000100000HEX_S1[4]
100001000000DBL_S2[4]
100010000000DBL_N1[3]
virtex2 INT_IOI switchbox INT muxes IMUX_IOI_TS2[1]
BitsDestination
MAIN[9][32]MAIN[9][35]MAIN[8][35]MAIN[8][32]MAIN[10][33]MAIN[12][33]MAIN[13][35]MAIN[10][35]MAIN[11][33]MAIN[11][35]MAIN[13][33]MAIN[12][35]IMUX_IOI_TS2[1]
Source
000000000000PULLUP
000100000001OMUX_N12
000100000010HEX_S2[4]
000100000100IMUX_G3_FAN[1]
000100001000DBL_S1[3]
000100010000DBL_E1[4]
000100100000HEX_N5[4]
000101000000HEX_N3[4]
000110000000IMUX_G0_FAN[1]
001000000001HEX_N4[4]
001000000010DBL_W0[4]
001000000100DBL_W1[2]
001000001000DBL_N1[4]
001000010000DBL_W2[4]
001000100000DBL_E0[3]
001001000000DBL_S0[4]
001010000000DBL_N2[4]
010000000001DBL_E2[4]
010000000010HEX_S4[4]
010000000100HEX_S5[4]
010000001000DBL_W1[3]
010000010000DBL_W1[4]
010000100000HEX_N1[4]
010001000000HEX_S3[4]
010010000000HEX_N0[4]
100000000001DBL_N0[3]
100000000010HEX_N2[4]
100000000100DBL_S1[4]
100000001000DBL_E1[3]
100000010000HEX_S6[4]
100000100000HEX_S1[4]
100001000000DBL_S2[4]
100010000000DBL_N1[3]
virtex2 INT_IOI switchbox INT muxes IMUX_IOI_TS2[2]
BitsDestination
MAIN[9][38]MAIN[9][37]MAIN[8][37]MAIN[8][38]MAIN[10][39]MAIN[12][39]MAIN[13][37]MAIN[10][37]MAIN[11][39]MAIN[11][37]MAIN[13][39]MAIN[12][37]IMUX_IOI_TS2[2]
Source
000000000000PULLUP
000100000001OMUX_N12
000100000010HEX_S2[4]
000100000100IMUX_G3_FAN[1]
000100001000DBL_S1[3]
000100010000DBL_E1[4]
000100100000HEX_N5[4]
000101000000HEX_N3[4]
000110000000IMUX_G0_FAN[1]
001000000001HEX_N4[4]
001000000010DBL_W0[4]
001000000100DBL_W1[2]
001000001000DBL_N1[4]
001000010000DBL_W2[4]
001000100000DBL_E0[3]
001001000000DBL_S0[4]
001010000000DBL_N2[4]
010000000001DBL_E2[4]
010000000010HEX_S4[4]
010000000100HEX_S5[4]
010000001000DBL_W1[3]
010000010000DBL_W1[4]
010000100000HEX_N1[4]
010001000000HEX_S3[4]
010010000000HEX_N0[4]
100000000001DBL_N0[3]
100000000010HEX_N2[4]
100000000100DBL_S1[4]
100000001000DBL_E1[3]
100000010000HEX_S6[4]
100000100000HEX_S1[4]
100001000000DBL_S2[4]
100010000000DBL_N1[3]
virtex2 INT_IOI switchbox INT muxes IMUX_IOI_TS2[3]
BitsDestination
MAIN[9][39]MAIN[9][36]MAIN[8][36]MAIN[8][39]MAIN[10][38]MAIN[12][38]MAIN[13][36]MAIN[10][36]MAIN[11][38]MAIN[11][36]MAIN[13][38]MAIN[12][36]IMUX_IOI_TS2[3]
Source
000000000000PULLUP
000100000001OMUX_N12
000100000010HEX_S2[4]
000100000100IMUX_G3_FAN[1]
000100001000DBL_S1[3]
000100010000DBL_E1[4]
000100100000HEX_N5[4]
000101000000HEX_N3[4]
000110000000IMUX_G0_FAN[1]
001000000001HEX_N4[4]
001000000010DBL_W0[4]
001000000100DBL_W1[2]
001000001000DBL_N1[4]
001000010000DBL_W2[4]
001000100000DBL_E0[3]
001001000000DBL_S0[4]
001010000000DBL_N2[4]
010000000001DBL_E2[4]
010000000010HEX_S4[4]
010000000100HEX_S5[4]
010000001000DBL_W1[3]
010000010000DBL_W1[4]
010000100000HEX_N1[4]
010001000000HEX_S3[4]
010010000000HEX_N0[4]
100000000001DBL_N0[3]
100000000010HEX_N2[4]
100000000100DBL_S1[4]
100000001000DBL_E1[3]
100000010000HEX_S6[4]
100000100000HEX_S1[4]
100001000000DBL_S2[4]
100010000000DBL_N1[3]
virtex2 INT_IOI switchbox INT muxes IMUX_IOI_ICE[0]
BitsDestination
MAIN[9][46]MAIN[9][45]MAIN[8][45]MAIN[8][46]MAIN[10][47]MAIN[13][45]MAIN[12][47]MAIN[10][45]MAIN[11][45]MAIN[11][47]MAIN[13][47]MAIN[12][45]IMUX_IOI_ICE[0]
Source
000000000000PULLUP
000100000001OMUX_E8
000100000010HEX_S6[5]
000100000100DBL_S1[5]
000100001000IMUX_G3_FAN[0]
000100010000DBL_N2[5]
000100100000HEX_N4[5]
000101000000HEX_S3[5]
000110000000IMUX_G0_FAN[0]
001000000001HEX_N2[5]
001000000010DBL_W0[6]
001000000100DBL_N1[6]
001000001000DBL_S1[7]
001000010000DBL_W2[6]
001000100000DBL_E0[5]
001001000000DBL_S0[6]
001010000000DBL_S1[6]
010000000001DBL_E2[5]
010000000010HEX_S1[5]
010000000100DBL_W1[5]
010000001000HEX_S2[5]
010000010000DBL_E1[6]
010000100000HEX_N5[5]
010001000000HEX_S4[5]
010010000000HEX_S5[5]
100000000001DBL_N0[5]
100000000010HEX_N0[5]
100000000100DBL_E1[5]
100000001000DBL_W1[6]
100000010000HEX_N1[5]
100000100000DBL_S2[5]
100001000000HEX_N3[5]
100010000000DBL_N1[5]
virtex2 INT_IOI switchbox INT muxes IMUX_IOI_ICE[1]
BitsDestination
MAIN[9][47]MAIN[9][44]MAIN[8][44]MAIN[8][47]MAIN[10][46]MAIN[13][44]MAIN[12][46]MAIN[10][44]MAIN[11][44]MAIN[11][46]MAIN[13][46]MAIN[12][44]IMUX_IOI_ICE[1]
Source
000000000000PULLUP
000100000001OMUX_E8
000100000010HEX_S6[5]
000100000100DBL_S1[5]
000100001000IMUX_G3_FAN[0]
000100010000DBL_N2[5]
000100100000HEX_N4[5]
000101000000HEX_S3[5]
000110000000IMUX_G0_FAN[0]
001000000001HEX_N2[5]
001000000010DBL_W0[6]
001000000100DBL_N1[6]
001000001000DBL_S1[7]
001000010000DBL_W2[6]
001000100000DBL_E0[5]
001001000000DBL_S0[6]
001010000000DBL_S1[6]
010000000001DBL_E2[5]
010000000010HEX_S1[5]
010000000100DBL_W1[5]
010000001000HEX_S2[5]
010000010000DBL_E1[6]
010000100000HEX_N5[5]
010001000000HEX_S4[5]
010010000000HEX_S5[5]
100000000001DBL_N0[5]
100000000010HEX_N0[5]
100000000100DBL_E1[5]
100000001000DBL_W1[6]
100000010000HEX_N1[5]
100000100000DBL_S2[5]
100001000000HEX_N3[5]
100010000000DBL_N1[5]
virtex2 INT_IOI switchbox INT muxes IMUX_IOI_ICE[2]
BitsDestination
MAIN[9][41]MAIN[9][42]MAIN[8][42]MAIN[8][41]MAIN[10][40]MAIN[13][42]MAIN[12][40]MAIN[10][42]MAIN[11][42]MAIN[11][40]MAIN[13][40]MAIN[12][42]IMUX_IOI_ICE[2]
Source
000000000000PULLUP
000100000001OMUX_E8
000100000010HEX_S6[5]
000100000100DBL_S1[5]
000100001000IMUX_G3_FAN[0]
000100010000DBL_N2[5]
000100100000HEX_N4[5]
000101000000HEX_S3[5]
000110000000IMUX_G0_FAN[0]
001000000001HEX_N2[5]
001000000010DBL_W0[6]
001000000100DBL_N1[6]
001000001000DBL_S1[7]
001000010000DBL_W2[6]
001000100000DBL_E0[5]
001001000000DBL_S0[6]
001010000000DBL_S1[6]
010000000001DBL_E2[5]
010000000010HEX_S1[5]
010000000100DBL_W1[5]
010000001000HEX_S2[5]
010000010000DBL_E1[6]
010000100000HEX_N5[5]
010001000000HEX_S4[5]
010010000000HEX_S5[5]
100000000001DBL_N0[5]
100000000010HEX_N0[5]
100000000100DBL_E1[5]
100000001000DBL_W1[6]
100000010000HEX_N1[5]
100000100000DBL_S2[5]
100001000000HEX_N3[5]
100010000000DBL_N1[5]
virtex2 INT_IOI switchbox INT muxes IMUX_IOI_ICE[3]
BitsDestination
MAIN[9][40]MAIN[9][43]MAIN[8][43]MAIN[8][40]MAIN[10][41]MAIN[13][43]MAIN[12][41]MAIN[10][43]MAIN[11][43]MAIN[11][41]MAIN[13][41]MAIN[12][43]IMUX_IOI_ICE[3]
Source
000000000000PULLUP
000100000001OMUX_E8
000100000010HEX_S6[5]
000100000100DBL_S1[5]
000100001000IMUX_G3_FAN[0]
000100010000DBL_N2[5]
000100100000HEX_N4[5]
000101000000HEX_S3[5]
000110000000IMUX_G0_FAN[0]
001000000001HEX_N2[5]
001000000010DBL_W0[6]
001000000100DBL_N1[6]
001000001000DBL_S1[7]
001000010000DBL_W2[6]
001000100000DBL_E0[5]
001001000000DBL_S0[6]
001010000000DBL_S1[6]
010000000001DBL_E2[5]
010000000010HEX_S1[5]
010000000100DBL_W1[5]
010000001000HEX_S2[5]
010000010000DBL_E1[6]
010000100000HEX_N5[5]
010001000000HEX_S4[5]
010010000000HEX_S5[5]
100000000001DBL_N0[5]
100000000010HEX_N0[5]
100000000100DBL_E1[5]
100000001000DBL_W1[6]
100000010000HEX_N1[5]
100000100000DBL_S2[5]
100001000000HEX_N3[5]
100010000000DBL_N1[5]
virtex2 INT_IOI switchbox INT muxes IMUX_IOI_TCE[0]
BitsDestination
MAIN[9][73]MAIN[9][74]MAIN[8][74]MAIN[8][73]MAIN[10][72]MAIN[12][72]MAIN[13][72]MAIN[10][74]MAIN[11][72]MAIN[11][74]MAIN[13][74]MAIN[12][74]IMUX_IOI_TCE[0]
Source
000000000000PULLUP
000100000001OMUX_W14
000100000010HEX_S2[8]
000100000100IMUX_G1_FAN[1]
000100001000DBL_S1[8]
000100010000DBL_E1[9]
000100100000HEX_S4[8]
000101000000HEX_S5[8]
000110000000IMUX_G2_FAN[1]
001000000001HEX_N3[8]
001000000010DBL_W0[8]
001000000100DBL_W1[7]
001000001000DBL_N1[9]
001000010000DBL_W2[9]
001000100000DBL_E0[9]
001001000000DBL_S0[8]
001010000000DBL_N2[9]
010000000001DBL_E2[9]
010000000010HEX_S1[8]
010000000100HEX_N1[8]
010000001000DBL_W1[8]
010000010000DBL_W1[9]
010000100000HEX_N5[8]
010001000000HEX_S3[8]
010010000000HEX_N0[8]
100000000001DBL_N0[9]
100000000010HEX_N2[8]
100000000100DBL_S1[9]
100000001000DBL_E1[8]
100000010000HEX_S6[8]
100000100000HEX_N4[8]
100001000000DBL_S2[9]
100010000000DBL_N1[8]
virtex2 INT_IOI switchbox INT muxes IMUX_IOI_TCE[1]
BitsDestination
MAIN[9][72]MAIN[9][75]MAIN[8][75]MAIN[8][72]MAIN[10][73]MAIN[12][73]MAIN[13][73]MAIN[10][75]MAIN[11][73]MAIN[11][75]MAIN[13][75]MAIN[12][75]IMUX_IOI_TCE[1]
Source
000000000000PULLUP
000100000001OMUX_W14
000100000010HEX_S2[8]
000100000100IMUX_G1_FAN[1]
000100001000DBL_S1[8]
000100010000DBL_E1[9]
000100100000HEX_S4[8]
000101000000HEX_S5[8]
000110000000IMUX_G2_FAN[1]
001000000001HEX_N3[8]
001000000010DBL_W0[8]
001000000100DBL_W1[7]
001000001000DBL_N1[9]
001000010000DBL_W2[9]
001000100000DBL_E0[9]
001001000000DBL_S0[8]
001010000000DBL_N2[9]
010000000001DBL_E2[9]
010000000010HEX_S1[8]
010000000100HEX_N1[8]
010000001000DBL_W1[8]
010000010000DBL_W1[9]
010000100000HEX_N5[8]
010001000000HEX_S3[8]
010010000000HEX_N0[8]
100000000001DBL_N0[9]
100000000010HEX_N2[8]
100000000100DBL_S1[9]
100000001000DBL_E1[8]
100000010000HEX_S6[8]
100000100000HEX_N4[8]
100001000000DBL_S2[9]
100010000000DBL_N1[8]
virtex2 INT_IOI switchbox INT muxes IMUX_IOI_TCE[2]
BitsDestination
MAIN[9][78]MAIN[9][77]MAIN[8][77]MAIN[8][78]MAIN[10][79]MAIN[12][79]MAIN[13][79]MAIN[10][77]MAIN[11][79]MAIN[11][77]MAIN[13][77]MAIN[12][77]IMUX_IOI_TCE[2]
Source
000000000000PULLUP
000100000001OMUX_W14
000100000010HEX_S2[8]
000100000100IMUX_G1_FAN[1]
000100001000DBL_S1[8]
000100010000DBL_E1[9]
000100100000HEX_S4[8]
000101000000HEX_S5[8]
000110000000IMUX_G2_FAN[1]
001000000001HEX_N3[8]
001000000010DBL_W0[8]
001000000100DBL_W1[7]
001000001000DBL_N1[9]
001000010000DBL_W2[9]
001000100000DBL_E0[9]
001001000000DBL_S0[8]
001010000000DBL_N2[9]
010000000001DBL_E2[9]
010000000010HEX_S1[8]
010000000100HEX_N1[8]
010000001000DBL_W1[8]
010000010000DBL_W1[9]
010000100000HEX_N5[8]
010001000000HEX_S3[8]
010010000000HEX_N0[8]
100000000001DBL_N0[9]
100000000010HEX_N2[8]
100000000100DBL_S1[9]
100000001000DBL_E1[8]
100000010000HEX_S6[8]
100000100000HEX_N4[8]
100001000000DBL_S2[9]
100010000000DBL_N1[8]
virtex2 INT_IOI switchbox INT muxes IMUX_IOI_TCE[3]
BitsDestination
MAIN[9][79]MAIN[9][76]MAIN[8][76]MAIN[8][79]MAIN[10][78]MAIN[12][78]MAIN[13][78]MAIN[10][76]MAIN[11][78]MAIN[11][76]MAIN[13][76]MAIN[12][76]IMUX_IOI_TCE[3]
Source
000000000000PULLUP
000100000001OMUX_W14
000100000010HEX_S2[8]
000100000100IMUX_G1_FAN[1]
000100001000DBL_S1[8]
000100010000DBL_E1[9]
000100100000HEX_S4[8]
000101000000HEX_S5[8]
000110000000IMUX_G2_FAN[1]
001000000001HEX_N3[8]
001000000010DBL_W0[8]
001000000100DBL_W1[7]
001000001000DBL_N1[9]
001000010000DBL_W2[9]
001000100000DBL_E0[9]
001001000000DBL_S0[8]
001010000000DBL_N2[9]
010000000001DBL_E2[9]
010000000010HEX_S1[8]
010000000100HEX_N1[8]
010000001000DBL_W1[8]
010000010000DBL_W1[9]
010000100000HEX_N5[8]
010001000000HEX_S3[8]
010010000000HEX_N0[8]
100000000001DBL_N0[9]
100000000010HEX_N2[8]
100000000100DBL_S1[9]
100000001000DBL_E1[8]
100000010000HEX_S6[8]
100000100000HEX_N4[8]
100001000000DBL_S2[9]
100010000000DBL_N1[8]

Bitstream

virtex2 INT_IOI rect MAIN
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21
B79 - - - - INT: mux IMUX_CE[2] bit 5 INT: mux IMUX_CE[3] bit 1 INT: mux OMUX[14] bit 0 INT: mux OMUX[15] bit 9 INT: mux IMUX_IOI_TCE[3] bit 8 INT: mux IMUX_IOI_TCE[3] bit 11 INT: mux IMUX_IOI_TCE[2] bit 7 INT: mux IMUX_IOI_TCE[2] bit 3 INT: mux IMUX_IOI_TCE[2] bit 6 INT: mux IMUX_IOI_TCE[2] bit 5 INT: mux DBL_E0[9] bit 0 INT: mux DBL_W0[9] bit 7 INT: mux DBL_E0[9] bit 5 INT: mux DBL_E0[9] bit 7 INT: mux HEX_W0[9] bit 0 INT: mux HEX_W0[9] bit 3 INT: mux HEX_W0[9] bit 4 INT: mux LV[18] bit 1
B78 - - - - INT: !invert IMUX_CE_OPTINV[3] ← IMUX_CE[3] INT: mux IMUX_CE[3] bit 3 INT: mux OMUX[15] bit 8 INT: mux OMUX[15] bit 6 INT: mux IMUX_IOI_TCE[2] bit 8 INT: mux IMUX_IOI_TCE[2] bit 11 INT: mux IMUX_IOI_TCE[3] bit 7 INT: mux IMUX_IOI_TCE[3] bit 3 INT: mux IMUX_IOI_TCE[3] bit 6 INT: mux IMUX_IOI_TCE[3] bit 5 INT: mux DBL_E0[9] bit 1 INT: mux DBL_W0[9] bit 4 INT: mux DBL_W0[9] bit 3 INT: mux DBL_W0[9] bit 0 INT: mux HEX_E0[9] bit 1 INT: mux HEX_E0[9] bit 3 INT: mux HEX_E0[9] bit 5 INT: mux HEX_W0[9] bit 6
B77 - - - - INT: mux IMUX_CE[3] bit 0 INT: mux IMUX_CE[3] bit 2 INT: mux OMUX[15] bit 0 INT: mux OMUX[15] bit 7 INT: mux IMUX_IOI_TCE[2] bit 9 INT: mux IMUX_IOI_TCE[2] bit 10 INT: mux IMUX_IOI_TCE[2] bit 4 INT: mux IMUX_IOI_TCE[2] bit 2 INT: mux IMUX_IOI_TCE[2] bit 0 INT: mux IMUX_IOI_TCE[2] bit 1 INT: mux DBL_W0[9] bit 5 INT: mux DBL_E0[9] bit 3 INT: mux DBL_W0[9] bit 2 INT: mux DBL_W0[9] bit 1 INT: mux HEX_W0[9] bit 2 INT: mux HEX_W0[9] bit 1 INT: mux HEX_E0[9] bit 6 INT: mux LV[18] bit 3
B76 - - - - INT: mux IMUX_CE[3] bit 4 INT: mux IMUX_CE[3] bit 5 INT: mux OMUX[14] bit 1 INT: mux OMUX[15] bit 1 INT: mux IMUX_IOI_TCE[3] bit 9 INT: mux IMUX_IOI_TCE[3] bit 10 INT: mux IMUX_IOI_TCE[3] bit 4 INT: mux IMUX_IOI_TCE[3] bit 2 INT: mux IMUX_IOI_TCE[3] bit 0 INT: mux IMUX_IOI_TCE[3] bit 1 INT: mux DBL_W0[9] bit 6 INT: mux DBL_E0[9] bit 2 INT: mux DBL_E0[9] bit 4 INT: mux DBL_E0[9] bit 6 INT: mux HEX_E0[9] bit 2 INT: mux HEX_E0[9] bit 0 INT: mux HEX_E0[9] bit 4 INT: mux HEX_W0[9] bit 5
B75 - - - - INT: mux IMUX_CE[2] bit 4 INT: mux IMUX_CE[2] bit 7 INT: mux OMUX[15] bit 3 INT: mux OMUX[14] bit 3 INT: mux IMUX_IOI_TCE[1] bit 9 INT: mux IMUX_IOI_TCE[1] bit 10 INT: mux IMUX_IOI_TCE[1] bit 4 INT: mux IMUX_IOI_TCE[1] bit 2 INT: mux IMUX_IOI_TCE[1] bit 0 INT: mux IMUX_IOI_TCE[1] bit 1 INT: mux DBL_S0[9] bit 4 INT: mux DBL_N0[9] bit 2 INT: mux DBL_S0[9] bit 0 INT: mux DBL_S0[9] bit 3 INT: mux HEX_N0[9] bit 1 INT: mux HEX_N0[9] bit 3 INT: mux HEX_N0[9] bit 5 INT: mux LV[6] bit 0
B74 - - - - INT: mux IMUX_CE[3] bit 7 INT: mux IMUX_CE[3] bit 6 INT: mux OMUX[15] bit 2 INT: mux OMUX[14] bit 2 INT: mux IMUX_IOI_TCE[0] bit 9 INT: mux IMUX_IOI_TCE[0] bit 10 INT: mux IMUX_IOI_TCE[0] bit 4 INT: mux IMUX_IOI_TCE[0] bit 2 INT: mux IMUX_IOI_TCE[0] bit 0 INT: mux IMUX_IOI_TCE[0] bit 1 INT: mux DBL_S0[9] bit 5 INT: mux DBL_N0[9] bit 0 INT: mux DBL_N0[9] bit 7 INT: mux DBL_N0[9] bit 5 INT: mux HEX_S0[9] bit 1 INT: mux HEX_S0[9] bit 2 INT: mux HEX_S0[9] bit 4 INT: mux HEX_N0[9] bit 4
B73 - - - - INT: mux IMUX_CE[2] bit 0 INT: mux IMUX_CE[2] bit 1 INT: mux OMUX[14] bit 4 INT: mux OMUX[15] bit 4 INT: mux IMUX_IOI_TCE[0] bit 8 INT: mux IMUX_IOI_TCE[0] bit 11 INT: mux IMUX_IOI_TCE[1] bit 7 INT: mux IMUX_IOI_TCE[1] bit 3 INT: mux IMUX_IOI_TCE[1] bit 6 INT: mux IMUX_IOI_TCE[1] bit 5 INT: mux DBL_N0[9] bit 1 INT: mux DBL_S0[9] bit 6 INT: mux DBL_N0[9] bit 6 INT: mux DBL_N0[9] bit 4 INT: mux HEX_N0[9] bit 2 INT: mux HEX_N0[9] bit 0 INT: mux HEX_S0[9] bit 5 INT: mux LV[6] bit 6
B72 - - - - INT: !invert IMUX_CE_OPTINV[2] ← IMUX_CE[2] INT: mux IMUX_CE[2] bit 3 INT: mux OMUX[15] bit 5 INT: mux OMUX[14] bit 7 INT: mux IMUX_IOI_TCE[1] bit 8 INT: mux IMUX_IOI_TCE[1] bit 11 INT: mux IMUX_IOI_TCE[0] bit 7 INT: mux IMUX_IOI_TCE[0] bit 3 INT: mux IMUX_IOI_TCE[0] bit 6 INT: mux IMUX_IOI_TCE[0] bit 5 INT: mux DBL_N0[9] bit 3 INT: mux DBL_S0[9] bit 7 INT: mux DBL_S0[9] bit 1 INT: mux DBL_S0[9] bit 2 INT: mux HEX_S0[9] bit 3 INT: mux HEX_S0[9] bit 0 INT: mux HEX_S0[9] bit 6 INT: mux HEX_N0[9] bit 6
B71 - - - - INT: mux IMUX_CE[2] bit 6 INT: mux IMUX_CE[2] bit 2 INT: mux OMUX[14] bit 8 INT: mux OMUX[14] bit 6 - - INT: mux IMUX_G3_DATA[5] bit 7 INT: mux IMUX_G3_DATA[5] bit 5 INT: mux IMUX_G3_DATA[5] bit 2 INT: mux IMUX_G3_DATA[5] bit 3 INT: mux DBL_E0[8] bit 2 INT: mux DBL_W0[8] bit 3 INT: mux DBL_E0[8] bit 4 INT: mux DBL_E0[8] bit 7 INT: mux HEX_E0[8] bit 0 INT: mux HEX_E0[8] bit 3 INT: mux HEX_E0[8] bit 4 INT: mux LV[6] bit 2
B70 - - - - INT: mux IMUX_CE[1] bit 5 INT: mux IMUX_CE[1] bit 2 INT: mux OMUX[14] bit 5 INT: mux OMUX[14] bit 9 INT: mux IMUX_G3_DATA[5] bit 8 INT: mux IMUX_G3_DATA[5] bit 11 - - - - INT: mux DBL_E0[8] bit 0 INT: mux DBL_W0[8] bit 0 INT: mux DBL_W0[8] bit 7 INT: mux DBL_W0[8] bit 4 INT: mux HEX_W0[8] bit 0 INT: mux HEX_W0[8] bit 3 INT: mux HEX_W0[8] bit 4 INT: mux HEX_E0[8] bit 5
B69 - - - - INT: !invert IMUX_CE_OPTINV[1] ← IMUX_CE[1] INT: mux IMUX_CE[1] bit 3 INT: mux OMUX[12] bit 0 INT: mux OMUX[13] bit 9 INT: mux IMUX_G3_DATA[5] bit 9 INT: mux IMUX_G3_DATA[5] bit 10 INT: mux IMUX_G3_DATA[5] bit 6 INT: mux IMUX_G3_DATA[5] bit 4 INT: mux IMUX_G3_DATA[5] bit 1 INT: mux IMUX_G3_DATA[5] bit 0 INT: mux DBL_W0[8] bit 2 INT: mux DBL_E0[8] bit 3 INT: mux DBL_W0[8] bit 6 INT: mux DBL_W0[8] bit 5 INT: mux HEX_E0[8] bit 2 INT: mux HEX_E0[8] bit 1 INT: mux HEX_W0[8] bit 5 INT: mux LV[6] bit 3
B68 - - - - INT: mux IMUX_CE[1] bit 1 INT: mux IMUX_CE[1] bit 0 INT: mux OMUX[13] bit 8 INT: mux OMUX[13] bit 6 - - - - - - INT: mux DBL_W0[8] bit 1 INT: mux DBL_E0[8] bit 1 INT: mux DBL_E0[8] bit 5 INT: mux DBL_E0[8] bit 6 INT: mux HEX_W0[8] bit 2 INT: mux HEX_W0[8] bit 1 INT: mux HEX_W0[8] bit 6 INT: mux HEX_E0[8] bit 6
B67 - - - - INT: mux IMUX_CE[0] bit 4 INT: mux IMUX_CE[0] bit 5 INT: mux OMUX[13] bit 0 INT: mux OMUX[13] bit 7 INT: mux IMUX_G3_DATA[6] bit 9 INT: mux IMUX_G3_DATA[6] bit 10 INT: mux IMUX_G3_DATA[6] bit 6 INT: mux IMUX_G3_DATA[6] bit 4 INT: mux IMUX_G3_DATA[6] bit 1 INT: mux IMUX_G3_DATA[6] bit 0 INT: mux DBL_S0[8] bit 3 INT: mux DBL_N0[8] bit 1 INT: mux DBL_S0[8] bit 5 INT: mux DBL_S0[8] bit 7 INT: mux HEX_S0[8] bit 1 INT: mux HEX_S0[8] bit 3 INT: mux HEX_S0[8] bit 5 INT: mux LV[18] bit 6
B66 - - - - INT: mux IMUX_CE[1] bit 6 INT: mux IMUX_CE[1] bit 4 INT: mux OMUX[12] bit 1 INT: mux OMUX[13] bit 1 INT: mux IMUX_G3_DATA[7] bit 9 INT: mux IMUX_G3_DATA[7] bit 10 INT: mux IMUX_G3_DATA[7] bit 6 INT: mux IMUX_G3_DATA[7] bit 4 INT: mux IMUX_G3_DATA[7] bit 1 INT: mux IMUX_G3_DATA[7] bit 0 INT: mux DBL_S0[8] bit 0 INT: mux DBL_N0[8] bit 0 INT: mux DBL_N0[8] bit 7 INT: mux DBL_N0[8] bit 5 INT: mux HEX_N0[8] bit 1 INT: mux HEX_N0[8] bit 2 INT: mux HEX_N0[8] bit 5 INT: mux HEX_S0[8] bit 4
B65 - - - - INT: mux IMUX_CE[0] bit 6 INT: mux IMUX_CE[0] bit 7 INT: mux OMUX[13] bit 3 INT: mux OMUX[12] bit 3 INT: mux IMUX_G3_DATA[7] bit 8 INT: mux IMUX_G3_DATA[7] bit 11 INT: mux IMUX_G3_DATA[6] bit 7 INT: mux IMUX_G3_DATA[6] bit 5 INT: mux IMUX_G3_DATA[6] bit 2 INT: mux IMUX_G3_DATA[6] bit 3 INT: mux DBL_N0[8] bit 3 INT: mux DBL_S0[8] bit 1 INT: mux DBL_N0[8] bit 6 INT: mux DBL_N0[8] bit 4 INT: mux HEX_S0[8] bit 2 INT: mux HEX_S0[8] bit 0 INT: mux HEX_N0[8] bit 4 INT: mux LV[6] bit 1
B64 - - - - INT: mux IMUX_CE[0] bit 1 INT: mux IMUX_CE[0] bit 2 INT: mux OMUX[13] bit 2 INT: mux OMUX[12] bit 2 INT: mux IMUX_G3_DATA[6] bit 8 INT: mux IMUX_G3_DATA[6] bit 11 INT: mux IMUX_G3_DATA[7] bit 7 INT: mux IMUX_G3_DATA[7] bit 5 INT: mux IMUX_G3_DATA[7] bit 2 INT: mux IMUX_G3_DATA[7] bit 3 INT: mux DBL_N0[8] bit 2 INT: mux DBL_S0[8] bit 2 INT: mux DBL_S0[8] bit 4 INT: mux DBL_S0[8] bit 6 INT: mux HEX_N0[8] bit 3 INT: mux HEX_N0[8] bit 0 INT: mux HEX_N0[8] bit 6 INT: mux HEX_S0[8] bit 6
B63 - - - - INT: !invert IMUX_CE_OPTINV[0] ← IMUX_CE[0] INT: mux IMUX_CE[0] bit 3 INT: mux OMUX[12] bit 4 INT: mux OMUX[13] bit 4 INT: mux IMUX_G3_FAN[0] bit 8 INT: mux IMUX_G3_FAN[0] bit 11 INT: mux IMUX_G3_FAN[1] bit 7 INT: mux IMUX_G3_FAN[1] bit 5 INT: mux IMUX_G3_FAN[1] bit 2 INT: mux IMUX_G3_FAN[1] bit 3 INT: mux DBL_E0[7] bit 2 INT: mux DBL_W0[7] bit 3 INT: mux DBL_E0[7] bit 4 INT: mux DBL_E0[7] bit 7 INT: mux HEX_W0[7] bit 0 INT: mux HEX_W0[7] bit 3 INT: mux HEX_W0[7] bit 4 INT: mux LV[18] bit 0
B62 - - - - INT: mux IMUX_CE[1] bit 7 INT: mux IMUX_CE[0] bit 0 INT: mux OMUX[13] bit 5 INT: mux OMUX[12] bit 7 INT: mux IMUX_G3_FAN[1] bit 8 INT: mux IMUX_G3_FAN[1] bit 11 INT: mux IMUX_G3_FAN[0] bit 7 INT: mux IMUX_G3_FAN[0] bit 5 INT: mux IMUX_G3_FAN[0] bit 2 INT: mux IMUX_G3_FAN[0] bit 3 INT: mux DBL_E0[7] bit 0 INT: mux DBL_W0[7] bit 0 INT: mux DBL_W0[7] bit 7 INT: mux DBL_W0[7] bit 4 INT: mux HEX_E0[7] bit 0 INT: mux HEX_E0[7] bit 3 INT: mux HEX_E0[7] bit 4 INT: mux HEX_W0[7] bit 5
B61 - - - - INT: mux IMUX_CLK[2] bit 0 INT: mux IMUX_CLK[3] bit 7 INT: mux OMUX[12] bit 8 INT: mux OMUX[12] bit 6 INT: mux IMUX_G3_FAN[1] bit 9 INT: mux IMUX_G3_FAN[1] bit 10 INT: mux IMUX_G3_FAN[1] bit 6 INT: mux IMUX_G3_FAN[1] bit 4 INT: mux IMUX_G3_FAN[1] bit 1 INT: mux IMUX_G3_FAN[1] bit 0 INT: mux DBL_W0[7] bit 2 INT: mux DBL_E0[7] bit 3 INT: mux DBL_W0[7] bit 6 INT: mux DBL_W0[7] bit 5 INT: mux HEX_W0[7] bit 2 INT: mux HEX_W0[7] bit 1 INT: mux HEX_E0[7] bit 5 INT: mux LV[6] bit 5
B60 - - - - INT: invert IMUX_CLK_OPTINV[3] ← IMUX_CLK[3] INT: mux IMUX_CLK[3] bit 9 INT: mux OMUX[12] bit 5 INT: mux OMUX[12] bit 9 INT: mux IMUX_G3_FAN[0] bit 9 INT: mux IMUX_G3_FAN[0] bit 10 INT: mux IMUX_G3_FAN[0] bit 6 INT: mux IMUX_G3_FAN[0] bit 4 INT: mux IMUX_G3_FAN[0] bit 1 INT: mux IMUX_G3_FAN[0] bit 0 INT: mux DBL_W0[7] bit 1 INT: mux DBL_E0[7] bit 1 INT: mux DBL_E0[7] bit 5 INT: mux DBL_E0[7] bit 6 INT: mux HEX_E0[7] bit 2 INT: mux HEX_E0[7] bit 1 INT: mux HEX_E0[7] bit 6 INT: mux HEX_W0[7] bit 6
B59 - - - - INT: mux IMUX_CLK[3] bit 6 INT: mux IMUX_CLK[3] bit 8 INT: mux OMUX[10] bit 0 INT: mux OMUX[11] bit 9 INT: mux IMUX_G2_FAN[0] bit 9 INT: mux IMUX_G2_FAN[0] bit 10 INT: mux IMUX_G2_FAN[0] bit 6 INT: mux IMUX_G2_FAN[0] bit 5 INT: mux IMUX_G2_FAN[0] bit 1 INT: mux IMUX_G2_FAN[0] bit 3 INT: mux DBL_S0[7] bit 4 INT: mux DBL_N0[7] bit 6 INT: mux DBL_S0[7] bit 1 INT: mux DBL_S0[7] bit 3 INT: mux HEX_N0[7] bit 1 INT: mux HEX_N0[7] bit 3 INT: mux HEX_N0[7] bit 6 INT: mux LV[18] bit 2
B58 - - - - INT: mux IMUX_CLK[3] bit 3 INT: mux IMUX_CLK[3] bit 0 INT: mux OMUX[11] bit 8 INT: mux OMUX[11] bit 6 INT: mux IMUX_G2_FAN[1] bit 9 INT: mux IMUX_G2_FAN[1] bit 10 INT: mux IMUX_G2_FAN[1] bit 6 INT: mux IMUX_G2_FAN[1] bit 5 INT: mux IMUX_G2_FAN[1] bit 1 INT: mux IMUX_G2_FAN[1] bit 3 INT: mux DBL_S0[7] bit 5 INT: mux DBL_N0[7] bit 5 INT: mux DBL_N0[7] bit 3 INT: mux DBL_N0[7] bit 1 INT: mux HEX_S0[7] bit 1 INT: mux HEX_S0[7] bit 2 INT: mux HEX_S0[7] bit 5 INT: mux HEX_N0[7] bit 5
B57 - - - - INT: mux IMUX_CLK[2] bit 3 INT: mux IMUX_CLK[2] bit 1 INT: mux OMUX[11] bit 0 INT: mux OMUX[11] bit 7 INT: mux IMUX_G2_FAN[1] bit 8 INT: mux IMUX_G2_FAN[1] bit 11 INT: mux IMUX_G2_FAN[0] bit 7 INT: mux IMUX_G2_FAN[0] bit 4 INT: mux IMUX_G2_FAN[0] bit 0 INT: mux IMUX_G2_FAN[0] bit 2 INT: mux DBL_N0[7] bit 4 INT: mux DBL_S0[7] bit 6 INT: mux DBL_N0[7] bit 2 INT: mux DBL_N0[7] bit 0 INT: mux HEX_N0[7] bit 2 INT: mux HEX_N0[7] bit 0 INT: mux HEX_S0[7] bit 6 INT: mux LV[18] bit 4
B56 - - - - INT: mux IMUX_CLK[3] bit 1 INT: mux IMUX_CLK[3] bit 2 INT: mux OMUX[10] bit 1 INT: mux OMUX[11] bit 1 INT: mux IMUX_G2_FAN[0] bit 8 INT: mux IMUX_G2_FAN[0] bit 11 INT: mux IMUX_G2_FAN[1] bit 7 INT: mux IMUX_G2_FAN[1] bit 4 INT: mux IMUX_G2_FAN[1] bit 0 INT: mux IMUX_G2_FAN[1] bit 2 INT: mux DBL_N0[7] bit 7 INT: mux DBL_S0[7] bit 7 INT: mux DBL_S0[7] bit 0 INT: mux DBL_S0[7] bit 2 INT: mux HEX_S0[7] bit 3 INT: mux HEX_S0[7] bit 0 INT: mux HEX_S0[7] bit 4 INT: mux HEX_N0[7] bit 4
B55 - - - - INT: mux IMUX_CLK[2] bit 4 INT: mux IMUX_CLK[2] bit 2 INT: mux OMUX[11] bit 3 INT: mux OMUX[10] bit 3 INT: mux IMUX_G2_DATA[6] bit 8 INT: mux IMUX_G2_DATA[6] bit 11 INT: mux IMUX_G2_DATA[7] bit 7 INT: mux IMUX_G2_DATA[7] bit 4 INT: mux IMUX_G2_DATA[7] bit 0 INT: mux IMUX_G2_DATA[7] bit 2 INT: mux DBL_E0[6] bit 1 INT: mux DBL_W0[6] bit 7 INT: mux DBL_E0[6] bit 5 INT: mux DBL_E0[6] bit 7 INT: mux HEX_E0[6] bit 1 INT: mux HEX_E0[6] bit 3 INT: mux HEX_E0[6] bit 5 INT: mux LV[6] bit 4
B54 - - - - INT: mux IMUX_CLK[3] bit 4 INT: mux IMUX_CLK[2] bit 9 INT: mux OMUX[11] bit 2 INT: mux OMUX[10] bit 2 INT: mux IMUX_G2_DATA[7] bit 8 INT: mux IMUX_G2_DATA[7] bit 11 INT: mux IMUX_G2_DATA[6] bit 7 INT: mux IMUX_G2_DATA[6] bit 4 INT: mux IMUX_G2_DATA[6] bit 0 INT: mux IMUX_G2_DATA[6] bit 2 INT: mux DBL_E0[6] bit 0 INT: mux DBL_W0[6] bit 5 INT: mux DBL_W0[6] bit 3 INT: mux DBL_W0[6] bit 0 INT: mux HEX_W0[6] bit 1 INT: mux HEX_W0[6] bit 3 INT: mux HEX_W0[6] bit 4 INT: mux HEX_E0[6] bit 4
B53 - - - - INT: mux IMUX_CLK[2] bit 6 INT: mux IMUX_CLK[2] bit 8 INT: mux OMUX[10] bit 4 INT: mux OMUX[11] bit 4 INT: mux IMUX_G2_DATA[7] bit 9 INT: mux IMUX_G2_DATA[7] bit 10 INT: mux IMUX_G2_DATA[7] bit 6 INT: mux IMUX_G2_DATA[7] bit 5 INT: mux IMUX_G2_DATA[7] bit 1 INT: mux IMUX_G2_DATA[7] bit 3 INT: mux DBL_W0[6] bit 4 INT: mux DBL_E0[6] bit 3 INT: mux DBL_W0[6] bit 2 INT: mux DBL_W0[6] bit 1 INT: mux HEX_E0[6] bit 2 INT: mux HEX_E0[6] bit 0 INT: mux HEX_W0[6] bit 5 INT: mux LV[18] bit 5
B52 - - - - INT: invert IMUX_CLK_OPTINV[2] ← IMUX_CLK[2] INT: mux IMUX_CLK[3] bit 5 INT: mux OMUX[11] bit 5 INT: mux OMUX[10] bit 7 INT: mux IMUX_G2_DATA[6] bit 9 INT: mux IMUX_G2_DATA[6] bit 10 INT: mux IMUX_G2_DATA[6] bit 6 INT: mux IMUX_G2_DATA[6] bit 5 INT: mux IMUX_G2_DATA[6] bit 1 INT: mux IMUX_G2_DATA[6] bit 3 INT: mux DBL_W0[6] bit 6 INT: mux DBL_E0[6] bit 2 INT: mux DBL_E0[6] bit 4 INT: mux DBL_E0[6] bit 6 INT: mux HEX_W0[6] bit 2 INT: mux HEX_W0[6] bit 0 INT: mux HEX_W0[6] bit 6 INT: mux HEX_E0[6] bit 6
B51 - - - - INT: mux IMUX_CLK[2] bit 5 INT: mux IMUX_CLK[2] bit 7 INT: mux OMUX[10] bit 8 INT: mux OMUX[10] bit 6 - - - - - - INT: mux DBL_S0[6] bit 3 INT: mux DBL_N0[6] bit 1 INT: mux DBL_S0[6] bit 4 INT: mux DBL_S0[6] bit 7 INT: mux HEX_S0[6] bit 0 INT: mux HEX_S0[6] bit 3 INT: mux HEX_S0[6] bit 4 INT: mux LH[0] bit 0
B50 - - - - INT: mux IMUX_CLK[1] bit 5 INT: mux IMUX_CLK[1] bit 7 INT: mux OMUX[10] bit 5 INT: mux OMUX[10] bit 9 INT: mux IMUX_G2_DATA[5] bit 9 INT: mux IMUX_G2_DATA[5] bit 10 INT: mux IMUX_G2_DATA[5] bit 6 INT: mux IMUX_G2_DATA[5] bit 5 INT: mux IMUX_G2_DATA[5] bit 1 INT: mux IMUX_G2_DATA[5] bit 3 INT: mux DBL_S0[6] bit 0 INT: mux DBL_N0[6] bit 0 INT: mux DBL_N0[6] bit 7 INT: mux DBL_N0[6] bit 4 INT: mux HEX_N0[6] bit 0 INT: mux HEX_N0[6] bit 2 INT: mux HEX_N0[6] bit 4 INT: mux HEX_S0[6] bit 5
B49 - - - - INT: invert IMUX_CLK_OPTINV[1] ← IMUX_CLK[1] INT: mux IMUX_CLK[0] bit 5 INT: mux OMUX[8] bit 0 INT: mux OMUX[9] bit 9 INT: mux IMUX_G2_DATA[5] bit 8 INT: mux IMUX_G2_DATA[5] bit 11 - - - - INT: mux DBL_N0[6] bit 3 INT: mux DBL_S0[6] bit 1 INT: mux DBL_N0[6] bit 6 INT: mux DBL_N0[6] bit 5 INT: mux HEX_S0[6] bit 2 INT: mux HEX_S0[6] bit 1 INT: mux HEX_N0[6] bit 5 INT: mux LH[0] bit 1
B48 - - - - INT: mux IMUX_CLK[1] bit 6 INT: mux IMUX_CLK[1] bit 8 INT: mux OMUX[9] bit 8 INT: mux OMUX[9] bit 6 - - INT: mux IMUX_G2_DATA[5] bit 7 INT: mux IMUX_G2_DATA[5] bit 4 INT: mux IMUX_G2_DATA[5] bit 0 INT: mux IMUX_G2_DATA[5] bit 2 INT: mux DBL_N0[6] bit 2 INT: mux DBL_S0[6] bit 2 INT: mux DBL_S0[6] bit 5 INT: mux DBL_S0[6] bit 6 INT: mux HEX_N0[6] bit 3 INT: mux HEX_N0[6] bit 1 INT: mux HEX_N0[6] bit 6 INT: mux HEX_S0[6] bit 6
B47 - - - - INT: mux IMUX_CLK[0] bit 4 INT: mux IMUX_CLK[1] bit 9 INT: mux OMUX[9] bit 0 INT: mux OMUX[9] bit 7 INT: mux IMUX_IOI_ICE[1] bit 8 INT: mux IMUX_IOI_ICE[1] bit 11 INT: mux IMUX_IOI_ICE[0] bit 7 INT: mux IMUX_IOI_ICE[0] bit 2 INT: mux IMUX_IOI_ICE[0] bit 5 INT: mux IMUX_IOI_ICE[0] bit 1 INT: mux DBL_E0[5] bit 2 INT: mux DBL_W0[5] bit 3 INT: mux DBL_E0[5] bit 4 INT: mux DBL_E0[5] bit 7 INT: mux HEX_W0[5] bit 1 INT: mux HEX_W0[5] bit 3 INT: mux HEX_W0[5] bit 5 INT: mux LH[0] bit 2
B46 - - - - INT: mux IMUX_CLK[1] bit 4 INT: mux IMUX_CLK[1] bit 2 INT: mux OMUX[8] bit 1 INT: mux OMUX[9] bit 1 INT: mux IMUX_IOI_ICE[0] bit 8 INT: mux IMUX_IOI_ICE[0] bit 11 INT: mux IMUX_IOI_ICE[1] bit 7 INT: mux IMUX_IOI_ICE[1] bit 2 INT: mux IMUX_IOI_ICE[1] bit 5 INT: mux IMUX_IOI_ICE[1] bit 1 INT: mux DBL_E0[5] bit 0 INT: mux DBL_W0[5] bit 0 INT: mux DBL_W0[5] bit 7 INT: mux DBL_W0[5] bit 5 INT: mux HEX_E0[5] bit 0 INT: mux HEX_E0[5] bit 3 INT: mux HEX_E0[5] bit 4 INT: mux HEX_W0[5] bit 4
B45 - - - - INT: mux IMUX_CLK[0] bit 1 INT: mux IMUX_CLK[0] bit 2 INT: mux OMUX[9] bit 3 INT: mux OMUX[8] bit 3 INT: mux IMUX_IOI_ICE[0] bit 9 INT: mux IMUX_IOI_ICE[0] bit 10 INT: mux IMUX_IOI_ICE[0] bit 4 INT: mux IMUX_IOI_ICE[0] bit 3 INT: mux IMUX_IOI_ICE[0] bit 0 INT: mux IMUX_IOI_ICE[0] bit 6 INT: mux DBL_W0[5] bit 2 INT: mux DBL_E0[5] bit 3 INT: mux DBL_W0[5] bit 6 INT: mux DBL_W0[5] bit 4 INT: mux HEX_W0[5] bit 2 INT: mux HEX_W0[5] bit 0 INT: mux HEX_E0[5] bit 5 INT: mux LH[12] bit 1
B44 - - - - INT: mux IMUX_CLK[1] bit 3 INT: mux IMUX_CLK[1] bit 1 INT: mux OMUX[9] bit 2 INT: mux OMUX[8] bit 2 INT: mux IMUX_IOI_ICE[1] bit 9 INT: mux IMUX_IOI_ICE[1] bit 10 INT: mux IMUX_IOI_ICE[1] bit 4 INT: mux IMUX_IOI_ICE[1] bit 3 INT: mux IMUX_IOI_ICE[1] bit 0 INT: mux IMUX_IOI_ICE[1] bit 6 INT: mux DBL_W0[5] bit 1 INT: mux DBL_E0[5] bit 1 INT: mux DBL_E0[5] bit 5 INT: mux DBL_E0[5] bit 6 INT: mux HEX_E0[5] bit 2 INT: mux HEX_E0[5] bit 1 INT: mux HEX_E0[5] bit 6 INT: mux HEX_W0[5] bit 6
B43 - - - - INT: mux IMUX_CLK[0] bit 3 INT: mux IMUX_CLK[0] bit 0 INT: mux OMUX[8] bit 4 INT: mux OMUX[9] bit 4 INT: mux IMUX_IOI_ICE[3] bit 9 INT: mux IMUX_IOI_ICE[3] bit 10 INT: mux IMUX_IOI_ICE[3] bit 4 INT: mux IMUX_IOI_ICE[3] bit 3 INT: mux IMUX_IOI_ICE[3] bit 0 INT: mux IMUX_IOI_ICE[3] bit 6 INT: mux DBL_S0[5] bit 3 INT: mux DBL_N0[5] bit 1 INT: mux DBL_S0[5] bit 4 INT: mux DBL_S0[5] bit 7 INT: mux HEX_N0[5] bit 1 INT: mux HEX_N0[5] bit 3 INT: mux HEX_N0[5] bit 5 INT: mux LH[12] bit 0
B42 - - - - INT: mux IMUX_CLK[0] bit 6 INT: mux IMUX_CLK[0] bit 8 INT: mux OMUX[9] bit 5 INT: mux OMUX[8] bit 7 INT: mux IMUX_IOI_ICE[2] bit 9 INT: mux IMUX_IOI_ICE[2] bit 10 INT: mux IMUX_IOI_ICE[2] bit 4 INT: mux IMUX_IOI_ICE[2] bit 3 INT: mux IMUX_IOI_ICE[2] bit 0 INT: mux IMUX_IOI_ICE[2] bit 6 INT: mux DBL_S0[5] bit 0 INT: mux DBL_N0[5] bit 0 INT: mux DBL_N0[5] bit 7 INT: mux DBL_N0[5] bit 5 INT: mux HEX_S0[5] bit 0 INT: mux HEX_S0[5] bit 2 INT: mux HEX_S0[5] bit 4 INT: mux HEX_N0[5] bit 4
B41 - - - - INT: invert IMUX_CLK_OPTINV[0] ← IMUX_CLK[0] INT: mux IMUX_CLK[0] bit 9 INT: mux OMUX[8] bit 8 INT: mux OMUX[8] bit 6 INT: mux IMUX_IOI_ICE[2] bit 8 INT: mux IMUX_IOI_ICE[2] bit 11 INT: mux IMUX_IOI_ICE[3] bit 7 INT: mux IMUX_IOI_ICE[3] bit 2 INT: mux IMUX_IOI_ICE[3] bit 5 INT: mux IMUX_IOI_ICE[3] bit 1 INT: mux DBL_N0[5] bit 3 INT: mux DBL_S0[5] bit 1 INT: mux DBL_N0[5] bit 6 INT: mux DBL_N0[5] bit 4 INT: mux HEX_N0[5] bit 2 INT: mux HEX_N0[5] bit 0 INT: mux HEX_S0[5] bit 5 INT: mux LH[12] bit 2
B40 - - - - INT: mux IMUX_CLK[1] bit 0 INT: mux IMUX_CLK[0] bit 7 INT: mux OMUX[8] bit 5 INT: mux OMUX[8] bit 9 INT: mux IMUX_IOI_ICE[3] bit 8 INT: mux IMUX_IOI_ICE[3] bit 11 INT: mux IMUX_IOI_ICE[2] bit 7 INT: mux IMUX_IOI_ICE[2] bit 2 INT: mux IMUX_IOI_ICE[2] bit 5 INT: mux IMUX_IOI_ICE[2] bit 1 INT: mux DBL_N0[5] bit 2 INT: mux DBL_S0[5] bit 2 INT: mux DBL_S0[5] bit 5 INT: mux DBL_S0[5] bit 6 INT: mux HEX_S0[5] bit 3 INT: mux HEX_S0[5] bit 1 INT: mux HEX_S0[5] bit 6 INT: mux HEX_N0[5] bit 6
B39 - - - - INT: mux IMUX_IOI_ICLK[2] bit 0 INT: mux IMUX_IOI_ICLK[3] bit 7 INT: mux OMUX[6] bit 0 INT: mux OMUX[7] bit 9 INT: mux IMUX_IOI_TS2[3] bit 8 INT: mux IMUX_IOI_TS2[3] bit 11 INT: mux IMUX_IOI_TS2[2] bit 7 INT: mux IMUX_IOI_TS2[2] bit 3 INT: mux IMUX_IOI_TS2[2] bit 6 INT: mux IMUX_IOI_TS2[2] bit 1 INT: mux DBL_E0[4] bit 2 INT: mux DBL_W0[4] bit 3 INT: mux DBL_E0[4] bit 5 INT: mux DBL_E0[4] bit 7 INT: mux HEX_E0[4] bit 1 INT: mux HEX_E0[4] bit 3 INT: mux HEX_E0[4] bit 5 INT: mux LH[18] bit 2
B38 - - - - - INT: mux IMUX_IOI_ICLK[3] bit 9 INT: mux OMUX[7] bit 8 INT: mux OMUX[7] bit 6 INT: mux IMUX_IOI_TS2[2] bit 8 INT: mux IMUX_IOI_TS2[2] bit 11 INT: mux IMUX_IOI_TS2[3] bit 7 INT: mux IMUX_IOI_TS2[3] bit 3 INT: mux IMUX_IOI_TS2[3] bit 6 INT: mux IMUX_IOI_TS2[3] bit 1 INT: mux DBL_E0[4] bit 0 INT: mux DBL_W0[4] bit 0 INT: mux DBL_W0[4] bit 7 INT: mux DBL_W0[4] bit 5 INT: mux HEX_W0[4] bit 1 INT: mux HEX_W0[4] bit 3 INT: mux HEX_W0[4] bit 5 INT: mux HEX_E0[4] bit 4
B37 - - - - INT: mux IMUX_IOI_ICLK[3] bit 6 INT: mux IMUX_IOI_ICLK[3] bit 8 INT: mux OMUX[7] bit 0 INT: mux OMUX[7] bit 7 INT: mux IMUX_IOI_TS2[2] bit 9 INT: mux IMUX_IOI_TS2[2] bit 10 INT: mux IMUX_IOI_TS2[2] bit 4 INT: mux IMUX_IOI_TS2[2] bit 2 INT: mux IMUX_IOI_TS2[2] bit 0 INT: mux IMUX_IOI_TS2[2] bit 5 INT: mux DBL_W0[4] bit 2 INT: mux DBL_E0[4] bit 3 INT: mux DBL_W0[4] bit 6 INT: mux DBL_W0[4] bit 4 INT: mux HEX_E0[4] bit 2 INT: mux HEX_E0[4] bit 0 INT: mux HEX_W0[4] bit 4 INT: mux LH[18] bit 1
B36 - - - - INT: mux IMUX_IOI_ICLK[3] bit 3 INT: mux IMUX_IOI_ICLK[3] bit 0 INT: mux OMUX[6] bit 1 INT: mux OMUX[7] bit 1 INT: mux IMUX_IOI_TS2[3] bit 9 INT: mux IMUX_IOI_TS2[3] bit 10 INT: mux IMUX_IOI_TS2[3] bit 4 INT: mux IMUX_IOI_TS2[3] bit 2 INT: mux IMUX_IOI_TS2[3] bit 0 INT: mux IMUX_IOI_TS2[3] bit 5 INT: mux DBL_W0[4] bit 1 INT: mux DBL_E0[4] bit 1 INT: mux DBL_E0[4] bit 4 INT: mux DBL_E0[4] bit 6 INT: mux HEX_W0[4] bit 2 INT: mux HEX_W0[4] bit 0 INT: mux HEX_W0[4] bit 6 INT: mux HEX_E0[4] bit 6
B35 - - - - INT: mux IMUX_IOI_ICLK[2] bit 3 INT: mux IMUX_IOI_ICLK[2] bit 1 INT: mux OMUX[7] bit 3 INT: mux OMUX[6] bit 3 INT: mux IMUX_IOI_TS2[1] bit 9 INT: mux IMUX_IOI_TS2[1] bit 10 INT: mux IMUX_IOI_TS2[1] bit 4 INT: mux IMUX_IOI_TS2[1] bit 2 INT: mux IMUX_IOI_TS2[1] bit 0 INT: mux IMUX_IOI_TS2[1] bit 5 INT: mux DBL_S0[4] bit 3 INT: mux DBL_N0[4] bit 1 INT: mux DBL_S0[4] bit 4 INT: mux DBL_S0[4] bit 7 INT: mux HEX_S0[4] bit 0 INT: mux HEX_S0[4] bit 3 INT: mux HEX_S0[4] bit 4 INT: mux LH[18] bit 0
B34 - - - - INT: mux IMUX_IOI_ICLK[3] bit 1 INT: mux IMUX_IOI_ICLK[3] bit 2 INT: mux OMUX[7] bit 2 INT: mux OMUX[6] bit 2 INT: mux IMUX_IOI_TS2[0] bit 9 INT: mux IMUX_IOI_TS2[0] bit 10 INT: mux IMUX_IOI_TS2[0] bit 4 INT: mux IMUX_IOI_TS2[0] bit 2 INT: mux IMUX_IOI_TS2[0] bit 0 INT: mux IMUX_IOI_TS2[0] bit 5 INT: mux DBL_S0[4] bit 0 INT: mux DBL_N0[4] bit 0 INT: mux DBL_N0[4] bit 7 INT: mux DBL_N0[4] bit 4 INT: mux HEX_N0[4] bit 0 INT: mux HEX_N0[4] bit 2 INT: mux HEX_N0[4] bit 4 INT: mux HEX_S0[4] bit 5
B33 - - - - INT: mux IMUX_IOI_ICLK[2] bit 4 INT: mux IMUX_IOI_ICLK[2] bit 2 INT: mux OMUX[6] bit 4 INT: mux OMUX[7] bit 4 INT: mux IMUX_IOI_TS2[0] bit 8 INT: mux IMUX_IOI_TS2[0] bit 11 INT: mux IMUX_IOI_TS2[1] bit 7 INT: mux IMUX_IOI_TS2[1] bit 3 INT: mux IMUX_IOI_TS2[1] bit 6 INT: mux IMUX_IOI_TS2[1] bit 1 INT: mux DBL_N0[4] bit 3 INT: mux DBL_S0[4] bit 1 INT: mux DBL_N0[4] bit 6 INT: mux DBL_N0[4] bit 5 INT: mux HEX_S0[4] bit 2 INT: mux HEX_S0[4] bit 1 INT: mux HEX_N0[4] bit 5 INT: mux LH[6] bit 1
B32 - - - - INT: mux IMUX_IOI_ICLK[3] bit 4 INT: mux IMUX_IOI_ICLK[2] bit 9 INT: mux OMUX[7] bit 5 INT: mux OMUX[6] bit 7 INT: mux IMUX_IOI_TS2[1] bit 8 INT: mux IMUX_IOI_TS2[1] bit 11 INT: mux IMUX_IOI_TS2[0] bit 7 INT: mux IMUX_IOI_TS2[0] bit 3 INT: mux IMUX_IOI_TS2[0] bit 6 INT: mux IMUX_IOI_TS2[0] bit 1 INT: mux DBL_N0[4] bit 2 INT: mux DBL_S0[4] bit 2 INT: mux DBL_S0[4] bit 5 INT: mux DBL_S0[4] bit 6 INT: mux HEX_N0[4] bit 3 INT: mux HEX_N0[4] bit 1 INT: mux HEX_N0[4] bit 6 INT: mux HEX_S0[4] bit 6
B31 - - - - INT: mux IMUX_IOI_ICLK[2] bit 6 INT: mux IMUX_IOI_ICLK[2] bit 8 INT: mux OMUX[6] bit 8 INT: mux OMUX[6] bit 6 - - INT: mux IMUX_G1_DATA[5] bit 7 INT: mux IMUX_G1_DATA[5] bit 5 INT: mux IMUX_G1_DATA[5] bit 1 INT: mux IMUX_G1_DATA[5] bit 2 INT: mux DBL_E0[3] bit 2 INT: mux DBL_W0[3] bit 3 INT: mux DBL_E0[3] bit 4 INT: mux DBL_E0[3] bit 7 INT: mux HEX_W0[3] bit 1 INT: mux HEX_W0[3] bit 3 INT: mux HEX_W0[3] bit 5 INT: mux LH[6] bit 2
B30 - - - - - INT: mux IMUX_IOI_ICLK[3] bit 5 INT: mux OMUX[6] bit 5 INT: mux OMUX[6] bit 9 INT: mux IMUX_G1_DATA[5] bit 9 INT: mux IMUX_G1_DATA[5] bit 11 - - - - INT: mux DBL_E0[3] bit 0 INT: mux DBL_W0[3] bit 0 INT: mux DBL_W0[3] bit 7 INT: mux DBL_W0[3] bit 5 INT: mux HEX_E0[3] bit 0 INT: mux HEX_E0[3] bit 3 INT: mux HEX_E0[3] bit 4 INT: mux HEX_W0[3] bit 4
B29 - - - - INT: mux IMUX_IOI_ICLK[2] bit 5 INT: mux IMUX_IOI_ICLK[2] bit 7 INT: mux OMUX[4] bit 0 INT: mux OMUX[5] bit 9 INT: mux IMUX_G1_DATA[5] bit 8 INT: mux IMUX_G1_DATA[5] bit 10 INT: mux IMUX_G1_DATA[5] bit 6 INT: mux IMUX_G1_DATA[5] bit 4 INT: mux IMUX_G1_DATA[5] bit 0 INT: mux IMUX_G1_DATA[5] bit 3 INT: mux DBL_W0[3] bit 2 INT: mux DBL_E0[3] bit 3 INT: mux DBL_W0[3] bit 6 INT: mux DBL_W0[3] bit 4 INT: mux HEX_W0[3] bit 2 INT: mux HEX_W0[3] bit 0 INT: mux HEX_E0[3] bit 5 INT: mux LH[6] bit 0
B28 - - - - INT: mux IMUX_IOI_ICLK[1] bit 5 INT: mux IMUX_IOI_ICLK[1] bit 7 INT: mux OMUX[5] bit 8 INT: mux OMUX[5] bit 6 - - - - - - INT: mux DBL_W0[3] bit 1 INT: mux DBL_E0[3] bit 1 INT: mux DBL_E0[3] bit 5 INT: mux DBL_E0[3] bit 6 INT: mux HEX_E0[3] bit 2 INT: mux HEX_E0[3] bit 1 INT: mux HEX_E0[3] bit 6 INT: mux HEX_W0[3] bit 6
B27 - - - - - INT: mux IMUX_IOI_ICLK[0] bit 5 INT: mux OMUX[5] bit 0 INT: mux OMUX[5] bit 7 INT: mux IMUX_G1_DATA[6] bit 8 INT: mux IMUX_G1_DATA[6] bit 10 INT: mux IMUX_G1_DATA[6] bit 6 INT: mux IMUX_G1_DATA[6] bit 4 INT: mux IMUX_G1_DATA[6] bit 0 INT: mux IMUX_G1_DATA[6] bit 3 INT: mux DBL_S0[3] bit 3 INT: mux DBL_N0[3] bit 1 INT: mux DBL_S0[3] bit 5 INT: mux DBL_S0[3] bit 7 INT: mux HEX_N0[3] bit 0 INT: mux HEX_N0[3] bit 3 INT: mux HEX_N0[3] bit 4 INT: mux LV[12] bit 4
B26 - - - - INT: mux IMUX_IOI_ICLK[1] bit 6 INT: mux IMUX_IOI_ICLK[1] bit 8 INT: mux OMUX[4] bit 1 INT: mux OMUX[5] bit 1 INT: mux IMUX_G1_DATA[7] bit 8 INT: mux IMUX_G1_DATA[7] bit 10 INT: mux IMUX_G1_DATA[7] bit 6 INT: mux IMUX_G1_DATA[7] bit 4 INT: mux IMUX_G1_DATA[7] bit 0 INT: mux IMUX_G1_DATA[7] bit 3 INT: mux DBL_S0[3] bit 0 INT: mux DBL_N0[3] bit 0 INT: mux DBL_N0[3] bit 7 INT: mux DBL_N0[3] bit 4 INT: mux HEX_S0[3] bit 1 INT: mux HEX_S0[3] bit 2 INT: mux HEX_S0[3] bit 5 INT: mux HEX_N0[3] bit 5
B25 - - - - INT: mux IMUX_IOI_ICLK[0] bit 4 INT: mux IMUX_IOI_ICLK[1] bit 9 INT: mux OMUX[5] bit 3 INT: mux OMUX[4] bit 3 INT: mux IMUX_G1_DATA[7] bit 9 INT: mux IMUX_G1_DATA[7] bit 11 INT: mux IMUX_G1_DATA[6] bit 7 INT: mux IMUX_G1_DATA[6] bit 5 INT: mux IMUX_G1_DATA[6] bit 1 INT: mux IMUX_G1_DATA[6] bit 2 INT: mux DBL_N0[3] bit 3 INT: mux DBL_S0[3] bit 1 INT: mux DBL_N0[3] bit 6 INT: mux DBL_N0[3] bit 5 INT: mux HEX_N0[3] bit 2 INT: mux HEX_N0[3] bit 1 INT: mux HEX_S0[3] bit 4 INT: mux LV[0] bit 3
B24 - - - - INT: mux IMUX_IOI_ICLK[1] bit 4 INT: mux IMUX_IOI_ICLK[1] bit 2 INT: mux OMUX[5] bit 2 INT: mux OMUX[4] bit 2 INT: mux IMUX_G1_DATA[6] bit 9 INT: mux IMUX_G1_DATA[6] bit 11 INT: mux IMUX_G1_DATA[7] bit 7 INT: mux IMUX_G1_DATA[7] bit 5 INT: mux IMUX_G1_DATA[7] bit 1 INT: mux IMUX_G1_DATA[7] bit 2 INT: mux DBL_N0[3] bit 2 INT: mux DBL_S0[3] bit 2 INT: mux DBL_S0[3] bit 4 INT: mux DBL_S0[3] bit 6 INT: mux HEX_S0[3] bit 3 INT: mux HEX_S0[3] bit 0 INT: mux HEX_S0[3] bit 6 INT: mux HEX_N0[3] bit 6
B23 - - - - INT: mux IMUX_IOI_ICLK[0] bit 1 INT: mux IMUX_IOI_ICLK[0] bit 2 INT: mux OMUX[4] bit 4 INT: mux OMUX[5] bit 4 INT: mux IMUX_G1_FAN[0] bit 9 INT: mux IMUX_G1_FAN[0] bit 11 INT: mux IMUX_G1_FAN[1] bit 7 INT: mux IMUX_G1_FAN[1] bit 5 INT: mux IMUX_G1_FAN[1] bit 1 INT: mux IMUX_G1_FAN[1] bit 2 INT: mux DBL_E0[2] bit 4 INT: mux DBL_W0[2] bit 7 INT: mux DBL_E0[2] bit 1 INT: mux DBL_E0[2] bit 3 INT: mux HEX_E0[2] bit 1 INT: mux HEX_E0[2] bit 3 INT: mux HEX_E0[2] bit 5 INT: mux LV[12] bit 3
B22 - - - - INT: mux IMUX_IOI_ICLK[1] bit 3 INT: mux IMUX_IOI_ICLK[1] bit 1 INT: mux OMUX[5] bit 5 INT: mux OMUX[4] bit 7 INT: mux IMUX_G1_FAN[1] bit 9 INT: mux IMUX_G1_FAN[1] bit 11 INT: mux IMUX_G1_FAN[0] bit 7 INT: mux IMUX_G1_FAN[0] bit 5 INT: mux IMUX_G1_FAN[0] bit 1 INT: mux IMUX_G1_FAN[0] bit 2 INT: mux DBL_E0[2] bit 5 INT: mux DBL_W0[2] bit 5 INT: mux DBL_W0[2] bit 3 INT: mux DBL_W0[2] bit 1 INT: mux HEX_W0[2] bit 1 INT: mux HEX_W0[2] bit 3 INT: mux HEX_W0[2] bit 6 INT: mux HEX_E0[2] bit 6
B21 - - - - INT: mux IMUX_IOI_ICLK[0] bit 3 INT: mux IMUX_IOI_ICLK[0] bit 0 INT: mux OMUX[4] bit 8 INT: mux OMUX[4] bit 6 INT: mux IMUX_G1_FAN[1] bit 8 INT: mux IMUX_G1_FAN[1] bit 10 INT: mux IMUX_G1_FAN[1] bit 6 INT: mux IMUX_G1_FAN[1] bit 4 INT: mux IMUX_G1_FAN[1] bit 0 INT: mux IMUX_G1_FAN[1] bit 3 INT: mux DBL_W0[2] bit 4 INT: mux DBL_E0[2] bit 7 INT: mux DBL_W0[2] bit 2 INT: mux DBL_W0[2] bit 0 INT: mux HEX_E0[2] bit 2 INT: mux HEX_E0[2] bit 0 INT: mux HEX_W0[2] bit 5 INT: mux LV[0] bit 2
B20 - - - - INT: mux IMUX_IOI_ICLK[0] bit 6 INT: mux IMUX_IOI_ICLK[0] bit 8 INT: mux OMUX[4] bit 5 INT: mux OMUX[4] bit 9 INT: mux IMUX_G1_FAN[0] bit 8 INT: mux IMUX_G1_FAN[0] bit 10 INT: mux IMUX_G1_FAN[0] bit 6 INT: mux IMUX_G1_FAN[0] bit 4 INT: mux IMUX_G1_FAN[0] bit 0 INT: mux IMUX_G1_FAN[0] bit 3 INT: mux DBL_W0[2] bit 6 INT: mux DBL_E0[2] bit 6 INT: mux DBL_E0[2] bit 0 INT: mux DBL_E0[2] bit 2 INT: mux HEX_W0[2] bit 2 INT: mux HEX_W0[2] bit 0 INT: mux HEX_W0[2] bit 4 INT: mux HEX_E0[2] bit 4
B19 - - - - - INT: mux IMUX_IOI_ICLK[0] bit 9 INT: mux OMUX[2] bit 0 INT: mux OMUX[3] bit 9 INT: mux IMUX_G0_FAN[0] bit 9 INT: mux IMUX_G0_FAN[0] bit 10 INT: mux IMUX_G0_FAN[0] bit 6 INT: mux IMUX_G0_FAN[0] bit 5 INT: mux IMUX_G0_FAN[0] bit 2 INT: mux IMUX_G0_FAN[0] bit 1 INT: mux DBL_S0[2] bit 4 INT: mux DBL_N0[2] bit 6 INT: mux DBL_S0[2] bit 0 INT: mux DBL_S0[2] bit 3 INT: mux HEX_S0[2] bit 0 INT: mux HEX_S0[2] bit 3 INT: mux HEX_S0[2] bit 5 INT: mux LV[0] bit 4
B18 - - - - INT: mux IMUX_IOI_ICLK[1] bit 0 INT: mux IMUX_IOI_ICLK[0] bit 7 INT: mux OMUX[3] bit 8 INT: mux OMUX[3] bit 6 INT: mux IMUX_G0_FAN[1] bit 9 INT: mux IMUX_G0_FAN[1] bit 10 INT: mux IMUX_G0_FAN[1] bit 6 INT: mux IMUX_G0_FAN[1] bit 5 INT: mux IMUX_G0_FAN[1] bit 2 INT: mux IMUX_G0_FAN[1] bit 1 INT: mux DBL_S0[2] bit 5 INT: mux DBL_N0[2] bit 5 INT: mux DBL_N0[2] bit 3 INT: mux DBL_N0[2] bit 0 INT: mux HEX_N0[2] bit 1 INT: mux HEX_N0[2] bit 2 INT: mux HEX_N0[2] bit 4 INT: mux HEX_S0[2] bit 4
B17 - - - - INT: mux IMUX_SR[3] bit 5 INT: mux IMUX_SR[1] bit 1 INT: mux OMUX[3] bit 0 INT: mux OMUX[3] bit 7 INT: mux IMUX_G0_FAN[1] bit 8 INT: mux IMUX_G0_FAN[1] bit 11 INT: mux IMUX_G0_FAN[0] bit 7 INT: mux IMUX_G0_FAN[0] bit 4 INT: mux IMUX_G0_FAN[0] bit 0 INT: mux IMUX_G0_FAN[0] bit 3 INT: mux DBL_N0[2] bit 4 INT: mux DBL_S0[2] bit 6 INT: mux DBL_N0[2] bit 2 INT: mux DBL_N0[2] bit 1 INT: mux HEX_S0[2] bit 2 INT: mux HEX_S0[2] bit 1 INT: mux HEX_N0[2] bit 5 INT: mux LV[12] bit 2
B16 - - - - INT: !invert IMUX_SR_OPTINV[1] ← IMUX_SR[1] INT: mux IMUX_SR[1] bit 3 INT: mux OMUX[2] bit 1 INT: mux OMUX[3] bit 1 INT: mux IMUX_G0_FAN[0] bit 8 INT: mux IMUX_G0_FAN[0] bit 11 INT: mux IMUX_G0_FAN[1] bit 7 INT: mux IMUX_G0_FAN[1] bit 4 INT: mux IMUX_G0_FAN[1] bit 0 INT: mux IMUX_G0_FAN[1] bit 3 INT: mux DBL_N0[2] bit 7 INT: mux DBL_S0[2] bit 7 INT: mux DBL_S0[2] bit 1 INT: mux DBL_S0[2] bit 2 INT: mux HEX_N0[2] bit 3 INT: mux HEX_N0[2] bit 0 INT: mux HEX_N0[2] bit 6 INT: mux HEX_S0[2] bit 6
B15 - - - - INT: mux IMUX_SR[1] bit 0 INT: mux IMUX_SR[1] bit 2 INT: mux OMUX[3] bit 3 INT: mux OMUX[2] bit 3 INT: mux IMUX_G0_DATA[6] bit 8 INT: mux IMUX_G0_DATA[6] bit 11 INT: mux IMUX_G0_DATA[7] bit 7 INT: mux IMUX_G0_DATA[7] bit 4 INT: mux IMUX_G0_DATA[7] bit 0 INT: mux IMUX_G0_DATA[7] bit 3 INT: mux DBL_E0[1] bit 2 INT: mux DBL_W0[1] bit 3 INT: mux DBL_E0[1] bit 4 INT: mux DBL_E0[1] bit 7 INT: mux HEX_W0[1] bit 1 INT: mux HEX_W0[1] bit 2 INT: mux HEX_W0[1] bit 5 INT: mux LV[12] bit 0
B14 - - - - INT: mux IMUX_SR[1] bit 4 INT: mux IMUX_SR[1] bit 5 INT: mux OMUX[3] bit 2 INT: mux OMUX[2] bit 2 INT: mux IMUX_G0_DATA[7] bit 8 INT: mux IMUX_G0_DATA[7] bit 11 INT: mux IMUX_G0_DATA[6] bit 7 INT: mux IMUX_G0_DATA[6] bit 4 INT: mux IMUX_G0_DATA[6] bit 0 INT: mux IMUX_G0_DATA[6] bit 3 INT: mux DBL_E0[1] bit 0 INT: mux DBL_W0[1] bit 0 INT: mux DBL_W0[1] bit 6 INT: mux DBL_W0[1] bit 5 INT: mux HEX_E0[1] bit 0 INT: mux HEX_E0[1] bit 3 INT: mux HEX_E0[1] bit 4 INT: mux HEX_W0[1] bit 4
B13 - - - - INT: mux IMUX_SR[3] bit 4 INT: mux IMUX_SR[3] bit 7 INT: mux OMUX[2] bit 4 INT: mux OMUX[3] bit 4 INT: mux IMUX_G0_DATA[7] bit 9 INT: mux IMUX_G0_DATA[7] bit 10 INT: mux IMUX_G0_DATA[7] bit 6 INT: mux IMUX_G0_DATA[7] bit 5 INT: mux IMUX_G0_DATA[7] bit 2 INT: mux IMUX_G0_DATA[7] bit 1 INT: mux DBL_W0[1] bit 2 INT: mux DBL_E0[1] bit 3 INT: mux DBL_W0[1] bit 7 INT: mux DBL_W0[1] bit 4 INT: mux HEX_W0[1] bit 3 INT: mux HEX_W0[1] bit 0 INT: mux HEX_E0[1] bit 5 INT: mux LV[12] bit 6
B12 - - - - INT: mux IMUX_SR[1] bit 7 INT: mux IMUX_SR[1] bit 6 INT: mux OMUX[3] bit 5 INT: mux OMUX[2] bit 7 INT: mux IMUX_G0_DATA[6] bit 9 INT: mux IMUX_G0_DATA[6] bit 10 INT: mux IMUX_G0_DATA[6] bit 6 INT: mux IMUX_G0_DATA[6] bit 5 INT: mux IMUX_G0_DATA[6] bit 2 INT: mux IMUX_G0_DATA[6] bit 1 INT: mux DBL_W0[1] bit 1 INT: mux DBL_E0[1] bit 1 INT: mux DBL_E0[1] bit 5 INT: mux DBL_E0[1] bit 6 INT: mux HEX_E0[1] bit 2 INT: mux HEX_E0[1] bit 1 INT: mux HEX_E0[1] bit 6 INT: mux HEX_W0[1] bit 6
B11 - - - - INT: mux IMUX_SR[3] bit 0 INT: mux IMUX_SR[3] bit 1 INT: mux OMUX[2] bit 8 INT: mux OMUX[2] bit 6 - - - - - - INT: mux DBL_S0[1] bit 3 INT: mux DBL_N0[1] bit 1 INT: mux DBL_S0[1] bit 4 INT: mux DBL_S0[1] bit 7 INT: mux HEX_N0[1] bit 0 INT: mux HEX_N0[1] bit 3 INT: mux HEX_N0[1] bit 4 INT: mux LV[0] bit 1
B10 - - - - INT: !invert IMUX_SR_OPTINV[3] ← IMUX_SR[3] INT: mux IMUX_SR[3] bit 3 INT: mux OMUX[2] bit 5 INT: mux OMUX[2] bit 9 INT: mux IMUX_G0_DATA[5] bit 9 INT: mux IMUX_G0_DATA[5] bit 10 INT: mux IMUX_G0_DATA[5] bit 6 INT: mux IMUX_G0_DATA[5] bit 5 INT: mux IMUX_G0_DATA[5] bit 2 INT: mux IMUX_G0_DATA[5] bit 1 INT: mux DBL_S0[1] bit 0 INT: mux DBL_N0[1] bit 0 INT: mux DBL_N0[1] bit 7 INT: mux DBL_N0[1] bit 4 INT: mux HEX_S0[1] bit 0 INT: mux HEX_S0[1] bit 2 INT: mux HEX_S0[1] bit 4 INT: mux HEX_N0[1] bit 5
B9 - - - - INT: mux IMUX_SR[3] bit 6 INT: mux IMUX_SR[3] bit 2 INT: mux OMUX[0] bit 0 INT: mux OMUX[1] bit 9 INT: mux IMUX_G0_DATA[5] bit 8 INT: mux IMUX_G0_DATA[5] bit 11 - - - - INT: mux DBL_N0[1] bit 3 INT: mux DBL_S0[1] bit 1 INT: mux DBL_N0[1] bit 6 INT: mux DBL_N0[1] bit 5 INT: mux HEX_N0[1] bit 2 INT: mux HEX_N0[1] bit 1 INT: mux HEX_S0[1] bit 5 INT: mux LV[0] bit 5
B8 - - - - INT: mux IMUX_SR[2] bit 5 INT: mux IMUX_SR[2] bit 2 INT: mux OMUX[1] bit 8 INT: mux OMUX[1] bit 6 - - INT: mux IMUX_G0_DATA[5] bit 7 INT: mux IMUX_G0_DATA[5] bit 4 INT: mux IMUX_G0_DATA[5] bit 0 INT: mux IMUX_G0_DATA[5] bit 3 INT: mux DBL_N0[1] bit 2 INT: mux DBL_S0[1] bit 2 INT: mux DBL_S0[1] bit 5 INT: mux DBL_S0[1] bit 6 INT: mux HEX_S0[1] bit 3 INT: mux HEX_S0[1] bit 1 INT: mux HEX_S0[1] bit 6 INT: mux HEX_N0[1] bit 6
B7 - - - - INT: !invert IMUX_SR_OPTINV[2] ← IMUX_SR[2] INT: mux IMUX_SR[2] bit 3 INT: mux OMUX[1] bit 0 INT: mux OMUX[1] bit 7 INT: mux IMUX_IOI_TS1[1] bit 8 INT: mux IMUX_IOI_TS1[1] bit 11 INT: mux IMUX_IOI_TS1[0] bit 7 INT: mux IMUX_IOI_TS1[0] bit 2 INT: mux IMUX_IOI_TS1[0] bit 5 INT: mux IMUX_IOI_TS1[0] bit 1 INT: mux DBL_E0[0] bit 2 INT: mux DBL_W0[0] bit 3 INT: mux DBL_E0[0] bit 4 INT: mux DBL_E0[0] bit 7 INT: mux HEX_E0[0] bit 0 INT: mux HEX_E0[0] bit 3 INT: mux HEX_E0[0] bit 4 INT: mux LV[0] bit 6
B6 - - - - INT: mux IMUX_SR[2] bit 1 INT: mux IMUX_SR[2] bit 0 INT: mux OMUX[0] bit 1 INT: mux OMUX[1] bit 1 INT: mux IMUX_IOI_TS1[0] bit 8 INT: mux IMUX_IOI_TS1[0] bit 11 INT: mux IMUX_IOI_TS1[1] bit 7 INT: mux IMUX_IOI_TS1[1] bit 2 INT: mux IMUX_IOI_TS1[1] bit 5 INT: mux IMUX_IOI_TS1[1] bit 1 INT: mux DBL_E0[0] bit 0 INT: mux DBL_W0[0] bit 0 INT: mux DBL_W0[0] bit 6 INT: mux DBL_W0[0] bit 5 INT: mux HEX_W0[0] bit 1 INT: mux HEX_W0[0] bit 2 INT: mux HEX_W0[0] bit 5 INT: mux HEX_E0[0] bit 5
B5 - - - - INT: mux IMUX_SR[0] bit 4 INT: mux IMUX_SR[0] bit 5 INT: mux OMUX[1] bit 3 INT: mux OMUX[0] bit 3 INT: mux IMUX_IOI_TS1[0] bit 9 INT: mux IMUX_IOI_TS1[0] bit 10 INT: mux IMUX_IOI_TS1[0] bit 4 INT: mux IMUX_IOI_TS1[0] bit 3 INT: mux IMUX_IOI_TS1[0] bit 0 INT: mux IMUX_IOI_TS1[0] bit 6 INT: mux DBL_W0[0] bit 2 INT: mux DBL_E0[0] bit 3 INT: mux DBL_W0[0] bit 7 INT: mux DBL_W0[0] bit 4 INT: mux HEX_E0[0] bit 2 INT: mux HEX_E0[0] bit 1 INT: mux HEX_W0[0] bit 4 INT: mux LV[0] bit 0
B4 - - - - INT: mux IMUX_SR[2] bit 6 INT: mux IMUX_SR[2] bit 4 INT: mux OMUX[1] bit 2 INT: mux OMUX[0] bit 2 INT: mux IMUX_IOI_TS1[1] bit 9 INT: mux IMUX_IOI_TS1[1] bit 10 INT: mux IMUX_IOI_TS1[1] bit 4 INT: mux IMUX_IOI_TS1[1] bit 3 INT: mux IMUX_IOI_TS1[1] bit 0 INT: mux IMUX_IOI_TS1[1] bit 6 INT: mux DBL_W0[0] bit 1 INT: mux DBL_E0[0] bit 1 INT: mux DBL_E0[0] bit 5 INT: mux DBL_E0[0] bit 6 INT: mux HEX_W0[0] bit 3 INT: mux HEX_W0[0] bit 0 INT: mux HEX_W0[0] bit 6 INT: mux HEX_E0[0] bit 6
B3 - - - - INT: mux IMUX_SR[0] bit 6 INT: mux IMUX_SR[0] bit 7 INT: mux OMUX[0] bit 4 INT: mux OMUX[1] bit 4 INT: mux IMUX_IOI_TS1[3] bit 9 INT: mux IMUX_IOI_TS1[3] bit 10 INT: mux IMUX_IOI_TS1[3] bit 4 INT: mux IMUX_IOI_TS1[3] bit 3 INT: mux IMUX_IOI_TS1[3] bit 0 INT: mux IMUX_IOI_TS1[3] bit 6 INT: mux DBL_S0[0] bit 4 INT: mux DBL_N0[0] bit 6 INT: mux DBL_S0[0] bit 1 INT: mux DBL_S0[0] bit 3 INT: mux HEX_S0[0] bit 1 INT: mux HEX_S0[0] bit 3 INT: mux HEX_S0[0] bit 6 INT: mux LV[12] bit 1
B2 - - - - INT: mux IMUX_SR[0] bit 1 INT: mux IMUX_SR[0] bit 2 INT: mux OMUX[1] bit 5 INT: mux OMUX[0] bit 7 INT: mux IMUX_IOI_TS1[2] bit 9 INT: mux IMUX_IOI_TS1[2] bit 10 INT: mux IMUX_IOI_TS1[2] bit 4 INT: mux IMUX_IOI_TS1[2] bit 3 INT: mux IMUX_IOI_TS1[2] bit 0 INT: mux IMUX_IOI_TS1[2] bit 6 INT: mux DBL_S0[0] bit 5 INT: mux DBL_N0[0] bit 5 INT: mux DBL_N0[0] bit 3 INT: mux DBL_N0[0] bit 1 INT: mux HEX_N0[0] bit 1 INT: mux HEX_N0[0] bit 2 INT: mux HEX_N0[0] bit 5 INT: mux HEX_S0[0] bit 5
B1 - - - - INT: !invert IMUX_SR_OPTINV[0] ← IMUX_SR[0] INT: mux IMUX_SR[0] bit 3 INT: mux OMUX[0] bit 8 INT: mux OMUX[0] bit 6 INT: mux IMUX_IOI_TS1[2] bit 8 INT: mux IMUX_IOI_TS1[2] bit 11 INT: mux IMUX_IOI_TS1[3] bit 7 INT: mux IMUX_IOI_TS1[3] bit 2 INT: mux IMUX_IOI_TS1[3] bit 5 INT: mux IMUX_IOI_TS1[3] bit 1 INT: mux DBL_N0[0] bit 4 INT: mux DBL_S0[0] bit 6 INT: mux DBL_N0[0] bit 2 INT: mux DBL_N0[0] bit 0 INT: mux HEX_S0[0] bit 2 INT: mux HEX_S0[0] bit 0 INT: mux HEX_N0[0] bit 6 INT: mux LV[12] bit 5
B0 - - - - INT: mux IMUX_SR[2] bit 7 INT: mux IMUX_SR[0] bit 0 INT: mux OMUX[0] bit 5 INT: mux OMUX[0] bit 9 INT: mux IMUX_IOI_TS1[3] bit 8 INT: mux IMUX_IOI_TS1[3] bit 11 INT: mux IMUX_IOI_TS1[2] bit 7 INT: mux IMUX_IOI_TS1[2] bit 2 INT: mux IMUX_IOI_TS1[2] bit 5 INT: mux IMUX_IOI_TS1[2] bit 1 INT: mux DBL_N0[0] bit 7 INT: mux DBL_S0[0] bit 7 INT: mux DBL_S0[0] bit 0 INT: mux DBL_S0[0] bit 2 INT: mux HEX_N0[0] bit 3 INT: mux HEX_N0[0] bit 0 INT: mux HEX_N0[0] bit 4 INT: mux HEX_S0[0] bit 4

INT_IOI_CLK_S

Used with the IOI_CLK_S tile (Virtex 2 Pro X special IOI tile used for the dedicated reference clock).

Tile INT_IOI_CLK_S

Cells: 1

Switchbox INT

virtex2 INT_IOI_CLK_S switchbox INT programmable inverters
DestinationSourceBit
IMUX_CLK_OPTINV[0]IMUX_CLK[0]MAIN[4][41]
IMUX_CLK_OPTINV[1]IMUX_CLK[1]MAIN[4][49]
IMUX_SR_OPTINV[0]IMUX_SR[0]!MAIN[4][1]
IMUX_SR_OPTINV[2]IMUX_SR[2]!MAIN[4][7]
IMUX_CE_OPTINV[0]IMUX_CE[0]!MAIN[4][63]
IMUX_CE_OPTINV[1]IMUX_CE[1]!MAIN[4][69]
virtex2 INT_IOI_CLK_S switchbox INT muxes OMUX[0]
BitsDestination
MAIN[7][0]MAIN[6][1]MAIN[7][2]MAIN[7][1]MAIN[7][5]MAIN[6][0]MAIN[7][4]MAIN[6][6]MAIN[6][9]OMUX[0]
Source
000000000off
000100001OUT_FAN[0]
000100010OUT_FAN[1]
000100100OUT_FAN[2]
001000100OUT_SEC[9]
010000001OUT_SEC[12]
010000100OUT_SEC[15]
010001000OUT_SEC[17]
100000100OUT_SEC[21]
100010000OUT_SEC[20]
virtex2 INT_IOI_CLK_S switchbox INT muxes OMUX[1]
BitsDestination
MAIN[7][9]MAIN[6][8]MAIN[7][7]MAIN[7][8]MAIN[6][5]MAIN[6][2]MAIN[6][4]MAIN[7][6]MAIN[6][7]OMUX[1]
Source
000000000off
000100001OUT_FAN[0]
000100010OUT_FAN[1]
000100100OUT_FAN[2]
001000100OUT_SEC[9]
010000001OUT_SEC[12]
010000100OUT_SEC[15]
010001000OUT_SEC[17]
100000100OUT_SEC[21]
100010000OUT_SEC[20]
virtex2 INT_IOI_CLK_S switchbox INT muxes OMUX[2]
BitsDestination
MAIN[7][10]MAIN[6][11]MAIN[7][12]MAIN[7][11]MAIN[7][15]MAIN[6][10]MAIN[7][14]MAIN[6][16]MAIN[6][19]OMUX[2]
Source
000000000off
000100001OUT_FAN[0]
000100010OUT_FAN[1]
000100100OUT_FAN[2]
001000100OUT_SEC[9]
010000001OUT_SEC[12]
010000100OUT_SEC[15]
010001000OUT_SEC[17]
100000100OUT_SEC[21]
100010000OUT_SEC[20]
virtex2 INT_IOI_CLK_S switchbox INT muxes OMUX[3]
BitsDestination
MAIN[7][19]MAIN[6][18]MAIN[7][17]MAIN[7][18]MAIN[6][15]MAIN[6][12]MAIN[6][14]MAIN[7][16]MAIN[6][17]OMUX[3]
Source
000000000off
000100001OUT_FAN[0]
000100010OUT_FAN[1]
000100100OUT_FAN[2]
001000100OUT_SEC[9]
010000001OUT_SEC[12]
010000100OUT_SEC[15]
010001000OUT_SEC[17]
100000100OUT_SEC[21]
100010000OUT_SEC[20]
virtex2 INT_IOI_CLK_S switchbox INT muxes OMUX[4]
BitsDestination
MAIN[7][20]MAIN[6][21]MAIN[7][22]MAIN[7][21]MAIN[7][25]MAIN[6][20]MAIN[7][24]MAIN[6][26]MAIN[6][29]OMUX[4]
Source
000000000off
000100001OUT_FAN[0]
000100010OUT_FAN[1]
000100100OUT_FAN[2]
001000100OUT_SEC[9]
010000001OUT_SEC[12]
010000100OUT_SEC[15]
010001000OUT_SEC[17]
100000100OUT_SEC[21]
100010000OUT_SEC[20]
virtex2 INT_IOI_CLK_S switchbox INT muxes OMUX[5]
BitsDestination
MAIN[7][29]MAIN[6][28]MAIN[7][27]MAIN[7][28]MAIN[6][25]MAIN[6][22]MAIN[6][24]MAIN[7][26]MAIN[6][27]OMUX[5]
Source
000000000off
000100001OUT_FAN[0]
000100010OUT_FAN[1]
000100100OUT_FAN[2]
001000100OUT_SEC[9]
010000001OUT_SEC[12]
010000100OUT_SEC[15]
010001000OUT_SEC[17]
100000100OUT_SEC[21]
100010000OUT_SEC[20]
virtex2 INT_IOI_CLK_S switchbox INT muxes OMUX[6]
BitsDestination
MAIN[7][30]MAIN[6][31]MAIN[7][32]MAIN[7][31]MAIN[7][35]MAIN[6][30]MAIN[7][34]MAIN[6][36]MAIN[6][39]OMUX[6]
Source
000000000off
000100001OUT_FAN[0]
000100010OUT_FAN[1]
000100100OUT_FAN[2]
001000100OUT_SEC[9]
010000001OUT_SEC[12]
010000100OUT_SEC[15]
010001000OUT_SEC[17]
100000100OUT_SEC[21]
100010000OUT_SEC[20]
virtex2 INT_IOI_CLK_S switchbox INT muxes OMUX[7]
BitsDestination
MAIN[7][39]MAIN[6][38]MAIN[7][37]MAIN[7][38]MAIN[6][35]MAIN[6][32]MAIN[6][34]MAIN[7][36]MAIN[6][37]OMUX[7]
Source
000000000off
000100001OUT_FAN[0]
000100010OUT_FAN[1]
000100100OUT_FAN[2]
001000100OUT_SEC[9]
010000001OUT_SEC[12]
010000100OUT_SEC[15]
010001000OUT_SEC[17]
100000100OUT_SEC[21]
100010000OUT_SEC[20]
virtex2 INT_IOI_CLK_S switchbox INT muxes OMUX[8]
BitsDestination
MAIN[7][40]MAIN[6][41]MAIN[7][42]MAIN[7][41]MAIN[7][45]MAIN[6][40]MAIN[7][44]MAIN[6][46]MAIN[6][49]OMUX[8]
Source
000000000off
000100001OUT_FAN[0]
000100010OUT_FAN[1]
000100100OUT_FAN[2]
001000100OUT_SEC[9]
010000001OUT_SEC[12]
010000100OUT_SEC[15]
010001000OUT_SEC[17]
100000100OUT_SEC[21]
100010000OUT_SEC[20]
virtex2 INT_IOI_CLK_S switchbox INT muxes OMUX[9]
BitsDestination
MAIN[7][49]MAIN[6][48]MAIN[7][47]MAIN[7][48]MAIN[6][45]MAIN[6][42]MAIN[6][44]MAIN[7][46]MAIN[6][47]OMUX[9]
Source
000000000off
000100001OUT_FAN[0]
000100010OUT_FAN[1]
000100100OUT_FAN[2]
001000100OUT_SEC[9]
010000001OUT_SEC[12]
010000100OUT_SEC[15]
010001000OUT_SEC[17]
100000100OUT_SEC[21]
100010000OUT_SEC[20]
virtex2 INT_IOI_CLK_S switchbox INT muxes OMUX[10]
BitsDestination
MAIN[7][50]MAIN[6][51]MAIN[7][52]MAIN[7][51]MAIN[7][55]MAIN[6][50]MAIN[7][54]MAIN[6][56]MAIN[6][59]OMUX[10]
Source
000000000off
000100001OUT_FAN[0]
000100010OUT_FAN[1]
000100100OUT_FAN[2]
001000100OUT_SEC[9]
010000001OUT_SEC[12]
010000100OUT_SEC[15]
010001000OUT_SEC[17]
100000100OUT_SEC[21]
100010000OUT_SEC[20]
virtex2 INT_IOI_CLK_S switchbox INT muxes OMUX[11]
BitsDestination
MAIN[7][59]MAIN[6][58]MAIN[7][57]MAIN[7][58]MAIN[6][55]MAIN[6][52]MAIN[6][54]MAIN[7][56]MAIN[6][57]OMUX[11]
Source
000000000off
000100001OUT_FAN[0]
000100010OUT_FAN[1]
000100100OUT_FAN[2]
001000100OUT_SEC[9]
010000001OUT_SEC[12]
010000100OUT_SEC[15]
010001000OUT_SEC[17]
100000100OUT_SEC[21]
100010000OUT_SEC[20]
virtex2 INT_IOI_CLK_S switchbox INT muxes OMUX[12]
BitsDestination
MAIN[7][60]MAIN[6][61]MAIN[7][62]MAIN[7][61]MAIN[7][65]MAIN[6][60]MAIN[7][64]MAIN[6][66]MAIN[6][69]OMUX[12]
Source
000000000off
000100001OUT_FAN[0]
000100010OUT_FAN[1]
000100100OUT_FAN[2]
001000100OUT_SEC[9]
010000001OUT_SEC[12]
010000100OUT_SEC[15]
010001000OUT_SEC[17]
100000100OUT_SEC[21]
100010000OUT_SEC[20]
virtex2 INT_IOI_CLK_S switchbox INT muxes OMUX[13]
BitsDestination
MAIN[7][69]MAIN[6][68]MAIN[7][67]MAIN[7][68]MAIN[6][65]MAIN[6][62]MAIN[6][64]MAIN[7][66]MAIN[6][67]OMUX[13]
Source
000000000off
000100001OUT_FAN[0]
000100010OUT_FAN[1]
000100100OUT_FAN[2]
001000100OUT_SEC[9]
010000001OUT_SEC[12]
010000100OUT_SEC[15]
010001000OUT_SEC[17]
100000100OUT_SEC[21]
100010000OUT_SEC[20]
virtex2 INT_IOI_CLK_S switchbox INT muxes OMUX[14]
BitsDestination
MAIN[7][70]MAIN[6][71]MAIN[7][72]MAIN[7][71]MAIN[7][75]MAIN[6][70]MAIN[7][74]MAIN[6][76]MAIN[6][79]OMUX[14]
Source
000000000off
000100001OUT_FAN[0]
000100010OUT_FAN[1]
000100100OUT_FAN[2]
001000100OUT_SEC[9]
010000001OUT_SEC[12]
010000100OUT_SEC[15]
010001000OUT_SEC[17]
100000100OUT_SEC[21]
100010000OUT_SEC[20]
virtex2 INT_IOI_CLK_S switchbox INT muxes OMUX[15]
BitsDestination
MAIN[7][79]MAIN[6][78]MAIN[7][77]MAIN[7][78]MAIN[6][75]MAIN[6][72]MAIN[6][74]MAIN[7][76]MAIN[6][77]OMUX[15]
Source
000000000off
000100001OUT_FAN[0]
000100010OUT_FAN[1]
000100100OUT_FAN[2]
001000100OUT_SEC[9]
010000001OUT_SEC[12]
010000100OUT_SEC[15]
010001000OUT_SEC[17]
100000100OUT_SEC[21]
100010000OUT_SEC[20]
virtex2 INT_IOI_CLK_S switchbox INT muxes DBL_W0[0]
BitsDestination
MAIN[16][5]MAIN[16][6]MAIN[17][6]MAIN[17][5]MAIN[15][7]MAIN[14][5]MAIN[14][4]MAIN[15][6]DBL_W0[0]
Source
00000000off
00010001OMUX_S0
00010010HEX_E6[0]
00011000HEX_N6[0]
00100001OMUX_NW10
00100010HEX_S6[1]
00101000HEX_W6[0]
01000001DBL_W2[0]
01000010HEX_N3[0]
01000100HEX_S3[0]
01001000DBL_N3[9]
10000001DBL_W2_N[8]
10000010DBL_S1[0]
10000100DBL_S2[2]
10001000DBL_N1[0]
virtex2 INT_IOI_CLK_S switchbox INT muxes DBL_W0[1]
BitsDestination
MAIN[16][13]MAIN[16][14]MAIN[17][14]MAIN[17][13]MAIN[15][15]MAIN[14][13]MAIN[14][12]MAIN[15][14]DBL_W0[1]
Source
00000000off
00010001OMUX[2]
00010010HEX_E6[1]
00010100OUT_FAN[2]
00011000HEX_N6[1]
00100001OMUX_W1
00100010HEX_S6[2]
00101000HEX_W6[1]
01000001DBL_W2[1]
01000010HEX_N3[1]
01000100HEX_S3[1]
01001000DBL_N2[0]
10000001DBL_W2_N[9]
10000010DBL_S1[1]
10000100DBL_S2[3]
10001000DBL_N1[1]
virtex2 INT_IOI_CLK_S switchbox INT muxes DBL_W0[2]
BitsDestination
MAIN[15][23]MAIN[14][20]MAIN[15][22]MAIN[14][21]MAIN[16][22]MAIN[16][21]MAIN[17][22]MAIN[17][21]DBL_W0[2]
Source
00000000off
00010001OMUX[4]
00010100DBL_S2[4]
00011000HEX_S3[2]
00100001OMUX[6]
00100010OMUX_WN14
00100100DBL_W2[0]
00101000DBL_W2[2]
01000001HEX_E6[2]
01000010HEX_S6[3]
01000100DBL_S1[2]
01001000HEX_N3[2]
10000001HEX_N6[2]
10000010HEX_W6[2]
10000100DBL_N1[2]
10001000DBL_N2[1]
virtex2 INT_IOI_CLK_S switchbox INT muxes DBL_W0[3]
BitsDestination
MAIN[16][30]MAIN[16][29]MAIN[17][30]MAIN[17][29]MAIN[15][31]MAIN[14][29]MAIN[14][28]MAIN[15][30]DBL_W0[3]
Source
00000000off
00010001OMUX_W6
00010010HEX_E6[3]
00011000HEX_N6[3]
00100001OMUX_NW10
00100010HEX_S6[4]
00100100OUT_FAN[2]
00101000HEX_W6[3]
01000001DBL_W2[1]
01000010DBL_S1[3]
01000100DBL_S2[5]
01001000DBL_N1[3]
10000001DBL_W2[3]
10000010HEX_N3[3]
10000100HEX_S3[3]
10001000DBL_N2[2]
virtex2 INT_IOI_CLK_S switchbox INT muxes DBL_W0[4]
BitsDestination
MAIN[16][38]MAIN[16][37]MAIN[17][38]MAIN[17][37]MAIN[15][39]MAIN[14][37]MAIN[14][36]MAIN[15][38]DBL_W0[4]
Source
00000000off
00010001OMUX_WS1
00010010HEX_E6[4]
00011000HEX_N6[4]
00100001OMUX_N12
00100010HEX_S6[5]
00101000HEX_W6[4]
01000001DBL_W2[2]
01000010DBL_S1[4]
01000100DBL_S2[6]
01001000DBL_N1[4]
10000001DBL_W2[4]
10000010HEX_N3[4]
10000100HEX_S3[4]
10001000DBL_N2[3]
virtex2 INT_IOI_CLK_S switchbox INT muxes DBL_W0[5]
BitsDestination
MAIN[16][46]MAIN[16][45]MAIN[17][46]MAIN[17][45]MAIN[15][47]MAIN[14][45]MAIN[14][44]MAIN[15][46]DBL_W0[5]
Source
00000000off
00010001OMUX_S3
00010010HEX_E6[5]
00010100OUT_FAN[1]
00011000HEX_N6[5]
00100001OMUX_WN14
00100010HEX_S6[6]
00101000HEX_W6[5]
01000001DBL_W2[3]
01000010DBL_S1[5]
01000100DBL_S2[7]
01001000DBL_N1[5]
10000001DBL_W2[5]
10000010HEX_N3[5]
10000100HEX_S3[5]
10001000DBL_N2[4]
virtex2 INT_IOI_CLK_S switchbox INT muxes DBL_W0[6]
BitsDestination
MAIN[15][55]MAIN[14][52]MAIN[15][54]MAIN[14][53]MAIN[16][54]MAIN[16][53]MAIN[17][53]MAIN[17][54]DBL_W0[6]
Source
00000000off
00010001OMUX[11]
00010010OUT_FAN[0]
00010100DBL_S2[8]
00011000HEX_S3[6]
00100001OMUX_W9
00100010OMUX_SW5
00100100DBL_W2[4]
00101000DBL_W2[6]
01000001HEX_S6[7]
01000010HEX_E6[6]
01000100DBL_S1[6]
01001000HEX_N3[6]
10000001HEX_W6[6]
10000010HEX_N6[6]
10000100DBL_N1[6]
10001000DBL_N2[5]
virtex2 INT_IOI_CLK_S switchbox INT muxes DBL_W0[7]
BitsDestination
MAIN[16][62]MAIN[16][61]MAIN[17][61]MAIN[17][62]MAIN[15][63]MAIN[14][61]MAIN[14][60]MAIN[15][62]DBL_W0[7]
Source
00000000off
00010001OMUX[9]
00010010HEX_S6[8]
00010100OUT_FAN[1]
00011000HEX_W6[7]
00100001OMUX_WS1
00100010HEX_E6[7]
00101000HEX_N6[7]
01000001DBL_W2[5]
01000010DBL_S1[7]
01000100DBL_S2[9]
01001000DBL_N1[7]
10000001DBL_W2[7]
10000010HEX_N3[7]
10000100HEX_S3[7]
10001000DBL_N2[6]
virtex2 INT_IOI_CLK_S switchbox INT muxes DBL_W0[8]
BitsDestination
MAIN[16][70]MAIN[16][69]MAIN[17][69]MAIN[17][70]MAIN[15][71]MAIN[14][69]MAIN[14][68]MAIN[15][70]DBL_W0[8]
Source
00000000off
00010001OMUX[13]
00010010HEX_S6[9]
00010100OUT_FAN[0]
00011000HEX_W6[8]
00100001OMUX_W14
00100010HEX_E6[8]
00101000HEX_N6[8]
01000001DBL_W2[6]
01000010DBL_S1[8]
01000100DBL_S3[0]
01001000DBL_N1[8]
10000001DBL_W2[8]
10000010HEX_N3[8]
10000100HEX_S3[8]
10001000DBL_N2[7]
virtex2 INT_IOI_CLK_S switchbox INT muxes DBL_W0[9]
BitsDestination
MAIN[15][79]MAIN[14][76]MAIN[14][77]MAIN[15][78]MAIN[16][78]MAIN[16][77]MAIN[17][77]MAIN[17][78]DBL_W0[9]
Source
00000000off
00010001OMUX[13]
00010010OMUX_SW5
00010100DBL_W2[7]
00011000DBL_W2[9]
00100001OMUX_S0
00100010OMUX[15]
00100100DBL_S3[1]
00101000HEX_S3[9]
01000001HEX_S7[0]
01000010HEX_E6[9]
01000100DBL_S1[9]
01001000HEX_N3[9]
10000001HEX_W6[9]
10000010HEX_N6[9]
10000100DBL_N1[9]
10001000DBL_N2[8]
virtex2 INT_IOI_CLK_S switchbox INT muxes DBL_E0[0]
BitsDestination
MAIN[17][7]MAIN[17][4]MAIN[16][4]MAIN[16][7]MAIN[15][5]MAIN[14][7]MAIN[15][4]MAIN[14][6]DBL_E0[0]
Source
00000000off
00010001OMUX_E2
00010010HEX_S6[1]
00011000HEX_W6[0]
00100001OMUX_EN8
00100010HEX_E6[0]
00101000HEX_N6[0]
01000001DBL_E2[0]
01000010DBL_S1[0]
01000100DBL_S2[2]
01001000DBL_N1[0]
10000001DBL_E2[2]
10000010HEX_N3[0]
10000100HEX_S3[0]
10001000DBL_N3[9]
virtex2 INT_IOI_CLK_S switchbox INT muxes DBL_E0[1]
BitsDestination
MAIN[17][15]MAIN[17][12]MAIN[16][12]MAIN[16][15]MAIN[15][13]MAIN[14][15]MAIN[15][12]MAIN[14][14]DBL_E0[1]
Source
00000000off
00010001OMUX_S4
00010010HEX_S6[2]
00011000HEX_W6[1]
00100001OMUX_N10
00100010HEX_E6[1]
00100100OUT_FAN[2]
00101000HEX_N6[1]
01000001DBL_E2[1]
01000010DBL_S1[1]
01000100DBL_S2[3]
01001000DBL_N1[1]
10000001DBL_E2[3]
10000010HEX_N3[1]
10000100HEX_S3[1]
10001000DBL_N2[0]
virtex2 INT_IOI_CLK_S switchbox INT muxes DBL_E0[2]
BitsDestination
MAIN[15][21]MAIN[15][20]MAIN[14][22]MAIN[14][23]MAIN[17][23]MAIN[17][20]MAIN[16][23]MAIN[16][20]DBL_E0[2]
Source
00000000off
00010001OMUX[4]
00010100DBL_S2[4]
00011000HEX_S3[2]
00100001OMUX_NE12
00100010OMUX[6]
00100100DBL_E2[2]
00101000DBL_E2[4]
01000001HEX_E6[2]
01000010HEX_S6[3]
01000100DBL_S1[2]
01001000HEX_N3[2]
10000001HEX_N6[2]
10000010HEX_W6[2]
10000100DBL_N1[2]
10001000DBL_N2[1]
virtex2 INT_IOI_CLK_S switchbox INT muxes DBL_E0[3]
BitsDestination
MAIN[17][31]MAIN[17][28]MAIN[16][28]MAIN[16][31]MAIN[15][29]MAIN[14][31]MAIN[15][28]MAIN[14][30]DBL_E0[3]
Source
00000000off
00010001OMUX_SE3
00010010HEX_S6[4]
00010100OUT_FAN[2]
00011000HEX_W6[3]
00100001OMUX_EN8
00100010HEX_E6[3]
00101000HEX_N6[3]
01000001DBL_E2[3]
01000010DBL_S1[3]
01000100DBL_S2[5]
01001000DBL_N1[3]
10000001DBL_E2[5]
10000010HEX_N3[3]
10000100HEX_S3[3]
10001000DBL_N2[2]
virtex2 INT_IOI_CLK_S switchbox INT muxes DBL_E0[4]
BitsDestination
MAIN[17][39]MAIN[17][36]MAIN[16][39]MAIN[16][36]MAIN[15][37]MAIN[14][39]MAIN[15][36]MAIN[14][38]DBL_E0[4]
Source
00000000off
00010001OMUX_E7
00010010HEX_E6[4]
00011000HEX_N6[4]
00100001OMUX_E8
00100010HEX_S6[5]
00101000HEX_W6[4]
01000001DBL_E2[4]
01000010DBL_S1[4]
01000100DBL_S2[6]
01001000DBL_N1[4]
10000001DBL_E2[6]
10000010HEX_N3[4]
10000100HEX_S3[4]
10001000DBL_N2[3]
virtex2 INT_IOI_CLK_S switchbox INT muxes DBL_E0[5]
BitsDestination
MAIN[17][47]MAIN[17][44]MAIN[16][44]MAIN[16][47]MAIN[15][45]MAIN[14][47]MAIN[15][44]MAIN[14][46]DBL_E0[5]
Source
00000000off
00010001OMUX_ES7
00010010HEX_S6[6]
00011000HEX_W6[5]
00100001OMUX_NE12
00100010HEX_E6[5]
00100100OUT_FAN[1]
00101000HEX_N6[5]
01000001DBL_E2[5]
01000010DBL_S1[5]
01000100DBL_S2[7]
01001000DBL_N1[5]
10000001DBL_E2[7]
10000010HEX_N3[5]
10000100HEX_S3[5]
10001000DBL_N2[4]
virtex2 INT_IOI_CLK_S switchbox INT muxes DBL_E0[6]
BitsDestination
MAIN[17][55]MAIN[17][52]MAIN[16][55]MAIN[16][52]MAIN[15][53]MAIN[15][52]MAIN[14][55]MAIN[14][54]DBL_E0[6]
Source
00000000off
00010001OMUX[9]
00010010OUT_FAN[0]
00010100HEX_E6[6]
00011000HEX_N6[6]
00100001OMUX_SE3
00100010OMUX[11]
00100100HEX_S6[7]
00101000HEX_W6[6]
01000001DBL_E2[6]
01000010DBL_S2[8]
01000100DBL_S1[6]
01001000DBL_N1[6]
10000001DBL_E2[8]
10000010HEX_S3[6]
10000100HEX_N3[6]
10001000DBL_N2[5]
virtex2 INT_IOI_CLK_S switchbox INT muxes DBL_E0[7]
BitsDestination
MAIN[17][63]MAIN[17][60]MAIN[16][60]MAIN[16][63]MAIN[15][61]MAIN[14][63]MAIN[15][60]MAIN[14][62]DBL_E0[7]
Source
00000000off
00010001OMUX_S5
00010010HEX_S6[8]
00010100OUT_FAN[1]
00011000HEX_W6[7]
00100001OMUX_N11
00100010HEX_E6[7]
00101000HEX_N6[7]
01000001DBL_E2[7]
01000010DBL_S1[7]
01000100DBL_S2[9]
01001000DBL_N1[7]
10000001DBL_E2[9]
10000010HEX_N3[7]
10000100HEX_S3[7]
10001000DBL_N2[6]
virtex2 INT_IOI_CLK_S switchbox INT muxes DBL_E0[8]
BitsDestination
MAIN[17][71]MAIN[17][68]MAIN[16][68]MAIN[16][71]MAIN[15][69]MAIN[14][71]MAIN[15][68]MAIN[14][70]DBL_E0[8]
Source
00000000off
00010001OMUX_ES7
00010010HEX_S6[9]
00010100OUT_FAN[0]
00011000HEX_W6[8]
00100001OMUX_E13
00100010HEX_E6[8]
00101000HEX_N6[8]
01000001DBL_E2[8]
01000010DBL_S1[8]
01000100DBL_S3[0]
01001000DBL_N1[8]
10000001DBL_E2_S[0]
10000010HEX_N3[8]
10000100HEX_S3[8]
10001000DBL_N2[7]
virtex2 INT_IOI_CLK_S switchbox INT muxes DBL_E0[9]
BitsDestination
MAIN[17][79]MAIN[17][76]MAIN[16][79]MAIN[16][76]MAIN[15][77]MAIN[15][76]MAIN[14][78]MAIN[14][79]DBL_E0[9]
Source
00000000off
00010001OMUX[15]
00010010OMUX_N15
00010100HEX_E6[9]
00011000HEX_N6[9]
00100001OMUX_S0
00100010OMUX_S2
00100100HEX_S7[0]
00101000HEX_W6[9]
01000001DBL_S3[1]
01000010DBL_E2[9]
01000100DBL_S1[9]
01001000DBL_N1[9]
10000001HEX_S3[9]
10000010DBL_E2_S[1]
10000100HEX_N3[9]
10001000DBL_N2[8]
virtex2 INT_IOI_CLK_S switchbox INT muxes DBL_S0[0]
BitsDestination
MAIN[15][0]MAIN[15][1]MAIN[14][2]MAIN[14][3]MAIN[17][3]MAIN[17][0]MAIN[16][3]MAIN[16][0]DBL_S0[0]
Source
00000000off
00010001OMUX[0]
00010100DBL_E2[1]
00011000HEX_E3[0]
00100001OMUX[2]
00100010OMUX_S0
00100100DBL_S2[0]
00101000DBL_S2[2]
01000001HEX_W6_N[9]
01000010HEX_N6[0]
01000100DBL_W1[0]
01001000DBL_W2_N[8]
10000001HEX_S6[0]
10000010HEX_E6[0]
10000100DBL_E1[0]
10001000HEX_W3[0]
virtex2 INT_IOI_CLK_S switchbox INT muxes DBL_S0[1]
BitsDestination
MAIN[17][11]MAIN[17][8]MAIN[16][8]MAIN[16][11]MAIN[14][11]MAIN[15][8]MAIN[15][9]MAIN[14][10]DBL_S0[1]
Source
00000000off
00010001OMUX[2]
00010010HEX_N6[1]
00010100HEX_E6[1]
00011000OUT_FAN[2]
00100001OMUX_E2
00100010HEX_W6[0]
00100100HEX_S6[1]
01000001DBL_S2[1]
01000010DBL_W1[1]
01000100DBL_E1[1]
01001000DBL_E2[2]
10000001DBL_S2[3]
10000010DBL_W2_N[9]
10000100HEX_W3[1]
10001000HEX_E3[1]
virtex2 INT_IOI_CLK_S switchbox INT muxes DBL_S0[2]
BitsDestination
MAIN[15][16]MAIN[15][17]MAIN[14][18]MAIN[14][19]MAIN[17][19]MAIN[17][16]MAIN[16][16]MAIN[16][19]DBL_S0[2]
Source
00000000off
00010001OMUX[4]
00010100DBL_E2[3]
00011000HEX_E3[2]
00100001OMUX[6]
00100010OMUX_S4
00100100DBL_S2[2]
00101000DBL_S2[4]
01000001HEX_N6[2]
01000010HEX_W6[1]
01000100DBL_W1[2]
01001000DBL_W2[0]
10000001HEX_E6[2]
10000010HEX_S6[2]
10000100DBL_E1[2]
10001000HEX_W3[2]
virtex2 INT_IOI_CLK_S switchbox INT muxes DBL_S0[3]
BitsDestination
MAIN[17][27]MAIN[17][24]MAIN[16][27]MAIN[16][24]MAIN[14][27]MAIN[15][24]MAIN[15][25]MAIN[14][26]DBL_S0[3]
Source
00000000off
00010001OMUX[6]
00010010HEX_W6[2]
00010100HEX_S6[3]
00100001OMUX_W6
00100010HEX_N6[3]
00100100HEX_E6[3]
01000001DBL_S2[3]
01000010DBL_W1[3]
01000100DBL_E1[3]
01001000DBL_E2[4]
10000001DBL_S2[5]
10000010DBL_W2[1]
10000100HEX_W3[3]
10001000HEX_E3[3]
virtex2 INT_IOI_CLK_S switchbox INT muxes DBL_S0[4]
BitsDestination
MAIN[17][35]MAIN[17][32]MAIN[16][32]MAIN[16][35]MAIN[14][35]MAIN[15][32]MAIN[15][33]MAIN[14][34]DBL_S0[4]
Source
00000000off
00010001OMUX_WS1
00010010HEX_N6[4]
00010100HEX_E6[4]
00100001OMUX_SE3
00100010HEX_W6[3]
00100100HEX_S6[4]
00101000OUT_FAN[2]
01000001DBL_S2[4]
01000010DBL_W1[4]
01000100DBL_E1[4]
01001000DBL_E2[5]
10000001DBL_S2[6]
10000010DBL_W2[2]
10000100HEX_W3[4]
10001000HEX_E3[4]
virtex2 INT_IOI_CLK_S switchbox INT muxes DBL_S0[5]
BitsDestination
MAIN[17][43]MAIN[17][40]MAIN[16][40]MAIN[16][43]MAIN[14][43]MAIN[15][40]MAIN[15][41]MAIN[14][42]DBL_S0[5]
Source
00000000off
00010001OMUX_S3
00010010HEX_N6[5]
00010100HEX_E6[5]
00011000OUT_FAN[1]
00100001OMUX_E8
00100010HEX_W6[4]
00100100HEX_S6[5]
01000001DBL_S2[5]
01000010DBL_W1[5]
01000100DBL_E1[5]
01001000DBL_E2[6]
10000001DBL_S2[7]
10000010DBL_W2[3]
10000100HEX_W3[5]
10001000HEX_E3[5]
virtex2 INT_IOI_CLK_S switchbox INT muxes DBL_S0[6]
BitsDestination
MAIN[17][51]MAIN[17][48]MAIN[16][48]MAIN[16][51]MAIN[14][51]MAIN[15][48]MAIN[15][49]MAIN[14][50]DBL_S0[6]
Source
00000000off
00010001OMUX_SW5
00010010HEX_N6[6]
00010100HEX_E6[6]
00011000OUT_FAN[0]
00100001OMUX_ES7
00100010HEX_W6[5]
00100100HEX_S6[6]
01000001DBL_S2[6]
01000010DBL_W1[6]
01000100DBL_E1[6]
01001000DBL_E2[7]
10000001DBL_S2[8]
10000010DBL_W2[4]
10000100HEX_W3[6]
10001000HEX_E3[6]
virtex2 INT_IOI_CLK_S switchbox INT muxes DBL_S0[7]
BitsDestination
MAIN[15][56]MAIN[15][57]MAIN[14][58]MAIN[14][59]MAIN[17][59]MAIN[17][56]MAIN[16][59]MAIN[16][56]DBL_S0[7]
Source
00000000off
00010001OMUX[11]
00010100DBL_E2[8]
00011000HEX_E3[7]
00100001OMUX_SE3
00100010OMUX_WS1
00100100DBL_S2[7]
00101000DBL_S2[9]
01000001HEX_W6[6]
01000010HEX_N6[7]
01000100DBL_W1[7]
01001000DBL_W2[5]
10000001HEX_S6[7]
10000010HEX_E6[7]
10000100DBL_E1[7]
10001000HEX_W3[7]
virtex2 INT_IOI_CLK_S switchbox INT muxes DBL_S0[8]
BitsDestination
MAIN[17][67]MAIN[17][64]MAIN[16][67]MAIN[16][64]MAIN[14][67]MAIN[15][64]MAIN[15][65]MAIN[14][66]DBL_S0[8]
Source
00000000off
00010001OMUX_S5
00010010HEX_W6[7]
00010100HEX_S6[8]
00011000OUT_FAN[1]
00100001OMUX_W14
00100010HEX_N6[8]
00100100HEX_E6[8]
01000001DBL_S2[8]
01000010DBL_W1[8]
01000100DBL_E1[8]
01001000DBL_E2[9]
10000001DBL_S3[0]
10000010DBL_W2[6]
10000100HEX_W3[8]
10001000HEX_E3[8]
virtex2 INT_IOI_CLK_S switchbox INT muxes DBL_S0[9]
BitsDestination
MAIN[15][72]MAIN[15][73]MAIN[14][74]MAIN[14][75]MAIN[17][75]MAIN[17][72]MAIN[16][72]MAIN[16][75]DBL_S0[9]
Source
00000000off
00010001OMUX[15]
00010010OUT_FAN[0]
00010100DBL_E2_S[0]
00011000HEX_E3[9]
00100001OMUX_SW5
00100010OMUX_ES7
00100100DBL_S2[9]
00101000DBL_S3[1]
01000001HEX_N6[9]
01000010HEX_W6[8]
01000100DBL_W1[9]
01001000DBL_W2[7]
10000001HEX_E6[9]
10000010HEX_S6[9]
10000100DBL_E1[9]
10001000HEX_W3[9]
virtex2 INT_IOI_CLK_S switchbox INT muxes DBL_N0[0]
BitsDestination
MAIN[14][0]MAIN[15][3]MAIN[15][2]MAIN[14][1]MAIN[16][2]MAIN[16][1]MAIN[17][2]MAIN[17][1]DBL_N0[0]
Source
00000000off
00010001OMUX[0]
00010100DBL_E2[1]
00011000HEX_E3[0]
00100001OMUX_N13
00100010OMUX_EN8
00100100DBL_N3[8]
00101000DBL_N2[0]
01000001HEX_W6_N[9]
01000010HEX_N6[0]
01000100DBL_W1[0]
01001000DBL_W2_N[8]
10000001HEX_S6[0]
10000010HEX_E6[0]
10000100DBL_E1[0]
10001000HEX_W3[0]
virtex2 INT_IOI_CLK_S switchbox INT muxes DBL_N0[1]
BitsDestination
MAIN[16][10]MAIN[16][9]MAIN[17][9]MAIN[17][10]MAIN[14][9]MAIN[14][8]MAIN[15][11]MAIN[15][10]DBL_N0[1]
Source
00000000off
00010001OMUX_N10
00010010HEX_N6[1]
00010100HEX_E6[1]
00011000OUT_FAN[2]
00100001OMUX_NW10
00100010HEX_W6[0]
00100100HEX_S6[1]
01000001DBL_N3[9]
01000010DBL_W1[1]
01000100DBL_E1[1]
01001000DBL_E2[2]
10000001DBL_N2[1]
10000010DBL_W2_N[9]
10000100HEX_W3[1]
10001000HEX_E3[1]
virtex2 INT_IOI_CLK_S switchbox INT muxes DBL_N0[2]
BitsDestination
MAIN[14][16]MAIN[15][19]MAIN[15][18]MAIN[14][17]MAIN[16][18]MAIN[16][17]MAIN[17][17]MAIN[17][18]DBL_N0[2]
Source
00000000off
00010001OMUX[4]
00010100DBL_E2[3]
00011000HEX_E3[2]
00100001OMUX_NE12
00100010OMUX_W1
00100100DBL_N2[0]
00101000DBL_N2[2]
01000001HEX_N6[2]
01000010HEX_W6[1]
01000100DBL_W1[2]
01001000DBL_W2[0]
10000001HEX_E6[2]
10000010HEX_S6[2]
10000100DBL_E1[2]
10001000HEX_W3[2]
virtex2 INT_IOI_CLK_S switchbox INT muxes DBL_N0[3]
BitsDestination
MAIN[16][26]MAIN[16][25]MAIN[17][25]MAIN[17][26]MAIN[14][25]MAIN[14][24]MAIN[15][27]MAIN[15][26]DBL_N0[3]
Source
00000000off
00010001OMUX_EN8
00010010HEX_N6[3]
00010100HEX_E6[3]
00100001OMUX_WN14
00100010HEX_W6[2]
00100100HEX_S6[3]
01000001DBL_N2[1]
01000010DBL_W1[3]
01000100DBL_E1[3]
01001000DBL_E2[4]
10000001DBL_N2[3]
10000010DBL_W2[1]
10000100HEX_W3[3]
10001000HEX_E3[3]
virtex2 INT_IOI_CLK_S switchbox INT muxes DBL_N0[4]
BitsDestination
MAIN[16][34]MAIN[16][33]MAIN[17][33]MAIN[17][34]MAIN[14][33]MAIN[14][32]MAIN[15][35]MAIN[15][34]DBL_N0[4]
Source
00000000off
00010001OMUX_E7
00010010HEX_N6[4]
00010100HEX_E6[4]
00100001OMUX_NW10
00100010HEX_W6[3]
00100100HEX_S6[4]
00101000OUT_FAN[2]
01000001DBL_N2[2]
01000010DBL_W1[4]
01000100DBL_E1[4]
01001000DBL_E2[5]
10000001DBL_N2[4]
10000010DBL_W2[2]
10000100HEX_W3[4]
10001000HEX_E3[4]
virtex2 INT_IOI_CLK_S switchbox INT muxes DBL_N0[5]
BitsDestination
MAIN[16][42]MAIN[16][41]MAIN[17][42]MAIN[17][41]MAIN[14][41]MAIN[14][40]MAIN[15][43]MAIN[15][42]DBL_N0[5]
Source
00000000off
00010001OMUX_N12
00010010HEX_W6[4]
00010100HEX_S6[5]
00100001OMUX_NE12
00100010HEX_N6[5]
00100100HEX_E6[5]
00101000OUT_FAN[1]
01000001DBL_N2[3]
01000010DBL_W1[5]
01000100DBL_E1[5]
01001000DBL_E2[6]
10000001DBL_N2[5]
10000010DBL_W2[3]
10000100HEX_W3[5]
10001000HEX_E3[5]
virtex2 INT_IOI_CLK_S switchbox INT muxes DBL_N0[6]
BitsDestination
MAIN[16][50]MAIN[16][49]MAIN[17][49]MAIN[17][50]MAIN[14][49]MAIN[14][48]MAIN[15][51]MAIN[15][50]DBL_N0[6]
Source
00000000off
00010001OMUX[9]
00010010HEX_N6[6]
00010100HEX_E6[6]
00011000OUT_FAN[0]
00100001OMUX_WN14
00100010HEX_W6[5]
00100100HEX_S6[6]
01000001DBL_N2[4]
01000010DBL_W1[6]
01000100DBL_E1[6]
01001000DBL_E2[7]
10000001DBL_N2[6]
10000010DBL_W2[4]
10000100HEX_W3[6]
10001000HEX_E3[6]
virtex2 INT_IOI_CLK_S switchbox INT muxes DBL_N0[7]
BitsDestination
MAIN[14][56]MAIN[15][59]MAIN[15][58]MAIN[14][57]MAIN[16][58]MAIN[16][57]MAIN[17][58]MAIN[17][57]DBL_N0[7]
Source
00000000off
00010001OMUX[11]
00010100DBL_E2[8]
00011000HEX_E3[7]
00100001OMUX_W9
00100010OMUX_N11
00100100DBL_N2[5]
00101000DBL_N2[7]
01000001HEX_W6[6]
01000010HEX_N6[7]
01000100DBL_W1[7]
01001000DBL_W2[5]
10000001HEX_S6[7]
10000010HEX_E6[7]
10000100DBL_E1[7]
10001000HEX_W3[7]
virtex2 INT_IOI_CLK_S switchbox INT muxes DBL_N0[8]
BitsDestination
MAIN[16][66]MAIN[16][65]MAIN[17][66]MAIN[17][65]MAIN[14][65]MAIN[14][64]MAIN[15][67]MAIN[15][66]DBL_N0[8]
Source
00000000off
00010001OMUX[9]
00010010HEX_W6[7]
00010100HEX_S6[8]
00011000OUT_FAN[1]
00100001OMUX_E13
00100010HEX_N6[8]
00100100HEX_E6[8]
01000001DBL_N2[6]
01000010DBL_W1[8]
01000100DBL_E1[8]
01001000DBL_E2[9]
10000001DBL_N2[8]
10000010DBL_W2[6]
10000100HEX_W3[8]
10001000HEX_E3[8]
virtex2 INT_IOI_CLK_S switchbox INT muxes DBL_N0[9]
BitsDestination
MAIN[16][74]MAIN[16][73]MAIN[17][74]MAIN[17][73]MAIN[14][72]MAIN[15][75]MAIN[14][73]MAIN[15][74]DBL_N0[9]
Source
00000000off
00010001OMUX[13]
00010010OUT_FAN[0]
00010100HEX_W6[8]
00011000HEX_S6[9]
00100001OMUX_N15
00100010OMUX[15]
00100100HEX_N6[9]
00101000HEX_E6[9]
01000001DBL_N2[7]
01000010DBL_E2_S[0]
01000100DBL_W1[9]
01001000DBL_E1[9]
10000001DBL_N2[9]
10000010HEX_E3[9]
10000100DBL_W2[7]
10001000HEX_W3[9]
virtex2 INT_IOI_CLK_S switchbox INT muxes HEX_W0[0]
BitsDestination
MAIN[20][4]MAIN[20][6]MAIN[20][5]MAIN[18][4]MAIN[19][6]MAIN[18][6]MAIN[19][4]HEX_W0[0]
Source
0000000off
0010001OMUX_S0
0010010HEX_S3[0]
0010100HEX_N3[0]
0011000LH[6]
0100010OMUX_NW10
0100100HEX_W6[0]
0101000HEX_W6_N[8]
1000010LH[18]
1000100HEX_N7[9]
1001000HEX_S6[2]
virtex2 INT_IOI_CLK_S switchbox INT muxes HEX_W0[1]
BitsDestination
MAIN[21][12]MAIN[20][15]MAIN[21][14]MAIN[18][13]MAIN[19][15]MAIN[18][15]MAIN[19][13]HEX_W0[1]
Source
0000000off
0010001OMUX[2]
0010100HEX_W6[1]
0011000HEX_W6_N[9]
0100001LH[0]
0100010OMUX_W1
0100100HEX_S3[1]
0101000HEX_N3[1]
1000001OUT_FAN[2]
1000010LH[12]
1000100HEX_N6[0]
1001000HEX_S6[3]
virtex2 INT_IOI_CLK_S switchbox INT muxes HEX_W0[2]
BitsDestination
MAIN[19][22]MAIN[18][20]MAIN[18][22]MAIN[19][20]MAIN[20][22]MAIN[20][21]MAIN[20][20]HEX_W0[2]
Source
0000000off
0001001OMUX[4]
0001010OMUX[6]
0010001LH[18]
0010010HEX_S3[2]
0010100OMUX_WN14
0100001HEX_S6[4]
0100010LH[6]
0100100HEX_W6[0]
1000001HEX_N6[1]
1000010HEX_N3[2]
1000100HEX_W6[2]
virtex2 INT_IOI_CLK_S switchbox INT muxes HEX_W0[3]
BitsDestination
MAIN[21][28]MAIN[20][31]MAIN[21][30]MAIN[19][31]MAIN[18][29]MAIN[18][31]MAIN[19][29]HEX_W0[3]
Source
0000000off
0010001OMUX_W6
0010010OUT_FAN[2]
0010100HEX_W6[1]
0011000HEX_W6[3]
0100001LH[0]
0100010OMUX_NW10
0100100HEX_N3[3]
0101000HEX_S3[3]
1000010LH[12]
1000100HEX_S6[5]
1001000HEX_N6[2]
virtex2 INT_IOI_CLK_S switchbox INT muxes HEX_W0[4]
BitsDestination
MAIN[20][36]MAIN[20][38]MAIN[20][37]MAIN[19][38]MAIN[18][36]MAIN[18][38]MAIN[19][36]HEX_W0[4]
Source
0000000off
0010001OMUX_WS1
0010010HEX_S3[4]
0010100LH[6]
0011000HEX_N3[4]
0100010OMUX_N12
0100100HEX_W6[2]
0101000HEX_W6[4]
1000010LH[18]
1000100HEX_S6[6]
1001000HEX_N6[3]
virtex2 INT_IOI_CLK_S switchbox INT muxes HEX_W0[5]
BitsDestination
MAIN[21][44]MAIN[20][47]MAIN[21][46]MAIN[19][47]MAIN[18][45]MAIN[18][47]MAIN[19][45]HEX_W0[5]
Source
0000000off
0010001OMUX_S3
0010100HEX_W6[3]
0011000HEX_W6[5]
0100001LH[0]
0100010OMUX_WN14
0100100HEX_N3[5]
0101000HEX_S3[5]
1000001OUT_FAN[1]
1000010LH[12]
1000100HEX_S6[7]
1001000HEX_N6[4]
virtex2 INT_IOI_CLK_S switchbox INT muxes HEX_W0[6]
BitsDestination
MAIN[20][52]MAIN[20][53]MAIN[20][54]MAIN[19][54]MAIN[18][52]MAIN[18][54]MAIN[19][52]HEX_W0[6]
Source
0000000off
0010001OMUX[11]
0010010OMUX_W9
0010100HEX_W6[4]
0011000HEX_W6[6]
0100001OMUX_SW5
0100010HEX_S3[6]
0100100LH[6]
0101000HEX_N3[6]
1000001OUT_FAN[0]
1000010LH[18]
1000100HEX_S6[8]
1001000HEX_N6[5]
virtex2 INT_IOI_CLK_S switchbox INT muxes HEX_W0[7]
BitsDestination
MAIN[21][60]MAIN[21][62]MAIN[20][63]MAIN[19][63]MAIN[18][61]MAIN[19][61]MAIN[18][63]HEX_W0[7]
Source
0000000off
0010001OMUX[9]
0010010LH[0]
0010100HEX_N3[7]
0011000HEX_S3[7]
0100001OUT_FAN[1]
0100010OMUX_WS1
0100100HEX_W6[5]
0101000HEX_W6[7]
1000001LH[12]
1000100HEX_S6[9]
1001000HEX_N6[6]
virtex2 INT_IOI_CLK_S switchbox INT muxes HEX_W0[8]
BitsDestination
MAIN[20][68]MAIN[20][69]MAIN[20][70]MAIN[19][70]MAIN[18][68]MAIN[19][68]MAIN[18][70]HEX_W0[8]
Source
0000000off
0010001OMUX[13]
0010010OUT_FAN[0]
0010100HEX_W6[6]
0011000HEX_W6[8]
0100001HEX_S3[8]
0100010OMUX_W14
0100100LH[6]
0101000HEX_N3[8]
1000001LH[18]
1000100HEX_S7[0]
1001000HEX_N6[7]
virtex2 INT_IOI_CLK_S switchbox INT muxes HEX_W0[9]
BitsDestination
MAIN[21][78]MAIN[21][76]MAIN[20][79]MAIN[19][79]MAIN[18][77]MAIN[19][77]MAIN[18][79]HEX_W0[9]
Source
0000000off
0010001OMUX[13]
0010010LH[0]
0010100HEX_N3[9]
0011000HEX_S3[9]
0100001LH[12]
0100010OMUX[15]
0100100HEX_S7[1]
0101000HEX_N6[8]
1000001OMUX_S0
1000010OMUX_SW5
1000100HEX_W6[7]
1001000HEX_W6[9]
virtex2 INT_IOI_CLK_S switchbox INT muxes HEX_E0[0]
BitsDestination
MAIN[21][4]MAIN[21][6]MAIN[20][7]MAIN[19][7]MAIN[18][5]MAIN[19][5]MAIN[18][7]HEX_E0[0]
Source
0000000off
0010001OMUX_E2
0010010LH[6]
0010100HEX_N3[0]
0011000HEX_S3[0]
0100010OMUX_EN8
0100100HEX_E6[0]
0101000HEX_E6[2]
1000001LH[18]
1000100HEX_S6[2]
1001000HEX_N7[9]
virtex2 INT_IOI_CLK_S switchbox INT muxes HEX_E0[1]
BitsDestination
MAIN[20][12]MAIN[20][13]MAIN[20][14]MAIN[19][14]MAIN[18][12]MAIN[19][12]MAIN[18][14]HEX_E0[1]
Source
0000000off
0010001OMUX_S4
0010100HEX_E6[1]
0011000HEX_E6[3]
0100001HEX_S3[1]
0100010OMUX_N10
0100100LH[0]
0101000HEX_N3[1]
1000001LH[12]
1000010OUT_FAN[2]
1000100HEX_S6[3]
1001000HEX_N6[0]
virtex2 INT_IOI_CLK_S switchbox INT muxes HEX_E0[2]
BitsDestination
MAIN[21][22]MAIN[20][23]MAIN[21][20]MAIN[19][23]MAIN[18][21]MAIN[18][23]MAIN[19][21]HEX_E0[2]
Source
0000000off
0010001OMUX[4]
0010010LH[18]
0010100HEX_S6[4]
0011000HEX_N6[1]
0100001LH[6]
0100010OMUX[6]
0100100HEX_N3[2]
0101000HEX_S3[2]
1000001OMUX_NE12
1000100HEX_E6[2]
1001000HEX_E6[4]
virtex2 INT_IOI_CLK_S switchbox INT muxes HEX_E0[3]
BitsDestination
MAIN[20][28]MAIN[20][29]MAIN[20][30]MAIN[19][30]MAIN[18][28]MAIN[19][28]MAIN[18][30]HEX_E0[3]
Source
0000000off
0010001OMUX_SE3
0010010OUT_FAN[2]
0010100HEX_E6[3]
0011000HEX_E6[5]
0100001HEX_S3[3]
0100010OMUX_EN8
0100100LH[0]
0101000HEX_N3[3]
1000001LH[12]
1000100HEX_S6[5]
1001000HEX_N6[2]
virtex2 INT_IOI_CLK_S switchbox INT muxes HEX_E0[4]
BitsDestination
MAIN[21][36]MAIN[20][39]MAIN[21][38]MAIN[19][39]MAIN[18][37]MAIN[18][39]MAIN[19][37]HEX_E0[4]
Source
0000000off
0010001OMUX_E7
0010100HEX_E6[4]
0011000HEX_E6[6]
0100001LH[6]
0100010OMUX_E8
0100100HEX_N3[4]
0101000HEX_S3[4]
1000010LH[18]
1000100HEX_S6[6]
1001000HEX_N6[3]
virtex2 INT_IOI_CLK_S switchbox INT muxes HEX_E0[5]
BitsDestination
MAIN[20][44]MAIN[20][45]MAIN[20][46]MAIN[19][46]MAIN[18][44]MAIN[19][44]MAIN[18][46]HEX_E0[5]
Source
0000000off
0010001OMUX_ES7
0010100HEX_E6[5]
0011000HEX_E6[7]
0100001HEX_S3[5]
0100010OMUX_NE12
0100100LH[0]
0101000HEX_N3[5]
1000001LH[12]
1000010OUT_FAN[1]
1000100HEX_S6[7]
1001000HEX_N6[4]
virtex2 INT_IOI_CLK_S switchbox INT muxes HEX_E0[6]
BitsDestination
MAIN[21][52]MAIN[20][55]MAIN[21][54]MAIN[19][55]MAIN[18][53]MAIN[18][55]MAIN[19][53]HEX_E0[6]
Source
0000000off
0010001OMUX[9]
0010010OMUX[11]
0010100HEX_E6[6]
0011000HEX_E6[8]
0100001LH[6]
0100010OMUX_SE3
0100100HEX_N3[6]
0101000HEX_S3[6]
1000001OUT_FAN[0]
1000010LH[18]
1000100HEX_S6[8]
1001000HEX_N6[5]
virtex2 INT_IOI_CLK_S switchbox INT muxes HEX_E0[7]
BitsDestination
MAIN[20][60]MAIN[20][61]MAIN[20][62]MAIN[19][62]MAIN[18][60]MAIN[19][60]MAIN[18][62]HEX_E0[7]
Source
0000000off
0010001OMUX_S5
0010010OUT_FAN[1]
0010100HEX_E6[7]
0011000HEX_E6[9]
0100001HEX_S3[7]
0100010OMUX_N11
0100100LH[0]
0101000HEX_N3[7]
1000001LH[12]
1000100HEX_S6[9]
1001000HEX_N6[6]
virtex2 INT_IOI_CLK_S switchbox INT muxes HEX_E0[8]
BitsDestination
MAIN[21][68]MAIN[21][70]MAIN[20][71]MAIN[19][71]MAIN[18][69]MAIN[19][69]MAIN[18][71]HEX_E0[8]
Source
0000000off
0010001OMUX_ES7
0010010LH[6]
0010100HEX_N3[8]
0011000HEX_S3[8]
0100001OUT_FAN[0]
0100010OMUX_E13
0100100HEX_E6[8]
0101000HEX_E6_S[0]
1000001LH[18]
1000100HEX_S7[0]
1001000HEX_N6[7]
virtex2 INT_IOI_CLK_S switchbox INT muxes HEX_E0[9]
BitsDestination
MAIN[20][77]MAIN[20][78]MAIN[20][76]MAIN[19][78]MAIN[18][76]MAIN[18][78]MAIN[19][76]HEX_E0[9]
Source
0000000off
0010001OMUX[15]
0010010LH[12]
0010100HEX_S7[1]
0011000HEX_N6[8]
0100001OMUX_S0
0100010OMUX_S2
0100100HEX_E6[9]
0101000HEX_E6_S[1]
1000001OMUX_N15
1000010HEX_S3[9]
1000100LH[0]
1001000HEX_N3[9]
virtex2 INT_IOI_CLK_S switchbox INT muxes HEX_S0[0]
BitsDestination
MAIN[20][3]MAIN[21][2]MAIN[21][0]MAIN[19][3]MAIN[18][1]MAIN[18][3]MAIN[19][1]HEX_S0[0]
Source
0000000off
0010001OMUX[0]
0010010LV[0]
0010100HEX_E6[1]
0011000HEX_W6_N[8]
0100001OMUX[2]
0100100HEX_S6[0]
0101000HEX_S6[2]
1000001LV[12]
1000010OMUX_S0
1000100HEX_W3[0]
1001000HEX_E3[0]
virtex2 INT_IOI_CLK_S switchbox INT muxes HEX_S0[1]
BitsDestination
MAIN[20][8]MAIN[20][9]MAIN[20][10]MAIN[18][8]MAIN[19][10]MAIN[19][8]MAIN[18][10]HEX_S0[1]
Source
0000000off
0010001OMUX[2]
0010010OUT_FAN[2]
0010100HEX_S6[3]
0011000HEX_S6[1]
0100001HEX_E3[1]
0100010OMUX_E2
0100100HEX_W3[1]
0101000LV[18]
1000001LV[6]
1000100HEX_W6_N[9]
1001000HEX_E6[2]
virtex2 INT_IOI_CLK_S switchbox INT muxes HEX_S0[2]
BitsDestination
MAIN[21][16]MAIN[20][19]MAIN[21][18]MAIN[19][19]MAIN[18][17]MAIN[19][17]MAIN[18][19]HEX_S0[2]
Source
0000000off
0010001OMUX[4]
0010010OMUX_S4
0010100HEX_S6[2]
0011000HEX_S6[4]
0100001OMUX[6]
0100010LV[12]
0100100HEX_W3[2]
0101000HEX_E3[2]
1000001LV[0]
1000100HEX_E6[3]
1001000HEX_W6[0]
virtex2 INT_IOI_CLK_S switchbox INT muxes HEX_S0[3]
BitsDestination
MAIN[20][24]MAIN[20][26]MAIN[20][25]MAIN[18][24]MAIN[19][26]MAIN[18][26]MAIN[19][24]HEX_S0[3]
Source
0000000off
0010001OMUX[6]
0010010HEX_E3[3]
0010100HEX_W3[3]
0011000LV[18]
0100010OMUX_W6
0100100HEX_S6[5]
0101000HEX_S6[3]
1000010LV[6]
1000100HEX_W6[1]
1001000HEX_E6[4]
virtex2 INT_IOI_CLK_S switchbox INT muxes HEX_S0[4]
BitsDestination
MAIN[21][32]MAIN[21][34]MAIN[20][35]MAIN[19][35]MAIN[18][33]MAIN[19][33]MAIN[18][35]HEX_S0[4]
Source
0000000off
0010001OMUX_WS1
0010010LV[12]
0010100HEX_W3[4]
0011000HEX_E3[4]
0100010OMUX_SE3
0100100HEX_S6[4]
0101000HEX_S6[6]
1000001LV[0]
1000010OUT_FAN[2]
1000100HEX_E6[5]
1001000HEX_W6[2]
virtex2 INT_IOI_CLK_S switchbox INT muxes HEX_S0[5]
BitsDestination
MAIN[20][40]MAIN[20][41]MAIN[20][42]MAIN[18][40]MAIN[19][42]MAIN[19][40]MAIN[18][42]HEX_S0[5]
Source
0000000off
0010001OMUX_S3
0010010OUT_FAN[1]
0010100HEX_S6[7]
0011000HEX_S6[5]
0100001HEX_E3[5]
0100010OMUX_E8
0100100HEX_W3[5]
0101000LV[18]
1000001LV[6]
1000100HEX_W6[3]
1001000HEX_E6[6]
virtex2 INT_IOI_CLK_S switchbox INT muxes HEX_S0[6]
BitsDestination
MAIN[21][48]MAIN[21][50]MAIN[20][51]MAIN[19][51]MAIN[18][49]MAIN[19][49]MAIN[18][51]HEX_S0[6]
Source
0000000off
0010001OMUX_SW5
0010010LV[12]
0010100HEX_W3[6]
0011000HEX_E3[6]
0100001OUT_FAN[0]
0100010OMUX_ES7
0100100HEX_S6[6]
0101000HEX_S6[8]
1000001LV[0]
1000100HEX_E6[7]
1001000HEX_W6[4]
virtex2 INT_IOI_CLK_S switchbox INT muxes HEX_S0[7]
BitsDestination
MAIN[20][57]MAIN[20][58]MAIN[20][56]MAIN[18][56]MAIN[19][58]MAIN[18][58]MAIN[19][56]HEX_S0[7]
Source
0000000off
0010001OMUX[11]
0010010LV[6]
0010100HEX_W6[5]
0011000HEX_E6[8]
0100010OMUX_WS1
0100100HEX_S6[9]
0101000HEX_S6[7]
1000001OMUX_SE3
1000010HEX_E3[7]
1000100HEX_W3[7]
1001000LV[18]
virtex2 INT_IOI_CLK_S switchbox INT muxes HEX_S0[8]
BitsDestination
MAIN[21][64]MAIN[20][67]MAIN[21][66]MAIN[19][67]MAIN[18][65]MAIN[18][67]MAIN[19][65]HEX_S0[8]
Source
0000000off
0010001OMUX_S5
0010100HEX_S6[8]
0011000HEX_S7[0]
0100001LV[12]
0100010OMUX_W14
0100100HEX_W3[8]
0101000HEX_E3[8]
1000001OUT_FAN[1]
1000010LV[0]
1000100HEX_E6[9]
1001000HEX_W6[6]
virtex2 INT_IOI_CLK_S switchbox INT muxes HEX_S0[9]
BitsDestination
MAIN[20][72]MAIN[20][73]MAIN[20][74]MAIN[18][72]MAIN[19][74]MAIN[18][74]MAIN[19][72]HEX_S0[9]
Source
0000000off
0010001OMUX[15]
0010010OMUX_SW5
0010100HEX_S7[1]
0011000HEX_S6[9]
0100001OMUX_ES7
0100010HEX_E3[9]
0100100HEX_W3[9]
0101000LV[18]
1000001OUT_FAN[0]
1000010LV[6]
1000100HEX_W6[7]
1001000HEX_E6_S[0]
virtex2 INT_IOI_CLK_S switchbox INT muxes HEX_N0[0]
BitsDestination
MAIN[20][1]MAIN[20][2]MAIN[20][0]MAIN[18][0]MAIN[19][2]MAIN[18][2]MAIN[19][0]HEX_N0[0]
Source
0000000off
0010001OMUX[0]
0010010LV[0]
0010100HEX_W6_N[8]
0011000HEX_E6[1]
0100010OMUX_EN8
0100100HEX_N6[0]
0101000HEX_N7[8]
1000001OMUX_N13
1000010HEX_E3[0]
1000100HEX_W3[0]
1001000LV[12]
virtex2 INT_IOI_CLK_S switchbox INT muxes HEX_N0[1]
BitsDestination
MAIN[21][8]MAIN[21][10]MAIN[20][11]MAIN[19][11]MAIN[18][9]MAIN[19][9]MAIN[18][11]HEX_N0[1]
Source
0000000off
0010001OMUX_N10
0010010LV[18]
0010100HEX_W3[1]
0011000HEX_E3[1]
0100001OUT_FAN[2]
0100010OMUX_NW10
0100100HEX_N7[9]
0101000HEX_N6[1]
1000001LV[6]
1000100HEX_E6[2]
1001000HEX_W6_N[9]
virtex2 INT_IOI_CLK_S switchbox INT muxes HEX_N0[2]
BitsDestination
MAIN[20][16]MAIN[20][17]MAIN[20][18]MAIN[18][16]MAIN[19][18]MAIN[18][18]MAIN[19][16]HEX_N0[2]
Source
0000000off
0010001OMUX[4]
0010010OMUX_NE12
0010100HEX_N6[2]
0011000HEX_N6[0]
0100001OMUX_W1
0100010HEX_E3[2]
0100100HEX_W3[2]
0101000LV[12]
1000010LV[0]
1000100HEX_W6[0]
1001000HEX_E6[3]
virtex2 INT_IOI_CLK_S switchbox INT muxes HEX_N0[3]
BitsDestination
MAIN[21][24]MAIN[21][26]MAIN[20][27]MAIN[19][27]MAIN[18][25]MAIN[19][25]MAIN[18][27]HEX_N0[3]
Source
0000000off
0010001OMUX_EN8
0010010LV[18]
0010100HEX_W3[3]
0011000HEX_E3[3]
0100010OMUX_WN14
0100100HEX_N6[1]
0101000HEX_N6[3]
1000001LV[6]
1000100HEX_E6[4]
1001000HEX_W6[1]
virtex2 INT_IOI_CLK_S switchbox INT muxes HEX_N0[4]
BitsDestination
MAIN[20][32]MAIN[20][33]MAIN[20][34]MAIN[18][32]MAIN[19][34]MAIN[19][32]MAIN[18][34]HEX_N0[4]
Source
0000000off
0010001OMUX_E7
0010100HEX_N6[4]
0011000HEX_N6[2]
0100001HEX_E3[4]
0100010OMUX_NW10
0100100HEX_W3[4]
0101000LV[12]
1000001LV[0]
1000010OUT_FAN[2]
1000100HEX_W6[2]
1001000HEX_E6[5]
virtex2 INT_IOI_CLK_S switchbox INT muxes HEX_N0[5]
BitsDestination
MAIN[21][40]MAIN[20][43]MAIN[21][42]MAIN[19][43]MAIN[18][41]MAIN[18][43]MAIN[19][41]HEX_N0[5]
Source
0000000off
0010001OMUX_N12
0010010OUT_FAN[1]
0010100HEX_N6[3]
0011000HEX_N6[5]
0100001LV[18]
0100010OMUX_NE12
0100100HEX_W3[5]
0101000HEX_E3[5]
1000010LV[6]
1000100HEX_E6[6]
1001000HEX_W6[3]
virtex2 INT_IOI_CLK_S switchbox INT muxes HEX_N0[6]
BitsDestination
MAIN[20][48]MAIN[20][49]MAIN[20][50]MAIN[18][48]MAIN[19][50]MAIN[19][48]MAIN[18][50]HEX_N0[6]
Source
0000000off
0010001OMUX[9]
0010010OUT_FAN[0]
0010100HEX_N6[6]
0011000HEX_N6[4]
0100001HEX_E3[6]
0100010OMUX_WN14
0100100HEX_W3[6]
0101000LV[12]
1000001LV[0]
1000100HEX_W6[4]
1001000HEX_E6[7]
virtex2 INT_IOI_CLK_S switchbox INT muxes HEX_N0[7]
BitsDestination
MAIN[20][59]MAIN[21][58]MAIN[21][56]MAIN[19][59]MAIN[18][57]MAIN[18][59]MAIN[19][57]HEX_N0[7]
Source
0000000off
0010001OMUX[11]
0010010LV[6]
0010100HEX_E6[8]
0011000HEX_W6[5]
0100001OMUX_W9
0100100HEX_N6[5]
0101000HEX_N6[7]
1000001LV[18]
1000010OMUX_N11
1000100HEX_W3[7]
1001000HEX_E3[7]
virtex2 INT_IOI_CLK_S switchbox INT muxes HEX_N0[8]
BitsDestination
MAIN[20][64]MAIN[20][66]MAIN[20][65]MAIN[18][64]MAIN[19][66]MAIN[18][66]MAIN[19][64]HEX_N0[8]
Source
0000000off
0010001OMUX[9]
0010010HEX_E3[8]
0010100HEX_W3[8]
0011000LV[12]
0100010OMUX_E13
0100100HEX_N6[8]
0101000HEX_N6[6]
1000001OUT_FAN[1]
1000010LV[0]
1000100HEX_W6[6]
1001000HEX_E6[9]
virtex2 INT_IOI_CLK_S switchbox INT muxes HEX_N0[9]
BitsDestination
MAIN[21][72]MAIN[20][75]MAIN[21][74]MAIN[19][75]MAIN[18][73]MAIN[18][75]MAIN[19][73]HEX_N0[9]
Source
0000000off
0010001OMUX[13]
0010010OMUX[15]
0010100HEX_N6[7]
0011000HEX_N6[9]
0100001LV[18]
0100010OMUX_N15
0100100HEX_W3[9]
0101000HEX_E3[9]
1000001OUT_FAN[0]
1000010LV[6]
1000100HEX_E6_S[0]
1001000HEX_W6[7]
virtex2 INT_IOI_CLK_S switchbox INT muxes LH[0]
BitsDestination
MAIN[21][47]MAIN[21][49]MAIN[21][51]LH[0]
Source
000off
001DBL_W1[5]
011OMUX_S4
101DBL_E1[6]
111OMUX[11]
virtex2 INT_IOI_CLK_S switchbox INT muxes LH[6]
BitsDestination
MAIN[21][31]MAIN[21][33]MAIN[21][29]LH[6]
Source
000off
001OMUX[4]
011OMUX_N15
101DBL_E1[4]
111DBL_W1[3]
virtex2 INT_IOI_CLK_S switchbox INT muxes LH[12]
BitsDestination
MAIN[21][41]MAIN[21][45]MAIN[21][43]LH[12]
Source
000off
001DBL_W1[5]
011OMUX_S4
101DBL_E1[6]
111OMUX[11]
virtex2 INT_IOI_CLK_S switchbox INT muxes LH[18]
BitsDestination
MAIN[21][39]MAIN[21][37]MAIN[21][35]LH[18]
Source
000off
001OMUX[4]
011OMUX_N15
101DBL_E1[4]
111DBL_W1[3]
virtex2 INT_IOI_CLK_S switchbox INT muxes LV[0]
BitsDestination
MAIN[21][7]MAIN[21][9]MAIN[21][19]MAIN[21][25]MAIN[21][21]MAIN[21][11]MAIN[21][5]LV[0]
Source
0000000off
0000011HEX_E1[1]
0000101OMUX_E2
0001001DBL_W1[1]
0010001HEX_E6[1]
0100001HEX_E4[1]
1000011OMUX[0]
1000101HEX_E2[1]
1001001HEX_E5[1]
1010001DBL_E1[2]
1100001HEX_E3[1]
virtex2 INT_IOI_CLK_S switchbox INT muxes LV[6]
BitsDestination
MAIN[21][73]MAIN[21][61]MAIN[21][55]MAIN[21][69]MAIN[21][71]MAIN[21][65]MAIN[21][75]LV[6]
Source
0000000off
0000011OMUX_W9
0000101DBL_W1[7]
0001001HEX_W5[7]
0010001HEX_W3[7]
0100001HEX_W4[7]
1000011OMUX[15]
1000101HEX_W2[7]
1001001DBL_E1[8]
1010001HEX_W0[7]
1100001HEX_W1[7]
virtex2 INT_IOI_CLK_S switchbox INT muxes LV[12]
BitsDestination
MAIN[21][13]MAIN[21][1]MAIN[21][27]MAIN[21][23]MAIN[21][17]MAIN[21][3]MAIN[21][15]LV[12]
Source
0000000off
0000011HEX_E1[1]
0000101OMUX_E2
0001001DBL_W1[1]
0010001HEX_E6[1]
0100001HEX_E4[1]
1000011OMUX[0]
1000101HEX_E2[1]
1001001HEX_E5[1]
1010001DBL_E1[2]
1100001HEX_E3[1]
virtex2 INT_IOI_CLK_S switchbox INT muxes LV[18]
BitsDestination
MAIN[21][67]MAIN[21][53]MAIN[21][57]MAIN[21][77]MAIN[21][59]MAIN[21][79]MAIN[21][63]LV[18]
Source
0000000off
0000011OMUX_W9
0000101DBL_W1[7]
0001001HEX_W5[7]
0010001HEX_W3[7]
0100001HEX_W4[7]
1000011OMUX[15]
1000101HEX_W2[7]
1001001DBL_E1[8]
1010001HEX_W0[7]
1100001HEX_W1[7]
virtex2 INT_IOI_CLK_S switchbox INT muxes IMUX_CLK[0]
BitsDestination
MAIN[5][41]MAIN[5][42]MAIN[5][40]MAIN[4][42]MAIN[5][49]MAIN[4][47]MAIN[4][43]MAIN[5][45]MAIN[4][45]MAIN[5][43]IMUX_CLK[0]
Source
0000000000off
0001000001GCLK[0]
0001000010GCLK[1]
0001000100GCLK[2]
0001001000HEX_N0[6]
0001010000HEX_N3[6]
0001100000HEX_S4[6]
0010000001GCLK[3]
0010000010HEX_S3[6]
0010000100GCLK[4]
0010001000HEX_S6[6]
0010010000HEX_N1[6]
0010100000HEX_N4[6]
0100000001GCLK[5]
0100000010HEX_N2[6]
0100000100HEX_N5[6]
0100001000GCLK[6]
0100010000HEX_S5[6]
0100100000HEX_S2[6]
1000000001GCLK[7]
1000000010DBL_W1[5]
1000000100DBL_E0[5]
1000001000DBL_E1[5]
1000010000DBL_W2[5]
1000100000HEX_S1[6]
virtex2 INT_IOI_CLK_S switchbox INT muxes IMUX_CLK[1]
BitsDestination
MAIN[5][47]MAIN[5][48]MAIN[5][50]MAIN[4][48]MAIN[4][50]MAIN[4][46]MAIN[4][44]MAIN[5][46]MAIN[5][44]MAIN[4][40]IMUX_CLK[1]
Source
0000000000off
0001000001GCLK[0]
0001000010GCLK[1]
0001000100GCLK[2]
0001001000HEX_N0[6]
0001010000HEX_N3[6]
0001100000HEX_S4[6]
0010000001GCLK[3]
0010000010HEX_S3[6]
0010000100GCLK[4]
0010001000HEX_S6[6]
0010010000HEX_N1[6]
0010100000HEX_N4[6]
0100000001GCLK[5]
0100000010HEX_N2[6]
0100000100HEX_N5[6]
0100001000GCLK[6]
0100010000HEX_S5[6]
0100100000HEX_S2[6]
1000000001GCLK[7]
1000000010DBL_W1[5]
1000000100DBL_E0[5]
1000001000DBL_E1[5]
1000010000DBL_W2[5]
1000100000HEX_S1[6]
virtex2 INT_IOI_CLK_S switchbox INT muxes IMUX_SR[0]
BitsDestination
MAIN[5][3]MAIN[4][3]MAIN[5][5]MAIN[4][5]MAIN[5][1]MAIN[5][2]MAIN[4][2]MAIN[5][0]IMUX_SR[0]
Source
00000000PULLUP
00010001DBL_W1[0]
00010010HEX_N1[0]
00010100HEX_N5[0]
00011000HEX_S4[0]
00100001DBL_W2[0]
00100010HEX_S5[0]
00100100HEX_S1[0]
00101000HEX_N3[0]
01000001HEX_N2[0]
01000010DBL_E0[0]
01000100HEX_S2[0]
01001000HEX_N0[0]
10000001HEX_S3[0]
10000010DBL_E1[0]
10000100HEX_N4[0]
10001000HEX_S6[0]
virtex2 INT_IOI_CLK_S switchbox INT muxes IMUX_SR[2]
BitsDestination
MAIN[4][0]MAIN[4][4]MAIN[4][8]MAIN[5][4]MAIN[5][7]MAIN[5][8]MAIN[4][6]MAIN[5][6]IMUX_SR[2]
Source
00000000PULLUP
00010001DBL_W1[0]
00010010HEX_N1[0]
00010100HEX_N5[0]
00011000HEX_S4[0]
00100001DBL_W2[0]
00100010HEX_S5[0]
00100100HEX_S1[0]
00101000HEX_N3[0]
01000001HEX_N2[0]
01000010DBL_E0[0]
01000100HEX_S2[0]
01001000HEX_N0[0]
10000001HEX_S3[0]
10000010DBL_E1[0]
10000100HEX_N4[0]
10001000HEX_S6[0]
virtex2 INT_IOI_CLK_S switchbox INT muxes IMUX_CE[0]
BitsDestination
MAIN[5][65]MAIN[4][65]MAIN[5][67]MAIN[4][67]MAIN[5][63]MAIN[5][64]MAIN[4][64]MAIN[5][62]IMUX_CE[0]
Source
00000000PULLUP
00010001DBL_W1[8]
00010010HEX_N0[9]
00010100HEX_N2[9]
00011000HEX_N3[9]
00100001DBL_W2[8]
00100010HEX_S6[9]
00100100HEX_S4[9]
00101000HEX_S3[9]
01000001HEX_S1[9]
01000010DBL_E0[8]
01000100HEX_S2[9]
01001000HEX_S5[9]
10000001HEX_N5[9]
10000010DBL_E1[8]
10000100HEX_N4[9]
10001000HEX_N1[9]
virtex2 INT_IOI_CLK_S switchbox INT muxes IMUX_CE[1]
BitsDestination
MAIN[4][62]MAIN[4][66]MAIN[4][70]MAIN[5][66]MAIN[5][69]MAIN[5][70]MAIN[4][68]MAIN[5][68]IMUX_CE[1]
Source
00000000PULLUP
00010001DBL_W1[8]
00010010HEX_N0[9]
00010100HEX_N2[9]
00011000HEX_N3[9]
00100001DBL_W2[8]
00100010HEX_S6[9]
00100100HEX_S4[9]
00101000HEX_S3[9]
01000001HEX_S1[9]
01000010DBL_E0[8]
01000100HEX_S2[9]
01001000HEX_S5[9]
10000001HEX_N5[9]
10000010DBL_E1[8]
10000100HEX_N4[9]
10001000HEX_N1[9]
virtex2 INT_IOI_CLK_S switchbox INT muxes IMUX_G0_FAN[0]
BitsDestination
MAIN[9][16]MAIN[9][19]MAIN[8][19]MAIN[8][16]MAIN[10][17]MAIN[10][19]MAIN[11][19]MAIN[11][17]MAIN[13][17]MAIN[12][19]MAIN[13][19]MAIN[12][17]IMUX_G0_FAN[0]
Source
000000000000off
000100000001OMUX_W1
000100000010OMUX_E2
000100000100OMUX_NW10
000100001000OMUX_N10
000100010000DBL_S1[0]
000100100000IMUX_G1_FAN[0]
000101000000DBL_N2[0]
000110000000IMUX_G2_FAN[0]
001000000001DBL_E0[1]
001000000010DBL_S0[0]
001000000100OMUX_EN8
001000001000DBL_W0[0]
001000010000DBL_N1[1]
001000100000DBL_S1[2]
001001000000DBL_W2[1]
001010000000DBL_S1[1]
010000000001DBL_E2[1]
010000000010DBL_S0[2]
010000000100DBL_E2[0]
010000001000DBL_E2[2]
010000010000DBL_W1[0]
010000100000DBL_E1[2]
010001000000DBL_E1[1]
010010000000DBL_N2[1]
100000000001DBL_S2[0]
100000000010DBL_S2[2]
100000000100DBL_N0[1]
100000001000DBL_S2[1]
100000010000DBL_E1[0]
100000100000DBL_W1[1]
100001000000DBL_W2[0]
100010000000DBL_N1[0]
virtex2 INT_IOI_CLK_S switchbox INT muxes IMUX_G0_FAN[1]
BitsDestination
MAIN[9][17]MAIN[9][18]MAIN[8][18]MAIN[8][17]MAIN[10][16]MAIN[10][18]MAIN[11][18]MAIN[11][16]MAIN[13][16]MAIN[12][18]MAIN[13][18]MAIN[12][16]IMUX_G0_FAN[1]
Source
000000000000off
000100000001OMUX_W1
000100000010OMUX_E2
000100000100OMUX_NW10
000100001000OMUX_N10
000100010000DBL_S1[0]
000100100000IMUX_G1_FAN[0]
000101000000DBL_N2[0]
000110000000IMUX_G2_FAN[0]
001000000001DBL_E0[1]
001000000010DBL_S0[0]
001000000100OMUX_EN8
001000001000DBL_W0[0]
001000010000DBL_N1[1]
001000100000DBL_S1[2]
001001000000DBL_W2[1]
001010000000DBL_S1[1]
010000000001DBL_E2[1]
010000000010DBL_S0[2]
010000000100DBL_E2[0]
010000001000DBL_E2[2]
010000010000DBL_W1[0]
010000100000DBL_E1[2]
010001000000DBL_E1[1]
010010000000DBL_N2[1]
100000000001DBL_S2[0]
100000000010DBL_S2[2]
100000000100DBL_N0[1]
100000001000DBL_S2[1]
100000010000DBL_E1[0]
100000100000DBL_W1[1]
100001000000DBL_W2[0]
100010000000DBL_N1[0]
virtex2 INT_IOI_CLK_S switchbox INT muxes IMUX_G0_DATA[5]
BitsDestination
MAIN[9][9]MAIN[9][10]MAIN[8][10]MAIN[8][9]MAIN[10][8]MAIN[10][10]MAIN[11][10]MAIN[11][8]MAIN[13][8]MAIN[12][10]MAIN[13][10]MAIN[12][8]IMUX_G0_DATA[5]
Source
000000000000PULLUP
000100000001OMUX_W1
000100000010OMUX_E2
000100000100OMUX_NW10
000100001000OMUX_N10
000100010000DBL_S1[0]
000100100000IMUX_G1_FAN[0]
000101000000DBL_N2[0]
000110000000IMUX_G2_FAN[0]
001000000001DBL_E0[1]
001000000010DBL_S0[0]
001000000100OMUX_EN8
001000001000DBL_W0[0]
001000010000DBL_N1[1]
001000100000DBL_S1[2]
001001000000DBL_W2[1]
001010000000DBL_S1[1]
010000000001DBL_E2[1]
010000000010DBL_S0[2]
010000000100DBL_E2[0]
010000001000DBL_E2[2]
010000010000DBL_W1[0]
010000100000DBL_E1[2]
010001000000DBL_E1[1]
010010000000DBL_N2[1]
100000000001DBL_S2[0]
100000000010DBL_S2[2]
100000000100DBL_N0[1]
100000001000DBL_S2[1]
100000010000DBL_E1[0]
100000100000DBL_W1[1]
100001000000DBL_W2[0]
100010000000DBL_N1[0]
virtex2 INT_IOI_CLK_S switchbox INT muxes IMUX_G0_DATA[6]
BitsDestination
MAIN[9][15]MAIN[9][12]MAIN[8][12]MAIN[8][15]MAIN[10][14]MAIN[10][12]MAIN[11][12]MAIN[11][14]MAIN[13][14]MAIN[12][12]MAIN[13][12]MAIN[12][14]IMUX_G0_DATA[6]
Source
000000000000PULLUP
000100000001OMUX_W1
000100000010OMUX_E2
000100000100OMUX_NW10
000100001000OMUX_N10
000100010000DBL_S1[0]
000100100000IMUX_G1_FAN[0]
000101000000DBL_N2[0]
000110000000IMUX_G2_FAN[0]
001000000001DBL_E0[1]
001000000010DBL_S0[0]
001000000100OMUX_EN8
001000001000DBL_W0[0]
001000010000DBL_N1[1]
001000100000DBL_S1[2]
001001000000DBL_W2[1]
001010000000DBL_S1[1]
010000000001DBL_E2[1]
010000000010DBL_S0[2]
010000000100DBL_E2[0]
010000001000DBL_E2[2]
010000010000DBL_W1[0]
010000100000DBL_E1[2]
010001000000DBL_E1[1]
010010000000DBL_N2[1]
100000000001DBL_S2[0]
100000000010DBL_S2[2]
100000000100DBL_N0[1]
100000001000DBL_S2[1]
100000010000DBL_E1[0]
100000100000DBL_W1[1]
100001000000DBL_W2[0]
100010000000DBL_N1[0]
virtex2 INT_IOI_CLK_S switchbox INT muxes IMUX_G0_DATA[7]
BitsDestination
MAIN[9][14]MAIN[9][13]MAIN[8][13]MAIN[8][14]MAIN[10][15]MAIN[10][13]MAIN[11][13]MAIN[11][15]MAIN[13][15]MAIN[12][13]MAIN[13][13]MAIN[12][15]IMUX_G0_DATA[7]
Source
000000000000PULLUP
000100000001OMUX_W1
000100000010OMUX_E2
000100000100OMUX_NW10
000100001000OMUX_N10
000100010000DBL_S1[0]
000100100000IMUX_G1_FAN[0]
000101000000DBL_N2[0]
000110000000IMUX_G2_FAN[0]
001000000001DBL_E0[1]
001000000010DBL_S0[0]
001000000100OMUX_EN8
001000001000DBL_W0[0]
001000010000DBL_N1[1]
001000100000DBL_S1[2]
001001000000DBL_W2[1]
001010000000DBL_S1[1]
010000000001DBL_E2[1]
010000000010DBL_S0[2]
010000000100DBL_E2[0]
010000001000DBL_E2[2]
010000010000DBL_W1[0]
010000100000DBL_E1[2]
010001000000DBL_E1[1]
010010000000DBL_N2[1]
100000000001DBL_S2[0]
100000000010DBL_S2[2]
100000000100DBL_N0[1]
100000001000DBL_S2[1]
100000010000DBL_E1[0]
100000100000DBL_W1[1]
100001000000DBL_W2[0]
100010000000DBL_N1[0]
virtex2 INT_IOI_CLK_S switchbox INT muxes IMUX_G1_FAN[0]
BitsDestination
MAIN[9][23]MAIN[9][20]MAIN[8][23]MAIN[8][20]MAIN[10][22]MAIN[10][20]MAIN[11][22]MAIN[11][20]MAIN[13][20]MAIN[13][22]MAIN[12][22]MAIN[12][20]IMUX_G1_FAN[0]
Source
000000000000off
000100000001OMUX_W6
000100000010DBL_S0[4]
000100000100DBL_W0[4]
000100001000DBL_E0[3]
000100010000DBL_W1[2]
000100100000DBL_N1[4]
000101000000DBL_W2[4]
000110000000DBL_N2[4]
001000000001OMUX_N12
001000000010OMUX_E7
001000000100OMUX_NE12
001000001000OMUX_WN14
001000010000IMUX_G3_FAN[1]
001000100000DBL_S1[3]
001001000000DBL_E1[4]
001010000000IMUX_G0_FAN[1]
010000000001DBL_E2[4]
010000000010DBL_E2[3]
010000000100DBL_W2[3]
010000001000DBL_W0[2]
010000010000DBL_N1[2]
010000100000DBL_W1[3]
010001000000DBL_W1[4]
010010000000DBL_N2[3]
100000000001DBL_N0[3]
100000000010DBL_S2[4]
100000000100DBL_S2[3]
100000001000DBL_W2[2]
100000010000DBL_S1[4]
100000100000DBL_E1[3]
100001000000DBL_N2[2]
100010000000DBL_N1[3]
virtex2 INT_IOI_CLK_S switchbox INT muxes IMUX_G1_FAN[1]
BitsDestination
MAIN[9][22]MAIN[9][21]MAIN[8][22]MAIN[8][21]MAIN[10][23]MAIN[10][21]MAIN[11][23]MAIN[11][21]MAIN[13][21]MAIN[13][23]MAIN[12][23]MAIN[12][21]IMUX_G1_FAN[1]
Source
000000000000off
000100000001OMUX_W6
000100000010DBL_S0[4]
000100000100DBL_W0[4]
000100001000DBL_E0[3]
000100010000DBL_W1[2]
000100100000DBL_N1[4]
000101000000DBL_W2[4]
000110000000DBL_N2[4]
001000000001OMUX_N12
001000000010OMUX_E7
001000000100OMUX_NE12
001000001000OMUX_WN14
001000010000IMUX_G3_FAN[1]
001000100000DBL_S1[3]
001001000000DBL_E1[4]
001010000000IMUX_G0_FAN[1]
010000000001DBL_E2[4]
010000000010DBL_E2[3]
010000000100DBL_W2[3]
010000001000DBL_W0[2]
010000010000DBL_N1[2]
010000100000DBL_W1[3]
010001000000DBL_W1[4]
010010000000DBL_N2[3]
100000000001DBL_N0[3]
100000000010DBL_S2[4]
100000000100DBL_S2[3]
100000001000DBL_W2[2]
100000010000DBL_S1[4]
100000100000DBL_E1[3]
100001000000DBL_N2[2]
100010000000DBL_N1[3]
virtex2 INT_IOI_CLK_S switchbox INT muxes IMUX_G1_DATA[5]
BitsDestination
MAIN[9][30]MAIN[9][29]MAIN[8][30]MAIN[8][29]MAIN[10][31]MAIN[10][29]MAIN[11][31]MAIN[11][29]MAIN[13][29]MAIN[13][31]MAIN[12][31]MAIN[12][29]IMUX_G1_DATA[5]
Source
000000000000PULLUP
000100000001OMUX_W6
000100000010DBL_S0[4]
000100000100DBL_W0[4]
000100001000DBL_E0[3]
000100010000DBL_W1[2]
000100100000DBL_N1[4]
000101000000DBL_W2[4]
000110000000DBL_N2[4]
001000000001OMUX_N12
001000000010OMUX_E7
001000000100OMUX_NE12
001000001000OMUX_WN14
001000010000IMUX_G3_FAN[1]
001000100000DBL_S1[3]
001001000000DBL_E1[4]
001010000000IMUX_G0_FAN[1]
010000000001DBL_E2[4]
010000000010DBL_E2[3]
010000000100DBL_W2[3]
010000001000DBL_W0[2]
010000010000DBL_N1[2]
010000100000DBL_W1[3]
010001000000DBL_W1[4]
010010000000DBL_N2[3]
100000000001DBL_N0[3]
100000000010DBL_S2[4]
100000000100DBL_S2[3]
100000001000DBL_W2[2]
100000010000DBL_S1[4]
100000100000DBL_E1[3]
100001000000DBL_N2[2]
100010000000DBL_N1[3]
virtex2 INT_IOI_CLK_S switchbox INT muxes IMUX_G1_DATA[6]
BitsDestination
MAIN[9][24]MAIN[9][27]MAIN[8][24]MAIN[8][27]MAIN[10][25]MAIN[10][27]MAIN[11][25]MAIN[11][27]MAIN[13][27]MAIN[13][25]MAIN[12][25]MAIN[12][27]IMUX_G1_DATA[6]
Source
000000000000PULLUP
000100000001OMUX_W6
000100000010DBL_S0[4]
000100000100DBL_W0[4]
000100001000DBL_E0[3]
000100010000DBL_W1[2]
000100100000DBL_N1[4]
000101000000DBL_W2[4]
000110000000DBL_N2[4]
001000000001OMUX_N12
001000000010OMUX_E7
001000000100OMUX_NE12
001000001000OMUX_WN14
001000010000IMUX_G3_FAN[1]
001000100000DBL_S1[3]
001001000000DBL_E1[4]
001010000000IMUX_G0_FAN[1]
010000000001DBL_E2[4]
010000000010DBL_E2[3]
010000000100DBL_W2[3]
010000001000DBL_W0[2]
010000010000DBL_N1[2]
010000100000DBL_W1[3]
010001000000DBL_W1[4]
010010000000DBL_N2[3]
100000000001DBL_N0[3]
100000000010DBL_S2[4]
100000000100DBL_S2[3]
100000001000DBL_W2[2]
100000010000DBL_S1[4]
100000100000DBL_E1[3]
100001000000DBL_N2[2]
100010000000DBL_N1[3]
virtex2 INT_IOI_CLK_S switchbox INT muxes IMUX_G1_DATA[7]
BitsDestination
MAIN[9][25]MAIN[9][26]MAIN[8][25]MAIN[8][26]MAIN[10][24]MAIN[10][26]MAIN[11][24]MAIN[11][26]MAIN[13][26]MAIN[13][24]MAIN[12][24]MAIN[12][26]IMUX_G1_DATA[7]
Source
000000000000PULLUP
000100000001OMUX_W6
000100000010DBL_S0[4]
000100000100DBL_W0[4]
000100001000DBL_E0[3]
000100010000DBL_W1[2]
000100100000DBL_N1[4]
000101000000DBL_W2[4]
000110000000DBL_N2[4]
001000000001OMUX_N12
001000000010OMUX_E7
001000000100OMUX_NE12
001000001000OMUX_WN14
001000010000IMUX_G3_FAN[1]
001000100000DBL_S1[3]
001001000000DBL_E1[4]
001010000000IMUX_G0_FAN[1]
010000000001DBL_E2[4]
010000000010DBL_E2[3]
010000000100DBL_W2[3]
010000001000DBL_W0[2]
010000010000DBL_N1[2]
010000100000DBL_W1[3]
010001000000DBL_W1[4]
010010000000DBL_N2[3]
100000000001DBL_N0[3]
100000000010DBL_S2[4]
100000000100DBL_S2[3]
100000001000DBL_W2[2]
100000010000DBL_S1[4]
100000100000DBL_E1[3]
100001000000DBL_N2[2]
100010000000DBL_N1[3]
virtex2 INT_IOI_CLK_S switchbox INT muxes IMUX_G2_FAN[0]
BitsDestination
MAIN[9][56]MAIN[9][59]MAIN[8][59]MAIN[8][56]MAIN[10][57]MAIN[10][59]MAIN[11][59]MAIN[11][57]MAIN[13][59]MAIN[13][57]MAIN[12][59]MAIN[12][57]IMUX_G2_FAN[0]
Source
000000000000off
000100000001OMUX_WS1
000100000010OMUX_E8
000100000100OMUX_SE3
000100001000OMUX_W9
000100010000DBL_S1[5]
000100100000IMUX_G3_FAN[0]
000101000000DBL_N2[5]
000110000000IMUX_G0_FAN[0]
001000000001DBL_E0[5]
001000000010OMUX_S3
001000000100DBL_W0[6]
001000001000DBL_S0[6]
001000010000DBL_N1[6]
001000100000DBL_S1[7]
001001000000DBL_W2[6]
001010000000DBL_S1[6]
010000000001DBL_E2[6]
010000000010DBL_E2[5]
010000000100DBL_E2[7]
010000001000DBL_E0[7]
010000010000DBL_W1[5]
010000100000DBL_E1[7]
010001000000DBL_E1[6]
010010000000DBL_N2[6]
100000000001DBL_S2[5]
100000000010DBL_N0[5]
100000000100DBL_S2[6]
100000001000DBL_S2[7]
100000010000DBL_E1[5]
100000100000DBL_W1[6]
100001000000DBL_W2[5]
100010000000DBL_N1[5]
virtex2 INT_IOI_CLK_S switchbox INT muxes IMUX_G2_FAN[1]
BitsDestination
MAIN[9][57]MAIN[9][58]MAIN[8][58]MAIN[8][57]MAIN[10][56]MAIN[10][58]MAIN[11][58]MAIN[11][56]MAIN[13][58]MAIN[13][56]MAIN[12][58]MAIN[12][56]IMUX_G2_FAN[1]
Source
000000000000off
000100000001OMUX_WS1
000100000010OMUX_E8
000100000100OMUX_SE3
000100001000OMUX_W9
000100010000DBL_S1[5]
000100100000IMUX_G3_FAN[0]
000101000000DBL_N2[5]
000110000000IMUX_G0_FAN[0]
001000000001DBL_E0[5]
001000000010OMUX_S3
001000000100DBL_W0[6]
001000001000DBL_S0[6]
001000010000DBL_N1[6]
001000100000DBL_S1[7]
001001000000DBL_W2[6]
001010000000DBL_S1[6]
010000000001DBL_E2[6]
010000000010DBL_E2[5]
010000000100DBL_E2[7]
010000001000DBL_E0[7]
010000010000DBL_W1[5]
010000100000DBL_E1[7]
010001000000DBL_E1[6]
010010000000DBL_N2[6]
100000000001DBL_S2[5]
100000000010DBL_N0[5]
100000000100DBL_S2[6]
100000001000DBL_S2[7]
100000010000DBL_E1[5]
100000100000DBL_W1[6]
100001000000DBL_W2[5]
100010000000DBL_N1[5]
virtex2 INT_IOI_CLK_S switchbox INT muxes IMUX_G3_FAN[0]
BitsDestination
MAIN[9][63]MAIN[9][60]MAIN[8][60]MAIN[8][63]MAIN[10][62]MAIN[10][60]MAIN[11][62]MAIN[11][60]MAIN[13][62]MAIN[12][62]MAIN[12][60]MAIN[13][60]IMUX_G3_FAN[0]
Source
000000000000off
000100000001OMUX_S5
000100000010OMUX_W14
000100000100OMUX_ES7
000100001000OMUX_E13
000100010000IMUX_G1_FAN[1]
000100100000DBL_S1[8]
000101000000DBL_E1[9]
000110000000IMUX_G2_FAN[1]
001000000001DBL_W0[8]
001000000010OMUX_SW5
001000000100DBL_S0[8]
001000001000DBL_E0[9]
001000010000DBL_W1[7]
001000100000DBL_N1[9]
001001000000DBL_W2[9]
001010000000DBL_N2[9]
010000000001DBL_N0[7]
010000000010DBL_E2[9]
010000000100DBL_E2[8]
010000001000DBL_W2[8]
010000010000DBL_N1[7]
010000100000DBL_W1[8]
010001000000DBL_W1[9]
010010000000DBL_N2[8]
100000000001DBL_W2[7]
100000000010DBL_N0[9]
100000000100DBL_S2[9]
100000001000DBL_S2[8]
100000010000DBL_S1[9]
100000100000DBL_E1[8]
100001000000DBL_N2[7]
100010000000DBL_N1[8]
virtex2 INT_IOI_CLK_S switchbox INT muxes IMUX_G3_FAN[1]
BitsDestination
MAIN[9][62]MAIN[9][61]MAIN[8][61]MAIN[8][62]MAIN[10][63]MAIN[10][61]MAIN[11][63]MAIN[11][61]MAIN[13][63]MAIN[12][63]MAIN[12][61]MAIN[13][61]IMUX_G3_FAN[1]
Source
000000000000off
000100000001OMUX_S5
000100000010OMUX_W14
000100000100OMUX_ES7
000100001000OMUX_E13
000100010000IMUX_G1_FAN[1]
000100100000DBL_S1[8]
000101000000DBL_E1[9]
000110000000IMUX_G2_FAN[1]
001000000001DBL_W0[8]
001000000010OMUX_SW5
001000000100DBL_S0[8]
001000001000DBL_E0[9]
001000010000DBL_W1[7]
001000100000DBL_N1[9]
001001000000DBL_W2[9]
001010000000DBL_N2[9]
010000000001DBL_N0[7]
010000000010DBL_E2[9]
010000000100DBL_E2[8]
010000001000DBL_W2[8]
010000010000DBL_N1[7]
010000100000DBL_W1[8]
010001000000DBL_W1[9]
010010000000DBL_N2[8]
100000000001DBL_W2[7]
100000000010DBL_N0[9]
100000000100DBL_S2[9]
100000001000DBL_S2[8]
100000010000DBL_S1[9]
100000100000DBL_E1[8]
100001000000DBL_N2[7]
100010000000DBL_N1[8]
virtex2 INT_IOI_CLK_S switchbox INT muxes IMUX_IOI_ICLK[0]
BitsDestination
MAIN[5][19]MAIN[5][20]MAIN[5][18]MAIN[4][20]MAIN[5][27]MAIN[4][25]MAIN[4][21]MAIN[5][23]MAIN[4][23]MAIN[5][21]IMUX_IOI_ICLK[0]
Source
0000000000off
0001000001GCLK[0]
0001000010GCLK[1]
0001000100GCLK[2]
0001001000HEX_N0[3]
0001010000HEX_N3[3]
0001100000HEX_S4[3]
0010000001GCLK[3]
0010000010HEX_S3[3]
0010000100GCLK[4]
0010001000HEX_S6[3]
0010010000HEX_N1[3]
0010100000HEX_N4[3]
0100000001GCLK[5]
0100000010HEX_N2[3]
0100000100HEX_N5[3]
0100001000GCLK[6]
0100010000HEX_S5[3]
0100100000HEX_S2[3]
1000000001GCLK[7]
1000000010DBL_E1[3]
1000000100DBL_W1[3]
1000001000DBL_W2[3]
1000010000DBL_E0[3]
1000100000HEX_S1[3]
virtex2 INT_IOI_CLK_S switchbox INT muxes IMUX_IOI_ICLK[1]
BitsDestination
MAIN[5][25]MAIN[5][26]MAIN[5][28]MAIN[4][26]MAIN[4][28]MAIN[4][24]MAIN[4][22]MAIN[5][24]MAIN[5][22]MAIN[4][18]IMUX_IOI_ICLK[1]
Source
0000000000off
0001000001GCLK[0]
0001000010GCLK[1]
0001000100GCLK[2]
0001001000HEX_N0[3]
0001010000HEX_N3[3]
0001100000HEX_S4[3]
0010000001GCLK[3]
0010000010HEX_S3[3]
0010000100GCLK[4]
0010001000HEX_S6[3]
0010010000HEX_N1[3]
0010100000HEX_N4[3]
0100000001GCLK[5]
0100000010HEX_N2[3]
0100000100HEX_N5[3]
0100001000GCLK[6]
0100010000HEX_S5[3]
0100100000HEX_S2[3]
1000000001GCLK[7]
1000000010DBL_E1[3]
1000000100DBL_W1[3]
1000001000DBL_W2[3]
1000010000DBL_E0[3]
1000100000HEX_S1[3]
virtex2 INT_IOI_CLK_S switchbox INT muxes IMUX_IOI_TS1[0]
BitsDestination
MAIN[9][6]MAIN[9][5]MAIN[8][5]MAIN[8][6]MAIN[10][7]MAIN[13][5]MAIN[12][7]MAIN[10][5]MAIN[11][5]MAIN[11][7]MAIN[13][7]MAIN[12][5]IMUX_IOI_TS1[0]
Source
000000000000PULLUP
000100000001OMUX_NW10
000100000010HEX_N4[1]
000100000100DBL_S1[0]
000100001000IMUX_G1_FAN[0]
000100010000DBL_N2[0]
000100100000HEX_N2[1]
000101000000HEX_S2[1]
000110000000IMUX_G2_FAN[0]
001000000001HEX_N0[1]
001000000010DBL_W0[0]
001000000100DBL_N1[1]
001000001000DBL_S1[2]
001000010000DBL_W2[1]
001000100000DBL_E0[1]
001001000000DBL_S0[0]
001010000000DBL_S1[1]
010000000001DBL_E2[0]
010000000010HEX_S6[1]
010000000100DBL_W1[0]
010000001000HEX_S5[1]
010000010000DBL_E1[1]
010000100000HEX_S4[1]
010001000000HEX_S1[1]
010010000000HEX_N3[1]
100000000001DBL_N0[1]
100000000010HEX_N1[1]
100000000100DBL_E1[0]
100000001000DBL_W1[1]
100000010000HEX_S3[1]
100000100000DBL_S2[0]
100001000000HEX_N5[1]
100010000000DBL_N1[0]
virtex2 INT_IOI_CLK_S switchbox INT muxes IMUX_IOI_TS1[1]
BitsDestination
MAIN[9][7]MAIN[9][4]MAIN[8][4]MAIN[8][7]MAIN[10][6]MAIN[13][4]MAIN[12][6]MAIN[10][4]MAIN[11][4]MAIN[11][6]MAIN[13][6]MAIN[12][4]IMUX_IOI_TS1[1]
Source
000000000000PULLUP
000100000001OMUX_NW10
000100000010HEX_N4[1]
000100000100DBL_S1[0]
000100001000IMUX_G1_FAN[0]
000100010000DBL_N2[0]
000100100000HEX_N2[1]
000101000000HEX_S2[1]
000110000000IMUX_G2_FAN[0]
001000000001HEX_N0[1]
001000000010DBL_W0[0]
001000000100DBL_N1[1]
001000001000DBL_S1[2]
001000010000DBL_W2[1]
001000100000DBL_E0[1]
001001000000DBL_S0[0]
001010000000DBL_S1[1]
010000000001DBL_E2[0]
010000000010HEX_S6[1]
010000000100DBL_W1[0]
010000001000HEX_S5[1]
010000010000DBL_E1[1]
010000100000HEX_S4[1]
010001000000HEX_S1[1]
010010000000HEX_N3[1]
100000000001DBL_N0[1]
100000000010HEX_N1[1]
100000000100DBL_E1[0]
100000001000DBL_W1[1]
100000010000HEX_S3[1]
100000100000DBL_S2[0]
100001000000HEX_N5[1]
100010000000DBL_N1[0]
virtex2 INT_IOI_CLK_S switchbox INT muxes IMUX_IOI_TS2[0]
BitsDestination
MAIN[9][33]MAIN[9][34]MAIN[8][34]MAIN[8][33]MAIN[10][32]MAIN[12][32]MAIN[13][34]MAIN[10][34]MAIN[11][32]MAIN[11][34]MAIN[13][32]MAIN[12][34]IMUX_IOI_TS2[0]
Source
000000000000PULLUP
000100000001OMUX_N12
000100000010HEX_S2[4]
000100000100IMUX_G3_FAN[1]
000100001000DBL_S1[3]
000100010000DBL_E1[4]
000100100000HEX_N5[4]
000101000000HEX_N3[4]
000110000000IMUX_G0_FAN[1]
001000000001HEX_N4[4]
001000000010DBL_W0[4]
001000000100DBL_W1[2]
001000001000DBL_N1[4]
001000010000DBL_W2[4]
001000100000DBL_E0[3]
001001000000DBL_S0[4]
001010000000DBL_N2[4]
010000000001DBL_E2[4]
010000000010HEX_S4[4]
010000000100HEX_S5[4]
010000001000DBL_W1[3]
010000010000DBL_W1[4]
010000100000HEX_N1[4]
010001000000HEX_S3[4]
010010000000HEX_N0[4]
100000000001DBL_N0[3]
100000000010HEX_N2[4]
100000000100DBL_S1[4]
100000001000DBL_E1[3]
100000010000HEX_S6[4]
100000100000HEX_S1[4]
100001000000DBL_S2[4]
100010000000DBL_N1[3]
virtex2 INT_IOI_CLK_S switchbox INT muxes IMUX_IOI_TS2[1]
BitsDestination
MAIN[9][32]MAIN[9][35]MAIN[8][35]MAIN[8][32]MAIN[10][33]MAIN[12][33]MAIN[13][35]MAIN[10][35]MAIN[11][33]MAIN[11][35]MAIN[13][33]MAIN[12][35]IMUX_IOI_TS2[1]
Source
000000000000PULLUP
000100000001OMUX_N12
000100000010HEX_S2[4]
000100000100IMUX_G3_FAN[1]
000100001000DBL_S1[3]
000100010000DBL_E1[4]
000100100000HEX_N5[4]
000101000000HEX_N3[4]
000110000000IMUX_G0_FAN[1]
001000000001HEX_N4[4]
001000000010DBL_W0[4]
001000000100DBL_W1[2]
001000001000DBL_N1[4]
001000010000DBL_W2[4]
001000100000DBL_E0[3]
001001000000DBL_S0[4]
001010000000DBL_N2[4]
010000000001DBL_E2[4]
010000000010HEX_S4[4]
010000000100HEX_S5[4]
010000001000DBL_W1[3]
010000010000DBL_W1[4]
010000100000HEX_N1[4]
010001000000HEX_S3[4]
010010000000HEX_N0[4]
100000000001DBL_N0[3]
100000000010HEX_N2[4]
100000000100DBL_S1[4]
100000001000DBL_E1[3]
100000010000HEX_S6[4]
100000100000HEX_S1[4]
100001000000DBL_S2[4]
100010000000DBL_N1[3]
virtex2 INT_IOI_CLK_S switchbox INT muxes IMUX_IOI_ICE[0]
BitsDestination
MAIN[9][46]MAIN[9][45]MAIN[8][45]MAIN[8][46]MAIN[10][47]MAIN[13][45]MAIN[12][47]MAIN[10][45]MAIN[11][45]MAIN[11][47]MAIN[13][47]MAIN[12][45]IMUX_IOI_ICE[0]
Source
000000000000PULLUP
000100000001OMUX_E8
000100000010HEX_S6[5]
000100000100DBL_S1[5]
000100001000IMUX_G3_FAN[0]
000100010000DBL_N2[5]
000100100000HEX_N4[5]
000101000000HEX_S3[5]
000110000000IMUX_G0_FAN[0]
001000000001HEX_N2[5]
001000000010DBL_W0[6]
001000000100DBL_N1[6]
001000001000DBL_S1[7]
001000010000DBL_W2[6]
001000100000DBL_E0[5]
001001000000DBL_S0[6]
001010000000DBL_S1[6]
010000000001DBL_E2[5]
010000000010HEX_S1[5]
010000000100DBL_W1[5]
010000001000HEX_S2[5]
010000010000DBL_E1[6]
010000100000HEX_N5[5]
010001000000HEX_S4[5]
010010000000HEX_S5[5]
100000000001DBL_N0[5]
100000000010HEX_N0[5]
100000000100DBL_E1[5]
100000001000DBL_W1[6]
100000010000HEX_N1[5]
100000100000DBL_S2[5]
100001000000HEX_N3[5]
100010000000DBL_N1[5]
virtex2 INT_IOI_CLK_S switchbox INT muxes IMUX_IOI_ICE[1]
BitsDestination
MAIN[9][47]MAIN[9][44]MAIN[8][44]MAIN[8][47]MAIN[10][46]MAIN[13][44]MAIN[12][46]MAIN[10][44]MAIN[11][44]MAIN[11][46]MAIN[13][46]MAIN[12][44]IMUX_IOI_ICE[1]
Source
000000000000PULLUP
000100000001OMUX_E8
000100000010HEX_S6[5]
000100000100DBL_S1[5]
000100001000IMUX_G3_FAN[0]
000100010000DBL_N2[5]
000100100000HEX_N4[5]
000101000000HEX_S3[5]
000110000000IMUX_G0_FAN[0]
001000000001HEX_N2[5]
001000000010DBL_W0[6]
001000000100DBL_N1[6]
001000001000DBL_S1[7]
001000010000DBL_W2[6]
001000100000DBL_E0[5]
001001000000DBL_S0[6]
001010000000DBL_S1[6]
010000000001DBL_E2[5]
010000000010HEX_S1[5]
010000000100DBL_W1[5]
010000001000HEX_S2[5]
010000010000DBL_E1[6]
010000100000HEX_N5[5]
010001000000HEX_S4[5]
010010000000HEX_S5[5]
100000000001DBL_N0[5]
100000000010HEX_N0[5]
100000000100DBL_E1[5]
100000001000DBL_W1[6]
100000010000HEX_N1[5]
100000100000DBL_S2[5]
100001000000HEX_N3[5]
100010000000DBL_N1[5]
virtex2 INT_IOI_CLK_S switchbox INT muxes IMUX_IOI_TCE[0]
BitsDestination
MAIN[9][73]MAIN[9][74]MAIN[8][74]MAIN[8][73]MAIN[10][72]MAIN[12][72]MAIN[13][72]MAIN[10][74]MAIN[11][72]MAIN[11][74]MAIN[13][74]MAIN[12][74]IMUX_IOI_TCE[0]
Source
000000000000PULLUP
000100000001OMUX_W14
000100000010HEX_S2[8]
000100000100IMUX_G1_FAN[1]
000100001000DBL_S1[8]
000100010000DBL_E1[9]
000100100000HEX_S4[8]
000101000000HEX_S5[8]
000110000000IMUX_G2_FAN[1]
001000000001HEX_N3[8]
001000000010DBL_W0[8]
001000000100DBL_W1[7]
001000001000DBL_N1[9]
001000010000DBL_W2[9]
001000100000DBL_E0[9]
001001000000DBL_S0[8]
001010000000DBL_N2[9]
010000000001DBL_E2[9]
010000000010HEX_S1[8]
010000000100HEX_N1[8]
010000001000DBL_W1[8]
010000010000DBL_W1[9]
010000100000HEX_N5[8]
010001000000HEX_S3[8]
010010000000HEX_N0[8]
100000000001DBL_N0[9]
100000000010HEX_N2[8]
100000000100DBL_S1[9]
100000001000DBL_E1[8]
100000010000HEX_S6[8]
100000100000HEX_N4[8]
100001000000DBL_S2[9]
100010000000DBL_N1[8]
virtex2 INT_IOI_CLK_S switchbox INT muxes IMUX_IOI_TCE[1]
BitsDestination
MAIN[9][72]MAIN[9][75]MAIN[8][75]MAIN[8][72]MAIN[10][73]MAIN[12][73]MAIN[13][73]MAIN[10][75]MAIN[11][73]MAIN[11][75]MAIN[13][75]MAIN[12][75]IMUX_IOI_TCE[1]
Source
000000000000PULLUP
000100000001OMUX_W14
000100000010HEX_S2[8]
000100000100IMUX_G1_FAN[1]
000100001000DBL_S1[8]
000100010000DBL_E1[9]
000100100000HEX_S4[8]
000101000000HEX_S5[8]
000110000000IMUX_G2_FAN[1]
001000000001HEX_N3[8]
001000000010DBL_W0[8]
001000000100DBL_W1[7]
001000001000DBL_N1[9]
001000010000DBL_W2[9]
001000100000DBL_E0[9]
001001000000DBL_S0[8]
001010000000DBL_N2[9]
010000000001DBL_E2[9]
010000000010HEX_S1[8]
010000000100HEX_N1[8]
010000001000DBL_W1[8]
010000010000DBL_W1[9]
010000100000HEX_N5[8]
010001000000HEX_S3[8]
010010000000HEX_N0[8]
100000000001DBL_N0[9]
100000000010HEX_N2[8]
100000000100DBL_S1[9]
100000001000DBL_E1[8]
100000010000HEX_S6[8]
100000100000HEX_N4[8]
100001000000DBL_S2[9]
100010000000DBL_N1[8]

Bitstream

virtex2 INT_IOI_CLK_S rect MAIN
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21
B79 - - - - - - INT: mux OMUX[14] bit 0 INT: mux OMUX[15] bit 8 - - - - - - INT: mux DBL_E0[9] bit 0 INT: mux DBL_W0[9] bit 7 INT: mux DBL_E0[9] bit 5 INT: mux DBL_E0[9] bit 7 INT: mux HEX_W0[9] bit 0 INT: mux HEX_W0[9] bit 3 INT: mux HEX_W0[9] bit 4 INT: mux LV[18] bit 1
B78 - - - - - - INT: mux OMUX[15] bit 7 INT: mux OMUX[15] bit 5 - - - - - - INT: mux DBL_E0[9] bit 1 INT: mux DBL_W0[9] bit 4 INT: mux DBL_W0[9] bit 3 INT: mux DBL_W0[9] bit 0 INT: mux HEX_E0[9] bit 1 INT: mux HEX_E0[9] bit 3 INT: mux HEX_E0[9] bit 5 INT: mux HEX_W0[9] bit 6
B77 - - - - - - INT: mux OMUX[15] bit 0 INT: mux OMUX[15] bit 6 - - - - - - INT: mux DBL_W0[9] bit 5 INT: mux DBL_E0[9] bit 3 INT: mux DBL_W0[9] bit 2 INT: mux DBL_W0[9] bit 1 INT: mux HEX_W0[9] bit 2 INT: mux HEX_W0[9] bit 1 INT: mux HEX_E0[9] bit 6 INT: mux LV[18] bit 3
B76 - - - - - - INT: mux OMUX[14] bit 1 INT: mux OMUX[15] bit 1 - - - - - - INT: mux DBL_W0[9] bit 6 INT: mux DBL_E0[9] bit 2 INT: mux DBL_E0[9] bit 4 INT: mux DBL_E0[9] bit 6 INT: mux HEX_E0[9] bit 2 INT: mux HEX_E0[9] bit 0 INT: mux HEX_E0[9] bit 4 INT: mux HEX_W0[9] bit 5
B75 - - - - - - INT: mux OMUX[15] bit 4 INT: mux OMUX[14] bit 4 INT: mux IMUX_IOI_TCE[1] bit 9 INT: mux IMUX_IOI_TCE[1] bit 10 INT: mux IMUX_IOI_TCE[1] bit 4 INT: mux IMUX_IOI_TCE[1] bit 2 INT: mux IMUX_IOI_TCE[1] bit 0 INT: mux IMUX_IOI_TCE[1] bit 1 INT: mux DBL_S0[9] bit 4 INT: mux DBL_N0[9] bit 2 INT: mux DBL_S0[9] bit 0 INT: mux DBL_S0[9] bit 3 INT: mux HEX_N0[9] bit 1 INT: mux HEX_N0[9] bit 3 INT: mux HEX_N0[9] bit 5 INT: mux LV[6] bit 0
B74 - - - - - - INT: mux OMUX[15] bit 2 INT: mux OMUX[14] bit 2 INT: mux IMUX_IOI_TCE[0] bit 9 INT: mux IMUX_IOI_TCE[0] bit 10 INT: mux IMUX_IOI_TCE[0] bit 4 INT: mux IMUX_IOI_TCE[0] bit 2 INT: mux IMUX_IOI_TCE[0] bit 0 INT: mux IMUX_IOI_TCE[0] bit 1 INT: mux DBL_S0[9] bit 5 INT: mux DBL_N0[9] bit 0 INT: mux DBL_N0[9] bit 7 INT: mux DBL_N0[9] bit 5 INT: mux HEX_S0[9] bit 1 INT: mux HEX_S0[9] bit 2 INT: mux HEX_S0[9] bit 4 INT: mux HEX_N0[9] bit 4
B73 - - - - - - - - INT: mux IMUX_IOI_TCE[0] bit 8 INT: mux IMUX_IOI_TCE[0] bit 11 INT: mux IMUX_IOI_TCE[1] bit 7 INT: mux IMUX_IOI_TCE[1] bit 3 INT: mux IMUX_IOI_TCE[1] bit 6 INT: mux IMUX_IOI_TCE[1] bit 5 INT: mux DBL_N0[9] bit 1 INT: mux DBL_S0[9] bit 6 INT: mux DBL_N0[9] bit 6 INT: mux DBL_N0[9] bit 4 INT: mux HEX_N0[9] bit 2 INT: mux HEX_N0[9] bit 0 INT: mux HEX_S0[9] bit 5 INT: mux LV[6] bit 6
B72 - - - - - - INT: mux OMUX[15] bit 3 INT: mux OMUX[14] bit 6 INT: mux IMUX_IOI_TCE[1] bit 8 INT: mux IMUX_IOI_TCE[1] bit 11 INT: mux IMUX_IOI_TCE[0] bit 7 INT: mux IMUX_IOI_TCE[0] bit 3 INT: mux IMUX_IOI_TCE[0] bit 6 INT: mux IMUX_IOI_TCE[0] bit 5 INT: mux DBL_N0[9] bit 3 INT: mux DBL_S0[9] bit 7 INT: mux DBL_S0[9] bit 1 INT: mux DBL_S0[9] bit 2 INT: mux HEX_S0[9] bit 3 INT: mux HEX_S0[9] bit 0 INT: mux HEX_S0[9] bit 6 INT: mux HEX_N0[9] bit 6
B71 - - - - - - INT: mux OMUX[14] bit 7 INT: mux OMUX[14] bit 5 - - - - - - INT: mux DBL_E0[8] bit 2 INT: mux DBL_W0[8] bit 3 INT: mux DBL_E0[8] bit 4 INT: mux DBL_E0[8] bit 7 INT: mux HEX_E0[8] bit 0 INT: mux HEX_E0[8] bit 3 INT: mux HEX_E0[8] bit 4 INT: mux LV[6] bit 2
B70 - - - - INT: mux IMUX_CE[1] bit 5 INT: mux IMUX_CE[1] bit 2 INT: mux OMUX[14] bit 3 INT: mux OMUX[14] bit 8 - - - - - - INT: mux DBL_E0[8] bit 0 INT: mux DBL_W0[8] bit 0 INT: mux DBL_W0[8] bit 7 INT: mux DBL_W0[8] bit 4 INT: mux HEX_W0[8] bit 0 INT: mux HEX_W0[8] bit 3 INT: mux HEX_W0[8] bit 4 INT: mux HEX_E0[8] bit 5
B69 - - - - INT: !invert IMUX_CE_OPTINV[1] ← IMUX_CE[1] INT: mux IMUX_CE[1] bit 3 INT: mux OMUX[12] bit 0 INT: mux OMUX[13] bit 8 - - - - - - INT: mux DBL_W0[8] bit 2 INT: mux DBL_E0[8] bit 3 INT: mux DBL_W0[8] bit 6 INT: mux DBL_W0[8] bit 5 INT: mux HEX_E0[8] bit 2 INT: mux HEX_E0[8] bit 1 INT: mux HEX_W0[8] bit 5 INT: mux LV[6] bit 3
B68 - - - - INT: mux IMUX_CE[1] bit 1 INT: mux IMUX_CE[1] bit 0 INT: mux OMUX[13] bit 7 INT: mux OMUX[13] bit 5 - - - - - - INT: mux DBL_W0[8] bit 1 INT: mux DBL_E0[8] bit 1 INT: mux DBL_E0[8] bit 5 INT: mux DBL_E0[8] bit 6 INT: mux HEX_W0[8] bit 2 INT: mux HEX_W0[8] bit 1 INT: mux HEX_W0[8] bit 6 INT: mux HEX_E0[8] bit 6
B67 - - - - INT: mux IMUX_CE[0] bit 4 INT: mux IMUX_CE[0] bit 5 INT: mux OMUX[13] bit 0 INT: mux OMUX[13] bit 6 - - - - - - INT: mux DBL_S0[8] bit 3 INT: mux DBL_N0[8] bit 1 INT: mux DBL_S0[8] bit 5 INT: mux DBL_S0[8] bit 7 INT: mux HEX_S0[8] bit 1 INT: mux HEX_S0[8] bit 3 INT: mux HEX_S0[8] bit 5 INT: mux LV[18] bit 6
B66 - - - - INT: mux IMUX_CE[1] bit 6 INT: mux IMUX_CE[1] bit 4 INT: mux OMUX[12] bit 1 INT: mux OMUX[13] bit 1 - - - - - - INT: mux DBL_S0[8] bit 0 INT: mux DBL_N0[8] bit 0 INT: mux DBL_N0[8] bit 7 INT: mux DBL_N0[8] bit 5 INT: mux HEX_N0[8] bit 1 INT: mux HEX_N0[8] bit 2 INT: mux HEX_N0[8] bit 5 INT: mux HEX_S0[8] bit 4
B65 - - - - INT: mux IMUX_CE[0] bit 6 INT: mux IMUX_CE[0] bit 7 INT: mux OMUX[13] bit 4 INT: mux OMUX[12] bit 4 - - - - - - INT: mux DBL_N0[8] bit 3 INT: mux DBL_S0[8] bit 1 INT: mux DBL_N0[8] bit 6 INT: mux DBL_N0[8] bit 4 INT: mux HEX_S0[8] bit 2 INT: mux HEX_S0[8] bit 0 INT: mux HEX_N0[8] bit 4 INT: mux LV[6] bit 1
B64 - - - - INT: mux IMUX_CE[0] bit 1 INT: mux IMUX_CE[0] bit 2 INT: mux OMUX[13] bit 2 INT: mux OMUX[12] bit 2 - - - - - - INT: mux DBL_N0[8] bit 2 INT: mux DBL_S0[8] bit 2 INT: mux DBL_S0[8] bit 4 INT: mux DBL_S0[8] bit 6 INT: mux HEX_N0[8] bit 3 INT: mux HEX_N0[8] bit 0 INT: mux HEX_N0[8] bit 6 INT: mux HEX_S0[8] bit 6
B63 - - - - INT: !invert IMUX_CE_OPTINV[0] ← IMUX_CE[0] INT: mux IMUX_CE[0] bit 3 - - INT: mux IMUX_G3_FAN[0] bit 8 INT: mux IMUX_G3_FAN[0] bit 11 INT: mux IMUX_G3_FAN[1] bit 7 INT: mux IMUX_G3_FAN[1] bit 5 INT: mux IMUX_G3_FAN[1] bit 2 INT: mux IMUX_G3_FAN[1] bit 3 INT: mux DBL_E0[7] bit 2 INT: mux DBL_W0[7] bit 3 INT: mux DBL_E0[7] bit 4 INT: mux DBL_E0[7] bit 7 INT: mux HEX_W0[7] bit 0 INT: mux HEX_W0[7] bit 3 INT: mux HEX_W0[7] bit 4 INT: mux LV[18] bit 0
B62 - - - - INT: mux IMUX_CE[1] bit 7 INT: mux IMUX_CE[0] bit 0 INT: mux OMUX[13] bit 3 INT: mux OMUX[12] bit 6 INT: mux IMUX_G3_FAN[1] bit 8 INT: mux IMUX_G3_FAN[1] bit 11 INT: mux IMUX_G3_FAN[0] bit 7 INT: mux IMUX_G3_FAN[0] bit 5 INT: mux IMUX_G3_FAN[0] bit 2 INT: mux IMUX_G3_FAN[0] bit 3 INT: mux DBL_E0[7] bit 0 INT: mux DBL_W0[7] bit 0 INT: mux DBL_W0[7] bit 7 INT: mux DBL_W0[7] bit 4 INT: mux HEX_E0[7] bit 0 INT: mux HEX_E0[7] bit 3 INT: mux HEX_E0[7] bit 4 INT: mux HEX_W0[7] bit 5
B61 - - - - - - INT: mux OMUX[12] bit 7 INT: mux OMUX[12] bit 5 INT: mux IMUX_G3_FAN[1] bit 9 INT: mux IMUX_G3_FAN[1] bit 10 INT: mux IMUX_G3_FAN[1] bit 6 INT: mux IMUX_G3_FAN[1] bit 4 INT: mux IMUX_G3_FAN[1] bit 1 INT: mux IMUX_G3_FAN[1] bit 0 INT: mux DBL_W0[7] bit 2 INT: mux DBL_E0[7] bit 3 INT: mux DBL_W0[7] bit 6 INT: mux DBL_W0[7] bit 5 INT: mux HEX_W0[7] bit 2 INT: mux HEX_W0[7] bit 1 INT: mux HEX_E0[7] bit 5 INT: mux LV[6] bit 5
B60 - - - - - - INT: mux OMUX[12] bit 3 INT: mux OMUX[12] bit 8 INT: mux IMUX_G3_FAN[0] bit 9 INT: mux IMUX_G3_FAN[0] bit 10 INT: mux IMUX_G3_FAN[0] bit 6 INT: mux IMUX_G3_FAN[0] bit 4 INT: mux IMUX_G3_FAN[0] bit 1 INT: mux IMUX_G3_FAN[0] bit 0 INT: mux DBL_W0[7] bit 1 INT: mux DBL_E0[7] bit 1 INT: mux DBL_E0[7] bit 5 INT: mux DBL_E0[7] bit 6 INT: mux HEX_E0[7] bit 2 INT: mux HEX_E0[7] bit 1 INT: mux HEX_E0[7] bit 6 INT: mux HEX_W0[7] bit 6
B59 - - - - - - INT: mux OMUX[10] bit 0 INT: mux OMUX[11] bit 8 INT: mux IMUX_G2_FAN[0] bit 9 INT: mux IMUX_G2_FAN[0] bit 10 INT: mux IMUX_G2_FAN[0] bit 6 INT: mux IMUX_G2_FAN[0] bit 5 INT: mux IMUX_G2_FAN[0] bit 1 INT: mux IMUX_G2_FAN[0] bit 3 INT: mux DBL_S0[7] bit 4 INT: mux DBL_N0[7] bit 6 INT: mux DBL_S0[7] bit 1 INT: mux DBL_S0[7] bit 3 INT: mux HEX_N0[7] bit 1 INT: mux HEX_N0[7] bit 3 INT: mux HEX_N0[7] bit 6 INT: mux LV[18] bit 2
B58 - - - - - - INT: mux OMUX[11] bit 7 INT: mux OMUX[11] bit 5 INT: mux IMUX_G2_FAN[1] bit 9 INT: mux IMUX_G2_FAN[1] bit 10 INT: mux IMUX_G2_FAN[1] bit 6 INT: mux IMUX_G2_FAN[1] bit 5 INT: mux IMUX_G2_FAN[1] bit 1 INT: mux IMUX_G2_FAN[1] bit 3 INT: mux DBL_S0[7] bit 5 INT: mux DBL_N0[7] bit 5 INT: mux DBL_N0[7] bit 3 INT: mux DBL_N0[7] bit 1 INT: mux HEX_S0[7] bit 1 INT: mux HEX_S0[7] bit 2 INT: mux HEX_S0[7] bit 5 INT: mux HEX_N0[7] bit 5
B57 - - - - - - INT: mux OMUX[11] bit 0 INT: mux OMUX[11] bit 6 INT: mux IMUX_G2_FAN[1] bit 8 INT: mux IMUX_G2_FAN[1] bit 11 INT: mux IMUX_G2_FAN[0] bit 7 INT: mux IMUX_G2_FAN[0] bit 4 INT: mux IMUX_G2_FAN[0] bit 0 INT: mux IMUX_G2_FAN[0] bit 2 INT: mux DBL_N0[7] bit 4 INT: mux DBL_S0[7] bit 6 INT: mux DBL_N0[7] bit 2 INT: mux DBL_N0[7] bit 0 INT: mux HEX_N0[7] bit 2 INT: mux HEX_N0[7] bit 0 INT: mux HEX_S0[7] bit 6 INT: mux LV[18] bit 4
B56 - - - - - - INT: mux OMUX[10] bit 1 INT: mux OMUX[11] bit 1 INT: mux IMUX_G2_FAN[0] bit 8 INT: mux IMUX_G2_FAN[0] bit 11 INT: mux IMUX_G2_FAN[1] bit 7 INT: mux IMUX_G2_FAN[1] bit 4 INT: mux IMUX_G2_FAN[1] bit 0 INT: mux IMUX_G2_FAN[1] bit 2 INT: mux DBL_N0[7] bit 7 INT: mux DBL_S0[7] bit 7 INT: mux DBL_S0[7] bit 0 INT: mux DBL_S0[7] bit 2 INT: mux HEX_S0[7] bit 3 INT: mux HEX_S0[7] bit 0 INT: mux HEX_S0[7] bit 4 INT: mux HEX_N0[7] bit 4
B55 - - - - - - INT: mux OMUX[11] bit 4 INT: mux OMUX[10] bit 4 - - - - - - INT: mux DBL_E0[6] bit 1 INT: mux DBL_W0[6] bit 7 INT: mux DBL_E0[6] bit 5 INT: mux DBL_E0[6] bit 7 INT: mux HEX_E0[6] bit 1 INT: mux HEX_E0[6] bit 3 INT: mux HEX_E0[6] bit 5 INT: mux LV[6] bit 4
B54 - - - - - - INT: mux OMUX[11] bit 2 INT: mux OMUX[10] bit 2 - - - - - - INT: mux DBL_E0[6] bit 0 INT: mux DBL_W0[6] bit 5 INT: mux DBL_W0[6] bit 3 INT: mux DBL_W0[6] bit 0 INT: mux HEX_W0[6] bit 1 INT: mux HEX_W0[6] bit 3 INT: mux HEX_W0[6] bit 4 INT: mux HEX_E0[6] bit 4
B53 - - - - - - - - - - - - - - INT: mux DBL_W0[6] bit 4 INT: mux DBL_E0[6] bit 3 INT: mux DBL_W0[6] bit 2 INT: mux DBL_W0[6] bit 1 INT: mux HEX_E0[6] bit 2 INT: mux HEX_E0[6] bit 0 INT: mux HEX_W0[6] bit 5 INT: mux LV[18] bit 5
B52 - - - - - - INT: mux OMUX[11] bit 3 INT: mux OMUX[10] bit 6 - - - - - - INT: mux DBL_W0[6] bit 6 INT: mux DBL_E0[6] bit 2 INT: mux DBL_E0[6] bit 4 INT: mux DBL_E0[6] bit 6 INT: mux HEX_W0[6] bit 2 INT: mux HEX_W0[6] bit 0 INT: mux HEX_W0[6] bit 6 INT: mux HEX_E0[6] bit 6
B51 - - - - - - INT: mux OMUX[10] bit 7 INT: mux OMUX[10] bit 5 - - - - - - INT: mux DBL_S0[6] bit 3 INT: mux DBL_N0[6] bit 1 INT: mux DBL_S0[6] bit 4 INT: mux DBL_S0[6] bit 7 INT: mux HEX_S0[6] bit 0 INT: mux HEX_S0[6] bit 3 INT: mux HEX_S0[6] bit 4 INT: mux LH[0] bit 0
B50 - - - - INT: mux IMUX_CLK[1] bit 5 INT: mux IMUX_CLK[1] bit 7 INT: mux OMUX[10] bit 3 INT: mux OMUX[10] bit 8 - - - - - - INT: mux DBL_S0[6] bit 0 INT: mux DBL_N0[6] bit 0 INT: mux DBL_N0[6] bit 7 INT: mux DBL_N0[6] bit 4 INT: mux HEX_N0[6] bit 0 INT: mux HEX_N0[6] bit 2 INT: mux HEX_N0[6] bit 4 INT: mux HEX_S0[6] bit 5
B49 - - - - INT: invert IMUX_CLK_OPTINV[1] ← IMUX_CLK[1] INT: mux IMUX_CLK[0] bit 5 INT: mux OMUX[8] bit 0 INT: mux OMUX[9] bit 8 - - - - - - INT: mux DBL_N0[6] bit 3 INT: mux DBL_S0[6] bit 1 INT: mux DBL_N0[6] bit 6 INT: mux DBL_N0[6] bit 5 INT: mux HEX_S0[6] bit 2 INT: mux HEX_S0[6] bit 1 INT: mux HEX_N0[6] bit 5 INT: mux LH[0] bit 1
B48 - - - - INT: mux IMUX_CLK[1] bit 6 INT: mux IMUX_CLK[1] bit 8 INT: mux OMUX[9] bit 7 INT: mux OMUX[9] bit 5 - - - - - - INT: mux DBL_N0[6] bit 2 INT: mux DBL_S0[6] bit 2 INT: mux DBL_S0[6] bit 5 INT: mux DBL_S0[6] bit 6 INT: mux HEX_N0[6] bit 3 INT: mux HEX_N0[6] bit 1 INT: mux HEX_N0[6] bit 6 INT: mux HEX_S0[6] bit 6
B47 - - - - INT: mux IMUX_CLK[0] bit 4 INT: mux IMUX_CLK[1] bit 9 INT: mux OMUX[9] bit 0 INT: mux OMUX[9] bit 6 INT: mux IMUX_IOI_ICE[1] bit 8 INT: mux IMUX_IOI_ICE[1] bit 11 INT: mux IMUX_IOI_ICE[0] bit 7 INT: mux IMUX_IOI_ICE[0] bit 2 INT: mux IMUX_IOI_ICE[0] bit 5 INT: mux IMUX_IOI_ICE[0] bit 1 INT: mux DBL_E0[5] bit 2 INT: mux DBL_W0[5] bit 3 INT: mux DBL_E0[5] bit 4 INT: mux DBL_E0[5] bit 7 INT: mux HEX_W0[5] bit 1 INT: mux HEX_W0[5] bit 3 INT: mux HEX_W0[5] bit 5 INT: mux LH[0] bit 2
B46 - - - - INT: mux IMUX_CLK[1] bit 4 INT: mux IMUX_CLK[1] bit 2 INT: mux OMUX[8] bit 1 INT: mux OMUX[9] bit 1 INT: mux IMUX_IOI_ICE[0] bit 8 INT: mux IMUX_IOI_ICE[0] bit 11 INT: mux IMUX_IOI_ICE[1] bit 7 INT: mux IMUX_IOI_ICE[1] bit 2 INT: mux IMUX_IOI_ICE[1] bit 5 INT: mux IMUX_IOI_ICE[1] bit 1 INT: mux DBL_E0[5] bit 0 INT: mux DBL_W0[5] bit 0 INT: mux DBL_W0[5] bit 7 INT: mux DBL_W0[5] bit 5 INT: mux HEX_E0[5] bit 0 INT: mux HEX_E0[5] bit 3 INT: mux HEX_E0[5] bit 4 INT: mux HEX_W0[5] bit 4
B45 - - - - INT: mux IMUX_CLK[0] bit 1 INT: mux IMUX_CLK[0] bit 2 INT: mux OMUX[9] bit 4 INT: mux OMUX[8] bit 4 INT: mux IMUX_IOI_ICE[0] bit 9 INT: mux IMUX_IOI_ICE[0] bit 10 INT: mux IMUX_IOI_ICE[0] bit 4 INT: mux IMUX_IOI_ICE[0] bit 3 INT: mux IMUX_IOI_ICE[0] bit 0 INT: mux IMUX_IOI_ICE[0] bit 6 INT: mux DBL_W0[5] bit 2 INT: mux DBL_E0[5] bit 3 INT: mux DBL_W0[5] bit 6 INT: mux DBL_W0[5] bit 4 INT: mux HEX_W0[5] bit 2 INT: mux HEX_W0[5] bit 0 INT: mux HEX_E0[5] bit 5 INT: mux LH[12] bit 1
B44 - - - - INT: mux IMUX_CLK[1] bit 3 INT: mux IMUX_CLK[1] bit 1 INT: mux OMUX[9] bit 2 INT: mux OMUX[8] bit 2 INT: mux IMUX_IOI_ICE[1] bit 9 INT: mux IMUX_IOI_ICE[1] bit 10 INT: mux IMUX_IOI_ICE[1] bit 4 INT: mux IMUX_IOI_ICE[1] bit 3 INT: mux IMUX_IOI_ICE[1] bit 0 INT: mux IMUX_IOI_ICE[1] bit 6 INT: mux DBL_W0[5] bit 1 INT: mux DBL_E0[5] bit 1 INT: mux DBL_E0[5] bit 5 INT: mux DBL_E0[5] bit 6 INT: mux HEX_E0[5] bit 2 INT: mux HEX_E0[5] bit 1 INT: mux HEX_E0[5] bit 6 INT: mux HEX_W0[5] bit 6
B43 - - - - INT: mux IMUX_CLK[0] bit 3 INT: mux IMUX_CLK[0] bit 0 - - - - - - - - INT: mux DBL_S0[5] bit 3 INT: mux DBL_N0[5] bit 1 INT: mux DBL_S0[5] bit 4 INT: mux DBL_S0[5] bit 7 INT: mux HEX_N0[5] bit 1 INT: mux HEX_N0[5] bit 3 INT: mux HEX_N0[5] bit 5 INT: mux LH[12] bit 0
B42 - - - - INT: mux IMUX_CLK[0] bit 6 INT: mux IMUX_CLK[0] bit 8 INT: mux OMUX[9] bit 3 INT: mux OMUX[8] bit 6 - - - - - - INT: mux DBL_S0[5] bit 0 INT: mux DBL_N0[5] bit 0 INT: mux DBL_N0[5] bit 7 INT: mux DBL_N0[5] bit 5 INT: mux HEX_S0[5] bit 0 INT: mux HEX_S0[5] bit 2 INT: mux HEX_S0[5] bit 4 INT: mux HEX_N0[5] bit 4
B41 - - - - INT: invert IMUX_CLK_OPTINV[0] ← IMUX_CLK[0] INT: mux IMUX_CLK[0] bit 9 INT: mux OMUX[8] bit 7 INT: mux OMUX[8] bit 5 - - - - - - INT: mux DBL_N0[5] bit 3 INT: mux DBL_S0[5] bit 1 INT: mux DBL_N0[5] bit 6 INT: mux DBL_N0[5] bit 4 INT: mux HEX_N0[5] bit 2 INT: mux HEX_N0[5] bit 0 INT: mux HEX_S0[5] bit 5 INT: mux LH[12] bit 2
B40 - - - - INT: mux IMUX_CLK[1] bit 0 INT: mux IMUX_CLK[0] bit 7 INT: mux OMUX[8] bit 3 INT: mux OMUX[8] bit 8 - - - - - - INT: mux DBL_N0[5] bit 2 INT: mux DBL_S0[5] bit 2 INT: mux DBL_S0[5] bit 5 INT: mux DBL_S0[5] bit 6 INT: mux HEX_S0[5] bit 3 INT: mux HEX_S0[5] bit 1 INT: mux HEX_S0[5] bit 6 INT: mux HEX_N0[5] bit 6
B39 - - - - - - INT: mux OMUX[6] bit 0 INT: mux OMUX[7] bit 8 - - - - - - INT: mux DBL_E0[4] bit 2 INT: mux DBL_W0[4] bit 3 INT: mux DBL_E0[4] bit 5 INT: mux DBL_E0[4] bit 7 INT: mux HEX_E0[4] bit 1 INT: mux HEX_E0[4] bit 3 INT: mux HEX_E0[4] bit 5 INT: mux LH[18] bit 2
B38 - - - - - - INT: mux OMUX[7] bit 7 INT: mux OMUX[7] bit 5 - - - - - - INT: mux DBL_E0[4] bit 0 INT: mux DBL_W0[4] bit 0 INT: mux DBL_W0[4] bit 7 INT: mux DBL_W0[4] bit 5 INT: mux HEX_W0[4] bit 1 INT: mux HEX_W0[4] bit 3 INT: mux HEX_W0[4] bit 5 INT: mux HEX_E0[4] bit 4
B37 - - - - - - INT: mux OMUX[7] bit 0 INT: mux OMUX[7] bit 6 - - - - - - INT: mux DBL_W0[4] bit 2 INT: mux DBL_E0[4] bit 3 INT: mux DBL_W0[4] bit 6 INT: mux DBL_W0[4] bit 4 INT: mux HEX_E0[4] bit 2 INT: mux HEX_E0[4] bit 0 INT: mux HEX_W0[4] bit 4 INT: mux LH[18] bit 1
B36 - - - - - - INT: mux OMUX[6] bit 1 INT: mux OMUX[7] bit 1 - - - - - - INT: mux DBL_W0[4] bit 1 INT: mux DBL_E0[4] bit 1 INT: mux DBL_E0[4] bit 4 INT: mux DBL_E0[4] bit 6 INT: mux HEX_W0[4] bit 2 INT: mux HEX_W0[4] bit 0 INT: mux HEX_W0[4] bit 6 INT: mux HEX_E0[4] bit 6
B35 - - - - - - INT: mux OMUX[7] bit 4 INT: mux OMUX[6] bit 4 INT: mux IMUX_IOI_TS2[1] bit 9 INT: mux IMUX_IOI_TS2[1] bit 10 INT: mux IMUX_IOI_TS2[1] bit 4 INT: mux IMUX_IOI_TS2[1] bit 2 INT: mux IMUX_IOI_TS2[1] bit 0 INT: mux IMUX_IOI_TS2[1] bit 5 INT: mux DBL_S0[4] bit 3 INT: mux DBL_N0[4] bit 1 INT: mux DBL_S0[4] bit 4 INT: mux DBL_S0[4] bit 7 INT: mux HEX_S0[4] bit 0 INT: mux HEX_S0[4] bit 3 INT: mux HEX_S0[4] bit 4 INT: mux LH[18] bit 0
B34 - - - - - - INT: mux OMUX[7] bit 2 INT: mux OMUX[6] bit 2 INT: mux IMUX_IOI_TS2[0] bit 9 INT: mux IMUX_IOI_TS2[0] bit 10 INT: mux IMUX_IOI_TS2[0] bit 4 INT: mux IMUX_IOI_TS2[0] bit 2 INT: mux IMUX_IOI_TS2[0] bit 0 INT: mux IMUX_IOI_TS2[0] bit 5 INT: mux DBL_S0[4] bit 0 INT: mux DBL_N0[4] bit 0 INT: mux DBL_N0[4] bit 7 INT: mux DBL_N0[4] bit 4 INT: mux HEX_N0[4] bit 0 INT: mux HEX_N0[4] bit 2 INT: mux HEX_N0[4] bit 4 INT: mux HEX_S0[4] bit 5
B33 - - - - - - - - INT: mux IMUX_IOI_TS2[0] bit 8 INT: mux IMUX_IOI_TS2[0] bit 11 INT: mux IMUX_IOI_TS2[1] bit 7 INT: mux IMUX_IOI_TS2[1] bit 3 INT: mux IMUX_IOI_TS2[1] bit 6 INT: mux IMUX_IOI_TS2[1] bit 1 INT: mux DBL_N0[4] bit 3 INT: mux DBL_S0[4] bit 1 INT: mux DBL_N0[4] bit 6 INT: mux DBL_N0[4] bit 5 INT: mux HEX_S0[4] bit 2 INT: mux HEX_S0[4] bit 1 INT: mux HEX_N0[4] bit 5 INT: mux LH[6] bit 1
B32 - - - - - - INT: mux OMUX[7] bit 3 INT: mux OMUX[6] bit 6 INT: mux IMUX_IOI_TS2[1] bit 8 INT: mux IMUX_IOI_TS2[1] bit 11 INT: mux IMUX_IOI_TS2[0] bit 7 INT: mux IMUX_IOI_TS2[0] bit 3 INT: mux IMUX_IOI_TS2[0] bit 6 INT: mux IMUX_IOI_TS2[0] bit 1 INT: mux DBL_N0[4] bit 2 INT: mux DBL_S0[4] bit 2 INT: mux DBL_S0[4] bit 5 INT: mux DBL_S0[4] bit 6 INT: mux HEX_N0[4] bit 3 INT: mux HEX_N0[4] bit 1 INT: mux HEX_N0[4] bit 6 INT: mux HEX_S0[4] bit 6
B31 - - - - - - INT: mux OMUX[6] bit 7 INT: mux OMUX[6] bit 5 - - INT: mux IMUX_G1_DATA[5] bit 7 INT: mux IMUX_G1_DATA[5] bit 5 INT: mux IMUX_G1_DATA[5] bit 1 INT: mux IMUX_G1_DATA[5] bit 2 INT: mux DBL_E0[3] bit 2 INT: mux DBL_W0[3] bit 3 INT: mux DBL_E0[3] bit 4 INT: mux DBL_E0[3] bit 7 INT: mux HEX_W0[3] bit 1 INT: mux HEX_W0[3] bit 3 INT: mux HEX_W0[3] bit 5 INT: mux LH[6] bit 2
B30 - - - - - - INT: mux OMUX[6] bit 3 INT: mux OMUX[6] bit 8 INT: mux IMUX_G1_DATA[5] bit 9 INT: mux IMUX_G1_DATA[5] bit 11 - - - - INT: mux DBL_E0[3] bit 0 INT: mux DBL_W0[3] bit 0 INT: mux DBL_W0[3] bit 7 INT: mux DBL_W0[3] bit 5 INT: mux HEX_E0[3] bit 0 INT: mux HEX_E0[3] bit 3 INT: mux HEX_E0[3] bit 4 INT: mux HEX_W0[3] bit 4
B29 - - - - - - INT: mux OMUX[4] bit 0 INT: mux OMUX[5] bit 8 INT: mux IMUX_G1_DATA[5] bit 8 INT: mux IMUX_G1_DATA[5] bit 10 INT: mux IMUX_G1_DATA[5] bit 6 INT: mux IMUX_G1_DATA[5] bit 4 INT: mux IMUX_G1_DATA[5] bit 0 INT: mux IMUX_G1_DATA[5] bit 3 INT: mux DBL_W0[3] bit 2 INT: mux DBL_E0[3] bit 3 INT: mux DBL_W0[3] bit 6 INT: mux DBL_W0[3] bit 4 INT: mux HEX_W0[3] bit 2 INT: mux HEX_W0[3] bit 0 INT: mux HEX_E0[3] bit 5 INT: mux LH[6] bit 0
B28 - - - - INT: mux IMUX_IOI_ICLK[1] bit 5 INT: mux IMUX_IOI_ICLK[1] bit 7 INT: mux OMUX[5] bit 7 INT: mux OMUX[5] bit 5 - - - - - - INT: mux DBL_W0[3] bit 1 INT: mux DBL_E0[3] bit 1 INT: mux DBL_E0[3] bit 5 INT: mux DBL_E0[3] bit 6 INT: mux HEX_E0[3] bit 2 INT: mux HEX_E0[3] bit 1 INT: mux HEX_E0[3] bit 6 INT: mux HEX_W0[3] bit 6
B27 - - - - - INT: mux IMUX_IOI_ICLK[0] bit 5 INT: mux OMUX[5] bit 0 INT: mux OMUX[5] bit 6 INT: mux IMUX_G1_DATA[6] bit 8 INT: mux IMUX_G1_DATA[6] bit 10 INT: mux IMUX_G1_DATA[6] bit 6 INT: mux IMUX_G1_DATA[6] bit 4 INT: mux IMUX_G1_DATA[6] bit 0 INT: mux IMUX_G1_DATA[6] bit 3 INT: mux DBL_S0[3] bit 3 INT: mux DBL_N0[3] bit 1 INT: mux DBL_S0[3] bit 5 INT: mux DBL_S0[3] bit 7 INT: mux HEX_N0[3] bit 0 INT: mux HEX_N0[3] bit 3 INT: mux HEX_N0[3] bit 4 INT: mux LV[12] bit 4
B26 - - - - INT: mux IMUX_IOI_ICLK[1] bit 6 INT: mux IMUX_IOI_ICLK[1] bit 8 INT: mux OMUX[4] bit 1 INT: mux OMUX[5] bit 1 INT: mux IMUX_G1_DATA[7] bit 8 INT: mux IMUX_G1_DATA[7] bit 10 INT: mux IMUX_G1_DATA[7] bit 6 INT: mux IMUX_G1_DATA[7] bit 4 INT: mux IMUX_G1_DATA[7] bit 0 INT: mux IMUX_G1_DATA[7] bit 3 INT: mux DBL_S0[3] bit 0 INT: mux DBL_N0[3] bit 0 INT: mux DBL_N0[3] bit 7 INT: mux DBL_N0[3] bit 4 INT: mux HEX_S0[3] bit 1 INT: mux HEX_S0[3] bit 2 INT: mux HEX_S0[3] bit 5 INT: mux HEX_N0[3] bit 5
B25 - - - - INT: mux IMUX_IOI_ICLK[0] bit 4 INT: mux IMUX_IOI_ICLK[1] bit 9 INT: mux OMUX[5] bit 4 INT: mux OMUX[4] bit 4 INT: mux IMUX_G1_DATA[7] bit 9 INT: mux IMUX_G1_DATA[7] bit 11 INT: mux IMUX_G1_DATA[6] bit 7 INT: mux IMUX_G1_DATA[6] bit 5 INT: mux IMUX_G1_DATA[6] bit 1 INT: mux IMUX_G1_DATA[6] bit 2 INT: mux DBL_N0[3] bit 3 INT: mux DBL_S0[3] bit 1 INT: mux DBL_N0[3] bit 6 INT: mux DBL_N0[3] bit 5 INT: mux HEX_N0[3] bit 2 INT: mux HEX_N0[3] bit 1 INT: mux HEX_S0[3] bit 4 INT: mux LV[0] bit 3
B24 - - - - INT: mux IMUX_IOI_ICLK[1] bit 4 INT: mux IMUX_IOI_ICLK[1] bit 2 INT: mux OMUX[5] bit 2 INT: mux OMUX[4] bit 2 INT: mux IMUX_G1_DATA[6] bit 9 INT: mux IMUX_G1_DATA[6] bit 11 INT: mux IMUX_G1_DATA[7] bit 7 INT: mux IMUX_G1_DATA[7] bit 5 INT: mux IMUX_G1_DATA[7] bit 1 INT: mux IMUX_G1_DATA[7] bit 2 INT: mux DBL_N0[3] bit 2 INT: mux DBL_S0[3] bit 2 INT: mux DBL_S0[3] bit 4 INT: mux DBL_S0[3] bit 6 INT: mux HEX_S0[3] bit 3 INT: mux HEX_S0[3] bit 0 INT: mux HEX_S0[3] bit 6 INT: mux HEX_N0[3] bit 6
B23 - - - - INT: mux IMUX_IOI_ICLK[0] bit 1 INT: mux IMUX_IOI_ICLK[0] bit 2 - - INT: mux IMUX_G1_FAN[0] bit 9 INT: mux IMUX_G1_FAN[0] bit 11 INT: mux IMUX_G1_FAN[1] bit 7 INT: mux IMUX_G1_FAN[1] bit 5 INT: mux IMUX_G1_FAN[1] bit 1 INT: mux IMUX_G1_FAN[1] bit 2 INT: mux DBL_E0[2] bit 4 INT: mux DBL_W0[2] bit 7 INT: mux DBL_E0[2] bit 1 INT: mux DBL_E0[2] bit 3 INT: mux HEX_E0[2] bit 1 INT: mux HEX_E0[2] bit 3 INT: mux HEX_E0[2] bit 5 INT: mux LV[12] bit 3
B22 - - - - INT: mux IMUX_IOI_ICLK[1] bit 3 INT: mux IMUX_IOI_ICLK[1] bit 1 INT: mux OMUX[5] bit 3 INT: mux OMUX[4] bit 6 INT: mux IMUX_G1_FAN[1] bit 9 INT: mux IMUX_G1_FAN[1] bit 11 INT: mux IMUX_G1_FAN[0] bit 7 INT: mux IMUX_G1_FAN[0] bit 5 INT: mux IMUX_G1_FAN[0] bit 1 INT: mux IMUX_G1_FAN[0] bit 2 INT: mux DBL_E0[2] bit 5 INT: mux DBL_W0[2] bit 5 INT: mux DBL_W0[2] bit 3 INT: mux DBL_W0[2] bit 1 INT: mux HEX_W0[2] bit 4 INT: mux HEX_W0[2] bit 6 INT: mux HEX_W0[2] bit 2 INT: mux HEX_E0[2] bit 6
B21 - - - - INT: mux IMUX_IOI_ICLK[0] bit 3 INT: mux IMUX_IOI_ICLK[0] bit 0 INT: mux OMUX[4] bit 7 INT: mux OMUX[4] bit 5 INT: mux IMUX_G1_FAN[1] bit 8 INT: mux IMUX_G1_FAN[1] bit 10 INT: mux IMUX_G1_FAN[1] bit 6 INT: mux IMUX_G1_FAN[1] bit 4 INT: mux IMUX_G1_FAN[1] bit 0 INT: mux IMUX_G1_FAN[1] bit 3 INT: mux DBL_W0[2] bit 4 INT: mux DBL_E0[2] bit 7 INT: mux DBL_W0[2] bit 2 INT: mux DBL_W0[2] bit 0 INT: mux HEX_E0[2] bit 2 INT: mux HEX_E0[2] bit 0 INT: mux HEX_W0[2] bit 1 INT: mux LV[0] bit 2
B20 - - - - INT: mux IMUX_IOI_ICLK[0] bit 6 INT: mux IMUX_IOI_ICLK[0] bit 8 INT: mux OMUX[4] bit 3 INT: mux OMUX[4] bit 8 INT: mux IMUX_G1_FAN[0] bit 8 INT: mux IMUX_G1_FAN[0] bit 10 INT: mux IMUX_G1_FAN[0] bit 6 INT: mux IMUX_G1_FAN[0] bit 4 INT: mux IMUX_G1_FAN[0] bit 0 INT: mux IMUX_G1_FAN[0] bit 3 INT: mux DBL_W0[2] bit 6 INT: mux DBL_E0[2] bit 6 INT: mux DBL_E0[2] bit 0 INT: mux DBL_E0[2] bit 2 INT: mux HEX_W0[2] bit 5 INT: mux HEX_W0[2] bit 3 INT: mux HEX_W0[2] bit 0 INT: mux HEX_E0[2] bit 4
B19 - - - - - INT: mux IMUX_IOI_ICLK[0] bit 9 INT: mux OMUX[2] bit 0 INT: mux OMUX[3] bit 8 INT: mux IMUX_G0_FAN[0] bit 9 INT: mux IMUX_G0_FAN[0] bit 10 INT: mux IMUX_G0_FAN[0] bit 6 INT: mux IMUX_G0_FAN[0] bit 5 INT: mux IMUX_G0_FAN[0] bit 2 INT: mux IMUX_G0_FAN[0] bit 1 INT: mux DBL_S0[2] bit 4 INT: mux DBL_N0[2] bit 6 INT: mux DBL_S0[2] bit 0 INT: mux DBL_S0[2] bit 3 INT: mux HEX_S0[2] bit 0 INT: mux HEX_S0[2] bit 3 INT: mux HEX_S0[2] bit 5 INT: mux LV[0] bit 4
B18 - - - - INT: mux IMUX_IOI_ICLK[1] bit 0 INT: mux IMUX_IOI_ICLK[0] bit 7 INT: mux OMUX[3] bit 7 INT: mux OMUX[3] bit 5 INT: mux IMUX_G0_FAN[1] bit 9 INT: mux IMUX_G0_FAN[1] bit 10 INT: mux IMUX_G0_FAN[1] bit 6 INT: mux IMUX_G0_FAN[1] bit 5 INT: mux IMUX_G0_FAN[1] bit 2 INT: mux IMUX_G0_FAN[1] bit 1 INT: mux DBL_S0[2] bit 5 INT: mux DBL_N0[2] bit 5 INT: mux DBL_N0[2] bit 3 INT: mux DBL_N0[2] bit 0 INT: mux HEX_N0[2] bit 1 INT: mux HEX_N0[2] bit 2 INT: mux HEX_N0[2] bit 4 INT: mux HEX_S0[2] bit 4
B17 - - - - - - INT: mux OMUX[3] bit 0 INT: mux OMUX[3] bit 6 INT: mux IMUX_G0_FAN[1] bit 8 INT: mux IMUX_G0_FAN[1] bit 11 INT: mux IMUX_G0_FAN[0] bit 7 INT: mux IMUX_G0_FAN[0] bit 4 INT: mux IMUX_G0_FAN[0] bit 0 INT: mux IMUX_G0_FAN[0] bit 3 INT: mux DBL_N0[2] bit 4 INT: mux DBL_S0[2] bit 6 INT: mux DBL_N0[2] bit 2 INT: mux DBL_N0[2] bit 1 INT: mux HEX_S0[2] bit 2 INT: mux HEX_S0[2] bit 1 INT: mux HEX_N0[2] bit 5 INT: mux LV[12] bit 2
B16 - - - - - - INT: mux OMUX[2] bit 1 INT: mux OMUX[3] bit 1 INT: mux IMUX_G0_FAN[0] bit 8 INT: mux IMUX_G0_FAN[0] bit 11 INT: mux IMUX_G0_FAN[1] bit 7 INT: mux IMUX_G0_FAN[1] bit 4 INT: mux IMUX_G0_FAN[1] bit 0 INT: mux IMUX_G0_FAN[1] bit 3 INT: mux DBL_N0[2] bit 7 INT: mux DBL_S0[2] bit 7 INT: mux DBL_S0[2] bit 1 INT: mux DBL_S0[2] bit 2 INT: mux HEX_N0[2] bit 3 INT: mux HEX_N0[2] bit 0 INT: mux HEX_N0[2] bit 6 INT: mux HEX_S0[2] bit 6
B15 - - - - - - INT: mux OMUX[3] bit 4 INT: mux OMUX[2] bit 4 INT: mux IMUX_G0_DATA[6] bit 8 INT: mux IMUX_G0_DATA[6] bit 11 INT: mux IMUX_G0_DATA[7] bit 7 INT: mux IMUX_G0_DATA[7] bit 4 INT: mux IMUX_G0_DATA[7] bit 0 INT: mux IMUX_G0_DATA[7] bit 3 INT: mux DBL_E0[1] bit 2 INT: mux DBL_W0[1] bit 3 INT: mux DBL_E0[1] bit 4 INT: mux DBL_E0[1] bit 7 INT: mux HEX_W0[1] bit 1 INT: mux HEX_W0[1] bit 2 INT: mux HEX_W0[1] bit 5 INT: mux LV[12] bit 0
B14 - - - - - - INT: mux OMUX[3] bit 2 INT: mux OMUX[2] bit 2 INT: mux IMUX_G0_DATA[7] bit 8 INT: mux IMUX_G0_DATA[7] bit 11 INT: mux IMUX_G0_DATA[6] bit 7 INT: mux IMUX_G0_DATA[6] bit 4 INT: mux IMUX_G0_DATA[6] bit 0 INT: mux IMUX_G0_DATA[6] bit 3 INT: mux DBL_E0[1] bit 0 INT: mux DBL_W0[1] bit 0 INT: mux DBL_W0[1] bit 6 INT: mux DBL_W0[1] bit 5 INT: mux HEX_E0[1] bit 0 INT: mux HEX_E0[1] bit 3 INT: mux HEX_E0[1] bit 4 INT: mux HEX_W0[1] bit 4
B13 - - - - - - - - INT: mux IMUX_G0_DATA[7] bit 9 INT: mux IMUX_G0_DATA[7] bit 10 INT: mux IMUX_G0_DATA[7] bit 6 INT: mux IMUX_G0_DATA[7] bit 5 INT: mux IMUX_G0_DATA[7] bit 2 INT: mux IMUX_G0_DATA[7] bit 1 INT: mux DBL_W0[1] bit 2 INT: mux DBL_E0[1] bit 3 INT: mux DBL_W0[1] bit 7 INT: mux DBL_W0[1] bit 4 INT: mux HEX_W0[1] bit 3 INT: mux HEX_W0[1] bit 0 INT: mux HEX_E0[1] bit 5 INT: mux LV[12] bit 6
B12 - - - - - - INT: mux OMUX[3] bit 3 INT: mux OMUX[2] bit 6 INT: mux IMUX_G0_DATA[6] bit 9 INT: mux IMUX_G0_DATA[6] bit 10 INT: mux IMUX_G0_DATA[6] bit 6 INT: mux IMUX_G0_DATA[6] bit 5 INT: mux IMUX_G0_DATA[6] bit 2 INT: mux IMUX_G0_DATA[6] bit 1 INT: mux DBL_W0[1] bit 1 INT: mux DBL_E0[1] bit 1 INT: mux DBL_E0[1] bit 5 INT: mux DBL_E0[1] bit 6 INT: mux HEX_E0[1] bit 2 INT: mux HEX_E0[1] bit 1 INT: mux HEX_E0[1] bit 6 INT: mux HEX_W0[1] bit 6
B11 - - - - - - INT: mux OMUX[2] bit 7 INT: mux OMUX[2] bit 5 - - - - - - INT: mux DBL_S0[1] bit 3 INT: mux DBL_N0[1] bit 1 INT: mux DBL_S0[1] bit 4 INT: mux DBL_S0[1] bit 7 INT: mux HEX_N0[1] bit 0 INT: mux HEX_N0[1] bit 3 INT: mux HEX_N0[1] bit 4 INT: mux LV[0] bit 1
B10 - - - - - - INT: mux OMUX[2] bit 3 INT: mux OMUX[2] bit 8 INT: mux IMUX_G0_DATA[5] bit 9 INT: mux IMUX_G0_DATA[5] bit 10 INT: mux IMUX_G0_DATA[5] bit 6 INT: mux IMUX_G0_DATA[5] bit 5 INT: mux IMUX_G0_DATA[5] bit 2 INT: mux IMUX_G0_DATA[5] bit 1 INT: mux DBL_S0[1] bit 0 INT: mux DBL_N0[1] bit 0 INT: mux DBL_N0[1] bit 7 INT: mux DBL_N0[1] bit 4 INT: mux HEX_S0[1] bit 0 INT: mux HEX_S0[1] bit 2 INT: mux HEX_S0[1] bit 4 INT: mux HEX_N0[1] bit 5
B9 - - - - - - INT: mux OMUX[0] bit 0 INT: mux OMUX[1] bit 8 INT: mux IMUX_G0_DATA[5] bit 8 INT: mux IMUX_G0_DATA[5] bit 11 - - - - INT: mux DBL_N0[1] bit 3 INT: mux DBL_S0[1] bit 1 INT: mux DBL_N0[1] bit 6 INT: mux DBL_N0[1] bit 5 INT: mux HEX_N0[1] bit 2 INT: mux HEX_N0[1] bit 1 INT: mux HEX_S0[1] bit 5 INT: mux LV[0] bit 5
B8 - - - - INT: mux IMUX_SR[2] bit 5 INT: mux IMUX_SR[2] bit 2 INT: mux OMUX[1] bit 7 INT: mux OMUX[1] bit 5 - - INT: mux IMUX_G0_DATA[5] bit 7 INT: mux IMUX_G0_DATA[5] bit 4 INT: mux IMUX_G0_DATA[5] bit 0 INT: mux IMUX_G0_DATA[5] bit 3 INT: mux DBL_N0[1] bit 2 INT: mux DBL_S0[1] bit 2 INT: mux DBL_S0[1] bit 5 INT: mux DBL_S0[1] bit 6 INT: mux HEX_S0[1] bit 3 INT: mux HEX_S0[1] bit 1 INT: mux HEX_S0[1] bit 6 INT: mux HEX_N0[1] bit 6
B7 - - - - INT: !invert IMUX_SR_OPTINV[2] ← IMUX_SR[2] INT: mux IMUX_SR[2] bit 3 INT: mux OMUX[1] bit 0 INT: mux OMUX[1] bit 6 INT: mux IMUX_IOI_TS1[1] bit 8 INT: mux IMUX_IOI_TS1[1] bit 11 INT: mux IMUX_IOI_TS1[0] bit 7 INT: mux IMUX_IOI_TS1[0] bit 2 INT: mux IMUX_IOI_TS1[0] bit 5 INT: mux IMUX_IOI_TS1[0] bit 1 INT: mux DBL_E0[0] bit 2 INT: mux DBL_W0[0] bit 3 INT: mux DBL_E0[0] bit 4 INT: mux DBL_E0[0] bit 7 INT: mux HEX_E0[0] bit 0 INT: mux HEX_E0[0] bit 3 INT: mux HEX_E0[0] bit 4 INT: mux LV[0] bit 6
B6 - - - - INT: mux IMUX_SR[2] bit 1 INT: mux IMUX_SR[2] bit 0 INT: mux OMUX[0] bit 1 INT: mux OMUX[1] bit 1 INT: mux IMUX_IOI_TS1[0] bit 8 INT: mux IMUX_IOI_TS1[0] bit 11 INT: mux IMUX_IOI_TS1[1] bit 7 INT: mux IMUX_IOI_TS1[1] bit 2 INT: mux IMUX_IOI_TS1[1] bit 5 INT: mux IMUX_IOI_TS1[1] bit 1 INT: mux DBL_E0[0] bit 0 INT: mux DBL_W0[0] bit 0 INT: mux DBL_W0[0] bit 6 INT: mux DBL_W0[0] bit 5 INT: mux HEX_W0[0] bit 1 INT: mux HEX_W0[0] bit 2 INT: mux HEX_W0[0] bit 5 INT: mux HEX_E0[0] bit 5
B5 - - - - INT: mux IMUX_SR[0] bit 4 INT: mux IMUX_SR[0] bit 5 INT: mux OMUX[1] bit 4 INT: mux OMUX[0] bit 4 INT: mux IMUX_IOI_TS1[0] bit 9 INT: mux IMUX_IOI_TS1[0] bit 10 INT: mux IMUX_IOI_TS1[0] bit 4 INT: mux IMUX_IOI_TS1[0] bit 3 INT: mux IMUX_IOI_TS1[0] bit 0 INT: mux IMUX_IOI_TS1[0] bit 6 INT: mux DBL_W0[0] bit 2 INT: mux DBL_E0[0] bit 3 INT: mux DBL_W0[0] bit 7 INT: mux DBL_W0[0] bit 4 INT: mux HEX_E0[0] bit 2 INT: mux HEX_E0[0] bit 1 INT: mux HEX_W0[0] bit 4 INT: mux LV[0] bit 0
B4 - - - - INT: mux IMUX_SR[2] bit 6 INT: mux IMUX_SR[2] bit 4 INT: mux OMUX[1] bit 2 INT: mux OMUX[0] bit 2 INT: mux IMUX_IOI_TS1[1] bit 9 INT: mux IMUX_IOI_TS1[1] bit 10 INT: mux IMUX_IOI_TS1[1] bit 4 INT: mux IMUX_IOI_TS1[1] bit 3 INT: mux IMUX_IOI_TS1[1] bit 0 INT: mux IMUX_IOI_TS1[1] bit 6 INT: mux DBL_W0[0] bit 1 INT: mux DBL_E0[0] bit 1 INT: mux DBL_E0[0] bit 5 INT: mux DBL_E0[0] bit 6 INT: mux HEX_W0[0] bit 3 INT: mux HEX_W0[0] bit 0 INT: mux HEX_W0[0] bit 6 INT: mux HEX_E0[0] bit 6
B3 - - - - INT: mux IMUX_SR[0] bit 6 INT: mux IMUX_SR[0] bit 7 - - - - - - - - INT: mux DBL_S0[0] bit 4 INT: mux DBL_N0[0] bit 6 INT: mux DBL_S0[0] bit 1 INT: mux DBL_S0[0] bit 3 INT: mux HEX_S0[0] bit 1 INT: mux HEX_S0[0] bit 3 INT: mux HEX_S0[0] bit 6 INT: mux LV[12] bit 1
B2 - - - - INT: mux IMUX_SR[0] bit 1 INT: mux IMUX_SR[0] bit 2 INT: mux OMUX[1] bit 3 INT: mux OMUX[0] bit 6 - - - - - - INT: mux DBL_S0[0] bit 5 INT: mux DBL_N0[0] bit 5 INT: mux DBL_N0[0] bit 3 INT: mux DBL_N0[0] bit 1 INT: mux HEX_N0[0] bit 1 INT: mux HEX_N0[0] bit 2 INT: mux HEX_N0[0] bit 5 INT: mux HEX_S0[0] bit 5
B1 - - - - INT: !invert IMUX_SR_OPTINV[0] ← IMUX_SR[0] INT: mux IMUX_SR[0] bit 3 INT: mux OMUX[0] bit 7 INT: mux OMUX[0] bit 5 - - - - - - INT: mux DBL_N0[0] bit 4 INT: mux DBL_S0[0] bit 6 INT: mux DBL_N0[0] bit 2 INT: mux DBL_N0[0] bit 0 INT: mux HEX_S0[0] bit 2 INT: mux HEX_S0[0] bit 0 INT: mux HEX_N0[0] bit 6 INT: mux LV[12] bit 5
B0 - - - - INT: mux IMUX_SR[2] bit 7 INT: mux IMUX_SR[0] bit 0 INT: mux OMUX[0] bit 3 INT: mux OMUX[0] bit 8 - - - - - - INT: mux DBL_N0[0] bit 7 INT: mux DBL_S0[0] bit 7 INT: mux DBL_S0[0] bit 0 INT: mux DBL_S0[0] bit 2 INT: mux HEX_N0[0] bit 3 INT: mux HEX_N0[0] bit 0 INT: mux HEX_N0[0] bit 4 INT: mux HEX_S0[0] bit 4

INT_IOI_CLK_N

Used with the IOI_CLK_N tile (Virtex 2 Pro X special IOI tile used for the dedicated reference clock).

Tile INT_IOI_CLK_N

Cells: 1

Switchbox INT

virtex2 INT_IOI_CLK_N switchbox INT programmable inverters
DestinationSourceBit
IMUX_CLK_OPTINV[2]IMUX_CLK[2]MAIN[4][52]
IMUX_CLK_OPTINV[3]IMUX_CLK[3]MAIN[4][60]
IMUX_SR_OPTINV[1]IMUX_SR[1]!MAIN[4][16]
IMUX_SR_OPTINV[3]IMUX_SR[3]!MAIN[4][10]
IMUX_CE_OPTINV[2]IMUX_CE[2]!MAIN[4][72]
IMUX_CE_OPTINV[3]IMUX_CE[3]!MAIN[4][78]
virtex2 INT_IOI_CLK_N switchbox INT muxes OMUX[0]
BitsDestination
MAIN[7][0]MAIN[6][1]MAIN[7][2]MAIN[7][1]MAIN[6][0]MAIN[6][6]MAIN[6][3]MAIN[7][5]MAIN[7][4]MAIN[6][9]OMUX[0]
Source
0000000000off
0001000001OUT_FAN[0]
0001000010OUT_FAN[2]
0001000100OUT_FAN[3]
0010001000OUT_SEC[10]
0100000100OUT_SEC[14]
0100010000OUT_SEC[13]
1000000001OUT_SEC[18]
1000001000OUT_SEC[22]
1000100000OUT_SEC[23]
virtex2 INT_IOI_CLK_N switchbox INT muxes OMUX[1]
BitsDestination
MAIN[7][9]MAIN[6][8]MAIN[7][7]MAIN[7][8]MAIN[6][2]MAIN[7][6]MAIN[7][3]MAIN[6][5]MAIN[6][4]MAIN[6][7]OMUX[1]
Source
0000000000off
0001000001OUT_FAN[0]
0001000010OUT_FAN[2]
0001000100OUT_FAN[3]
0010001000OUT_SEC[10]
0100000100OUT_SEC[14]
0100010000OUT_SEC[13]
1000000001OUT_SEC[18]
1000001000OUT_SEC[22]
1000100000OUT_SEC[23]
virtex2 INT_IOI_CLK_N switchbox INT muxes OMUX[2]
BitsDestination
MAIN[7][10]MAIN[6][11]MAIN[7][12]MAIN[7][11]MAIN[6][10]MAIN[6][16]MAIN[6][13]MAIN[7][15]MAIN[7][14]MAIN[6][19]OMUX[2]
Source
0000000000off
0001000001OUT_FAN[0]
0001000010OUT_FAN[2]
0001000100OUT_FAN[3]
0010001000OUT_SEC[10]
0100000100OUT_SEC[14]
0100010000OUT_SEC[13]
1000000001OUT_SEC[18]
1000001000OUT_SEC[22]
1000100000OUT_SEC[23]
virtex2 INT_IOI_CLK_N switchbox INT muxes OMUX[3]
BitsDestination
MAIN[7][19]MAIN[6][18]MAIN[7][17]MAIN[7][18]MAIN[6][12]MAIN[7][16]MAIN[7][13]MAIN[6][15]MAIN[6][14]MAIN[6][17]OMUX[3]
Source
0000000000off
0001000001OUT_FAN[0]
0001000010OUT_FAN[2]
0001000100OUT_FAN[3]
0010001000OUT_SEC[10]
0100000100OUT_SEC[14]
0100010000OUT_SEC[13]
1000000001OUT_SEC[18]
1000001000OUT_SEC[22]
1000100000OUT_SEC[23]
virtex2 INT_IOI_CLK_N switchbox INT muxes OMUX[4]
BitsDestination
MAIN[7][20]MAIN[6][21]MAIN[7][22]MAIN[7][21]MAIN[6][20]MAIN[6][26]MAIN[6][23]MAIN[7][25]MAIN[7][24]MAIN[6][29]OMUX[4]
Source
0000000000off
0001000001OUT_FAN[0]
0001000010OUT_FAN[2]
0001000100OUT_FAN[3]
0010001000OUT_SEC[10]
0100000100OUT_SEC[14]
0100010000OUT_SEC[13]
1000000001OUT_SEC[18]
1000001000OUT_SEC[22]
1000100000OUT_SEC[23]
virtex2 INT_IOI_CLK_N switchbox INT muxes OMUX[5]
BitsDestination
MAIN[7][29]MAIN[6][28]MAIN[7][27]MAIN[7][28]MAIN[6][22]MAIN[7][26]MAIN[7][23]MAIN[6][25]MAIN[6][24]MAIN[6][27]OMUX[5]
Source
0000000000off
0001000001OUT_FAN[0]
0001000010OUT_FAN[2]
0001000100OUT_FAN[3]
0010001000OUT_SEC[10]
0100000100OUT_SEC[14]
0100010000OUT_SEC[13]
1000000001OUT_SEC[18]
1000001000OUT_SEC[22]
1000100000OUT_SEC[23]
virtex2 INT_IOI_CLK_N switchbox INT muxes OMUX[6]
BitsDestination
MAIN[7][30]MAIN[6][31]MAIN[7][32]MAIN[7][31]MAIN[6][30]MAIN[6][36]MAIN[6][33]MAIN[7][35]MAIN[7][34]MAIN[6][39]OMUX[6]
Source
0000000000off
0001000001OUT_FAN[0]
0001000010OUT_FAN[2]
0001000100OUT_FAN[3]
0010001000OUT_SEC[10]
0100000100OUT_SEC[14]
0100010000OUT_SEC[13]
1000000001OUT_SEC[18]
1000001000OUT_SEC[22]
1000100000OUT_SEC[23]
virtex2 INT_IOI_CLK_N switchbox INT muxes OMUX[7]
BitsDestination
MAIN[7][39]MAIN[6][38]MAIN[7][37]MAIN[7][38]MAIN[6][32]MAIN[7][36]MAIN[7][33]MAIN[6][35]MAIN[6][34]MAIN[6][37]OMUX[7]
Source
0000000000off
0001000001OUT_FAN[0]
0001000010OUT_FAN[2]
0001000100OUT_FAN[3]
0010001000OUT_SEC[10]
0100000100OUT_SEC[14]
0100010000OUT_SEC[13]
1000000001OUT_SEC[18]
1000001000OUT_SEC[22]
1000100000OUT_SEC[23]
virtex2 INT_IOI_CLK_N switchbox INT muxes OMUX[8]
BitsDestination
MAIN[7][40]MAIN[6][41]MAIN[7][42]MAIN[7][41]MAIN[6][40]MAIN[6][46]MAIN[6][43]MAIN[7][45]MAIN[7][44]MAIN[6][49]OMUX[8]
Source
0000000000off
0001000001OUT_FAN[0]
0001000010OUT_FAN[2]
0001000100OUT_FAN[3]
0010001000OUT_SEC[10]
0100000100OUT_SEC[14]
0100010000OUT_SEC[13]
1000000001OUT_SEC[18]
1000001000OUT_SEC[22]
1000100000OUT_SEC[23]
virtex2 INT_IOI_CLK_N switchbox INT muxes OMUX[9]
BitsDestination
MAIN[7][49]MAIN[6][48]MAIN[7][47]MAIN[7][48]MAIN[6][42]MAIN[7][46]MAIN[7][43]MAIN[6][45]MAIN[6][44]MAIN[6][47]OMUX[9]
Source
0000000000off
0001000001OUT_FAN[0]
0001000010OUT_FAN[2]
0001000100OUT_FAN[3]
0010001000OUT_SEC[10]
0100000100OUT_SEC[14]
0100010000OUT_SEC[13]
1000000001OUT_SEC[18]
1000001000OUT_SEC[22]
1000100000OUT_SEC[23]
virtex2 INT_IOI_CLK_N switchbox INT muxes OMUX[10]
BitsDestination
MAIN[7][50]MAIN[6][51]MAIN[7][52]MAIN[7][51]MAIN[6][50]MAIN[6][56]MAIN[6][53]MAIN[7][55]MAIN[7][54]MAIN[6][59]OMUX[10]
Source
0000000000off
0001000001OUT_FAN[0]
0001000010OUT_FAN[2]
0001000100OUT_FAN[3]
0010001000OUT_SEC[10]
0100000100OUT_SEC[14]
0100010000OUT_SEC[13]
1000000001OUT_SEC[18]
1000001000OUT_SEC[22]
1000100000OUT_SEC[23]
virtex2 INT_IOI_CLK_N switchbox INT muxes OMUX[11]
BitsDestination
MAIN[7][59]MAIN[6][58]MAIN[7][57]MAIN[7][58]MAIN[6][52]MAIN[7][56]MAIN[7][53]MAIN[6][55]MAIN[6][54]MAIN[6][57]OMUX[11]
Source
0000000000off
0001000001OUT_FAN[0]
0001000010OUT_FAN[2]
0001000100OUT_FAN[3]
0010001000OUT_SEC[10]
0100000100OUT_SEC[14]
0100010000OUT_SEC[13]
1000000001OUT_SEC[18]
1000001000OUT_SEC[22]
1000100000OUT_SEC[23]
virtex2 INT_IOI_CLK_N switchbox INT muxes OMUX[12]
BitsDestination
MAIN[7][60]MAIN[6][61]MAIN[7][62]MAIN[7][61]MAIN[6][60]MAIN[6][66]MAIN[6][63]MAIN[7][65]MAIN[7][64]MAIN[6][69]OMUX[12]
Source
0000000000off
0001000001OUT_FAN[0]
0001000010OUT_FAN[2]
0001000100OUT_FAN[3]
0010001000OUT_SEC[10]
0100000100OUT_SEC[14]
0100010000OUT_SEC[13]
1000000001OUT_SEC[18]
1000001000OUT_SEC[22]
1000100000OUT_SEC[23]
virtex2 INT_IOI_CLK_N switchbox INT muxes OMUX[13]
BitsDestination
MAIN[7][69]MAIN[6][68]MAIN[7][67]MAIN[7][68]MAIN[6][62]MAIN[7][66]MAIN[7][63]MAIN[6][65]MAIN[6][64]MAIN[6][67]OMUX[13]
Source
0000000000off
0001000001OUT_FAN[0]
0001000010OUT_FAN[2]
0001000100OUT_FAN[3]
0010001000OUT_SEC[10]
0100000100OUT_SEC[14]
0100010000OUT_SEC[13]
1000000001OUT_SEC[18]
1000001000OUT_SEC[22]
1000100000OUT_SEC[23]
virtex2 INT_IOI_CLK_N switchbox INT muxes OMUX[14]
BitsDestination
MAIN[7][70]MAIN[6][71]MAIN[7][72]MAIN[7][71]MAIN[6][70]MAIN[6][76]MAIN[6][73]MAIN[7][75]MAIN[7][74]MAIN[6][79]OMUX[14]
Source
0000000000off
0001000001OUT_FAN[0]
0001000010OUT_FAN[2]
0001000100OUT_FAN[3]
0010001000OUT_SEC[10]
0100000100OUT_SEC[14]
0100010000OUT_SEC[13]
1000000001OUT_SEC[18]
1000001000OUT_SEC[22]
1000100000OUT_SEC[23]
virtex2 INT_IOI_CLK_N switchbox INT muxes OMUX[15]
BitsDestination
MAIN[7][79]MAIN[6][78]MAIN[7][77]MAIN[7][78]MAIN[6][72]MAIN[7][76]MAIN[7][73]MAIN[6][75]MAIN[6][74]MAIN[6][77]OMUX[15]
Source
0000000000off
0001000001OUT_FAN[0]
0001000010OUT_FAN[2]
0001000100OUT_FAN[3]
0010001000OUT_SEC[10]
0100000100OUT_SEC[14]
0100010000OUT_SEC[13]
1000000001OUT_SEC[18]
1000001000OUT_SEC[22]
1000100000OUT_SEC[23]
virtex2 INT_IOI_CLK_N switchbox INT muxes DBL_W0[0]
BitsDestination
MAIN[16][5]MAIN[16][6]MAIN[17][6]MAIN[17][5]MAIN[15][7]MAIN[14][5]MAIN[14][4]MAIN[15][6]DBL_W0[0]
Source
00000000off
00010001OMUX_S0
00010010HEX_E6[0]
00010100OUT_FAN[3]
00011000HEX_N6[0]
00100001OMUX_NW10
00100010HEX_S6[1]
00101000HEX_W6[0]
01000001DBL_W2[0]
01000010HEX_N3[0]
01000100HEX_S3[0]
01001000DBL_N3[9]
10000001DBL_W2_N[8]
10000010DBL_S1[0]
10000100DBL_S2[2]
10001000DBL_N1[0]
virtex2 INT_IOI_CLK_N switchbox INT muxes DBL_W0[1]
BitsDestination
MAIN[16][13]MAIN[16][14]MAIN[17][14]MAIN[17][13]MAIN[15][15]MAIN[14][13]MAIN[14][12]MAIN[15][14]DBL_W0[1]
Source
00000000off
00010001OMUX[2]
00010010HEX_E6[1]
00010100OUT_FAN[2]
00011000HEX_N6[1]
00100001OMUX_W1
00100010HEX_S6[2]
00101000HEX_W6[1]
01000001DBL_W2[1]
01000010HEX_N3[1]
01000100HEX_S3[1]
01001000DBL_N2[0]
10000001DBL_W2_N[9]
10000010DBL_S1[1]
10000100DBL_S2[3]
10001000DBL_N1[1]
virtex2 INT_IOI_CLK_N switchbox INT muxes DBL_W0[2]
BitsDestination
MAIN[15][23]MAIN[14][20]MAIN[15][22]MAIN[14][21]MAIN[16][22]MAIN[16][21]MAIN[17][22]MAIN[17][21]DBL_W0[2]
Source
00000000off
00010001OMUX[4]
00010010OUT_FAN[3]
00010100DBL_S2[4]
00011000HEX_S3[2]
00100001OMUX[6]
00100010OMUX_WN14
00100100DBL_W2[0]
00101000DBL_W2[2]
01000001HEX_E6[2]
01000010HEX_S6[3]
01000100DBL_S1[2]
01001000HEX_N3[2]
10000001HEX_N6[2]
10000010HEX_W6[2]
10000100DBL_N1[2]
10001000DBL_N2[1]
virtex2 INT_IOI_CLK_N switchbox INT muxes DBL_W0[3]
BitsDestination
MAIN[16][30]MAIN[16][29]MAIN[17][30]MAIN[17][29]MAIN[15][31]MAIN[14][29]MAIN[14][28]MAIN[15][30]DBL_W0[3]
Source
00000000off
00010001OMUX_W6
00010010HEX_E6[3]
00011000HEX_N6[3]
00100001OMUX_NW10
00100010HEX_S6[4]
00100100OUT_FAN[2]
00101000HEX_W6[3]
01000001DBL_W2[1]
01000010DBL_S1[3]
01000100DBL_S2[5]
01001000DBL_N1[3]
10000001DBL_W2[3]
10000010HEX_N3[3]
10000100HEX_S3[3]
10001000DBL_N2[2]
virtex2 INT_IOI_CLK_N switchbox INT muxes DBL_W0[4]
BitsDestination
MAIN[16][38]MAIN[16][37]MAIN[17][38]MAIN[17][37]MAIN[15][39]MAIN[14][37]MAIN[14][36]MAIN[15][38]DBL_W0[4]
Source
00000000off
00010001OMUX_WS1
00010010HEX_E6[4]
00011000HEX_N6[4]
00100001OMUX_N12
00100010HEX_S6[5]
00101000HEX_W6[4]
01000001DBL_W2[2]
01000010DBL_S1[4]
01000100DBL_S2[6]
01001000DBL_N1[4]
10000001DBL_W2[4]
10000010HEX_N3[4]
10000100HEX_S3[4]
10001000DBL_N2[3]
virtex2 INT_IOI_CLK_N switchbox INT muxes DBL_W0[5]
BitsDestination
MAIN[16][46]MAIN[16][45]MAIN[17][46]MAIN[17][45]MAIN[15][47]MAIN[14][45]MAIN[14][44]MAIN[15][46]DBL_W0[5]
Source
00000000off
00010001OMUX_S3
00010010HEX_E6[5]
00011000HEX_N6[5]
00100001OMUX_WN14
00100010HEX_S6[6]
00101000HEX_W6[5]
01000001DBL_W2[3]
01000010DBL_S1[5]
01000100DBL_S2[7]
01001000DBL_N1[5]
10000001DBL_W2[5]
10000010HEX_N3[5]
10000100HEX_S3[5]
10001000DBL_N2[4]
virtex2 INT_IOI_CLK_N switchbox INT muxes DBL_W0[6]
BitsDestination
MAIN[15][55]MAIN[14][52]MAIN[15][54]MAIN[14][53]MAIN[16][54]MAIN[16][53]MAIN[17][53]MAIN[17][54]DBL_W0[6]
Source
00000000off
00010001OMUX[11]
00010010OUT_FAN[0]
00010100DBL_S2[8]
00011000HEX_S3[6]
00100001OMUX_W9
00100010OMUX_SW5
00100100DBL_W2[4]
00101000DBL_W2[6]
01000001HEX_S6[7]
01000010HEX_E6[6]
01000100DBL_S1[6]
01001000HEX_N3[6]
10000001HEX_W6[6]
10000010HEX_N6[6]
10000100DBL_N1[6]
10001000DBL_N2[5]
virtex2 INT_IOI_CLK_N switchbox INT muxes DBL_W0[7]
BitsDestination
MAIN[16][62]MAIN[16][61]MAIN[17][61]MAIN[17][62]MAIN[15][63]MAIN[14][61]MAIN[14][60]MAIN[15][62]DBL_W0[7]
Source
00000000off
00010001OMUX[9]
00010010HEX_S6[8]
00011000HEX_W6[7]
00100001OMUX_WS1
00100010HEX_E6[7]
00101000HEX_N6[7]
01000001DBL_W2[5]
01000010DBL_S1[7]
01000100DBL_S2[9]
01001000DBL_N1[7]
10000001DBL_W2[7]
10000010HEX_N3[7]
10000100HEX_S3[7]
10001000DBL_N2[6]
virtex2 INT_IOI_CLK_N switchbox INT muxes DBL_W0[8]
BitsDestination
MAIN[16][70]MAIN[16][69]MAIN[17][69]MAIN[17][70]MAIN[15][71]MAIN[14][69]MAIN[14][68]MAIN[15][70]DBL_W0[8]
Source
00000000off
00010001OMUX[13]
00010010HEX_S6[9]
00010100OUT_FAN[0]
00011000HEX_W6[8]
00100001OMUX_W14
00100010HEX_E6[8]
00101000HEX_N6[8]
01000001DBL_W2[6]
01000010DBL_S1[8]
01000100DBL_S3[0]
01001000DBL_N1[8]
10000001DBL_W2[8]
10000010HEX_N3[8]
10000100HEX_S3[8]
10001000DBL_N2[7]
virtex2 INT_IOI_CLK_N switchbox INT muxes DBL_W0[9]
BitsDestination
MAIN[15][79]MAIN[14][76]MAIN[14][77]MAIN[15][78]MAIN[16][78]MAIN[16][77]MAIN[17][77]MAIN[17][78]DBL_W0[9]
Source
00000000off
00010001OMUX[13]
00010010OMUX_SW5
00010100DBL_W2[7]
00011000DBL_W2[9]
00100001OMUX_S0
00100010OMUX[15]
00100100DBL_S3[1]
00101000HEX_S3[9]
01000001HEX_S7[0]
01000010HEX_E6[9]
01000100DBL_S1[9]
01001000HEX_N3[9]
10000001HEX_W6[9]
10000010HEX_N6[9]
10000100DBL_N1[9]
10001000DBL_N2[8]
virtex2 INT_IOI_CLK_N switchbox INT muxes DBL_E0[0]
BitsDestination
MAIN[17][7]MAIN[17][4]MAIN[16][4]MAIN[16][7]MAIN[15][5]MAIN[14][7]MAIN[15][4]MAIN[14][6]DBL_E0[0]
Source
00000000off
00010001OMUX_E2
00010010HEX_S6[1]
00011000HEX_W6[0]
00100001OMUX_EN8
00100010HEX_E6[0]
00100100OUT_FAN[3]
00101000HEX_N6[0]
01000001DBL_E2[0]
01000010DBL_S1[0]
01000100DBL_S2[2]
01001000DBL_N1[0]
10000001DBL_E2[2]
10000010HEX_N3[0]
10000100HEX_S3[0]
10001000DBL_N3[9]
virtex2 INT_IOI_CLK_N switchbox INT muxes DBL_E0[1]
BitsDestination
MAIN[17][15]MAIN[17][12]MAIN[16][12]MAIN[16][15]MAIN[15][13]MAIN[14][15]MAIN[15][12]MAIN[14][14]DBL_E0[1]
Source
00000000off
00010001OMUX_S4
00010010HEX_S6[2]
00011000HEX_W6[1]
00100001OMUX_N10
00100010HEX_E6[1]
00100100OUT_FAN[2]
00101000HEX_N6[1]
01000001DBL_E2[1]
01000010DBL_S1[1]
01000100DBL_S2[3]
01001000DBL_N1[1]
10000001DBL_E2[3]
10000010HEX_N3[1]
10000100HEX_S3[1]
10001000DBL_N2[0]
virtex2 INT_IOI_CLK_N switchbox INT muxes DBL_E0[2]
BitsDestination
MAIN[15][21]MAIN[15][20]MAIN[14][22]MAIN[14][23]MAIN[17][23]MAIN[17][20]MAIN[16][23]MAIN[16][20]DBL_E0[2]
Source
00000000off
00010001OMUX[4]
00010010OUT_FAN[3]
00010100DBL_S2[4]
00011000HEX_S3[2]
00100001OMUX_NE12
00100010OMUX[6]
00100100DBL_E2[2]
00101000DBL_E2[4]
01000001HEX_E6[2]
01000010HEX_S6[3]
01000100DBL_S1[2]
01001000HEX_N3[2]
10000001HEX_N6[2]
10000010HEX_W6[2]
10000100DBL_N1[2]
10001000DBL_N2[1]
virtex2 INT_IOI_CLK_N switchbox INT muxes DBL_E0[3]
BitsDestination
MAIN[17][31]MAIN[17][28]MAIN[16][28]MAIN[16][31]MAIN[15][29]MAIN[14][31]MAIN[15][28]MAIN[14][30]DBL_E0[3]
Source
00000000off
00010001OMUX_SE3
00010010HEX_S6[4]
00010100OUT_FAN[2]
00011000HEX_W6[3]
00100001OMUX_EN8
00100010HEX_E6[3]
00101000HEX_N6[3]
01000001DBL_E2[3]
01000010DBL_S1[3]
01000100DBL_S2[5]
01001000DBL_N1[3]
10000001DBL_E2[5]
10000010HEX_N3[3]
10000100HEX_S3[3]
10001000DBL_N2[2]
virtex2 INT_IOI_CLK_N switchbox INT muxes DBL_E0[4]
BitsDestination
MAIN[17][39]MAIN[17][36]MAIN[16][39]MAIN[16][36]MAIN[15][37]MAIN[14][39]MAIN[15][36]MAIN[14][38]DBL_E0[4]
Source
00000000off
00010001OMUX_E7
00010010HEX_E6[4]
00011000HEX_N6[4]
00100001OMUX_E8
00100010HEX_S6[5]
00101000HEX_W6[4]
01000001DBL_E2[4]
01000010DBL_S1[4]
01000100DBL_S2[6]
01001000DBL_N1[4]
10000001DBL_E2[6]
10000010HEX_N3[4]
10000100HEX_S3[4]
10001000DBL_N2[3]
virtex2 INT_IOI_CLK_N switchbox INT muxes DBL_E0[5]
BitsDestination
MAIN[17][47]MAIN[17][44]MAIN[16][44]MAIN[16][47]MAIN[15][45]MAIN[14][47]MAIN[15][44]MAIN[14][46]DBL_E0[5]
Source
00000000off
00010001OMUX_ES7
00010010HEX_S6[6]
00011000HEX_W6[5]
00100001OMUX_NE12
00100010HEX_E6[5]
00101000HEX_N6[5]
01000001DBL_E2[5]
01000010DBL_S1[5]
01000100DBL_S2[7]
01001000DBL_N1[5]
10000001DBL_E2[7]
10000010HEX_N3[5]
10000100HEX_S3[5]
10001000DBL_N2[4]
virtex2 INT_IOI_CLK_N switchbox INT muxes DBL_E0[6]
BitsDestination
MAIN[17][55]MAIN[17][52]MAIN[16][55]MAIN[16][52]MAIN[15][53]MAIN[15][52]MAIN[14][55]MAIN[14][54]DBL_E0[6]
Source
00000000off
00010001OMUX[9]
00010010OUT_FAN[0]
00010100HEX_E6[6]
00011000HEX_N6[6]
00100001OMUX_SE3
00100010OMUX[11]
00100100HEX_S6[7]
00101000HEX_W6[6]
01000001DBL_E2[6]
01000010DBL_S2[8]
01000100DBL_S1[6]
01001000DBL_N1[6]
10000001DBL_E2[8]
10000010HEX_S3[6]
10000100HEX_N3[6]
10001000DBL_N2[5]
virtex2 INT_IOI_CLK_N switchbox INT muxes DBL_E0[7]
BitsDestination
MAIN[17][63]MAIN[17][60]MAIN[16][60]MAIN[16][63]MAIN[15][61]MAIN[14][63]MAIN[15][60]MAIN[14][62]DBL_E0[7]
Source
00000000off
00010001OMUX_S5
00010010HEX_S6[8]
00011000HEX_W6[7]
00100001OMUX_N11
00100010HEX_E6[7]
00101000HEX_N6[7]
01000001DBL_E2[7]
01000010DBL_S1[7]
01000100DBL_S2[9]
01001000DBL_N1[7]
10000001DBL_E2[9]
10000010HEX_N3[7]
10000100HEX_S3[7]
10001000DBL_N2[6]
virtex2 INT_IOI_CLK_N switchbox INT muxes DBL_E0[8]
BitsDestination
MAIN[17][71]MAIN[17][68]MAIN[16][68]MAIN[16][71]MAIN[15][69]MAIN[14][71]MAIN[15][68]MAIN[14][70]DBL_E0[8]
Source
00000000off
00010001OMUX_ES7
00010010HEX_S6[9]
00010100OUT_FAN[0]
00011000HEX_W6[8]
00100001OMUX_E13
00100010HEX_E6[8]
00101000HEX_N6[8]
01000001DBL_E2[8]
01000010DBL_S1[8]
01000100DBL_S3[0]
01001000DBL_N1[8]
10000001DBL_E2_S[0]
10000010HEX_N3[8]
10000100HEX_S3[8]
10001000DBL_N2[7]
virtex2 INT_IOI_CLK_N switchbox INT muxes DBL_E0[9]
BitsDestination
MAIN[17][79]MAIN[17][76]MAIN[16][79]MAIN[16][76]MAIN[15][77]MAIN[15][76]MAIN[14][78]MAIN[14][79]DBL_E0[9]
Source
00000000off
00010001OMUX[15]
00010010OMUX_N15
00010100HEX_E6[9]
00011000HEX_N6[9]
00100001OMUX_S0
00100010OMUX_S2
00100100HEX_S7[0]
00101000HEX_W6[9]
01000001DBL_S3[1]
01000010DBL_E2[9]
01000100DBL_S1[9]
01001000DBL_N1[9]
10000001HEX_S3[9]
10000010DBL_E2_S[1]
10000100HEX_N3[9]
10001000DBL_N2[8]
virtex2 INT_IOI_CLK_N switchbox INT muxes DBL_S0[0]
BitsDestination
MAIN[15][0]MAIN[15][1]MAIN[14][2]MAIN[14][3]MAIN[17][3]MAIN[17][0]MAIN[16][3]MAIN[16][0]DBL_S0[0]
Source
00000000off
00010001OMUX[0]
00010010OUT_FAN[3]
00010100DBL_E2[1]
00011000HEX_E3[0]
00100001OMUX[2]
00100010OMUX_S0
00100100DBL_S2[0]
00101000DBL_S2[2]
01000001HEX_W6_N[9]
01000010HEX_N6[0]
01000100DBL_W1[0]
01001000DBL_W2_N[8]
10000001HEX_S6[0]
10000010HEX_E6[0]
10000100DBL_E1[0]
10001000HEX_W3[0]
virtex2 INT_IOI_CLK_N switchbox INT muxes DBL_S0[1]
BitsDestination
MAIN[17][11]MAIN[17][8]MAIN[16][8]MAIN[16][11]MAIN[14][11]MAIN[15][8]MAIN[15][9]MAIN[14][10]DBL_S0[1]
Source
00000000off
00010001OMUX[2]
00010010HEX_N6[1]
00010100HEX_E6[1]
00011000OUT_FAN[2]
00100001OMUX_E2
00100010HEX_W6[0]
00100100HEX_S6[1]
01000001DBL_S2[1]
01000010DBL_W1[1]
01000100DBL_E1[1]
01001000DBL_E2[2]
10000001DBL_S2[3]
10000010DBL_W2_N[9]
10000100HEX_W3[1]
10001000HEX_E3[1]
virtex2 INT_IOI_CLK_N switchbox INT muxes DBL_S0[2]
BitsDestination
MAIN[15][16]MAIN[15][17]MAIN[14][18]MAIN[14][19]MAIN[17][19]MAIN[17][16]MAIN[16][16]MAIN[16][19]DBL_S0[2]
Source
00000000off
00010001OMUX[4]
00010100DBL_E2[3]
00011000HEX_E3[2]
00100001OMUX[6]
00100010OMUX_S4
00100100DBL_S2[2]
00101000DBL_S2[4]
01000001HEX_N6[2]
01000010HEX_W6[1]
01000100DBL_W1[2]
01001000DBL_W2[0]
10000001HEX_E6[2]
10000010HEX_S6[2]
10000100DBL_E1[2]
10001000HEX_W3[2]
virtex2 INT_IOI_CLK_N switchbox INT muxes DBL_S0[3]
BitsDestination
MAIN[17][27]MAIN[17][24]MAIN[16][27]MAIN[16][24]MAIN[14][27]MAIN[15][24]MAIN[15][25]MAIN[14][26]DBL_S0[3]
Source
00000000off
00010001OMUX[6]
00010010HEX_W6[2]
00010100HEX_S6[3]
00011000OUT_FAN[3]
00100001OMUX_W6
00100010HEX_N6[3]
00100100HEX_E6[3]
01000001DBL_S2[3]
01000010DBL_W1[3]
01000100DBL_E1[3]
01001000DBL_E2[4]
10000001DBL_S2[5]
10000010DBL_W2[1]
10000100HEX_W3[3]
10001000HEX_E3[3]
virtex2 INT_IOI_CLK_N switchbox INT muxes DBL_S0[4]
BitsDestination
MAIN[17][35]MAIN[17][32]MAIN[16][32]MAIN[16][35]MAIN[14][35]MAIN[15][32]MAIN[15][33]MAIN[14][34]DBL_S0[4]
Source
00000000off
00010001OMUX_WS1
00010010HEX_N6[4]
00010100HEX_E6[4]
00100001OMUX_SE3
00100010HEX_W6[3]
00100100HEX_S6[4]
00101000OUT_FAN[2]
01000001DBL_S2[4]
01000010DBL_W1[4]
01000100DBL_E1[4]
01001000DBL_E2[5]
10000001DBL_S2[6]
10000010DBL_W2[2]
10000100HEX_W3[4]
10001000HEX_E3[4]
virtex2 INT_IOI_CLK_N switchbox INT muxes DBL_S0[5]
BitsDestination
MAIN[17][43]MAIN[17][40]MAIN[16][40]MAIN[16][43]MAIN[14][43]MAIN[15][40]MAIN[15][41]MAIN[14][42]DBL_S0[5]
Source
00000000off
00010001OMUX_S3
00010010HEX_N6[5]
00010100HEX_E6[5]
00100001OMUX_E8
00100010HEX_W6[4]
00100100HEX_S6[5]
01000001DBL_S2[5]
01000010DBL_W1[5]
01000100DBL_E1[5]
01001000DBL_E2[6]
10000001DBL_S2[7]
10000010DBL_W2[3]
10000100HEX_W3[5]
10001000HEX_E3[5]
virtex2 INT_IOI_CLK_N switchbox INT muxes DBL_S0[6]
BitsDestination
MAIN[17][51]MAIN[17][48]MAIN[16][48]MAIN[16][51]MAIN[14][51]MAIN[15][48]MAIN[15][49]MAIN[14][50]DBL_S0[6]
Source
00000000off
00010001OMUX_SW5
00010010HEX_N6[6]
00010100HEX_E6[6]
00011000OUT_FAN[0]
00100001OMUX_ES7
00100010HEX_W6[5]
00100100HEX_S6[6]
01000001DBL_S2[6]
01000010DBL_W1[6]
01000100DBL_E1[6]
01001000DBL_E2[7]
10000001DBL_S2[8]
10000010DBL_W2[4]
10000100HEX_W3[6]
10001000HEX_E3[6]
virtex2 INT_IOI_CLK_N switchbox INT muxes DBL_S0[7]
BitsDestination
MAIN[15][56]MAIN[15][57]MAIN[14][58]MAIN[14][59]MAIN[17][59]MAIN[17][56]MAIN[16][59]MAIN[16][56]DBL_S0[7]
Source
00000000off
00010001OMUX[11]
00010100DBL_E2[8]
00011000HEX_E3[7]
00100001OMUX_SE3
00100010OMUX_WS1
00100100DBL_S2[7]
00101000DBL_S2[9]
01000001HEX_W6[6]
01000010HEX_N6[7]
01000100DBL_W1[7]
01001000DBL_W2[5]
10000001HEX_S6[7]
10000010HEX_E6[7]
10000100DBL_E1[7]
10001000HEX_W3[7]
virtex2 INT_IOI_CLK_N switchbox INT muxes DBL_S0[8]
BitsDestination
MAIN[17][67]MAIN[17][64]MAIN[16][67]MAIN[16][64]MAIN[14][67]MAIN[15][64]MAIN[15][65]MAIN[14][66]DBL_S0[8]
Source
00000000off
00010001OMUX_S5
00010010HEX_W6[7]
00010100HEX_S6[8]
00100001OMUX_W14
00100010HEX_N6[8]
00100100HEX_E6[8]
01000001DBL_S2[8]
01000010DBL_W1[8]
01000100DBL_E1[8]
01001000DBL_E2[9]
10000001DBL_S3[0]
10000010DBL_W2[6]
10000100HEX_W3[8]
10001000HEX_E3[8]
virtex2 INT_IOI_CLK_N switchbox INT muxes DBL_S0[9]
BitsDestination
MAIN[15][72]MAIN[15][73]MAIN[14][74]MAIN[14][75]MAIN[17][75]MAIN[17][72]MAIN[16][72]MAIN[16][75]DBL_S0[9]
Source
00000000off
00010001OMUX[15]
00010010OUT_FAN[0]
00010100DBL_E2_S[0]
00011000HEX_E3[9]
00100001OMUX_SW5
00100010OMUX_ES7
00100100DBL_S2[9]
00101000DBL_S3[1]
01000001HEX_N6[9]
01000010HEX_W6[8]
01000100DBL_W1[9]
01001000DBL_W2[7]
10000001HEX_E6[9]
10000010HEX_S6[9]
10000100DBL_E1[9]
10001000HEX_W3[9]
virtex2 INT_IOI_CLK_N switchbox INT muxes DBL_N0[0]
BitsDestination
MAIN[14][0]MAIN[15][3]MAIN[15][2]MAIN[14][1]MAIN[16][2]MAIN[16][1]MAIN[17][2]MAIN[17][1]DBL_N0[0]
Source
00000000off
00010001OMUX[0]
00010010OUT_FAN[3]
00010100DBL_E2[1]
00011000HEX_E3[0]
00100001OMUX_N13
00100010OMUX_EN8
00100100DBL_N3[8]
00101000DBL_N2[0]
01000001HEX_W6_N[9]
01000010HEX_N6[0]
01000100DBL_W1[0]
01001000DBL_W2_N[8]
10000001HEX_S6[0]
10000010HEX_E6[0]
10000100DBL_E1[0]
10001000HEX_W3[0]
virtex2 INT_IOI_CLK_N switchbox INT muxes DBL_N0[1]
BitsDestination
MAIN[16][10]MAIN[16][9]MAIN[17][9]MAIN[17][10]MAIN[14][9]MAIN[14][8]MAIN[15][11]MAIN[15][10]DBL_N0[1]
Source
00000000off
00010001OMUX_N10
00010010HEX_N6[1]
00010100HEX_E6[1]
00011000OUT_FAN[2]
00100001OMUX_NW10
00100010HEX_W6[0]
00100100HEX_S6[1]
01000001DBL_N3[9]
01000010DBL_W1[1]
01000100DBL_E1[1]
01001000DBL_E2[2]
10000001DBL_N2[1]
10000010DBL_W2_N[9]
10000100HEX_W3[1]
10001000HEX_E3[1]
virtex2 INT_IOI_CLK_N switchbox INT muxes DBL_N0[2]
BitsDestination
MAIN[14][16]MAIN[15][19]MAIN[15][18]MAIN[14][17]MAIN[16][18]MAIN[16][17]MAIN[17][17]MAIN[17][18]DBL_N0[2]
Source
00000000off
00010001OMUX[4]
00010100DBL_E2[3]
00011000HEX_E3[2]
00100001OMUX_NE12
00100010OMUX_W1
00100100DBL_N2[0]
00101000DBL_N2[2]
01000001HEX_N6[2]
01000010HEX_W6[1]
01000100DBL_W1[2]
01001000DBL_W2[0]
10000001HEX_E6[2]
10000010HEX_S6[2]
10000100DBL_E1[2]
10001000HEX_W3[2]
virtex2 INT_IOI_CLK_N switchbox INT muxes DBL_N0[3]
BitsDestination
MAIN[16][26]MAIN[16][25]MAIN[17][25]MAIN[17][26]MAIN[14][25]MAIN[14][24]MAIN[15][27]MAIN[15][26]DBL_N0[3]
Source
00000000off
00010001OMUX_EN8
00010010HEX_N6[3]
00010100HEX_E6[3]
00100001OMUX_WN14
00100010HEX_W6[2]
00100100HEX_S6[3]
00101000OUT_FAN[3]
01000001DBL_N2[1]
01000010DBL_W1[3]
01000100DBL_E1[3]
01001000DBL_E2[4]
10000001DBL_N2[3]
10000010DBL_W2[1]
10000100HEX_W3[3]
10001000HEX_E3[3]
virtex2 INT_IOI_CLK_N switchbox INT muxes DBL_N0[4]
BitsDestination
MAIN[16][34]MAIN[16][33]MAIN[17][33]MAIN[17][34]MAIN[14][33]MAIN[14][32]MAIN[15][35]MAIN[15][34]DBL_N0[4]
Source
00000000off
00010001OMUX_E7
00010010HEX_N6[4]
00010100HEX_E6[4]
00100001OMUX_NW10
00100010HEX_W6[3]
00100100HEX_S6[4]
00101000OUT_FAN[2]
01000001DBL_N2[2]
01000010DBL_W1[4]
01000100DBL_E1[4]
01001000DBL_E2[5]
10000001DBL_N2[4]
10000010DBL_W2[2]
10000100HEX_W3[4]
10001000HEX_E3[4]
virtex2 INT_IOI_CLK_N switchbox INT muxes DBL_N0[5]
BitsDestination
MAIN[16][42]MAIN[16][41]MAIN[17][42]MAIN[17][41]MAIN[14][41]MAIN[14][40]MAIN[15][43]MAIN[15][42]DBL_N0[5]
Source
00000000off
00010001OMUX_N12
00010010HEX_W6[4]
00010100HEX_S6[5]
00100001OMUX_NE12
00100010HEX_N6[5]
00100100HEX_E6[5]
01000001DBL_N2[3]
01000010DBL_W1[5]
01000100DBL_E1[5]
01001000DBL_E2[6]
10000001DBL_N2[5]
10000010DBL_W2[3]
10000100HEX_W3[5]
10001000HEX_E3[5]
virtex2 INT_IOI_CLK_N switchbox INT muxes DBL_N0[6]
BitsDestination
MAIN[16][50]MAIN[16][49]MAIN[17][49]MAIN[17][50]MAIN[14][49]MAIN[14][48]MAIN[15][51]MAIN[15][50]DBL_N0[6]
Source
00000000off
00010001OMUX[9]
00010010HEX_N6[6]
00010100HEX_E6[6]
00011000OUT_FAN[0]
00100001OMUX_WN14
00100010HEX_W6[5]
00100100HEX_S6[6]
01000001DBL_N2[4]
01000010DBL_W1[6]
01000100DBL_E1[6]
01001000DBL_E2[7]
10000001DBL_N2[6]
10000010DBL_W2[4]
10000100HEX_W3[6]
10001000HEX_E3[6]
virtex2 INT_IOI_CLK_N switchbox INT muxes DBL_N0[7]
BitsDestination
MAIN[14][56]MAIN[15][59]MAIN[15][58]MAIN[14][57]MAIN[16][58]MAIN[16][57]MAIN[17][58]MAIN[17][57]DBL_N0[7]
Source
00000000off
00010001OMUX[11]
00010100DBL_E2[8]
00011000HEX_E3[7]
00100001OMUX_W9
00100010OMUX_N11
00100100DBL_N2[5]
00101000DBL_N2[7]
01000001HEX_W6[6]
01000010HEX_N6[7]
01000100DBL_W1[7]
01001000DBL_W2[5]
10000001HEX_S6[7]
10000010HEX_E6[7]
10000100DBL_E1[7]
10001000HEX_W3[7]
virtex2 INT_IOI_CLK_N switchbox INT muxes DBL_N0[8]
BitsDestination
MAIN[16][66]MAIN[16][65]MAIN[17][66]MAIN[17][65]MAIN[14][65]MAIN[14][64]MAIN[15][67]MAIN[15][66]DBL_N0[8]
Source
00000000off
00010001OMUX[9]
00010010HEX_W6[7]
00010100HEX_S6[8]
00100001OMUX_E13
00100010HEX_N6[8]
00100100HEX_E6[8]
01000001DBL_N2[6]
01000010DBL_W1[8]
01000100DBL_E1[8]
01001000DBL_E2[9]
10000001DBL_N2[8]
10000010DBL_W2[6]
10000100HEX_W3[8]
10001000HEX_E3[8]
virtex2 INT_IOI_CLK_N switchbox INT muxes DBL_N0[9]
BitsDestination
MAIN[16][74]MAIN[16][73]MAIN[17][74]MAIN[17][73]MAIN[14][72]MAIN[15][75]MAIN[14][73]MAIN[15][74]DBL_N0[9]
Source
00000000off
00010001OMUX[13]
00010010OUT_FAN[0]
00010100HEX_W6[8]
00011000HEX_S6[9]
00100001OMUX_N15
00100010OMUX[15]
00100100HEX_N6[9]
00101000HEX_E6[9]
01000001DBL_N2[7]
01000010DBL_E2_S[0]
01000100DBL_W1[9]
01001000DBL_E1[9]
10000001DBL_N2[9]
10000010HEX_E3[9]
10000100DBL_W2[7]
10001000HEX_W3[9]
virtex2 INT_IOI_CLK_N switchbox INT muxes HEX_W0[0]
BitsDestination
MAIN[20][4]MAIN[20][6]MAIN[20][5]MAIN[18][4]MAIN[19][6]MAIN[18][6]MAIN[19][4]HEX_W0[0]
Source
0000000off
0010001OMUX_S0
0010010HEX_S3[0]
0010100HEX_N3[0]
0011000LH[6]
0100010OMUX_NW10
0100100HEX_W6[0]
0101000HEX_W6_N[8]
1000001OUT_FAN[3]
1000010LH[18]
1000100HEX_N7[9]
1001000HEX_S6[2]
virtex2 INT_IOI_CLK_N switchbox INT muxes HEX_W0[1]
BitsDestination
MAIN[21][12]MAIN[20][15]MAIN[21][14]MAIN[18][13]MAIN[19][15]MAIN[18][15]MAIN[19][13]HEX_W0[1]
Source
0000000off
0010001OMUX[2]
0010100HEX_W6[1]
0011000HEX_W6_N[9]
0100001LH[0]
0100010OMUX_W1
0100100HEX_S3[1]
0101000HEX_N3[1]
1000001OUT_FAN[2]
1000010LH[12]
1000100HEX_N6[0]
1001000HEX_S6[3]
virtex2 INT_IOI_CLK_N switchbox INT muxes HEX_W0[2]
BitsDestination
MAIN[20][22]MAIN[20][21]MAIN[20][20]MAIN[19][22]MAIN[18][20]MAIN[18][22]MAIN[19][20]HEX_W0[2]
Source
0000000off
0010001OMUX[4]
0010010LH[18]
0010100HEX_S6[4]
0011000HEX_N6[1]
0100001OMUX[6]
0100010HEX_S3[2]
0100100LH[6]
0101000HEX_N3[2]
1000001OUT_FAN[3]
1000010OMUX_WN14
1000100HEX_W6[0]
1001000HEX_W6[2]
virtex2 INT_IOI_CLK_N switchbox INT muxes HEX_W0[3]
BitsDestination
MAIN[21][28]MAIN[20][31]MAIN[21][30]MAIN[19][31]MAIN[18][29]MAIN[18][31]MAIN[19][29]HEX_W0[3]
Source
0000000off
0010001OMUX_W6
0010010OUT_FAN[2]
0010100HEX_W6[1]
0011000HEX_W6[3]
0100001LH[0]
0100010OMUX_NW10
0100100HEX_N3[3]
0101000HEX_S3[3]
1000010LH[12]
1000100HEX_S6[5]
1001000HEX_N6[2]
virtex2 INT_IOI_CLK_N switchbox INT muxes HEX_W0[4]
BitsDestination
MAIN[20][36]MAIN[20][38]MAIN[20][37]MAIN[19][38]MAIN[18][36]MAIN[18][38]MAIN[19][36]HEX_W0[4]
Source
0000000off
0010001OMUX_WS1
0010010HEX_S3[4]
0010100LH[6]
0011000HEX_N3[4]
0100010OMUX_N12
0100100HEX_W6[2]
0101000HEX_W6[4]
1000010LH[18]
1000100HEX_S6[6]
1001000HEX_N6[3]
virtex2 INT_IOI_CLK_N switchbox INT muxes HEX_W0[5]
BitsDestination
MAIN[21][44]MAIN[20][47]MAIN[21][46]MAIN[19][47]MAIN[18][45]MAIN[18][47]MAIN[19][45]HEX_W0[5]
Source
0000000off
0010001OMUX_S3
0010100HEX_W6[3]
0011000HEX_W6[5]
0100001LH[0]
0100010OMUX_WN14
0100100HEX_N3[5]
0101000HEX_S3[5]
1000010LH[12]
1000100HEX_S6[7]
1001000HEX_N6[4]
virtex2 INT_IOI_CLK_N switchbox INT muxes HEX_W0[6]
BitsDestination
MAIN[20][52]MAIN[20][53]MAIN[20][54]MAIN[19][54]MAIN[18][52]MAIN[18][54]MAIN[19][52]HEX_W0[6]
Source
0000000off
0010001OMUX[11]
0010010OMUX_W9
0010100HEX_W6[4]
0011000HEX_W6[6]
0100001OMUX_SW5
0100010HEX_S3[6]
0100100LH[6]
0101000HEX_N3[6]
1000001OUT_FAN[0]
1000010LH[18]
1000100HEX_S6[8]
1001000HEX_N6[5]
virtex2 INT_IOI_CLK_N switchbox INT muxes HEX_W0[7]
BitsDestination
MAIN[21][60]MAIN[21][62]MAIN[20][63]MAIN[19][63]MAIN[18][61]MAIN[19][61]MAIN[18][63]HEX_W0[7]
Source
0000000off
0010001OMUX[9]
0010010LH[0]
0010100HEX_N3[7]
0011000HEX_S3[7]
0100010OMUX_WS1
0100100HEX_W6[5]
0101000HEX_W6[7]
1000001LH[12]
1000100HEX_S6[9]
1001000HEX_N6[6]
virtex2 INT_IOI_CLK_N switchbox INT muxes HEX_W0[8]
BitsDestination
MAIN[20][68]MAIN[20][69]MAIN[20][70]MAIN[19][70]MAIN[18][68]MAIN[19][68]MAIN[18][70]HEX_W0[8]
Source
0000000off
0010001OMUX[13]
0010010OUT_FAN[0]
0010100HEX_W6[6]
0011000HEX_W6[8]
0100001HEX_S3[8]
0100010OMUX_W14
0100100LH[6]
0101000HEX_N3[8]
1000001LH[18]
1000100HEX_S7[0]
1001000HEX_N6[7]
virtex2 INT_IOI_CLK_N switchbox INT muxes HEX_W0[9]
BitsDestination
MAIN[21][78]MAIN[21][76]MAIN[20][79]MAIN[19][79]MAIN[18][77]MAIN[19][77]MAIN[18][79]HEX_W0[9]
Source
0000000off
0010001OMUX[13]
0010010LH[0]
0010100HEX_N3[9]
0011000HEX_S3[9]
0100001LH[12]
0100010OMUX[15]
0100100HEX_S7[1]
0101000HEX_N6[8]
1000001OMUX_S0
1000010OMUX_SW5
1000100HEX_W6[7]
1001000HEX_W6[9]
virtex2 INT_IOI_CLK_N switchbox INT muxes HEX_E0[0]
BitsDestination
MAIN[21][4]MAIN[21][6]MAIN[20][7]MAIN[19][7]MAIN[18][5]MAIN[19][5]MAIN[18][7]HEX_E0[0]
Source
0000000off
0010001OMUX_E2
0010010LH[6]
0010100HEX_N3[0]
0011000HEX_S3[0]
0100010OMUX_EN8
0100100HEX_E6[0]
0101000HEX_E6[2]
1000001LH[18]
1000010OUT_FAN[3]
1000100HEX_S6[2]
1001000HEX_N7[9]
virtex2 INT_IOI_CLK_N switchbox INT muxes HEX_E0[1]
BitsDestination
MAIN[20][12]MAIN[20][13]MAIN[20][14]MAIN[19][14]MAIN[18][12]MAIN[19][12]MAIN[18][14]HEX_E0[1]
Source
0000000off
0010001OMUX_S4
0010100HEX_E6[1]
0011000HEX_E6[3]
0100001HEX_S3[1]
0100010OMUX_N10
0100100LH[0]
0101000HEX_N3[1]
1000001LH[12]
1000010OUT_FAN[2]
1000100HEX_S6[3]
1001000HEX_N6[0]
virtex2 INT_IOI_CLK_N switchbox INT muxes HEX_E0[2]
BitsDestination
MAIN[21][22]MAIN[20][23]MAIN[21][20]MAIN[19][23]MAIN[18][21]MAIN[18][23]MAIN[19][21]HEX_E0[2]
Source
0000000off
0010001OMUX[4]
0010010LH[18]
0010100HEX_S6[4]
0011000HEX_N6[1]
0100001LH[6]
0100010OMUX[6]
0100100HEX_N3[2]
0101000HEX_S3[2]
1000001OMUX_NE12
1000010OUT_FAN[3]
1000100HEX_E6[2]
1001000HEX_E6[4]
virtex2 INT_IOI_CLK_N switchbox INT muxes HEX_E0[3]
BitsDestination
MAIN[20][28]MAIN[20][29]MAIN[20][30]MAIN[19][30]MAIN[18][28]MAIN[19][28]MAIN[18][30]HEX_E0[3]
Source
0000000off
0010001OMUX_SE3
0010010OUT_FAN[2]
0010100HEX_E6[3]
0011000HEX_E6[5]
0100001HEX_S3[3]
0100010OMUX_EN8
0100100LH[0]
0101000HEX_N3[3]
1000001LH[12]
1000100HEX_S6[5]
1001000HEX_N6[2]
virtex2 INT_IOI_CLK_N switchbox INT muxes HEX_E0[4]
BitsDestination
MAIN[21][36]MAIN[20][39]MAIN[21][38]MAIN[19][39]MAIN[18][37]MAIN[18][39]MAIN[19][37]HEX_E0[4]
Source
0000000off
0010001OMUX_E7
0010100HEX_E6[4]
0011000HEX_E6[6]
0100001LH[6]
0100010OMUX_E8
0100100HEX_N3[4]
0101000HEX_S3[4]
1000010LH[18]
1000100HEX_S6[6]
1001000HEX_N6[3]
virtex2 INT_IOI_CLK_N switchbox INT muxes HEX_E0[5]
BitsDestination
MAIN[20][44]MAIN[20][45]MAIN[20][46]MAIN[19][46]MAIN[18][44]MAIN[19][44]MAIN[18][46]HEX_E0[5]
Source
0000000off
0010001OMUX_ES7
0010100HEX_E6[5]
0011000HEX_E6[7]
0100001HEX_S3[5]
0100010OMUX_NE12
0100100LH[0]
0101000HEX_N3[5]
1000001LH[12]
1000100HEX_S6[7]
1001000HEX_N6[4]
virtex2 INT_IOI_CLK_N switchbox INT muxes HEX_E0[6]
BitsDestination
MAIN[21][52]MAIN[20][55]MAIN[21][54]MAIN[19][55]MAIN[18][53]MAIN[18][55]MAIN[19][53]HEX_E0[6]
Source
0000000off
0010001OMUX[9]
0010010OMUX[11]
0010100HEX_E6[6]
0011000HEX_E6[8]
0100001LH[6]
0100010OMUX_SE3
0100100HEX_N3[6]
0101000HEX_S3[6]
1000001OUT_FAN[0]
1000010LH[18]
1000100HEX_S6[8]
1001000HEX_N6[5]
virtex2 INT_IOI_CLK_N switchbox INT muxes HEX_E0[7]
BitsDestination
MAIN[20][60]MAIN[20][61]MAIN[20][62]MAIN[19][62]MAIN[18][60]MAIN[19][60]MAIN[18][62]HEX_E0[7]
Source
0000000off
0010001OMUX_S5
0010100HEX_E6[7]
0011000HEX_E6[9]
0100001HEX_S3[7]
0100010OMUX_N11
0100100LH[0]
0101000HEX_N3[7]
1000001LH[12]
1000100HEX_S6[9]
1001000HEX_N6[6]
virtex2 INT_IOI_CLK_N switchbox INT muxes HEX_E0[8]
BitsDestination
MAIN[21][68]MAIN[21][70]MAIN[20][71]MAIN[19][71]MAIN[18][69]MAIN[19][69]MAIN[18][71]HEX_E0[8]
Source
0000000off
0010001OMUX_ES7
0010010LH[6]
0010100HEX_N3[8]
0011000HEX_S3[8]
0100001OUT_FAN[0]
0100010OMUX_E13
0100100HEX_E6[8]
0101000HEX_E6_S[0]
1000001LH[18]
1000100HEX_S7[0]
1001000HEX_N6[7]
virtex2 INT_IOI_CLK_N switchbox INT muxes HEX_E0[9]
BitsDestination
MAIN[20][77]MAIN[20][78]MAIN[20][76]MAIN[19][78]MAIN[18][76]MAIN[18][78]MAIN[19][76]HEX_E0[9]
Source
0000000off
0010001OMUX[15]
0010010LH[12]
0010100HEX_S7[1]
0011000HEX_N6[8]
0100001OMUX_S0
0100010OMUX_S2
0100100HEX_E6[9]
0101000HEX_E6_S[1]
1000001OMUX_N15
1000010HEX_S3[9]
1000100LH[0]
1001000HEX_N3[9]
virtex2 INT_IOI_CLK_N switchbox INT muxes HEX_S0[0]
BitsDestination
MAIN[20][3]MAIN[21][2]MAIN[21][0]MAIN[19][3]MAIN[18][1]MAIN[18][3]MAIN[19][1]HEX_S0[0]
Source
0000000off
0010001OMUX[0]
0010010LV[0]
0010100HEX_E6[1]
0011000HEX_W6_N[8]
0100001OMUX[2]
0100010OUT_FAN[3]
0100100HEX_S6[0]
0101000HEX_S6[2]
1000001LV[12]
1000010OMUX_S0
1000100HEX_W3[0]
1001000HEX_E3[0]
virtex2 INT_IOI_CLK_N switchbox INT muxes HEX_S0[1]
BitsDestination
MAIN[20][8]MAIN[20][9]MAIN[20][10]MAIN[18][8]MAIN[19][10]MAIN[19][8]MAIN[18][10]HEX_S0[1]
Source
0000000off
0010001OMUX[2]
0010010OUT_FAN[2]
0010100HEX_S6[3]
0011000HEX_S6[1]
0100001HEX_E3[1]
0100010OMUX_E2
0100100HEX_W3[1]
0101000LV[18]
1000001LV[6]
1000100HEX_W6_N[9]
1001000HEX_E6[2]
virtex2 INT_IOI_CLK_N switchbox INT muxes HEX_S0[2]
BitsDestination
MAIN[21][16]MAIN[20][19]MAIN[21][18]MAIN[19][19]MAIN[18][17]MAIN[19][17]MAIN[18][19]HEX_S0[2]
Source
0000000off
0010001OMUX[4]
0010010OMUX_S4
0010100HEX_S6[2]
0011000HEX_S6[4]
0100001OMUX[6]
0100010LV[12]
0100100HEX_W3[2]
0101000HEX_E3[2]
1000001LV[0]
1000100HEX_E6[3]
1001000HEX_W6[0]
virtex2 INT_IOI_CLK_N switchbox INT muxes HEX_S0[3]
BitsDestination
MAIN[20][24]MAIN[20][26]MAIN[20][25]MAIN[18][24]MAIN[19][26]MAIN[18][26]MAIN[19][24]HEX_S0[3]
Source
0000000off
0010001OMUX[6]
0010010HEX_E3[3]
0010100HEX_W3[3]
0011000LV[18]
0100010OMUX_W6
0100100HEX_S6[5]
0101000HEX_S6[3]
1000001OUT_FAN[3]
1000010LV[6]
1000100HEX_W6[1]
1001000HEX_E6[4]
virtex2 INT_IOI_CLK_N switchbox INT muxes HEX_S0[4]
BitsDestination
MAIN[21][32]MAIN[21][34]MAIN[20][35]MAIN[19][35]MAIN[18][33]MAIN[19][33]MAIN[18][35]HEX_S0[4]
Source
0000000off
0010001OMUX_WS1
0010010LV[12]
0010100HEX_W3[4]
0011000HEX_E3[4]
0100010OMUX_SE3
0100100HEX_S6[4]
0101000HEX_S6[6]
1000001LV[0]
1000010OUT_FAN[2]
1000100HEX_E6[5]
1001000HEX_W6[2]
virtex2 INT_IOI_CLK_N switchbox INT muxes HEX_S0[5]
BitsDestination
MAIN[20][40]MAIN[20][41]MAIN[20][42]MAIN[18][40]MAIN[19][42]MAIN[19][40]MAIN[18][42]HEX_S0[5]
Source
0000000off
0010001OMUX_S3
0010100HEX_S6[7]
0011000HEX_S6[5]
0100001HEX_E3[5]
0100010OMUX_E8
0100100HEX_W3[5]
0101000LV[18]
1000001LV[6]
1000100HEX_W6[3]
1001000HEX_E6[6]
virtex2 INT_IOI_CLK_N switchbox INT muxes HEX_S0[6]
BitsDestination
MAIN[21][48]MAIN[21][50]MAIN[20][51]MAIN[19][51]MAIN[18][49]MAIN[19][49]MAIN[18][51]HEX_S0[6]
Source
0000000off
0010001OMUX_SW5
0010010LV[12]
0010100HEX_W3[6]
0011000HEX_E3[6]
0100001OUT_FAN[0]
0100010OMUX_ES7
0100100HEX_S6[6]
0101000HEX_S6[8]
1000001LV[0]
1000100HEX_E6[7]
1001000HEX_W6[4]
virtex2 INT_IOI_CLK_N switchbox INT muxes HEX_S0[7]
BitsDestination
MAIN[20][57]MAIN[20][58]MAIN[20][56]MAIN[18][56]MAIN[19][58]MAIN[18][58]MAIN[19][56]HEX_S0[7]
Source
0000000off
0010001OMUX[11]
0010010LV[6]
0010100HEX_W6[5]
0011000HEX_E6[8]
0100010OMUX_WS1
0100100HEX_S6[9]
0101000HEX_S6[7]
1000001OMUX_SE3
1000010HEX_E3[7]
1000100HEX_W3[7]
1001000LV[18]
virtex2 INT_IOI_CLK_N switchbox INT muxes HEX_S0[8]
BitsDestination
MAIN[21][64]MAIN[20][67]MAIN[21][66]MAIN[19][67]MAIN[18][65]MAIN[18][67]MAIN[19][65]HEX_S0[8]
Source
0000000off
0010001OMUX_S5
0010100HEX_S6[8]
0011000HEX_S7[0]
0100001LV[12]
0100010OMUX_W14
0100100HEX_W3[8]
0101000HEX_E3[8]
1000010LV[0]
1000100HEX_E6[9]
1001000HEX_W6[6]
virtex2 INT_IOI_CLK_N switchbox INT muxes HEX_S0[9]
BitsDestination
MAIN[20][72]MAIN[20][73]MAIN[20][74]MAIN[18][72]MAIN[19][74]MAIN[18][74]MAIN[19][72]HEX_S0[9]
Source
0000000off
0010001OMUX[15]
0010010OMUX_SW5
0010100HEX_S7[1]
0011000HEX_S6[9]
0100001OMUX_ES7
0100010HEX_E3[9]
0100100HEX_W3[9]
0101000LV[18]
1000001OUT_FAN[0]
1000010LV[6]
1000100HEX_W6[7]
1001000HEX_E6_S[0]
virtex2 INT_IOI_CLK_N switchbox INT muxes HEX_N0[0]
BitsDestination
MAIN[20][1]MAIN[20][2]MAIN[20][0]MAIN[18][0]MAIN[19][2]MAIN[18][2]MAIN[19][0]HEX_N0[0]
Source
0000000off
0010001OMUX[0]
0010010LV[0]
0010100HEX_W6_N[8]
0011000HEX_E6[1]
0100001OUT_FAN[3]
0100010OMUX_EN8
0100100HEX_N6[0]
0101000HEX_N7[8]
1000001OMUX_N13
1000010HEX_E3[0]
1000100HEX_W3[0]
1001000LV[12]
virtex2 INT_IOI_CLK_N switchbox INT muxes HEX_N0[1]
BitsDestination
MAIN[21][8]MAIN[21][10]MAIN[20][11]MAIN[19][11]MAIN[18][9]MAIN[19][9]MAIN[18][11]HEX_N0[1]
Source
0000000off
0010001OMUX_N10
0010010LV[18]
0010100HEX_W3[1]
0011000HEX_E3[1]
0100001OUT_FAN[2]
0100010OMUX_NW10
0100100HEX_N7[9]
0101000HEX_N6[1]
1000001LV[6]
1000100HEX_E6[2]
1001000HEX_W6_N[9]
virtex2 INT_IOI_CLK_N switchbox INT muxes HEX_N0[2]
BitsDestination
MAIN[20][16]MAIN[20][17]MAIN[20][18]MAIN[18][16]MAIN[19][18]MAIN[18][18]MAIN[19][16]HEX_N0[2]
Source
0000000off
0010001OMUX[4]
0010010OMUX_NE12
0010100HEX_N6[2]
0011000HEX_N6[0]
0100001OMUX_W1
0100010HEX_E3[2]
0100100HEX_W3[2]
0101000LV[12]
1000010LV[0]
1000100HEX_W6[0]
1001000HEX_E6[3]
virtex2 INT_IOI_CLK_N switchbox INT muxes HEX_N0[3]
BitsDestination
MAIN[21][24]MAIN[21][26]MAIN[20][27]MAIN[19][27]MAIN[18][25]MAIN[19][25]MAIN[18][27]HEX_N0[3]
Source
0000000off
0010001OMUX_EN8
0010010LV[18]
0010100HEX_W3[3]
0011000HEX_E3[3]
0100010OMUX_WN14
0100100HEX_N6[1]
0101000HEX_N6[3]
1000001LV[6]
1000010OUT_FAN[3]
1000100HEX_E6[4]
1001000HEX_W6[1]
virtex2 INT_IOI_CLK_N switchbox INT muxes HEX_N0[4]
BitsDestination
MAIN[20][32]MAIN[20][33]MAIN[20][34]MAIN[18][32]MAIN[19][34]MAIN[19][32]MAIN[18][34]HEX_N0[4]
Source
0000000off
0010001OMUX_E7
0010100HEX_N6[4]
0011000HEX_N6[2]
0100001HEX_E3[4]
0100010OMUX_NW10
0100100HEX_W3[4]
0101000LV[12]
1000001LV[0]
1000010OUT_FAN[2]
1000100HEX_W6[2]
1001000HEX_E6[5]
virtex2 INT_IOI_CLK_N switchbox INT muxes HEX_N0[5]
BitsDestination
MAIN[21][40]MAIN[20][43]MAIN[21][42]MAIN[19][43]MAIN[18][41]MAIN[18][43]MAIN[19][41]HEX_N0[5]
Source
0000000off
0010001OMUX_N12
0010100HEX_N6[3]
0011000HEX_N6[5]
0100001LV[18]
0100010OMUX_NE12
0100100HEX_W3[5]
0101000HEX_E3[5]
1000010LV[6]
1000100HEX_E6[6]
1001000HEX_W6[3]
virtex2 INT_IOI_CLK_N switchbox INT muxes HEX_N0[6]
BitsDestination
MAIN[20][48]MAIN[20][49]MAIN[20][50]MAIN[18][48]MAIN[19][50]MAIN[19][48]MAIN[18][50]HEX_N0[6]
Source
0000000off
0010001OMUX[9]
0010010OUT_FAN[0]
0010100HEX_N6[6]
0011000HEX_N6[4]
0100001HEX_E3[6]
0100010OMUX_WN14
0100100HEX_W3[6]
0101000LV[12]
1000001LV[0]
1000100HEX_W6[4]
1001000HEX_E6[7]
virtex2 INT_IOI_CLK_N switchbox INT muxes HEX_N0[7]
BitsDestination
MAIN[20][59]MAIN[21][58]MAIN[21][56]MAIN[19][59]MAIN[18][57]MAIN[18][59]MAIN[19][57]HEX_N0[7]
Source
0000000off
0010001OMUX[11]
0010010LV[6]
0010100HEX_E6[8]
0011000HEX_W6[5]
0100001OMUX_W9
0100100HEX_N6[5]
0101000HEX_N6[7]
1000001LV[18]
1000010OMUX_N11
1000100HEX_W3[7]
1001000HEX_E3[7]
virtex2 INT_IOI_CLK_N switchbox INT muxes HEX_N0[8]
BitsDestination
MAIN[20][64]MAIN[20][66]MAIN[20][65]MAIN[18][64]MAIN[19][66]MAIN[18][66]MAIN[19][64]HEX_N0[8]
Source
0000000off
0010001OMUX[9]
0010010HEX_E3[8]
0010100HEX_W3[8]
0011000LV[12]
0100010OMUX_E13
0100100HEX_N6[8]
0101000HEX_N6[6]
1000010LV[0]
1000100HEX_W6[6]
1001000HEX_E6[9]
virtex2 INT_IOI_CLK_N switchbox INT muxes HEX_N0[9]
BitsDestination
MAIN[21][72]MAIN[20][75]MAIN[21][74]MAIN[19][75]MAIN[18][73]MAIN[18][75]MAIN[19][73]HEX_N0[9]
Source
0000000off
0010001OMUX[13]
0010010OMUX[15]
0010100HEX_N6[7]
0011000HEX_N6[9]
0100001LV[18]
0100010OMUX_N15
0100100HEX_W3[9]
0101000HEX_E3[9]
1000001OUT_FAN[0]
1000010LV[6]
1000100HEX_E6_S[0]
1001000HEX_W6[7]
virtex2 INT_IOI_CLK_N switchbox INT muxes LH[0]
BitsDestination
MAIN[21][47]MAIN[21][49]MAIN[21][51]LH[0]
Source
000off
001DBL_W1[5]
011OMUX_S4
101DBL_E1[6]
111OMUX[11]
virtex2 INT_IOI_CLK_N switchbox INT muxes LH[6]
BitsDestination
MAIN[21][31]MAIN[21][33]MAIN[21][29]LH[6]
Source
000off
001OMUX[4]
011OMUX_N15
101DBL_E1[4]
111DBL_W1[3]
virtex2 INT_IOI_CLK_N switchbox INT muxes LH[12]
BitsDestination
MAIN[21][41]MAIN[21][45]MAIN[21][43]LH[12]
Source
000off
001DBL_W1[5]
011OMUX_S4
101DBL_E1[6]
111OMUX[11]
virtex2 INT_IOI_CLK_N switchbox INT muxes LH[18]
BitsDestination
MAIN[21][39]MAIN[21][37]MAIN[21][35]LH[18]
Source
000off
001OMUX[4]
011OMUX_N15
101DBL_E1[4]
111DBL_W1[3]
virtex2 INT_IOI_CLK_N switchbox INT muxes LV[0]
BitsDestination
MAIN[21][7]MAIN[21][9]MAIN[21][19]MAIN[21][25]MAIN[21][21]MAIN[21][11]MAIN[21][5]LV[0]
Source
0000000off
0000011HEX_E1[1]
0000101OMUX_E2
0001001DBL_W1[1]
0010001HEX_E6[1]
0100001HEX_E4[1]
1000011OMUX[0]
1000101HEX_E2[1]
1001001HEX_E5[1]
1010001DBL_E1[2]
1100001HEX_E3[1]
virtex2 INT_IOI_CLK_N switchbox INT muxes LV[6]
BitsDestination
MAIN[21][73]MAIN[21][61]MAIN[21][55]MAIN[21][69]MAIN[21][71]MAIN[21][65]MAIN[21][75]LV[6]
Source
0000000off
0000011OMUX_W9
0000101DBL_W1[7]
0001001HEX_W5[7]
0010001HEX_W3[7]
0100001HEX_W4[7]
1000011OMUX[15]
1000101HEX_W2[7]
1001001DBL_E1[8]
1010001HEX_W0[7]
1100001HEX_W1[7]
virtex2 INT_IOI_CLK_N switchbox INT muxes LV[12]
BitsDestination
MAIN[21][13]MAIN[21][1]MAIN[21][27]MAIN[21][23]MAIN[21][17]MAIN[21][3]MAIN[21][15]LV[12]
Source
0000000off
0000011HEX_E1[1]
0000101OMUX_E2
0001001DBL_W1[1]
0010001HEX_E6[1]
0100001HEX_E4[1]
1000011OMUX[0]
1000101HEX_E2[1]
1001001HEX_E5[1]
1010001DBL_E1[2]
1100001HEX_E3[1]
virtex2 INT_IOI_CLK_N switchbox INT muxes LV[18]
BitsDestination
MAIN[21][67]MAIN[21][53]MAIN[21][57]MAIN[21][77]MAIN[21][59]MAIN[21][79]MAIN[21][63]LV[18]
Source
0000000off
0000011OMUX_W9
0000101DBL_W1[7]
0001001HEX_W5[7]
0010001HEX_W3[7]
0100001HEX_W4[7]
1000011OMUX[15]
1000101HEX_W2[7]
1001001DBL_E1[8]
1010001HEX_W0[7]
1100001HEX_W1[7]
virtex2 INT_IOI_CLK_N switchbox INT muxes IMUX_CLK[2]
BitsDestination
MAIN[5][54]MAIN[5][53]MAIN[5][51]MAIN[4][53]MAIN[4][51]MAIN[4][55]MAIN[4][57]MAIN[5][55]MAIN[5][57]MAIN[4][61]IMUX_CLK[2]
Source
0000000000off
0001000001GCLK[0]
0001000010GCLK[1]
0001000100GCLK[2]
0001001000HEX_N0[6]
0001010000HEX_N3[6]
0001100000HEX_S4[6]
0010000001GCLK[3]
0010000010HEX_S3[6]
0010000100GCLK[4]
0010001000HEX_S6[6]
0010010000HEX_N1[6]
0010100000HEX_N4[6]
0100000001GCLK[5]
0100000010HEX_N2[6]
0100000100HEX_N5[6]
0100001000GCLK[6]
0100010000HEX_S5[6]
0100100000HEX_S2[6]
1000000001GCLK[7]
1000000010DBL_W2[6]
1000000100DBL_E0[6]
1000001000DBL_E1[6]
1000010000DBL_W1[6]
1000100000HEX_S1[6]
virtex2 INT_IOI_CLK_N switchbox INT muxes IMUX_CLK[3]
BitsDestination
MAIN[5][60]MAIN[5][59]MAIN[5][61]MAIN[4][59]MAIN[5][52]MAIN[4][54]MAIN[4][58]MAIN[5][56]MAIN[4][56]MAIN[5][58]IMUX_CLK[3]
Source
0000000000off
0001000001GCLK[0]
0001000010GCLK[1]
0001000100GCLK[2]
0001001000HEX_N0[6]
0001010000HEX_N3[6]
0001100000HEX_S4[6]
0010000001GCLK[3]
0010000010HEX_S3[6]
0010000100GCLK[4]
0010001000HEX_S6[6]
0010010000HEX_N1[6]
0010100000HEX_N4[6]
0100000001GCLK[5]
0100000010HEX_N2[6]
0100000100HEX_N5[6]
0100001000GCLK[6]
0100010000HEX_S5[6]
0100100000HEX_S2[6]
1000000001GCLK[7]
1000000010DBL_W2[6]
1000000100DBL_E0[6]
1000001000DBL_E1[6]
1000010000DBL_W1[6]
1000100000HEX_S1[6]
virtex2 INT_IOI_CLK_N switchbox INT muxes IMUX_SR[1]
BitsDestination
MAIN[4][12]MAIN[5][12]MAIN[5][14]MAIN[4][14]MAIN[5][16]MAIN[5][15]MAIN[5][17]MAIN[4][15]IMUX_SR[1]
Source
00000000PULLUP
00010001DBL_W1[1]
00010010HEX_N2[0]
00010100HEX_S2[0]
00011000HEX_N0[0]
00100001DBL_W2[1]
00100010HEX_S3[0]
00100100HEX_N4[0]
00101000HEX_S6[0]
01000001HEX_S5[0]
01000010DBL_E0[1]
01000100HEX_S1[0]
01001000HEX_N3[0]
10000001HEX_N1[0]
10000010DBL_E1[1]
10000100HEX_N5[0]
10001000HEX_S4[0]
virtex2 INT_IOI_CLK_N switchbox INT muxes IMUX_SR[3]
BitsDestination
MAIN[5][13]MAIN[4][9]MAIN[4][17]MAIN[4][13]MAIN[5][10]MAIN[5][9]MAIN[5][11]MAIN[4][11]IMUX_SR[3]
Source
00000000PULLUP
00010001DBL_W1[1]
00010010HEX_N2[0]
00010100HEX_S2[0]
00011000HEX_N0[0]
00100001DBL_W2[1]
00100010HEX_S3[0]
00100100HEX_N4[0]
00101000HEX_S6[0]
01000001HEX_S5[0]
01000010DBL_E0[1]
01000100HEX_S1[0]
01001000HEX_N3[0]
10000001HEX_N1[0]
10000010DBL_E1[1]
10000100HEX_N5[0]
10001000HEX_S4[0]
virtex2 INT_IOI_CLK_N switchbox INT muxes IMUX_CE[2]
BitsDestination
MAIN[5][75]MAIN[4][71]MAIN[4][79]MAIN[4][75]MAIN[5][72]MAIN[5][71]MAIN[5][73]MAIN[4][73]IMUX_CE[2]
Source
00000000PULLUP
00010001DBL_W1[9]
00010010HEX_S1[9]
00010100HEX_S2[9]
00011000HEX_S5[9]
00100001DBL_W2[9]
00100010HEX_N5[9]
00100100HEX_N4[9]
00101000HEX_N1[9]
01000001HEX_S6[9]
01000010DBL_E0[9]
01000100HEX_S4[9]
01001000HEX_S3[9]
10000001HEX_N0[9]
10000010DBL_E1[9]
10000100HEX_N2[9]
10001000HEX_N3[9]
virtex2 INT_IOI_CLK_N switchbox INT muxes IMUX_CE[3]
BitsDestination
MAIN[4][74]MAIN[5][74]MAIN[5][76]MAIN[4][76]MAIN[5][78]MAIN[5][77]MAIN[5][79]MAIN[4][77]IMUX_CE[3]
Source
00000000PULLUP
00010001DBL_W1[9]
00010010HEX_S1[9]
00010100HEX_S2[9]
00011000HEX_S5[9]
00100001DBL_W2[9]
00100010HEX_N5[9]
00100100HEX_N4[9]
00101000HEX_N1[9]
01000001HEX_S6[9]
01000010DBL_E0[9]
01000100HEX_S4[9]
01001000HEX_S3[9]
10000001HEX_N0[9]
10000010DBL_E1[9]
10000100HEX_N2[9]
10001000HEX_N3[9]
virtex2 INT_IOI_CLK_N switchbox INT muxes IMUX_G0_FAN[0]
BitsDestination
MAIN[9][16]MAIN[9][19]MAIN[8][19]MAIN[8][16]MAIN[10][17]MAIN[10][19]MAIN[11][19]MAIN[11][17]MAIN[13][17]MAIN[12][19]MAIN[13][19]MAIN[12][17]IMUX_G0_FAN[0]
Source
000000000000PULLUP
000100000001OMUX_W1
000100000010OMUX_E2
000100000100OMUX_NW10
000100001000OMUX_N10
000100010000DBL_S1[0]
000100100000IMUX_G1_FAN[0]
000101000000DBL_N2[0]
000110000000IMUX_G2_FAN[0]
001000000001DBL_E0[1]
001000000010DBL_S0[0]
001000000100OMUX_EN8
001000001000DBL_W0[0]
001000010000DBL_N1[1]
001000100000DBL_S1[2]
001001000000DBL_W2[1]
001010000000DBL_S1[1]
010000000001DBL_E2[1]
010000000010DBL_S0[2]
010000000100DBL_E2[0]
010000001000DBL_E2[2]
010000010000DBL_W1[0]
010000100000DBL_E1[2]
010001000000DBL_E1[1]
010010000000DBL_N2[1]
100000000001DBL_S2[0]
100000000010DBL_S2[2]
100000000100DBL_N0[1]
100000001000DBL_S2[1]
100000010000DBL_E1[0]
100000100000DBL_W1[1]
100001000000DBL_W2[0]
100010000000DBL_N1[0]
virtex2 INT_IOI_CLK_N switchbox INT muxes IMUX_G0_FAN[1]
BitsDestination
MAIN[9][17]MAIN[9][18]MAIN[8][18]MAIN[8][17]MAIN[10][16]MAIN[10][18]MAIN[11][18]MAIN[11][16]MAIN[13][16]MAIN[12][18]MAIN[13][18]MAIN[12][16]IMUX_G0_FAN[1]
Source
000000000000PULLUP
000100000001OMUX_W1
000100000010OMUX_E2
000100000100OMUX_NW10
000100001000OMUX_N10
000100010000DBL_S1[0]
000100100000IMUX_G1_FAN[0]
000101000000DBL_N2[0]
000110000000IMUX_G2_FAN[0]
001000000001DBL_E0[1]
001000000010DBL_S0[0]
001000000100OMUX_EN8
001000001000DBL_W0[0]
001000010000DBL_N1[1]
001000100000DBL_S1[2]
001001000000DBL_W2[1]
001010000000DBL_S1[1]
010000000001DBL_E2[1]
010000000010DBL_S0[2]
010000000100DBL_E2[0]
010000001000DBL_E2[2]
010000010000DBL_W1[0]
010000100000DBL_E1[2]
010001000000DBL_E1[1]
010010000000DBL_N2[1]
100000000001DBL_S2[0]
100000000010DBL_S2[2]
100000000100DBL_N0[1]
100000001000DBL_S2[1]
100000010000DBL_E1[0]
100000100000DBL_W1[1]
100001000000DBL_W2[0]
100010000000DBL_N1[0]
virtex2 INT_IOI_CLK_N switchbox INT muxes IMUX_G1_FAN[0]
BitsDestination
MAIN[9][23]MAIN[9][20]MAIN[8][23]MAIN[8][20]MAIN[10][22]MAIN[10][20]MAIN[11][22]MAIN[11][20]MAIN[13][20]MAIN[13][22]MAIN[12][22]MAIN[12][20]IMUX_G1_FAN[0]
Source
000000000000PULLUP
000100000001OMUX_W6
000100000010DBL_S0[4]
000100000100DBL_W0[4]
000100001000DBL_E0[3]
000100010000DBL_W1[2]
000100100000DBL_N1[4]
000101000000DBL_W2[4]
000110000000DBL_N2[4]
001000000001OMUX_N12
001000000010OMUX_E7
001000000100OMUX_NE12
001000001000OMUX_WN14
001000010000IMUX_G3_FAN[1]
001000100000DBL_S1[3]
001001000000DBL_E1[4]
001010000000IMUX_G0_FAN[1]
010000000001DBL_E2[4]
010000000010DBL_E2[3]
010000000100DBL_W2[3]
010000001000DBL_W0[2]
010000010000DBL_N1[2]
010000100000DBL_W1[3]
010001000000DBL_W1[4]
010010000000DBL_N2[3]
100000000001DBL_N0[3]
100000000010DBL_S2[4]
100000000100DBL_S2[3]
100000001000DBL_W2[2]
100000010000DBL_S1[4]
100000100000DBL_E1[3]
100001000000DBL_N2[2]
100010000000DBL_N1[3]
virtex2 INT_IOI_CLK_N switchbox INT muxes IMUX_G1_FAN[1]
BitsDestination
MAIN[9][22]MAIN[9][21]MAIN[8][22]MAIN[8][21]MAIN[10][23]MAIN[10][21]MAIN[11][23]MAIN[11][21]MAIN[13][21]MAIN[13][23]MAIN[12][23]MAIN[12][21]IMUX_G1_FAN[1]
Source
000000000000PULLUP
000100000001OMUX_W6
000100000010DBL_S0[4]
000100000100DBL_W0[4]
000100001000DBL_E0[3]
000100010000DBL_W1[2]
000100100000DBL_N1[4]
000101000000DBL_W2[4]
000110000000DBL_N2[4]
001000000001OMUX_N12
001000000010OMUX_E7
001000000100OMUX_NE12
001000001000OMUX_WN14
001000010000IMUX_G3_FAN[1]
001000100000DBL_S1[3]
001001000000DBL_E1[4]
001010000000IMUX_G0_FAN[1]
010000000001DBL_E2[4]
010000000010DBL_E2[3]
010000000100DBL_W2[3]
010000001000DBL_W0[2]
010000010000DBL_N1[2]
010000100000DBL_W1[3]
010001000000DBL_W1[4]
010010000000DBL_N2[3]
100000000001DBL_N0[3]
100000000010DBL_S2[4]
100000000100DBL_S2[3]
100000001000DBL_W2[2]
100000010000DBL_S1[4]
100000100000DBL_E1[3]
100001000000DBL_N2[2]
100010000000DBL_N1[3]
virtex2 INT_IOI_CLK_N switchbox INT muxes IMUX_G2_FAN[0]
BitsDestination
MAIN[9][56]MAIN[9][59]MAIN[8][59]MAIN[8][56]MAIN[10][57]MAIN[10][59]MAIN[11][59]MAIN[11][57]MAIN[13][59]MAIN[13][57]MAIN[12][59]MAIN[12][57]IMUX_G2_FAN[0]
Source
000000000000PULLUP
000100000001OMUX_WS1
000100000010OMUX_E8
000100000100OMUX_SE3
000100001000OMUX_W9
000100010000DBL_S1[5]
000100100000IMUX_G3_FAN[0]
000101000000DBL_N2[5]
000110000000IMUX_G0_FAN[0]
001000000001DBL_E0[5]
001000000010OMUX_S3
001000000100DBL_W0[6]
001000001000DBL_S0[6]
001000010000DBL_N1[6]
001000100000DBL_S1[7]
001001000000DBL_W2[6]
001010000000DBL_S1[6]
010000000001DBL_E2[6]
010000000010DBL_E2[5]
010000000100DBL_E2[7]
010000001000DBL_E0[7]
010000010000DBL_W1[5]
010000100000DBL_E1[7]
010001000000DBL_E1[6]
010010000000DBL_N2[6]
100000000001DBL_S2[5]
100000000010DBL_N0[5]
100000000100DBL_S2[6]
100000001000DBL_S2[7]
100000010000DBL_E1[5]
100000100000DBL_W1[6]
100001000000DBL_W2[5]
100010000000DBL_N1[5]
virtex2 INT_IOI_CLK_N switchbox INT muxes IMUX_G2_FAN[1]
BitsDestination
MAIN[9][57]MAIN[9][58]MAIN[8][58]MAIN[8][57]MAIN[10][56]MAIN[10][58]MAIN[11][58]MAIN[11][56]MAIN[13][58]MAIN[13][56]MAIN[12][58]MAIN[12][56]IMUX_G2_FAN[1]
Source
000000000000PULLUP
000100000001OMUX_WS1
000100000010OMUX_E8
000100000100OMUX_SE3
000100001000OMUX_W9
000100010000DBL_S1[5]
000100100000IMUX_G3_FAN[0]
000101000000DBL_N2[5]
000110000000IMUX_G0_FAN[0]
001000000001DBL_E0[5]
001000000010OMUX_S3
001000000100DBL_W0[6]
001000001000DBL_S0[6]
001000010000DBL_N1[6]
001000100000DBL_S1[7]
001001000000DBL_W2[6]
001010000000DBL_S1[6]
010000000001DBL_E2[6]
010000000010DBL_E2[5]
010000000100DBL_E2[7]
010000001000DBL_E0[7]
010000010000DBL_W1[5]
010000100000DBL_E1[7]
010001000000DBL_E1[6]
010010000000DBL_N2[6]
100000000001DBL_S2[5]
100000000010DBL_N0[5]
100000000100DBL_S2[6]
100000001000DBL_S2[7]
100000010000DBL_E1[5]
100000100000DBL_W1[6]
100001000000DBL_W2[5]
100010000000DBL_N1[5]
virtex2 INT_IOI_CLK_N switchbox INT muxes IMUX_G2_DATA[5]
BitsDestination
MAIN[9][49]MAIN[9][50]MAIN[8][50]MAIN[8][49]MAIN[10][48]MAIN[10][50]MAIN[11][50]MAIN[11][48]MAIN[13][50]MAIN[13][48]MAIN[12][50]MAIN[12][48]IMUX_G2_DATA[5]
Source
000000000000PULLUP
000100000001OMUX_WS1
000100000010OMUX_E8
000100000100OMUX_SE3
000100001000OMUX_W9
000100010000DBL_S1[5]
000100100000IMUX_G3_FAN[0]
000101000000DBL_N2[5]
000110000000IMUX_G0_FAN[0]
001000000001DBL_E0[5]
001000000010OMUX_S3
001000000100DBL_W0[6]
001000001000DBL_S0[6]
001000010000DBL_N1[6]
001000100000DBL_S1[7]
001001000000DBL_W2[6]
001010000000DBL_S1[6]
010000000001DBL_E2[6]
010000000010DBL_E2[5]
010000000100DBL_E2[7]
010000001000DBL_E0[7]
010000010000DBL_W1[5]
010000100000DBL_E1[7]
010001000000DBL_E1[6]
010010000000DBL_N2[6]
100000000001DBL_S2[5]
100000000010DBL_N0[5]
100000000100DBL_S2[6]
100000001000DBL_S2[7]
100000010000DBL_E1[5]
100000100000DBL_W1[6]
100001000000DBL_W2[5]
100010000000DBL_N1[5]
virtex2 INT_IOI_CLK_N switchbox INT muxes IMUX_G2_DATA[6]
BitsDestination
MAIN[9][55]MAIN[9][52]MAIN[8][52]MAIN[8][55]MAIN[10][54]MAIN[10][52]MAIN[11][52]MAIN[11][54]MAIN[13][52]MAIN[13][54]MAIN[12][52]MAIN[12][54]IMUX_G2_DATA[6]
Source
000000000000PULLUP
000100000001OMUX_WS1
000100000010OMUX_E8
000100000100OMUX_SE3
000100001000OMUX_W9
000100010000DBL_S1[5]
000100100000IMUX_G3_FAN[0]
000101000000DBL_N2[5]
000110000000IMUX_G0_FAN[0]
001000000001DBL_E0[5]
001000000010OMUX_S3
001000000100DBL_W0[6]
001000001000DBL_S0[6]
001000010000DBL_N1[6]
001000100000DBL_S1[7]
001001000000DBL_W2[6]
001010000000DBL_S1[6]
010000000001DBL_E2[6]
010000000010DBL_E2[5]
010000000100DBL_E2[7]
010000001000DBL_E0[7]
010000010000DBL_W1[5]
010000100000DBL_E1[7]
010001000000DBL_E1[6]
010010000000DBL_N2[6]
100000000001DBL_S2[5]
100000000010DBL_N0[5]
100000000100DBL_S2[6]
100000001000DBL_S2[7]
100000010000DBL_E1[5]
100000100000DBL_W1[6]
100001000000DBL_W2[5]
100010000000DBL_N1[5]
virtex2 INT_IOI_CLK_N switchbox INT muxes IMUX_G2_DATA[7]
BitsDestination
MAIN[9][54]MAIN[9][53]MAIN[8][53]MAIN[8][54]MAIN[10][55]MAIN[10][53]MAIN[11][53]MAIN[11][55]MAIN[13][53]MAIN[13][55]MAIN[12][53]MAIN[12][55]IMUX_G2_DATA[7]
Source
000000000000PULLUP
000100000001OMUX_WS1
000100000010OMUX_E8
000100000100OMUX_SE3
000100001000OMUX_W9
000100010000DBL_S1[5]
000100100000IMUX_G3_FAN[0]
000101000000DBL_N2[5]
000110000000IMUX_G0_FAN[0]
001000000001DBL_E0[5]
001000000010OMUX_S3
001000000100DBL_W0[6]
001000001000DBL_S0[6]
001000010000DBL_N1[6]
001000100000DBL_S1[7]
001001000000DBL_W2[6]
001010000000DBL_S1[6]
010000000001DBL_E2[6]
010000000010DBL_E2[5]
010000000100DBL_E2[7]
010000001000DBL_E0[7]
010000010000DBL_W1[5]
010000100000DBL_E1[7]
010001000000DBL_E1[6]
010010000000DBL_N2[6]
100000000001DBL_S2[5]
100000000010DBL_N0[5]
100000000100DBL_S2[6]
100000001000DBL_S2[7]
100000010000DBL_E1[5]
100000100000DBL_W1[6]
100001000000DBL_W2[5]
100010000000DBL_N1[5]
virtex2 INT_IOI_CLK_N switchbox INT muxes IMUX_G3_FAN[0]
BitsDestination
MAIN[9][63]MAIN[9][60]MAIN[8][60]MAIN[8][63]MAIN[10][62]MAIN[10][60]MAIN[11][62]MAIN[11][60]MAIN[13][62]MAIN[12][62]MAIN[12][60]MAIN[13][60]IMUX_G3_FAN[0]
Source
000000000000PULLUP
000100000001OMUX_S5
000100000010OMUX_W14
000100000100OMUX_ES7
000100001000OMUX_E13
000100010000IMUX_G1_FAN[1]
000100100000DBL_S1[8]
000101000000DBL_E1[9]
000110000000IMUX_G2_FAN[1]
001000000001DBL_W0[8]
001000000010OMUX_SW5
001000000100DBL_S0[8]
001000001000DBL_E0[9]
001000010000DBL_W1[7]
001000100000DBL_N1[9]
001001000000DBL_W2[9]
001010000000DBL_N2[9]
010000000001DBL_N0[7]
010000000010DBL_E2[9]
010000000100DBL_E2[8]
010000001000DBL_W2[8]
010000010000DBL_N1[7]
010000100000DBL_W1[8]
010001000000DBL_W1[9]
010010000000DBL_N2[8]
100000000001DBL_W2[7]
100000000010DBL_N0[9]
100000000100DBL_S2[9]
100000001000DBL_S2[8]
100000010000DBL_S1[9]
100000100000DBL_E1[8]
100001000000DBL_N2[7]
100010000000DBL_N1[8]
virtex2 INT_IOI_CLK_N switchbox INT muxes IMUX_G3_FAN[1]
BitsDestination
MAIN[9][62]MAIN[9][61]MAIN[8][61]MAIN[8][62]MAIN[10][63]MAIN[10][61]MAIN[11][63]MAIN[11][61]MAIN[13][63]MAIN[12][63]MAIN[12][61]MAIN[13][61]IMUX_G3_FAN[1]
Source
000000000000PULLUP
000100000001OMUX_S5
000100000010OMUX_W14
000100000100OMUX_ES7
000100001000OMUX_E13
000100010000IMUX_G1_FAN[1]
000100100000DBL_S1[8]
000101000000DBL_E1[9]
000110000000IMUX_G2_FAN[1]
001000000001DBL_W0[8]
001000000010OMUX_SW5
001000000100DBL_S0[8]
001000001000DBL_E0[9]
001000010000DBL_W1[7]
001000100000DBL_N1[9]
001001000000DBL_W2[9]
001010000000DBL_N2[9]
010000000001DBL_N0[7]
010000000010DBL_E2[9]
010000000100DBL_E2[8]
010000001000DBL_W2[8]
010000010000DBL_N1[7]
010000100000DBL_W1[8]
010001000000DBL_W1[9]
010010000000DBL_N2[8]
100000000001DBL_W2[7]
100000000010DBL_N0[9]
100000000100DBL_S2[9]
100000001000DBL_S2[8]
100000010000DBL_S1[9]
100000100000DBL_E1[8]
100001000000DBL_N2[7]
100010000000DBL_N1[8]
virtex2 INT_IOI_CLK_N switchbox INT muxes IMUX_G3_DATA[5]
BitsDestination
MAIN[9][70]MAIN[9][69]MAIN[8][69]MAIN[8][70]MAIN[10][71]MAIN[10][69]MAIN[11][71]MAIN[11][69]MAIN[13][71]MAIN[12][71]MAIN[12][69]MAIN[13][69]IMUX_G3_DATA[5]
Source
000000000000PULLUP
000100000001OMUX_S5
000100000010OMUX_W14
000100000100OMUX_ES7
000100001000OMUX_E13
000100010000IMUX_G1_FAN[1]
000100100000DBL_S1[8]
000101000000DBL_E1[9]
000110000000IMUX_G2_FAN[1]
001000000001DBL_W0[8]
001000000010OMUX_SW5
001000000100DBL_S0[8]
001000001000DBL_E0[9]
001000010000DBL_W1[7]
001000100000DBL_N1[9]
001001000000DBL_W2[9]
001010000000DBL_N2[9]
010000000001DBL_N0[7]
010000000010DBL_E2[9]
010000000100DBL_E2[8]
010000001000DBL_W2[8]
010000010000DBL_N1[7]
010000100000DBL_W1[8]
010001000000DBL_W1[9]
010010000000DBL_N2[8]
100000000001DBL_W2[7]
100000000010DBL_N0[9]
100000000100DBL_S2[9]
100000001000DBL_S2[8]
100000010000DBL_S1[9]
100000100000DBL_E1[8]
100001000000DBL_N2[7]
100010000000DBL_N1[8]
virtex2 INT_IOI_CLK_N switchbox INT muxes IMUX_G3_DATA[6]
BitsDestination
MAIN[9][64]MAIN[9][67]MAIN[8][67]MAIN[8][64]MAIN[10][65]MAIN[10][67]MAIN[11][65]MAIN[11][67]MAIN[13][65]MAIN[12][65]MAIN[12][67]MAIN[13][67]IMUX_G3_DATA[6]
Source
000000000000PULLUP
000100000001OMUX_S5
000100000010OMUX_W14
000100000100OMUX_ES7
000100001000OMUX_E13
000100010000IMUX_G1_FAN[1]
000100100000DBL_S1[8]
000101000000DBL_E1[9]
000110000000IMUX_G2_FAN[1]
001000000001DBL_W0[8]
001000000010OMUX_SW5
001000000100DBL_S0[8]
001000001000DBL_E0[9]
001000010000DBL_W1[7]
001000100000DBL_N1[9]
001001000000DBL_W2[9]
001010000000DBL_N2[9]
010000000001DBL_N0[7]
010000000010DBL_E2[9]
010000000100DBL_E2[8]
010000001000DBL_W2[8]
010000010000DBL_N1[7]
010000100000DBL_W1[8]
010001000000DBL_W1[9]
010010000000DBL_N2[8]
100000000001DBL_W2[7]
100000000010DBL_N0[9]
100000000100DBL_S2[9]
100000001000DBL_S2[8]
100000010000DBL_S1[9]
100000100000DBL_E1[8]
100001000000DBL_N2[7]
100010000000DBL_N1[8]
virtex2 INT_IOI_CLK_N switchbox INT muxes IMUX_G3_DATA[7]
BitsDestination
MAIN[9][65]MAIN[9][66]MAIN[8][66]MAIN[8][65]MAIN[10][64]MAIN[10][66]MAIN[11][64]MAIN[11][66]MAIN[13][64]MAIN[12][64]MAIN[12][66]MAIN[13][66]IMUX_G3_DATA[7]
Source
000000000000PULLUP
000100000001OMUX_S5
000100000010OMUX_W14
000100000100OMUX_ES7
000100001000OMUX_E13
000100010000IMUX_G1_FAN[1]
000100100000DBL_S1[8]
000101000000DBL_E1[9]
000110000000IMUX_G2_FAN[1]
001000000001DBL_W0[8]
001000000010OMUX_SW5
001000000100DBL_S0[8]
001000001000DBL_E0[9]
001000010000DBL_W1[7]
001000100000DBL_N1[9]
001001000000DBL_W2[9]
001010000000DBL_N2[9]
010000000001DBL_N0[7]
010000000010DBL_E2[9]
010000000100DBL_E2[8]
010000001000DBL_W2[8]
010000010000DBL_N1[7]
010000100000DBL_W1[8]
010001000000DBL_W1[9]
010010000000DBL_N2[8]
100000000001DBL_W2[7]
100000000010DBL_N0[9]
100000000100DBL_S2[9]
100000001000DBL_S2[8]
100000010000DBL_S1[9]
100000100000DBL_E1[8]
100001000000DBL_N2[7]
100010000000DBL_N1[8]
virtex2 INT_IOI_CLK_N switchbox INT muxes IMUX_IOI_ICLK[2]
BitsDestination
MAIN[5][32]MAIN[5][31]MAIN[5][29]MAIN[4][31]MAIN[4][29]MAIN[4][33]MAIN[4][35]MAIN[5][33]MAIN[5][35]MAIN[4][39]IMUX_IOI_ICLK[2]
Source
0000000000off
0001000001GCLK[0]
0001000010GCLK[1]
0001000100GCLK[2]
0001001000HEX_N0[3]
0001010000HEX_N3[3]
0001100000HEX_S4[3]
0010000001GCLK[3]
0010000010HEX_S3[3]
0010000100GCLK[4]
0010001000HEX_S6[3]
0010010000HEX_N1[3]
0010100000HEX_N4[3]
0100000001GCLK[5]
0100000010DBL_W2[4]
0100000100HEX_N5[3]
0100001000GCLK[6]
0100010000HEX_S5[3]
0100100000HEX_S2[3]
1000000001GCLK[7]
1000000010HEX_N2[3]
1000000100DBL_E0[4]
1000001000DBL_W1[4]
1000010000DBL_E1[4]
1000100000HEX_S1[3]
virtex2 INT_IOI_CLK_N switchbox INT muxes IMUX_IOI_ICLK[3]
BitsDestination
MAIN[5][38]MAIN[5][37]MAIN[5][39]MAIN[4][37]MAIN[5][30]MAIN[4][32]MAIN[4][36]MAIN[5][34]MAIN[4][34]MAIN[5][36]IMUX_IOI_ICLK[3]
Source
0000000000off
0001000001GCLK[0]
0001000010GCLK[1]
0001000100GCLK[2]
0001001000HEX_N0[3]
0001010000HEX_N3[3]
0001100000HEX_S4[3]
0010000001GCLK[3]
0010000010HEX_S3[3]
0010000100GCLK[4]
0010001000HEX_S6[3]
0010010000HEX_N1[3]
0010100000HEX_N4[3]
0100000001GCLK[5]
0100000010DBL_W2[4]
0100000100HEX_N5[3]
0100001000GCLK[6]
0100010000HEX_S5[3]
0100100000HEX_S2[3]
1000000001GCLK[7]
1000000010HEX_N2[3]
1000000100DBL_E0[4]
1000001000DBL_W1[4]
1000010000DBL_E1[4]
1000100000HEX_S1[3]
virtex2 INT_IOI_CLK_N switchbox INT muxes IMUX_IOI_TS1[2]
BitsDestination
MAIN[9][1]MAIN[9][2]MAIN[8][2]MAIN[8][1]MAIN[10][0]MAIN[13][2]MAIN[12][0]MAIN[10][2]MAIN[11][2]MAIN[11][0]MAIN[13][0]MAIN[12][2]IMUX_IOI_TS1[2]
Source
000000000000PULLUP
000100000001OMUX_NW10
000100000010HEX_N4[1]
000100000100DBL_S1[0]
000100001000IMUX_G1_FAN[0]
000100010000DBL_N2[0]
000100100000HEX_N2[1]
000101000000HEX_S2[1]
000110000000IMUX_G2_FAN[0]
001000000001HEX_N0[1]
001000000010DBL_W0[0]
001000000100DBL_N1[1]
001000001000DBL_S1[2]
001000010000DBL_W2[1]
001000100000DBL_E0[1]
001001000000DBL_S0[0]
001010000000DBL_S1[1]
010000000001DBL_E2[0]
010000000010HEX_S6[1]
010000000100DBL_W1[0]
010000001000HEX_S5[1]
010000010000DBL_E1[1]
010000100000HEX_S4[1]
010001000000HEX_S1[1]
010010000000HEX_N3[1]
100000000001DBL_N0[1]
100000000010HEX_N1[1]
100000000100DBL_E1[0]
100000001000DBL_W1[1]
100000010000HEX_S3[1]
100000100000DBL_S2[0]
100001000000HEX_N5[1]
100010000000DBL_N1[0]
virtex2 INT_IOI_CLK_N switchbox INT muxes IMUX_IOI_TS1[3]
BitsDestination
MAIN[9][0]MAIN[9][3]MAIN[8][3]MAIN[8][0]MAIN[10][1]MAIN[13][3]MAIN[12][1]MAIN[10][3]MAIN[11][3]MAIN[11][1]MAIN[13][1]MAIN[12][3]IMUX_IOI_TS1[3]
Source
000000000000PULLUP
000100000001OMUX_NW10
000100000010HEX_N4[1]
000100000100DBL_S1[0]
000100001000IMUX_G1_FAN[0]
000100010000DBL_N2[0]
000100100000HEX_N2[1]
000101000000HEX_S2[1]
000110000000IMUX_G2_FAN[0]
001000000001HEX_N0[1]
001000000010DBL_W0[0]
001000000100DBL_N1[1]
001000001000DBL_S1[2]
001000010000DBL_W2[1]
001000100000DBL_E0[1]
001001000000DBL_S0[0]
001010000000DBL_S1[1]
010000000001DBL_E2[0]
010000000010HEX_S6[1]
010000000100DBL_W1[0]
010000001000HEX_S5[1]
010000010000DBL_E1[1]
010000100000HEX_S4[1]
010001000000HEX_S1[1]
010010000000HEX_N3[1]
100000000001DBL_N0[1]
100000000010HEX_N1[1]
100000000100DBL_E1[0]
100000001000DBL_W1[1]
100000010000HEX_S3[1]
100000100000DBL_S2[0]
100001000000HEX_N5[1]
100010000000DBL_N1[0]
virtex2 INT_IOI_CLK_N switchbox INT muxes IMUX_IOI_TS2[2]
BitsDestination
MAIN[9][38]MAIN[9][37]MAIN[8][37]MAIN[8][38]MAIN[10][39]MAIN[12][39]MAIN[13][37]MAIN[10][37]MAIN[11][39]MAIN[11][37]MAIN[13][39]MAIN[12][37]IMUX_IOI_TS2[2]
Source
000000000000PULLUP
000100000001OMUX_N12
000100000010HEX_S2[4]
000100000100IMUX_G3_FAN[1]
000100001000DBL_S1[3]
000100010000DBL_E1[4]
000100100000HEX_N5[4]
000101000000HEX_N3[4]
000110000000IMUX_G0_FAN[1]
001000000001HEX_N4[4]
001000000010DBL_W0[4]
001000000100DBL_W1[2]
001000001000DBL_N1[4]
001000010000DBL_W2[4]
001000100000DBL_E0[3]
001001000000DBL_S0[4]
001010000000DBL_N2[4]
010000000001DBL_E2[4]
010000000010HEX_S4[4]
010000000100HEX_S5[4]
010000001000DBL_W1[3]
010000010000DBL_W1[4]
010000100000HEX_N1[4]
010001000000HEX_S3[4]
010010000000HEX_N0[4]
100000000001DBL_N0[3]
100000000010HEX_N2[4]
100000000100DBL_S1[4]
100000001000DBL_E1[3]
100000010000HEX_S6[4]
100000100000HEX_S1[4]
100001000000DBL_S2[4]
100010000000DBL_N1[3]
virtex2 INT_IOI_CLK_N switchbox INT muxes IMUX_IOI_TS2[3]
BitsDestination
MAIN[9][39]MAIN[9][36]MAIN[8][36]MAIN[8][39]MAIN[10][38]MAIN[12][38]MAIN[13][36]MAIN[10][36]MAIN[11][38]MAIN[11][36]MAIN[13][38]MAIN[12][36]IMUX_IOI_TS2[3]
Source
000000000000PULLUP
000100000001OMUX_N12
000100000010HEX_S2[4]
000100000100IMUX_G3_FAN[1]
000100001000DBL_S1[3]
000100010000DBL_E1[4]
000100100000HEX_N5[4]
000101000000HEX_N3[4]
000110000000IMUX_G0_FAN[1]
001000000001HEX_N4[4]
001000000010DBL_W0[4]
001000000100DBL_W1[2]
001000001000DBL_N1[4]
001000010000DBL_W2[4]
001000100000DBL_E0[3]
001001000000DBL_S0[4]
001010000000DBL_N2[4]
010000000001DBL_E2[4]
010000000010HEX_S4[4]
010000000100HEX_S5[4]
010000001000DBL_W1[3]
010000010000DBL_W1[4]
010000100000HEX_N1[4]
010001000000HEX_S3[4]
010010000000HEX_N0[4]
100000000001DBL_N0[3]
100000000010HEX_N2[4]
100000000100DBL_S1[4]
100000001000DBL_E1[3]
100000010000HEX_S6[4]
100000100000HEX_S1[4]
100001000000DBL_S2[4]
100010000000DBL_N1[3]
virtex2 INT_IOI_CLK_N switchbox INT muxes IMUX_IOI_ICE[2]
BitsDestination
MAIN[9][41]MAIN[9][42]MAIN[8][42]MAIN[8][41]MAIN[10][40]MAIN[13][42]MAIN[12][40]MAIN[10][42]MAIN[11][42]MAIN[11][40]MAIN[13][40]MAIN[12][42]IMUX_IOI_ICE[2]
Source
000000000000PULLUP
000100000001OMUX_E8
000100000010HEX_S6[5]
000100000100DBL_S1[5]
000100001000IMUX_G3_FAN[0]
000100010000DBL_N2[5]
000100100000HEX_N4[5]
000101000000HEX_S3[5]
000110000000IMUX_G0_FAN[0]
001000000001HEX_N2[5]
001000000010DBL_W0[6]
001000000100DBL_N1[6]
001000001000DBL_S1[7]
001000010000DBL_W2[6]
001000100000DBL_E0[5]
001001000000DBL_S0[6]
001010000000DBL_S1[6]
010000000001DBL_E2[5]
010000000010HEX_S1[5]
010000000100DBL_W1[5]
010000001000HEX_S2[5]
010000010000DBL_E1[6]
010000100000HEX_N5[5]
010001000000HEX_S4[5]
010010000000HEX_S5[5]
100000000001DBL_N0[5]
100000000010HEX_N0[5]
100000000100DBL_E1[5]
100000001000DBL_W1[6]
100000010000HEX_N1[5]
100000100000DBL_S2[5]
100001000000HEX_N3[5]
100010000000DBL_N1[5]
virtex2 INT_IOI_CLK_N switchbox INT muxes IMUX_IOI_ICE[3]
BitsDestination
MAIN[9][40]MAIN[9][43]MAIN[8][43]MAIN[8][40]MAIN[10][41]MAIN[13][43]MAIN[12][41]MAIN[10][43]MAIN[11][43]MAIN[11][41]MAIN[13][41]MAIN[12][43]IMUX_IOI_ICE[3]
Source
000000000000PULLUP
000100000001OMUX_E8
000100000010HEX_S6[5]
000100000100DBL_S1[5]
000100001000IMUX_G3_FAN[0]
000100010000DBL_N2[5]
000100100000HEX_N4[5]
000101000000HEX_S3[5]
000110000000IMUX_G0_FAN[0]
001000000001HEX_N2[5]
001000000010DBL_W0[6]
001000000100DBL_N1[6]
001000001000DBL_S1[7]
001000010000DBL_W2[6]
001000100000DBL_E0[5]
001001000000DBL_S0[6]
001010000000DBL_S1[6]
010000000001DBL_E2[5]
010000000010HEX_S1[5]
010000000100DBL_W1[5]
010000001000HEX_S2[5]
010000010000DBL_E1[6]
010000100000HEX_N5[5]
010001000000HEX_S4[5]
010010000000HEX_S5[5]
100000000001DBL_N0[5]
100000000010HEX_N0[5]
100000000100DBL_E1[5]
100000001000DBL_W1[6]
100000010000HEX_N1[5]
100000100000DBL_S2[5]
100001000000HEX_N3[5]
100010000000DBL_N1[5]
virtex2 INT_IOI_CLK_N switchbox INT muxes IMUX_IOI_TCE[2]
BitsDestination
MAIN[9][78]MAIN[9][77]MAIN[8][77]MAIN[8][78]MAIN[10][79]MAIN[12][79]MAIN[13][79]MAIN[10][77]MAIN[11][79]MAIN[11][77]MAIN[13][77]MAIN[12][77]IMUX_IOI_TCE[2]
Source
000000000000PULLUP
000100000001OMUX_W14
000100000010HEX_S2[8]
000100000100IMUX_G1_FAN[1]
000100001000DBL_S1[8]
000100010000DBL_E1[9]
000100100000HEX_S4[8]
000101000000HEX_S5[8]
000110000000IMUX_G2_FAN[1]
001000000001HEX_N3[8]
001000000010DBL_W0[8]
001000000100DBL_W1[7]
001000001000DBL_N1[9]
001000010000DBL_W2[9]
001000100000DBL_E0[9]
001001000000DBL_S0[8]
001010000000DBL_N2[9]
010000000001DBL_E2[9]
010000000010HEX_S1[8]
010000000100HEX_N1[8]
010000001000DBL_W1[8]
010000010000DBL_W1[9]
010000100000HEX_N5[8]
010001000000HEX_S3[8]
010010000000HEX_N0[8]
100000000001DBL_N0[9]
100000000010HEX_N2[8]
100000000100DBL_S1[9]
100000001000DBL_E1[8]
100000010000HEX_S6[8]
100000100000HEX_N4[8]
100001000000DBL_S2[9]
100010000000DBL_N1[8]
virtex2 INT_IOI_CLK_N switchbox INT muxes IMUX_IOI_TCE[3]
BitsDestination
MAIN[9][79]MAIN[9][76]MAIN[8][76]MAIN[8][79]MAIN[10][78]MAIN[12][78]MAIN[13][78]MAIN[10][76]MAIN[11][78]MAIN[11][76]MAIN[13][76]MAIN[12][76]IMUX_IOI_TCE[3]
Source
000000000000PULLUP
000100000001OMUX_W14
000100000010HEX_S2[8]
000100000100IMUX_G1_FAN[1]
000100001000DBL_S1[8]
000100010000DBL_E1[9]
000100100000HEX_S4[8]
000101000000HEX_S5[8]
000110000000IMUX_G2_FAN[1]
001000000001HEX_N3[8]
001000000010DBL_W0[8]
001000000100DBL_W1[7]
001000001000DBL_N1[9]
001000010000DBL_W2[9]
001000100000DBL_E0[9]
001001000000DBL_S0[8]
001010000000DBL_N2[9]
010000000001DBL_E2[9]
010000000010HEX_S1[8]
010000000100HEX_N1[8]
010000001000DBL_W1[8]
010000010000DBL_W1[9]
010000100000HEX_N5[8]
010001000000HEX_S3[8]
010010000000HEX_N0[8]
100000000001DBL_N0[9]
100000000010HEX_N2[8]
100000000100DBL_S1[9]
100000001000DBL_E1[8]
100000010000HEX_S6[8]
100000100000HEX_N4[8]
100001000000DBL_S2[9]
100010000000DBL_N1[8]

Bitstream

virtex2 INT_IOI_CLK_N rect MAIN
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21
B79 - - - - INT: mux IMUX_CE[2] bit 5 INT: mux IMUX_CE[3] bit 1 INT: mux OMUX[14] bit 0 INT: mux OMUX[15] bit 9 INT: mux IMUX_IOI_TCE[3] bit 8 INT: mux IMUX_IOI_TCE[3] bit 11 INT: mux IMUX_IOI_TCE[2] bit 7 INT: mux IMUX_IOI_TCE[2] bit 3 INT: mux IMUX_IOI_TCE[2] bit 6 INT: mux IMUX_IOI_TCE[2] bit 5 INT: mux DBL_E0[9] bit 0 INT: mux DBL_W0[9] bit 7 INT: mux DBL_E0[9] bit 5 INT: mux DBL_E0[9] bit 7 INT: mux HEX_W0[9] bit 0 INT: mux HEX_W0[9] bit 3 INT: mux HEX_W0[9] bit 4 INT: mux LV[18] bit 1
B78 - - - - INT: !invert IMUX_CE_OPTINV[3] ← IMUX_CE[3] INT: mux IMUX_CE[3] bit 3 INT: mux OMUX[15] bit 8 INT: mux OMUX[15] bit 6 INT: mux IMUX_IOI_TCE[2] bit 8 INT: mux IMUX_IOI_TCE[2] bit 11 INT: mux IMUX_IOI_TCE[3] bit 7 INT: mux IMUX_IOI_TCE[3] bit 3 INT: mux IMUX_IOI_TCE[3] bit 6 INT: mux IMUX_IOI_TCE[3] bit 5 INT: mux DBL_E0[9] bit 1 INT: mux DBL_W0[9] bit 4 INT: mux DBL_W0[9] bit 3 INT: mux DBL_W0[9] bit 0 INT: mux HEX_E0[9] bit 1 INT: mux HEX_E0[9] bit 3 INT: mux HEX_E0[9] bit 5 INT: mux HEX_W0[9] bit 6
B77 - - - - INT: mux IMUX_CE[3] bit 0 INT: mux IMUX_CE[3] bit 2 INT: mux OMUX[15] bit 0 INT: mux OMUX[15] bit 7 INT: mux IMUX_IOI_TCE[2] bit 9 INT: mux IMUX_IOI_TCE[2] bit 10 INT: mux IMUX_IOI_TCE[2] bit 4 INT: mux IMUX_IOI_TCE[2] bit 2 INT: mux IMUX_IOI_TCE[2] bit 0 INT: mux IMUX_IOI_TCE[2] bit 1 INT: mux DBL_W0[9] bit 5 INT: mux DBL_E0[9] bit 3 INT: mux DBL_W0[9] bit 2 INT: mux DBL_W0[9] bit 1 INT: mux HEX_W0[9] bit 2 INT: mux HEX_W0[9] bit 1 INT: mux HEX_E0[9] bit 6 INT: mux LV[18] bit 3
B76 - - - - INT: mux IMUX_CE[3] bit 4 INT: mux IMUX_CE[3] bit 5 INT: mux OMUX[14] bit 4 INT: mux OMUX[15] bit 4 INT: mux IMUX_IOI_TCE[3] bit 9 INT: mux IMUX_IOI_TCE[3] bit 10 INT: mux IMUX_IOI_TCE[3] bit 4 INT: mux IMUX_IOI_TCE[3] bit 2 INT: mux IMUX_IOI_TCE[3] bit 0 INT: mux IMUX_IOI_TCE[3] bit 1 INT: mux DBL_W0[9] bit 6 INT: mux DBL_E0[9] bit 2 INT: mux DBL_E0[9] bit 4 INT: mux DBL_E0[9] bit 6 INT: mux HEX_E0[9] bit 2 INT: mux HEX_E0[9] bit 0 INT: mux HEX_E0[9] bit 4 INT: mux HEX_W0[9] bit 5
B75 - - - - INT: mux IMUX_CE[2] bit 4 INT: mux IMUX_CE[2] bit 7 INT: mux OMUX[15] bit 2 INT: mux OMUX[14] bit 2 - - - - - - INT: mux DBL_S0[9] bit 4 INT: mux DBL_N0[9] bit 2 INT: mux DBL_S0[9] bit 0 INT: mux DBL_S0[9] bit 3 INT: mux HEX_N0[9] bit 1 INT: mux HEX_N0[9] bit 3 INT: mux HEX_N0[9] bit 5 INT: mux LV[6] bit 0
B74 - - - - INT: mux IMUX_CE[3] bit 7 INT: mux IMUX_CE[3] bit 6 INT: mux OMUX[15] bit 1 INT: mux OMUX[14] bit 1 - - - - - - INT: mux DBL_S0[9] bit 5 INT: mux DBL_N0[9] bit 0 INT: mux DBL_N0[9] bit 7 INT: mux DBL_N0[9] bit 5 INT: mux HEX_S0[9] bit 1 INT: mux HEX_S0[9] bit 2 INT: mux HEX_S0[9] bit 4 INT: mux HEX_N0[9] bit 4
B73 - - - - INT: mux IMUX_CE[2] bit 0 INT: mux IMUX_CE[2] bit 1 INT: mux OMUX[14] bit 3 INT: mux OMUX[15] bit 3 - - - - - - INT: mux DBL_N0[9] bit 1 INT: mux DBL_S0[9] bit 6 INT: mux DBL_N0[9] bit 6 INT: mux DBL_N0[9] bit 4 INT: mux HEX_N0[9] bit 2 INT: mux HEX_N0[9] bit 0 INT: mux HEX_S0[9] bit 5 INT: mux LV[6] bit 6
B72 - - - - INT: !invert IMUX_CE_OPTINV[2] ← IMUX_CE[2] INT: mux IMUX_CE[2] bit 3 INT: mux OMUX[15] bit 5 INT: mux OMUX[14] bit 7 - - - - - - INT: mux DBL_N0[9] bit 3 INT: mux DBL_S0[9] bit 7 INT: mux DBL_S0[9] bit 1 INT: mux DBL_S0[9] bit 2 INT: mux HEX_S0[9] bit 3 INT: mux HEX_S0[9] bit 0 INT: mux HEX_S0[9] bit 6 INT: mux HEX_N0[9] bit 6
B71 - - - - INT: mux IMUX_CE[2] bit 6 INT: mux IMUX_CE[2] bit 2 INT: mux OMUX[14] bit 8 INT: mux OMUX[14] bit 6 - - INT: mux IMUX_G3_DATA[5] bit 7 INT: mux IMUX_G3_DATA[5] bit 5 INT: mux IMUX_G3_DATA[5] bit 2 INT: mux IMUX_G3_DATA[5] bit 3 INT: mux DBL_E0[8] bit 2 INT: mux DBL_W0[8] bit 3 INT: mux DBL_E0[8] bit 4 INT: mux DBL_E0[8] bit 7 INT: mux HEX_E0[8] bit 0 INT: mux HEX_E0[8] bit 3 INT: mux HEX_E0[8] bit 4 INT: mux LV[6] bit 2
B70 - - - - - - INT: mux OMUX[14] bit 5 INT: mux OMUX[14] bit 9 INT: mux IMUX_G3_DATA[5] bit 8 INT: mux IMUX_G3_DATA[5] bit 11 - - - - INT: mux DBL_E0[8] bit 0 INT: mux DBL_W0[8] bit 0 INT: mux DBL_W0[8] bit 7 INT: mux DBL_W0[8] bit 4 INT: mux HEX_W0[8] bit 0 INT: mux HEX_W0[8] bit 3 INT: mux HEX_W0[8] bit 4 INT: mux HEX_E0[8] bit 5
B69 - - - - - - INT: mux OMUX[12] bit 0 INT: mux OMUX[13] bit 9 INT: mux IMUX_G3_DATA[5] bit 9 INT: mux IMUX_G3_DATA[5] bit 10 INT: mux IMUX_G3_DATA[5] bit 6 INT: mux IMUX_G3_DATA[5] bit 4 INT: mux IMUX_G3_DATA[5] bit 1 INT: mux IMUX_G3_DATA[5] bit 0 INT: mux DBL_W0[8] bit 2 INT: mux DBL_E0[8] bit 3 INT: mux DBL_W0[8] bit 6 INT: mux DBL_W0[8] bit 5 INT: mux HEX_E0[8] bit 2 INT: mux HEX_E0[8] bit 1 INT: mux HEX_W0[8] bit 5 INT: mux LV[6] bit 3
B68 - - - - - - INT: mux OMUX[13] bit 8 INT: mux OMUX[13] bit 6 - - - - - - INT: mux DBL_W0[8] bit 1 INT: mux DBL_E0[8] bit 1 INT: mux DBL_E0[8] bit 5 INT: mux DBL_E0[8] bit 6 INT: mux HEX_W0[8] bit 2 INT: mux HEX_W0[8] bit 1 INT: mux HEX_W0[8] bit 6 INT: mux HEX_E0[8] bit 6
B67 - - - - - - INT: mux OMUX[13] bit 0 INT: mux OMUX[13] bit 7 INT: mux IMUX_G3_DATA[6] bit 9 INT: mux IMUX_G3_DATA[6] bit 10 INT: mux IMUX_G3_DATA[6] bit 6 INT: mux IMUX_G3_DATA[6] bit 4 INT: mux IMUX_G3_DATA[6] bit 1 INT: mux IMUX_G3_DATA[6] bit 0 INT: mux DBL_S0[8] bit 3 INT: mux DBL_N0[8] bit 1 INT: mux DBL_S0[8] bit 5 INT: mux DBL_S0[8] bit 7 INT: mux HEX_S0[8] bit 1 INT: mux HEX_S0[8] bit 3 INT: mux HEX_S0[8] bit 5 INT: mux LV[18] bit 6
B66 - - - - - - INT: mux OMUX[12] bit 4 INT: mux OMUX[13] bit 4 INT: mux IMUX_G3_DATA[7] bit 9 INT: mux IMUX_G3_DATA[7] bit 10 INT: mux IMUX_G3_DATA[7] bit 6 INT: mux IMUX_G3_DATA[7] bit 4 INT: mux IMUX_G3_DATA[7] bit 1 INT: mux IMUX_G3_DATA[7] bit 0 INT: mux DBL_S0[8] bit 0 INT: mux DBL_N0[8] bit 0 INT: mux DBL_N0[8] bit 7 INT: mux DBL_N0[8] bit 5 INT: mux HEX_N0[8] bit 1 INT: mux HEX_N0[8] bit 2 INT: mux HEX_N0[8] bit 5 INT: mux HEX_S0[8] bit 4
B65 - - - - - - INT: mux OMUX[13] bit 2 INT: mux OMUX[12] bit 2 INT: mux IMUX_G3_DATA[7] bit 8 INT: mux IMUX_G3_DATA[7] bit 11 INT: mux IMUX_G3_DATA[6] bit 7 INT: mux IMUX_G3_DATA[6] bit 5 INT: mux IMUX_G3_DATA[6] bit 2 INT: mux IMUX_G3_DATA[6] bit 3 INT: mux DBL_N0[8] bit 3 INT: mux DBL_S0[8] bit 1 INT: mux DBL_N0[8] bit 6 INT: mux DBL_N0[8] bit 4 INT: mux HEX_S0[8] bit 2 INT: mux HEX_S0[8] bit 0 INT: mux HEX_N0[8] bit 4 INT: mux LV[6] bit 1
B64 - - - - - - INT: mux OMUX[13] bit 1 INT: mux OMUX[12] bit 1 INT: mux IMUX_G3_DATA[6] bit 8 INT: mux IMUX_G3_DATA[6] bit 11 INT: mux IMUX_G3_DATA[7] bit 7 INT: mux IMUX_G3_DATA[7] bit 5 INT: mux IMUX_G3_DATA[7] bit 2 INT: mux IMUX_G3_DATA[7] bit 3 INT: mux DBL_N0[8] bit 2 INT: mux DBL_S0[8] bit 2 INT: mux DBL_S0[8] bit 4 INT: mux DBL_S0[8] bit 6 INT: mux HEX_N0[8] bit 3 INT: mux HEX_N0[8] bit 0 INT: mux HEX_N0[8] bit 6 INT: mux HEX_S0[8] bit 6
B63 - - - - - - INT: mux OMUX[12] bit 3 INT: mux OMUX[13] bit 3 INT: mux IMUX_G3_FAN[0] bit 8 INT: mux IMUX_G3_FAN[0] bit 11 INT: mux IMUX_G3_FAN[1] bit 7 INT: mux IMUX_G3_FAN[1] bit 5 INT: mux IMUX_G3_FAN[1] bit 2 INT: mux IMUX_G3_FAN[1] bit 3 INT: mux DBL_E0[7] bit 2 INT: mux DBL_W0[7] bit 3 INT: mux DBL_E0[7] bit 4 INT: mux DBL_E0[7] bit 7 INT: mux HEX_W0[7] bit 0 INT: mux HEX_W0[7] bit 3 INT: mux HEX_W0[7] bit 4 INT: mux LV[18] bit 0
B62 - - - - - - INT: mux OMUX[13] bit 5 INT: mux OMUX[12] bit 7 INT: mux IMUX_G3_FAN[1] bit 8 INT: mux IMUX_G3_FAN[1] bit 11 INT: mux IMUX_G3_FAN[0] bit 7 INT: mux IMUX_G3_FAN[0] bit 5 INT: mux IMUX_G3_FAN[0] bit 2 INT: mux IMUX_G3_FAN[0] bit 3 INT: mux DBL_E0[7] bit 0 INT: mux DBL_W0[7] bit 0 INT: mux DBL_W0[7] bit 7 INT: mux DBL_W0[7] bit 4 INT: mux HEX_E0[7] bit 0 INT: mux HEX_E0[7] bit 3 INT: mux HEX_E0[7] bit 4 INT: mux HEX_W0[7] bit 5
B61 - - - - INT: mux IMUX_CLK[2] bit 0 INT: mux IMUX_CLK[3] bit 7 INT: mux OMUX[12] bit 8 INT: mux OMUX[12] bit 6 INT: mux IMUX_G3_FAN[1] bit 9 INT: mux IMUX_G3_FAN[1] bit 10 INT: mux IMUX_G3_FAN[1] bit 6 INT: mux IMUX_G3_FAN[1] bit 4 INT: mux IMUX_G3_FAN[1] bit 1 INT: mux IMUX_G3_FAN[1] bit 0 INT: mux DBL_W0[7] bit 2 INT: mux DBL_E0[7] bit 3 INT: mux DBL_W0[7] bit 6 INT: mux DBL_W0[7] bit 5 INT: mux HEX_W0[7] bit 2 INT: mux HEX_W0[7] bit 1 INT: mux HEX_E0[7] bit 5 INT: mux LV[6] bit 5
B60 - - - - INT: invert IMUX_CLK_OPTINV[3] ← IMUX_CLK[3] INT: mux IMUX_CLK[3] bit 9 INT: mux OMUX[12] bit 5 INT: mux OMUX[12] bit 9 INT: mux IMUX_G3_FAN[0] bit 9 INT: mux IMUX_G3_FAN[0] bit 10 INT: mux IMUX_G3_FAN[0] bit 6 INT: mux IMUX_G3_FAN[0] bit 4 INT: mux IMUX_G3_FAN[0] bit 1 INT: mux IMUX_G3_FAN[0] bit 0 INT: mux DBL_W0[7] bit 1 INT: mux DBL_E0[7] bit 1 INT: mux DBL_E0[7] bit 5 INT: mux DBL_E0[7] bit 6 INT: mux HEX_E0[7] bit 2 INT: mux HEX_E0[7] bit 1 INT: mux HEX_E0[7] bit 6 INT: mux HEX_W0[7] bit 6
B59 - - - - INT: mux IMUX_CLK[3] bit 6 INT: mux IMUX_CLK[3] bit 8 INT: mux OMUX[10] bit 0 INT: mux OMUX[11] bit 9 INT: mux IMUX_G2_FAN[0] bit 9 INT: mux IMUX_G2_FAN[0] bit 10 INT: mux IMUX_G2_FAN[0] bit 6 INT: mux IMUX_G2_FAN[0] bit 5 INT: mux IMUX_G2_FAN[0] bit 1 INT: mux IMUX_G2_FAN[0] bit 3 INT: mux DBL_S0[7] bit 4 INT: mux DBL_N0[7] bit 6 INT: mux DBL_S0[7] bit 1 INT: mux DBL_S0[7] bit 3 INT: mux HEX_N0[7] bit 1 INT: mux HEX_N0[7] bit 3 INT: mux HEX_N0[7] bit 6 INT: mux LV[18] bit 2
B58 - - - - INT: mux IMUX_CLK[3] bit 3 INT: mux IMUX_CLK[3] bit 0 INT: mux OMUX[11] bit 8 INT: mux OMUX[11] bit 6 INT: mux IMUX_G2_FAN[1] bit 9 INT: mux IMUX_G2_FAN[1] bit 10 INT: mux IMUX_G2_FAN[1] bit 6 INT: mux IMUX_G2_FAN[1] bit 5 INT: mux IMUX_G2_FAN[1] bit 1 INT: mux IMUX_G2_FAN[1] bit 3 INT: mux DBL_S0[7] bit 5 INT: mux DBL_N0[7] bit 5 INT: mux DBL_N0[7] bit 3 INT: mux DBL_N0[7] bit 1 INT: mux HEX_S0[7] bit 1 INT: mux HEX_S0[7] bit 2 INT: mux HEX_S0[7] bit 5 INT: mux HEX_N0[7] bit 5
B57 - - - - INT: mux IMUX_CLK[2] bit 3 INT: mux IMUX_CLK[2] bit 1 INT: mux OMUX[11] bit 0 INT: mux OMUX[11] bit 7 INT: mux IMUX_G2_FAN[1] bit 8 INT: mux IMUX_G2_FAN[1] bit 11 INT: mux IMUX_G2_FAN[0] bit 7 INT: mux IMUX_G2_FAN[0] bit 4 INT: mux IMUX_G2_FAN[0] bit 0 INT: mux IMUX_G2_FAN[0] bit 2 INT: mux DBL_N0[7] bit 4 INT: mux DBL_S0[7] bit 6 INT: mux DBL_N0[7] bit 2 INT: mux DBL_N0[7] bit 0 INT: mux HEX_N0[7] bit 2 INT: mux HEX_N0[7] bit 0 INT: mux HEX_S0[7] bit 6 INT: mux LV[18] bit 4
B56 - - - - INT: mux IMUX_CLK[3] bit 1 INT: mux IMUX_CLK[3] bit 2 INT: mux OMUX[10] bit 4 INT: mux OMUX[11] bit 4 INT: mux IMUX_G2_FAN[0] bit 8 INT: mux IMUX_G2_FAN[0] bit 11 INT: mux IMUX_G2_FAN[1] bit 7 INT: mux IMUX_G2_FAN[1] bit 4 INT: mux IMUX_G2_FAN[1] bit 0 INT: mux IMUX_G2_FAN[1] bit 2 INT: mux DBL_N0[7] bit 7 INT: mux DBL_S0[7] bit 7 INT: mux DBL_S0[7] bit 0 INT: mux DBL_S0[7] bit 2 INT: mux HEX_S0[7] bit 3 INT: mux HEX_S0[7] bit 0 INT: mux HEX_S0[7] bit 4 INT: mux HEX_N0[7] bit 4
B55 - - - - INT: mux IMUX_CLK[2] bit 4 INT: mux IMUX_CLK[2] bit 2 INT: mux OMUX[11] bit 2 INT: mux OMUX[10] bit 2 INT: mux IMUX_G2_DATA[6] bit 8 INT: mux IMUX_G2_DATA[6] bit 11 INT: mux IMUX_G2_DATA[7] bit 7 INT: mux IMUX_G2_DATA[7] bit 4 INT: mux IMUX_G2_DATA[7] bit 0 INT: mux IMUX_G2_DATA[7] bit 2 INT: mux DBL_E0[6] bit 1 INT: mux DBL_W0[6] bit 7 INT: mux DBL_E0[6] bit 5 INT: mux DBL_E0[6] bit 7 INT: mux HEX_E0[6] bit 1 INT: mux HEX_E0[6] bit 3 INT: mux HEX_E0[6] bit 5 INT: mux LV[6] bit 4
B54 - - - - INT: mux IMUX_CLK[3] bit 4 INT: mux IMUX_CLK[2] bit 9 INT: mux OMUX[11] bit 1 INT: mux OMUX[10] bit 1 INT: mux IMUX_G2_DATA[7] bit 8 INT: mux IMUX_G2_DATA[7] bit 11 INT: mux IMUX_G2_DATA[6] bit 7 INT: mux IMUX_G2_DATA[6] bit 4 INT: mux IMUX_G2_DATA[6] bit 0 INT: mux IMUX_G2_DATA[6] bit 2 INT: mux DBL_E0[6] bit 0 INT: mux DBL_W0[6] bit 5 INT: mux DBL_W0[6] bit 3 INT: mux DBL_W0[6] bit 0 INT: mux HEX_W0[6] bit 1 INT: mux HEX_W0[6] bit 3 INT: mux HEX_W0[6] bit 4 INT: mux HEX_E0[6] bit 4
B53 - - - - INT: mux IMUX_CLK[2] bit 6 INT: mux IMUX_CLK[2] bit 8 INT: mux OMUX[10] bit 3 INT: mux OMUX[11] bit 3 INT: mux IMUX_G2_DATA[7] bit 9 INT: mux IMUX_G2_DATA[7] bit 10 INT: mux IMUX_G2_DATA[7] bit 6 INT: mux IMUX_G2_DATA[7] bit 5 INT: mux IMUX_G2_DATA[7] bit 1 INT: mux IMUX_G2_DATA[7] bit 3 INT: mux DBL_W0[6] bit 4 INT: mux DBL_E0[6] bit 3 INT: mux DBL_W0[6] bit 2 INT: mux DBL_W0[6] bit 1 INT: mux HEX_E0[6] bit 2 INT: mux HEX_E0[6] bit 0 INT: mux HEX_W0[6] bit 5 INT: mux LV[18] bit 5
B52 - - - - INT: invert IMUX_CLK_OPTINV[2] ← IMUX_CLK[2] INT: mux IMUX_CLK[3] bit 5 INT: mux OMUX[11] bit 5 INT: mux OMUX[10] bit 7 INT: mux IMUX_G2_DATA[6] bit 9 INT: mux IMUX_G2_DATA[6] bit 10 INT: mux IMUX_G2_DATA[6] bit 6 INT: mux IMUX_G2_DATA[6] bit 5 INT: mux IMUX_G2_DATA[6] bit 1 INT: mux IMUX_G2_DATA[6] bit 3 INT: mux DBL_W0[6] bit 6 INT: mux DBL_E0[6] bit 2 INT: mux DBL_E0[6] bit 4 INT: mux DBL_E0[6] bit 6 INT: mux HEX_W0[6] bit 2 INT: mux HEX_W0[6] bit 0 INT: mux HEX_W0[6] bit 6 INT: mux HEX_E0[6] bit 6
B51 - - - - INT: mux IMUX_CLK[2] bit 5 INT: mux IMUX_CLK[2] bit 7 INT: mux OMUX[10] bit 8 INT: mux OMUX[10] bit 6 - - - - - - INT: mux DBL_S0[6] bit 3 INT: mux DBL_N0[6] bit 1 INT: mux DBL_S0[6] bit 4 INT: mux DBL_S0[6] bit 7 INT: mux HEX_S0[6] bit 0 INT: mux HEX_S0[6] bit 3 INT: mux HEX_S0[6] bit 4 INT: mux LH[0] bit 0
B50 - - - - - - INT: mux OMUX[10] bit 5 INT: mux OMUX[10] bit 9 INT: mux IMUX_G2_DATA[5] bit 9 INT: mux IMUX_G2_DATA[5] bit 10 INT: mux IMUX_G2_DATA[5] bit 6 INT: mux IMUX_G2_DATA[5] bit 5 INT: mux IMUX_G2_DATA[5] bit 1 INT: mux IMUX_G2_DATA[5] bit 3 INT: mux DBL_S0[6] bit 0 INT: mux DBL_N0[6] bit 0 INT: mux DBL_N0[6] bit 7 INT: mux DBL_N0[6] bit 4 INT: mux HEX_N0[6] bit 0 INT: mux HEX_N0[6] bit 2 INT: mux HEX_N0[6] bit 4 INT: mux HEX_S0[6] bit 5
B49 - - - - - - INT: mux OMUX[8] bit 0 INT: mux OMUX[9] bit 9 INT: mux IMUX_G2_DATA[5] bit 8 INT: mux IMUX_G2_DATA[5] bit 11 - - - - INT: mux DBL_N0[6] bit 3 INT: mux DBL_S0[6] bit 1 INT: mux DBL_N0[6] bit 6 INT: mux DBL_N0[6] bit 5 INT: mux HEX_S0[6] bit 2 INT: mux HEX_S0[6] bit 1 INT: mux HEX_N0[6] bit 5 INT: mux LH[0] bit 1
B48 - - - - - - INT: mux OMUX[9] bit 8 INT: mux OMUX[9] bit 6 - - INT: mux IMUX_G2_DATA[5] bit 7 INT: mux IMUX_G2_DATA[5] bit 4 INT: mux IMUX_G2_DATA[5] bit 0 INT: mux IMUX_G2_DATA[5] bit 2 INT: mux DBL_N0[6] bit 2 INT: mux DBL_S0[6] bit 2 INT: mux DBL_S0[6] bit 5 INT: mux DBL_S0[6] bit 6 INT: mux HEX_N0[6] bit 3 INT: mux HEX_N0[6] bit 1 INT: mux HEX_N0[6] bit 6 INT: mux HEX_S0[6] bit 6
B47 - - - - - - INT: mux OMUX[9] bit 0 INT: mux OMUX[9] bit 7 - - - - - - INT: mux DBL_E0[5] bit 2 INT: mux DBL_W0[5] bit 3 INT: mux DBL_E0[5] bit 4 INT: mux DBL_E0[5] bit 7 INT: mux HEX_W0[5] bit 1 INT: mux HEX_W0[5] bit 3 INT: mux HEX_W0[5] bit 5 INT: mux LH[0] bit 2
B46 - - - - - - INT: mux OMUX[8] bit 4 INT: mux OMUX[9] bit 4 - - - - - - INT: mux DBL_E0[5] bit 0 INT: mux DBL_W0[5] bit 0 INT: mux DBL_W0[5] bit 7 INT: mux DBL_W0[5] bit 5 INT: mux HEX_E0[5] bit 0 INT: mux HEX_E0[5] bit 3 INT: mux HEX_E0[5] bit 4 INT: mux HEX_W0[5] bit 4
B45 - - - - - - INT: mux OMUX[9] bit 2 INT: mux OMUX[8] bit 2 - - - - - - INT: mux DBL_W0[5] bit 2 INT: mux DBL_E0[5] bit 3 INT: mux DBL_W0[5] bit 6 INT: mux DBL_W0[5] bit 4 INT: mux HEX_W0[5] bit 2 INT: mux HEX_W0[5] bit 0 INT: mux HEX_E0[5] bit 5 INT: mux LH[12] bit 1
B44 - - - - - - INT: mux OMUX[9] bit 1 INT: mux OMUX[8] bit 1 - - - - - - INT: mux DBL_W0[5] bit 1 INT: mux DBL_E0[5] bit 1 INT: mux DBL_E0[5] bit 5 INT: mux DBL_E0[5] bit 6 INT: mux HEX_E0[5] bit 2 INT: mux HEX_E0[5] bit 1 INT: mux HEX_E0[5] bit 6 INT: mux HEX_W0[5] bit 6
B43 - - - - - - INT: mux OMUX[8] bit 3 INT: mux OMUX[9] bit 3 INT: mux IMUX_IOI_ICE[3] bit 9 INT: mux IMUX_IOI_ICE[3] bit 10 INT: mux IMUX_IOI_ICE[3] bit 4 INT: mux IMUX_IOI_ICE[3] bit 3 INT: mux IMUX_IOI_ICE[3] bit 0 INT: mux IMUX_IOI_ICE[3] bit 6 INT: mux DBL_S0[5] bit 3 INT: mux DBL_N0[5] bit 1 INT: mux DBL_S0[5] bit 4 INT: mux DBL_S0[5] bit 7 INT: mux HEX_N0[5] bit 1 INT: mux HEX_N0[5] bit 3 INT: mux HEX_N0[5] bit 5 INT: mux LH[12] bit 0
B42 - - - - - - INT: mux OMUX[9] bit 5 INT: mux OMUX[8] bit 7 INT: mux IMUX_IOI_ICE[2] bit 9 INT: mux IMUX_IOI_ICE[2] bit 10 INT: mux IMUX_IOI_ICE[2] bit 4 INT: mux IMUX_IOI_ICE[2] bit 3 INT: mux IMUX_IOI_ICE[2] bit 0 INT: mux IMUX_IOI_ICE[2] bit 6 INT: mux DBL_S0[5] bit 0 INT: mux DBL_N0[5] bit 0 INT: mux DBL_N0[5] bit 7 INT: mux DBL_N0[5] bit 5 INT: mux HEX_S0[5] bit 0 INT: mux HEX_S0[5] bit 2 INT: mux HEX_S0[5] bit 4 INT: mux HEX_N0[5] bit 4
B41 - - - - - - INT: mux OMUX[8] bit 8 INT: mux OMUX[8] bit 6 INT: mux IMUX_IOI_ICE[2] bit 8 INT: mux IMUX_IOI_ICE[2] bit 11 INT: mux IMUX_IOI_ICE[3] bit 7 INT: mux IMUX_IOI_ICE[3] bit 2 INT: mux IMUX_IOI_ICE[3] bit 5 INT: mux IMUX_IOI_ICE[3] bit 1 INT: mux DBL_N0[5] bit 3 INT: mux DBL_S0[5] bit 1 INT: mux DBL_N0[5] bit 6 INT: mux DBL_N0[5] bit 4 INT: mux HEX_N0[5] bit 2 INT: mux HEX_N0[5] bit 0 INT: mux HEX_S0[5] bit 5 INT: mux LH[12] bit 2
B40 - - - - - - INT: mux OMUX[8] bit 5 INT: mux OMUX[8] bit 9 INT: mux IMUX_IOI_ICE[3] bit 8 INT: mux IMUX_IOI_ICE[3] bit 11 INT: mux IMUX_IOI_ICE[2] bit 7 INT: mux IMUX_IOI_ICE[2] bit 2 INT: mux IMUX_IOI_ICE[2] bit 5 INT: mux IMUX_IOI_ICE[2] bit 1 INT: mux DBL_N0[5] bit 2 INT: mux DBL_S0[5] bit 2 INT: mux DBL_S0[5] bit 5 INT: mux DBL_S0[5] bit 6 INT: mux HEX_S0[5] bit 3 INT: mux HEX_S0[5] bit 1 INT: mux HEX_S0[5] bit 6 INT: mux HEX_N0[5] bit 6
B39 - - - - INT: mux IMUX_IOI_ICLK[2] bit 0 INT: mux IMUX_IOI_ICLK[3] bit 7 INT: mux OMUX[6] bit 0 INT: mux OMUX[7] bit 9 INT: mux IMUX_IOI_TS2[3] bit 8 INT: mux IMUX_IOI_TS2[3] bit 11 INT: mux IMUX_IOI_TS2[2] bit 7 INT: mux IMUX_IOI_TS2[2] bit 3 INT: mux IMUX_IOI_TS2[2] bit 6 INT: mux IMUX_IOI_TS2[2] bit 1 INT: mux DBL_E0[4] bit 2 INT: mux DBL_W0[4] bit 3 INT: mux DBL_E0[4] bit 5 INT: mux DBL_E0[4] bit 7 INT: mux HEX_E0[4] bit 1 INT: mux HEX_E0[4] bit 3 INT: mux HEX_E0[4] bit 5 INT: mux LH[18] bit 2
B38 - - - - - INT: mux IMUX_IOI_ICLK[3] bit 9 INT: mux OMUX[7] bit 8 INT: mux OMUX[7] bit 6 INT: mux IMUX_IOI_TS2[2] bit 8 INT: mux IMUX_IOI_TS2[2] bit 11 INT: mux IMUX_IOI_TS2[3] bit 7 INT: mux IMUX_IOI_TS2[3] bit 3 INT: mux IMUX_IOI_TS2[3] bit 6 INT: mux IMUX_IOI_TS2[3] bit 1 INT: mux DBL_E0[4] bit 0 INT: mux DBL_W0[4] bit 0 INT: mux DBL_W0[4] bit 7 INT: mux DBL_W0[4] bit 5 INT: mux HEX_W0[4] bit 1 INT: mux HEX_W0[4] bit 3 INT: mux HEX_W0[4] bit 5 INT: mux HEX_E0[4] bit 4
B37 - - - - INT: mux IMUX_IOI_ICLK[3] bit 6 INT: mux IMUX_IOI_ICLK[3] bit 8 INT: mux OMUX[7] bit 0 INT: mux OMUX[7] bit 7 INT: mux IMUX_IOI_TS2[2] bit 9 INT: mux IMUX_IOI_TS2[2] bit 10 INT: mux IMUX_IOI_TS2[2] bit 4 INT: mux IMUX_IOI_TS2[2] bit 2 INT: mux IMUX_IOI_TS2[2] bit 0 INT: mux IMUX_IOI_TS2[2] bit 5 INT: mux DBL_W0[4] bit 2 INT: mux DBL_E0[4] bit 3 INT: mux DBL_W0[4] bit 6 INT: mux DBL_W0[4] bit 4 INT: mux HEX_E0[4] bit 2 INT: mux HEX_E0[4] bit 0 INT: mux HEX_W0[4] bit 4 INT: mux LH[18] bit 1
B36 - - - - INT: mux IMUX_IOI_ICLK[3] bit 3 INT: mux IMUX_IOI_ICLK[3] bit 0 INT: mux OMUX[6] bit 4 INT: mux OMUX[7] bit 4 INT: mux IMUX_IOI_TS2[3] bit 9 INT: mux IMUX_IOI_TS2[3] bit 10 INT: mux IMUX_IOI_TS2[3] bit 4 INT: mux IMUX_IOI_TS2[3] bit 2 INT: mux IMUX_IOI_TS2[3] bit 0 INT: mux IMUX_IOI_TS2[3] bit 5 INT: mux DBL_W0[4] bit 1 INT: mux DBL_E0[4] bit 1 INT: mux DBL_E0[4] bit 4 INT: mux DBL_E0[4] bit 6 INT: mux HEX_W0[4] bit 2 INT: mux HEX_W0[4] bit 0 INT: mux HEX_W0[4] bit 6 INT: mux HEX_E0[4] bit 6
B35 - - - - INT: mux IMUX_IOI_ICLK[2] bit 3 INT: mux IMUX_IOI_ICLK[2] bit 1 INT: mux OMUX[7] bit 2 INT: mux OMUX[6] bit 2 - - - - - - INT: mux DBL_S0[4] bit 3 INT: mux DBL_N0[4] bit 1 INT: mux DBL_S0[4] bit 4 INT: mux DBL_S0[4] bit 7 INT: mux HEX_S0[4] bit 0 INT: mux HEX_S0[4] bit 3 INT: mux HEX_S0[4] bit 4 INT: mux LH[18] bit 0
B34 - - - - INT: mux IMUX_IOI_ICLK[3] bit 1 INT: mux IMUX_IOI_ICLK[3] bit 2 INT: mux OMUX[7] bit 1 INT: mux OMUX[6] bit 1 - - - - - - INT: mux DBL_S0[4] bit 0 INT: mux DBL_N0[4] bit 0 INT: mux DBL_N0[4] bit 7 INT: mux DBL_N0[4] bit 4 INT: mux HEX_N0[4] bit 0 INT: mux HEX_N0[4] bit 2 INT: mux HEX_N0[4] bit 4 INT: mux HEX_S0[4] bit 5
B33 - - - - INT: mux IMUX_IOI_ICLK[2] bit 4 INT: mux IMUX_IOI_ICLK[2] bit 2 INT: mux OMUX[6] bit 3 INT: mux OMUX[7] bit 3 - - - - - - INT: mux DBL_N0[4] bit 3 INT: mux DBL_S0[4] bit 1 INT: mux DBL_N0[4] bit 6 INT: mux DBL_N0[4] bit 5 INT: mux HEX_S0[4] bit 2 INT: mux HEX_S0[4] bit 1 INT: mux HEX_N0[4] bit 5 INT: mux LH[6] bit 1
B32 - - - - INT: mux IMUX_IOI_ICLK[3] bit 4 INT: mux IMUX_IOI_ICLK[2] bit 9 INT: mux OMUX[7] bit 5 INT: mux OMUX[6] bit 7 - - - - - - INT: mux DBL_N0[4] bit 2 INT: mux DBL_S0[4] bit 2 INT: mux DBL_S0[4] bit 5 INT: mux DBL_S0[4] bit 6 INT: mux HEX_N0[4] bit 3 INT: mux HEX_N0[4] bit 1 INT: mux HEX_N0[4] bit 6 INT: mux HEX_S0[4] bit 6
B31 - - - - INT: mux IMUX_IOI_ICLK[2] bit 6 INT: mux IMUX_IOI_ICLK[2] bit 8 INT: mux OMUX[6] bit 8 INT: mux OMUX[6] bit 6 - - - - - - INT: mux DBL_E0[3] bit 2 INT: mux DBL_W0[3] bit 3 INT: mux DBL_E0[3] bit 4 INT: mux DBL_E0[3] bit 7 INT: mux HEX_W0[3] bit 1 INT: mux HEX_W0[3] bit 3 INT: mux HEX_W0[3] bit 5 INT: mux LH[6] bit 2
B30 - - - - - INT: mux IMUX_IOI_ICLK[3] bit 5 INT: mux OMUX[6] bit 5 INT: mux OMUX[6] bit 9 - - - - - - INT: mux DBL_E0[3] bit 0 INT: mux DBL_W0[3] bit 0 INT: mux DBL_W0[3] bit 7 INT: mux DBL_W0[3] bit 5 INT: mux HEX_E0[3] bit 0 INT: mux HEX_E0[3] bit 3 INT: mux HEX_E0[3] bit 4 INT: mux HEX_W0[3] bit 4
B29 - - - - INT: mux IMUX_IOI_ICLK[2] bit 5 INT: mux IMUX_IOI_ICLK[2] bit 7 INT: mux OMUX[4] bit 0 INT: mux OMUX[5] bit 9 - - - - - - INT: mux DBL_W0[3] bit 2 INT: mux DBL_E0[3] bit 3 INT: mux DBL_W0[3] bit 6 INT: mux DBL_W0[3] bit 4 INT: mux HEX_W0[3] bit 2 INT: mux HEX_W0[3] bit 0 INT: mux HEX_E0[3] bit 5 INT: mux LH[6] bit 0
B28 - - - - - - INT: mux OMUX[5] bit 8 INT: mux OMUX[5] bit 6 - - - - - - INT: mux DBL_W0[3] bit 1 INT: mux DBL_E0[3] bit 1 INT: mux DBL_E0[3] bit 5 INT: mux DBL_E0[3] bit 6 INT: mux HEX_E0[3] bit 2 INT: mux HEX_E0[3] bit 1 INT: mux HEX_E0[3] bit 6 INT: mux HEX_W0[3] bit 6
B27 - - - - - - INT: mux OMUX[5] bit 0 INT: mux OMUX[5] bit 7 - - - - - - INT: mux DBL_S0[3] bit 3 INT: mux DBL_N0[3] bit 1 INT: mux DBL_S0[3] bit 5 INT: mux DBL_S0[3] bit 7 INT: mux HEX_N0[3] bit 0 INT: mux HEX_N0[3] bit 3 INT: mux HEX_N0[3] bit 4 INT: mux LV[12] bit 4
B26 - - - - - - INT: mux OMUX[4] bit 4 INT: mux OMUX[5] bit 4 - - - - - - INT: mux DBL_S0[3] bit 0 INT: mux DBL_N0[3] bit 0 INT: mux DBL_N0[3] bit 7 INT: mux DBL_N0[3] bit 4 INT: mux HEX_S0[3] bit 1 INT: mux HEX_S0[3] bit 2 INT: mux HEX_S0[3] bit 5 INT: mux HEX_N0[3] bit 5
B25 - - - - - - INT: mux OMUX[5] bit 2 INT: mux OMUX[4] bit 2 - - - - - - INT: mux DBL_N0[3] bit 3 INT: mux DBL_S0[3] bit 1 INT: mux DBL_N0[3] bit 6 INT: mux DBL_N0[3] bit 5 INT: mux HEX_N0[3] bit 2 INT: mux HEX_N0[3] bit 1 INT: mux HEX_S0[3] bit 4 INT: mux LV[0] bit 3
B24 - - - - - - INT: mux OMUX[5] bit 1 INT: mux OMUX[4] bit 1 - - - - - - INT: mux DBL_N0[3] bit 2 INT: mux DBL_S0[3] bit 2 INT: mux DBL_S0[3] bit 4 INT: mux DBL_S0[3] bit 6 INT: mux HEX_S0[3] bit 3 INT: mux HEX_S0[3] bit 0 INT: mux HEX_S0[3] bit 6 INT: mux HEX_N0[3] bit 6
B23 - - - - - - INT: mux OMUX[4] bit 3 INT: mux OMUX[5] bit 3 INT: mux IMUX_G1_FAN[0] bit 9 INT: mux IMUX_G1_FAN[0] bit 11 INT: mux IMUX_G1_FAN[1] bit 7 INT: mux IMUX_G1_FAN[1] bit 5 INT: mux IMUX_G1_FAN[1] bit 1 INT: mux IMUX_G1_FAN[1] bit 2 INT: mux DBL_E0[2] bit 4 INT: mux DBL_W0[2] bit 7 INT: mux DBL_E0[2] bit 1 INT: mux DBL_E0[2] bit 3 INT: mux HEX_E0[2] bit 1 INT: mux HEX_E0[2] bit 3 INT: mux HEX_E0[2] bit 5 INT: mux LV[12] bit 3
B22 - - - - - - INT: mux OMUX[5] bit 5 INT: mux OMUX[4] bit 7 INT: mux IMUX_G1_FAN[1] bit 9 INT: mux IMUX_G1_FAN[1] bit 11 INT: mux IMUX_G1_FAN[0] bit 7 INT: mux IMUX_G1_FAN[0] bit 5 INT: mux IMUX_G1_FAN[0] bit 1 INT: mux IMUX_G1_FAN[0] bit 2 INT: mux DBL_E0[2] bit 5 INT: mux DBL_W0[2] bit 5 INT: mux DBL_W0[2] bit 3 INT: mux DBL_W0[2] bit 1 INT: mux HEX_W0[2] bit 1 INT: mux HEX_W0[2] bit 3 INT: mux HEX_W0[2] bit 6 INT: mux HEX_E0[2] bit 6
B21 - - - - - - INT: mux OMUX[4] bit 8 INT: mux OMUX[4] bit 6 INT: mux IMUX_G1_FAN[1] bit 8 INT: mux IMUX_G1_FAN[1] bit 10 INT: mux IMUX_G1_FAN[1] bit 6 INT: mux IMUX_G1_FAN[1] bit 4 INT: mux IMUX_G1_FAN[1] bit 0 INT: mux IMUX_G1_FAN[1] bit 3 INT: mux DBL_W0[2] bit 4 INT: mux DBL_E0[2] bit 7 INT: mux DBL_W0[2] bit 2 INT: mux DBL_W0[2] bit 0 INT: mux HEX_E0[2] bit 2 INT: mux HEX_E0[2] bit 0 INT: mux HEX_W0[2] bit 5 INT: mux LV[0] bit 2
B20 - - - - - - INT: mux OMUX[4] bit 5 INT: mux OMUX[4] bit 9 INT: mux IMUX_G1_FAN[0] bit 8 INT: mux IMUX_G1_FAN[0] bit 10 INT: mux IMUX_G1_FAN[0] bit 6 INT: mux IMUX_G1_FAN[0] bit 4 INT: mux IMUX_G1_FAN[0] bit 0 INT: mux IMUX_G1_FAN[0] bit 3 INT: mux DBL_W0[2] bit 6 INT: mux DBL_E0[2] bit 6 INT: mux DBL_E0[2] bit 0 INT: mux DBL_E0[2] bit 2 INT: mux HEX_W0[2] bit 2 INT: mux HEX_W0[2] bit 0 INT: mux HEX_W0[2] bit 4 INT: mux HEX_E0[2] bit 4
B19 - - - - - - INT: mux OMUX[2] bit 0 INT: mux OMUX[3] bit 9 INT: mux IMUX_G0_FAN[0] bit 9 INT: mux IMUX_G0_FAN[0] bit 10 INT: mux IMUX_G0_FAN[0] bit 6 INT: mux IMUX_G0_FAN[0] bit 5 INT: mux IMUX_G0_FAN[0] bit 2 INT: mux IMUX_G0_FAN[0] bit 1 INT: mux DBL_S0[2] bit 4 INT: mux DBL_N0[2] bit 6 INT: mux DBL_S0[2] bit 0 INT: mux DBL_S0[2] bit 3 INT: mux HEX_S0[2] bit 0 INT: mux HEX_S0[2] bit 3 INT: mux HEX_S0[2] bit 5 INT: mux LV[0] bit 4
B18 - - - - - - INT: mux OMUX[3] bit 8 INT: mux OMUX[3] bit 6 INT: mux IMUX_G0_FAN[1] bit 9 INT: mux IMUX_G0_FAN[1] bit 10 INT: mux IMUX_G0_FAN[1] bit 6 INT: mux IMUX_G0_FAN[1] bit 5 INT: mux IMUX_G0_FAN[1] bit 2 INT: mux IMUX_G0_FAN[1] bit 1 INT: mux DBL_S0[2] bit 5 INT: mux DBL_N0[2] bit 5 INT: mux DBL_N0[2] bit 3 INT: mux DBL_N0[2] bit 0 INT: mux HEX_N0[2] bit 1 INT: mux HEX_N0[2] bit 2 INT: mux HEX_N0[2] bit 4 INT: mux HEX_S0[2] bit 4
B17 - - - - INT: mux IMUX_SR[3] bit 5 INT: mux IMUX_SR[1] bit 1 INT: mux OMUX[3] bit 0 INT: mux OMUX[3] bit 7 INT: mux IMUX_G0_FAN[1] bit 8 INT: mux IMUX_G0_FAN[1] bit 11 INT: mux IMUX_G0_FAN[0] bit 7 INT: mux IMUX_G0_FAN[0] bit 4 INT: mux IMUX_G0_FAN[0] bit 0 INT: mux IMUX_G0_FAN[0] bit 3 INT: mux DBL_N0[2] bit 4 INT: mux DBL_S0[2] bit 6 INT: mux DBL_N0[2] bit 2 INT: mux DBL_N0[2] bit 1 INT: mux HEX_S0[2] bit 2 INT: mux HEX_S0[2] bit 1 INT: mux HEX_N0[2] bit 5 INT: mux LV[12] bit 2
B16 - - - - INT: !invert IMUX_SR_OPTINV[1] ← IMUX_SR[1] INT: mux IMUX_SR[1] bit 3 INT: mux OMUX[2] bit 4 INT: mux OMUX[3] bit 4 INT: mux IMUX_G0_FAN[0] bit 8 INT: mux IMUX_G0_FAN[0] bit 11 INT: mux IMUX_G0_FAN[1] bit 7 INT: mux IMUX_G0_FAN[1] bit 4 INT: mux IMUX_G0_FAN[1] bit 0 INT: mux IMUX_G0_FAN[1] bit 3 INT: mux DBL_N0[2] bit 7 INT: mux DBL_S0[2] bit 7 INT: mux DBL_S0[2] bit 1 INT: mux DBL_S0[2] bit 2 INT: mux HEX_N0[2] bit 3 INT: mux HEX_N0[2] bit 0 INT: mux HEX_N0[2] bit 6 INT: mux HEX_S0[2] bit 6
B15 - - - - INT: mux IMUX_SR[1] bit 0 INT: mux IMUX_SR[1] bit 2 INT: mux OMUX[3] bit 2 INT: mux OMUX[2] bit 2 - - - - - - INT: mux DBL_E0[1] bit 2 INT: mux DBL_W0[1] bit 3 INT: mux DBL_E0[1] bit 4 INT: mux DBL_E0[1] bit 7 INT: mux HEX_W0[1] bit 1 INT: mux HEX_W0[1] bit 2 INT: mux HEX_W0[1] bit 5 INT: mux LV[12] bit 0
B14 - - - - INT: mux IMUX_SR[1] bit 4 INT: mux IMUX_SR[1] bit 5 INT: mux OMUX[3] bit 1 INT: mux OMUX[2] bit 1 - - - - - - INT: mux DBL_E0[1] bit 0 INT: mux DBL_W0[1] bit 0 INT: mux DBL_W0[1] bit 6 INT: mux DBL_W0[1] bit 5 INT: mux HEX_E0[1] bit 0 INT: mux HEX_E0[1] bit 3 INT: mux HEX_E0[1] bit 4 INT: mux HEX_W0[1] bit 4
B13 - - - - INT: mux IMUX_SR[3] bit 4 INT: mux IMUX_SR[3] bit 7 INT: mux OMUX[2] bit 3 INT: mux OMUX[3] bit 3 - - - - - - INT: mux DBL_W0[1] bit 2 INT: mux DBL_E0[1] bit 3 INT: mux DBL_W0[1] bit 7 INT: mux DBL_W0[1] bit 4 INT: mux HEX_W0[1] bit 3 INT: mux HEX_W0[1] bit 0 INT: mux HEX_E0[1] bit 5 INT: mux LV[12] bit 6
B12 - - - - INT: mux IMUX_SR[1] bit 7 INT: mux IMUX_SR[1] bit 6 INT: mux OMUX[3] bit 5 INT: mux OMUX[2] bit 7 - - - - - - INT: mux DBL_W0[1] bit 1 INT: mux DBL_E0[1] bit 1 INT: mux DBL_E0[1] bit 5 INT: mux DBL_E0[1] bit 6 INT: mux HEX_E0[1] bit 2 INT: mux HEX_E0[1] bit 1 INT: mux HEX_E0[1] bit 6 INT: mux HEX_W0[1] bit 6
B11 - - - - INT: mux IMUX_SR[3] bit 0 INT: mux IMUX_SR[3] bit 1 INT: mux OMUX[2] bit 8 INT: mux OMUX[2] bit 6 - - - - - - INT: mux DBL_S0[1] bit 3 INT: mux DBL_N0[1] bit 1 INT: mux DBL_S0[1] bit 4 INT: mux DBL_S0[1] bit 7 INT: mux HEX_N0[1] bit 0 INT: mux HEX_N0[1] bit 3 INT: mux HEX_N0[1] bit 4 INT: mux LV[0] bit 1
B10 - - - - INT: !invert IMUX_SR_OPTINV[3] ← IMUX_SR[3] INT: mux IMUX_SR[3] bit 3 INT: mux OMUX[2] bit 5 INT: mux OMUX[2] bit 9 - - - - - - INT: mux DBL_S0[1] bit 0 INT: mux DBL_N0[1] bit 0 INT: mux DBL_N0[1] bit 7 INT: mux DBL_N0[1] bit 4 INT: mux HEX_S0[1] bit 0 INT: mux HEX_S0[1] bit 2 INT: mux HEX_S0[1] bit 4 INT: mux HEX_N0[1] bit 5
B9 - - - - INT: mux IMUX_SR[3] bit 6 INT: mux IMUX_SR[3] bit 2 INT: mux OMUX[0] bit 0 INT: mux OMUX[1] bit 9 - - - - - - INT: mux DBL_N0[1] bit 3 INT: mux DBL_S0[1] bit 1 INT: mux DBL_N0[1] bit 6 INT: mux DBL_N0[1] bit 5 INT: mux HEX_N0[1] bit 2 INT: mux HEX_N0[1] bit 1 INT: mux HEX_S0[1] bit 5 INT: mux LV[0] bit 5
B8 - - - - - - INT: mux OMUX[1] bit 8 INT: mux OMUX[1] bit 6 - - - - - - INT: mux DBL_N0[1] bit 2 INT: mux DBL_S0[1] bit 2 INT: mux DBL_S0[1] bit 5 INT: mux DBL_S0[1] bit 6 INT: mux HEX_S0[1] bit 3 INT: mux HEX_S0[1] bit 1 INT: mux HEX_S0[1] bit 6 INT: mux HEX_N0[1] bit 6
B7 - - - - - - INT: mux OMUX[1] bit 0 INT: mux OMUX[1] bit 7 - - - - - - INT: mux DBL_E0[0] bit 2 INT: mux DBL_W0[0] bit 3 INT: mux DBL_E0[0] bit 4 INT: mux DBL_E0[0] bit 7 INT: mux HEX_E0[0] bit 0 INT: mux HEX_E0[0] bit 3 INT: mux HEX_E0[0] bit 4 INT: mux LV[0] bit 6
B6 - - - - - - INT: mux OMUX[0] bit 4 INT: mux OMUX[1] bit 4 - - - - - - INT: mux DBL_E0[0] bit 0 INT: mux DBL_W0[0] bit 0 INT: mux DBL_W0[0] bit 6 INT: mux DBL_W0[0] bit 5 INT: mux HEX_W0[0] bit 1 INT: mux HEX_W0[0] bit 2 INT: mux HEX_W0[0] bit 5 INT: mux HEX_E0[0] bit 5
B5 - - - - - - INT: mux OMUX[1] bit 2 INT: mux OMUX[0] bit 2 - - - - - - INT: mux DBL_W0[0] bit 2 INT: mux DBL_E0[0] bit 3 INT: mux DBL_W0[0] bit 7 INT: mux DBL_W0[0] bit 4 INT: mux HEX_E0[0] bit 2 INT: mux HEX_E0[0] bit 1 INT: mux HEX_W0[0] bit 4 INT: mux LV[0] bit 0
B4 - - - - - - INT: mux OMUX[1] bit 1 INT: mux OMUX[0] bit 1 - - - - - - INT: mux DBL_W0[0] bit 1 INT: mux DBL_E0[0] bit 1 INT: mux DBL_E0[0] bit 5 INT: mux DBL_E0[0] bit 6 INT: mux HEX_W0[0] bit 3 INT: mux HEX_W0[0] bit 0 INT: mux HEX_W0[0] bit 6 INT: mux HEX_E0[0] bit 6
B3 - - - - - - INT: mux OMUX[0] bit 3 INT: mux OMUX[1] bit 3 INT: mux IMUX_IOI_TS1[3] bit 9 INT: mux IMUX_IOI_TS1[3] bit 10 INT: mux IMUX_IOI_TS1[3] bit 4 INT: mux IMUX_IOI_TS1[3] bit 3 INT: mux IMUX_IOI_TS1[3] bit 0 INT: mux IMUX_IOI_TS1[3] bit 6 INT: mux DBL_S0[0] bit 4 INT: mux DBL_N0[0] bit 6 INT: mux DBL_S0[0] bit 1 INT: mux DBL_S0[0] bit 3 INT: mux HEX_S0[0] bit 1 INT: mux HEX_S0[0] bit 3 INT: mux HEX_S0[0] bit 6 INT: mux LV[12] bit 1
B2 - - - - - - INT: mux OMUX[1] bit 5 INT: mux OMUX[0] bit 7 INT: mux IMUX_IOI_TS1[2] bit 9 INT: mux IMUX_IOI_TS1[2] bit 10 INT: mux IMUX_IOI_TS1[2] bit 4 INT: mux IMUX_IOI_TS1[2] bit 3 INT: mux IMUX_IOI_TS1[2] bit 0 INT: mux IMUX_IOI_TS1[2] bit 6 INT: mux DBL_S0[0] bit 5 INT: mux DBL_N0[0] bit 5 INT: mux DBL_N0[0] bit 3 INT: mux DBL_N0[0] bit 1 INT: mux HEX_N0[0] bit 1 INT: mux HEX_N0[0] bit 2 INT: mux HEX_N0[0] bit 5 INT: mux HEX_S0[0] bit 5
B1 - - - - - - INT: mux OMUX[0] bit 8 INT: mux OMUX[0] bit 6 INT: mux IMUX_IOI_TS1[2] bit 8 INT: mux IMUX_IOI_TS1[2] bit 11 INT: mux IMUX_IOI_TS1[3] bit 7 INT: mux IMUX_IOI_TS1[3] bit 2 INT: mux IMUX_IOI_TS1[3] bit 5 INT: mux IMUX_IOI_TS1[3] bit 1 INT: mux DBL_N0[0] bit 4 INT: mux DBL_S0[0] bit 6 INT: mux DBL_N0[0] bit 2 INT: mux DBL_N0[0] bit 0 INT: mux HEX_S0[0] bit 2 INT: mux HEX_S0[0] bit 0 INT: mux HEX_N0[0] bit 6 INT: mux LV[12] bit 5
B0 - - - - - - INT: mux OMUX[0] bit 5 INT: mux OMUX[0] bit 9 INT: mux IMUX_IOI_TS1[3] bit 8 INT: mux IMUX_IOI_TS1[3] bit 11 INT: mux IMUX_IOI_TS1[2] bit 7 INT: mux IMUX_IOI_TS1[2] bit 2 INT: mux IMUX_IOI_TS1[2] bit 5 INT: mux IMUX_IOI_TS1[2] bit 1 INT: mux DBL_N0[0] bit 7 INT: mux DBL_S0[0] bit 7 INT: mux DBL_S0[0] bit 0 INT: mux DBL_S0[0] bit 2 INT: mux HEX_N0[0] bit 3 INT: mux HEX_N0[0] bit 0 INT: mux HEX_N0[0] bit 4 INT: mux HEX_S0[0] bit 4

INT_DCM_V2

Used with the Virtex 2 DCM_V2 tile.

Tile INT_DCM_V2

Cells: 1

Switchbox INT

virtex2 INT_DCM_V2 switchbox INT programmable inverters
DestinationSourceBit
IMUX_DCM_CLK_OPTINV[0]IMUX_DCM_CLK[0]MAIN[4][38]
IMUX_DCM_CLK_OPTINV[1]IMUX_DCM_CLK[1]MAIN[4][48]
IMUX_DCM_CLK_OPTINV[2]IMUX_DCM_CLK[2]MAIN[4][51]
IMUX_SR_OPTINV[0]IMUX_SR[0]!MAIN[4][1]
IMUX_SR_OPTINV[1]IMUX_SR[1]!MAIN[4][16]
IMUX_SR_OPTINV[2]IMUX_SR[2]!MAIN[4][7]
IMUX_SR_OPTINV[3]IMUX_SR[3]!MAIN[4][10]
IMUX_CE_OPTINV[2]IMUX_CE[2]!MAIN[4][72]
IMUX_CE_OPTINV[3]IMUX_CE[3]!MAIN[4][78]
IMUX_TI_OPTINV[0]IMUX_TI[0]!MAIN[4][19]
IMUX_TI_OPTINV[1]IMUX_TI[1]!MAIN[4][27]
virtex2 INT_DCM_V2 switchbox INT muxes OMUX[0]
BitsDestination
MAIN[6][1]MAIN[7][2]MAIN[7][1]MAIN[7][0]MAIN[6][0]MAIN[6][3]MAIN[7][4]MAIN[7][5]MAIN[6][6]MAIN[6][9]OMUX[0]
Source
0000000000off
0001000001IMUX_SR[0]
0001000010IMUX_SR[2]
0001000100IMUX_G0_DATA[0]
0001001000IMUX_G0_DATA[1]
0001010000IMUX_G0_DATA[2]
0001100000IMUX_G0_DATA[3]
0010000100OUT_SEC[2]
0010001000OUT_SEC[3]
0010010000OUT_SEC[4]
0010100000OUT_SEC[5]
0100000001OUT_SEC[6]
0100000010OUT_SEC[7]
0100000100OUT_SEC[8]
0100001000OUT_SEC[9]
0100010000OUT_SEC[10]
0100100000OUT_SEC[11]
1000000001OUT_SEC[12]
1000000010OUT_SEC[13]
1000000100OUT_HALF0[17]
1000001000OUT_HALF0[16]
1000010000OUT_HALF0[15]
1000100000OUT_HALF0[14]
virtex2 INT_DCM_V2 switchbox INT muxes OMUX[1]
BitsDestination
MAIN[6][8]MAIN[7][7]MAIN[7][8]MAIN[7][9]MAIN[6][2]MAIN[7][3]MAIN[6][4]MAIN[6][5]MAIN[7][6]MAIN[6][7]OMUX[1]
Source
0000000000off
0001000001IMUX_SR[0]
0001000010IMUX_SR[2]
0001000100IMUX_G0_DATA[0]
0001001000IMUX_G0_DATA[1]
0001010000IMUX_G0_DATA[2]
0001100000IMUX_G0_DATA[3]
0010000100OUT_SEC[2]
0010001000OUT_SEC[3]
0010010000OUT_SEC[4]
0010100000OUT_SEC[5]
0100000001OUT_SEC[6]
0100000010OUT_SEC[7]
0100000100OUT_SEC[8]
0100001000OUT_SEC[9]
0100010000OUT_SEC[10]
0100100000OUT_SEC[11]
1000000001OUT_SEC[12]
1000000010OUT_SEC[13]
1000000100OUT_HALF0[17]
1000001000OUT_HALF0[16]
1000010000OUT_HALF0[15]
1000100000OUT_HALF0[14]
virtex2 INT_DCM_V2 switchbox INT muxes OMUX[2]
BitsDestination
MAIN[6][11]MAIN[7][12]MAIN[7][11]MAIN[7][10]MAIN[6][10]MAIN[6][13]MAIN[7][14]MAIN[7][15]MAIN[6][16]MAIN[6][19]OMUX[2]
Source
0000000000off
0001000001IMUX_SR[1]
0001000010IMUX_SR[3]
0001000100IMUX_G0_DATA[4]
0001001000IMUX_G0_DATA[5]
0001010000IMUX_G0_DATA[6]
0001100000IMUX_G0_DATA[7]
0010000100OUT_SEC[2]
0010001000OUT_SEC[3]
0010010000OUT_SEC[4]
0010100000OUT_SEC[5]
0100000001OUT_SEC[6]
0100000010OUT_SEC[7]
0100000100OUT_SEC[8]
0100001000OUT_SEC[9]
0100010000OUT_SEC[10]
0100100000OUT_SEC[11]
1000000001OUT_SEC[12]
1000000010OUT_SEC[13]
1000000100OUT_HALF0[17]
1000001000OUT_HALF0[16]
1000010000OUT_HALF0[15]
1000100000OUT_HALF0[14]
virtex2 INT_DCM_V2 switchbox INT muxes OMUX[3]
BitsDestination
MAIN[6][18]MAIN[7][17]MAIN[7][18]MAIN[7][19]MAIN[6][12]MAIN[7][13]MAIN[6][14]MAIN[6][15]MAIN[7][16]MAIN[6][17]OMUX[3]
Source
0000000000off
0001000001IMUX_SR[1]
0001000010IMUX_SR[3]
0001000100IMUX_G0_DATA[4]
0001001000IMUX_G0_DATA[5]
0001010000IMUX_G0_DATA[6]
0001100000IMUX_G0_DATA[7]
0010000100OUT_SEC[2]
0010001000OUT_SEC[3]
0010010000OUT_SEC[4]
0010100000OUT_SEC[5]
0100000001OUT_SEC[6]
0100000010OUT_SEC[7]
0100000100OUT_SEC[8]
0100001000OUT_SEC[9]
0100010000OUT_SEC[10]
0100100000OUT_SEC[11]
1000000001OUT_SEC[12]
1000000010OUT_SEC[13]
1000000100OUT_HALF0[17]
1000001000OUT_HALF0[16]
1000010000OUT_HALF0[15]
1000100000OUT_HALF0[14]
virtex2 INT_DCM_V2 switchbox INT muxes OMUX[4]
BitsDestination
MAIN[6][21]MAIN[7][22]MAIN[7][21]MAIN[7][20]MAIN[6][20]MAIN[6][23]MAIN[7][24]MAIN[7][25]MAIN[6][26]MAIN[6][29]OMUX[4]
Source
0000000000off
0001000001IMUX_TI[0]
0001000010IMUX_TI[1]
0001000100IMUX_G1_DATA[4]
0001001000IMUX_G1_DATA[5]
0001010000IMUX_G1_DATA[6]
0001100000IMUX_G1_DATA[7]
0010000100OUT_SEC[2]
0010001000OUT_SEC[3]
0010010000OUT_SEC[4]
0010100000OUT_SEC[5]
0100000001OUT_SEC[6]
0100000010OUT_SEC[7]
0100000100OUT_SEC[8]
0100001000OUT_SEC[9]
0100010000OUT_SEC[10]
0100100000OUT_SEC[11]
1000000001OUT_SEC[12]
1000000010OUT_SEC[13]
1000000100OUT_HALF0[17]
1000001000OUT_HALF0[16]
1000010000OUT_HALF0[15]
1000100000OUT_HALF0[14]
virtex2 INT_DCM_V2 switchbox INT muxes OMUX[5]
BitsDestination
MAIN[6][28]MAIN[7][27]MAIN[7][28]MAIN[7][29]MAIN[6][22]MAIN[7][23]MAIN[6][24]MAIN[6][25]MAIN[7][26]MAIN[6][27]OMUX[5]
Source
0000000000off
0001000001IMUX_TI[0]
0001000010IMUX_TI[1]
0001000100IMUX_G1_DATA[4]
0001001000IMUX_G1_DATA[5]
0001010000IMUX_G1_DATA[6]
0001100000IMUX_G1_DATA[7]
0010000100OUT_SEC[2]
0010001000OUT_SEC[3]
0010010000OUT_SEC[4]
0010100000OUT_SEC[5]
0100000001OUT_SEC[6]
0100000010OUT_SEC[7]
0100000100OUT_SEC[8]
0100001000OUT_SEC[9]
0100010000OUT_SEC[10]
0100100000OUT_SEC[11]
1000000001OUT_SEC[12]
1000000010OUT_SEC[13]
1000000100OUT_HALF0[17]
1000001000OUT_HALF0[16]
1000010000OUT_HALF0[15]
1000100000OUT_HALF0[14]
virtex2 INT_DCM_V2 switchbox INT muxes OMUX[6]
BitsDestination
MAIN[6][31]MAIN[7][32]MAIN[7][31]MAIN[7][30]MAIN[6][36]MAIN[6][39]MAIN[6][30]MAIN[6][33]MAIN[7][34]MAIN[7][35]OMUX[6]
Source
0000000000off
0001000001IMUX_G1_DATA[0]
0001000010IMUX_G1_DATA[1]
0001000100IMUX_G1_DATA[2]
0001001000IMUX_G1_DATA[3]
0010000001OUT_SEC[2]
0010000010OUT_SEC[3]
0010000100OUT_SEC[4]
0010001000OUT_SEC[5]
0100000001OUT_SEC[8]
0100000010OUT_SEC[9]
0100000100OUT_SEC[10]
0100001000OUT_SEC[11]
0100010000OUT_SEC[6]
0100100000OUT_SEC[7]
1000000001OUT_HALF0[17]
1000000010OUT_HALF0[16]
1000000100OUT_HALF0[15]
1000001000OUT_HALF0[14]
1000010000OUT_SEC[12]
1000100000OUT_SEC[13]
virtex2 INT_DCM_V2 switchbox INT muxes OMUX[7]
BitsDestination
MAIN[6][38]MAIN[7][37]MAIN[7][38]MAIN[7][39]MAIN[7][36]MAIN[6][37]MAIN[6][32]MAIN[7][33]MAIN[6][34]MAIN[6][35]OMUX[7]
Source
0000000000off
0001000001IMUX_G1_DATA[0]
0001000010IMUX_G1_DATA[1]
0001000100IMUX_G1_DATA[2]
0001001000IMUX_G1_DATA[3]
0010000001OUT_SEC[2]
0010000010OUT_SEC[3]
0010000100OUT_SEC[4]
0010001000OUT_SEC[5]
0100000001OUT_SEC[8]
0100000010OUT_SEC[9]
0100000100OUT_SEC[10]
0100001000OUT_SEC[11]
0100010000OUT_SEC[6]
0100100000OUT_SEC[7]
1000000001OUT_HALF0[17]
1000000010OUT_HALF0[16]
1000000100OUT_HALF0[15]
1000001000OUT_HALF0[14]
1000010000OUT_SEC[12]
1000100000OUT_SEC[13]
virtex2 INT_DCM_V2 switchbox INT muxes OMUX[8]
BitsDestination
MAIN[6][41]MAIN[7][42]MAIN[7][41]MAIN[7][40]MAIN[6][40]MAIN[6][43]MAIN[7][44]MAIN[7][45]MAIN[6][46]MAIN[6][49]OMUX[8]
Source
0000000000off
0001000001IMUX_DCM_CLK[0]
0001000010IMUX_DCM_CLK[1]
0001000100IMUX_G2_DATA[0]
0001001000IMUX_G2_DATA[1]
0001010000IMUX_G2_DATA[2]
0001100000IMUX_G2_DATA[3]
0010000100OUT_SEC[2]
0010001000OUT_SEC[3]
0010010000OUT_SEC[4]
0010100000OUT_SEC[5]
0100000001OUT_SEC[6]
0100000010OUT_SEC[7]
0100000100OUT_SEC[8]
0100001000OUT_SEC[9]
0100010000OUT_SEC[10]
0100100000OUT_SEC[11]
1000000001OUT_SEC[12]
1000000010OUT_SEC[13]
1000000100OUT_HALF1[17]
1000001000OUT_HALF1[16]
1000010000OUT_HALF1[15]
1000100000OUT_HALF1[14]
virtex2 INT_DCM_V2 switchbox INT muxes OMUX[9]
BitsDestination
MAIN[6][48]MAIN[7][47]MAIN[7][48]MAIN[7][49]MAIN[6][42]MAIN[7][43]MAIN[6][44]MAIN[6][45]MAIN[7][46]MAIN[6][47]OMUX[9]
Source
0000000000off
0001000001IMUX_DCM_CLK[0]
0001000010IMUX_DCM_CLK[1]
0001000100IMUX_G2_DATA[0]
0001001000IMUX_G2_DATA[1]
0001010000IMUX_G2_DATA[2]
0001100000IMUX_G2_DATA[3]
0010000100OUT_SEC[2]
0010001000OUT_SEC[3]
0010010000OUT_SEC[4]
0010100000OUT_SEC[5]
0100000001OUT_SEC[6]
0100000010OUT_SEC[7]
0100000100OUT_SEC[8]
0100001000OUT_SEC[9]
0100010000OUT_SEC[10]
0100100000OUT_SEC[11]
1000000001OUT_SEC[12]
1000000010OUT_SEC[13]
1000000100OUT_HALF1[17]
1000001000OUT_HALF1[16]
1000010000OUT_HALF1[15]
1000100000OUT_HALF1[14]
virtex2 INT_DCM_V2 switchbox INT muxes OMUX[10]
BitsDestination
MAIN[6][51]MAIN[7][52]MAIN[7][51]MAIN[7][50]MAIN[6][59]MAIN[6][50]MAIN[6][53]MAIN[7][54]MAIN[7][55]MAIN[6][56]OMUX[10]
Source
0000000000off
0001000001IMUX_DCM_CLK[2]
0001000010IMUX_G2_DATA[4]
0001000100IMUX_G2_DATA[5]
0001001000IMUX_G2_DATA[6]
0001010000IMUX_G2_DATA[7]
0010000010OUT_SEC[2]
0010000100OUT_SEC[3]
0010001000OUT_SEC[4]
0010010000OUT_SEC[5]
0100000001OUT_SEC[7]
0100000010OUT_SEC[8]
0100000100OUT_SEC[9]
0100001000OUT_SEC[10]
0100010000OUT_SEC[11]
0100100000OUT_SEC[6]
1000000001OUT_SEC[13]
1000000010OUT_HALF1[17]
1000000100OUT_HALF1[16]
1000001000OUT_HALF1[15]
1000010000OUT_HALF1[14]
1000100000OUT_SEC[12]
virtex2 INT_DCM_V2 switchbox INT muxes OMUX[11]
BitsDestination
MAIN[6][58]MAIN[7][57]MAIN[7][58]MAIN[7][59]MAIN[6][57]MAIN[6][52]MAIN[7][53]MAIN[6][54]MAIN[6][55]MAIN[7][56]OMUX[11]
Source
0000000000off
0001000001IMUX_DCM_CLK[2]
0001000010IMUX_G2_DATA[4]
0001000100IMUX_G2_DATA[5]
0001001000IMUX_G2_DATA[6]
0001010000IMUX_G2_DATA[7]
0010000010OUT_SEC[2]
0010000100OUT_SEC[3]
0010001000OUT_SEC[4]
0010010000OUT_SEC[5]
0100000001OUT_SEC[7]
0100000010OUT_SEC[8]
0100000100OUT_SEC[9]
0100001000OUT_SEC[10]
0100010000OUT_SEC[11]
0100100000OUT_SEC[6]
1000000001OUT_SEC[13]
1000000010OUT_HALF1[17]
1000000100OUT_HALF1[16]
1000001000OUT_HALF1[15]
1000010000OUT_HALF1[14]
1000100000OUT_SEC[12]
virtex2 INT_DCM_V2 switchbox INT muxes OMUX[12]
BitsDestination
MAIN[6][61]MAIN[7][62]MAIN[7][61]MAIN[7][60]MAIN[6][66]MAIN[6][69]MAIN[6][60]MAIN[6][63]MAIN[7][64]MAIN[7][65]OMUX[12]
Source
0000000000off
0001000001IMUX_G3_DATA[4]
0001000010IMUX_G3_DATA[5]
0001000100IMUX_G3_DATA[6]
0001001000IMUX_G3_DATA[7]
0010000001OUT_SEC[2]
0010000010OUT_SEC[3]
0010000100OUT_SEC[4]
0010001000OUT_SEC[5]
0100000001OUT_SEC[8]
0100000010OUT_SEC[9]
0100000100OUT_SEC[10]
0100001000OUT_SEC[11]
0100010000OUT_SEC[6]
0100100000OUT_SEC[7]
1000000001OUT_HALF1[17]
1000000010OUT_HALF1[16]
1000000100OUT_HALF1[15]
1000001000OUT_HALF1[14]
1000010000OUT_SEC[12]
1000100000OUT_SEC[13]
virtex2 INT_DCM_V2 switchbox INT muxes OMUX[13]
BitsDestination
MAIN[6][68]MAIN[7][67]MAIN[7][68]MAIN[7][69]MAIN[7][66]MAIN[6][67]MAIN[6][62]MAIN[7][63]MAIN[6][64]MAIN[6][65]OMUX[13]
Source
0000000000off
0001000001IMUX_G3_DATA[4]
0001000010IMUX_G3_DATA[5]
0001000100IMUX_G3_DATA[6]
0001001000IMUX_G3_DATA[7]
0010000001OUT_SEC[2]
0010000010OUT_SEC[3]
0010000100OUT_SEC[4]
0010001000OUT_SEC[5]
0100000001OUT_SEC[8]
0100000010OUT_SEC[9]
0100000100OUT_SEC[10]
0100001000OUT_SEC[11]
0100010000OUT_SEC[6]
0100100000OUT_SEC[7]
1000000001OUT_HALF1[17]
1000000010OUT_HALF1[16]
1000000100OUT_HALF1[15]
1000001000OUT_HALF1[14]
1000010000OUT_SEC[12]
1000100000OUT_SEC[13]
virtex2 INT_DCM_V2 switchbox INT muxes OMUX[14]
BitsDestination
MAIN[6][71]MAIN[7][72]MAIN[7][71]MAIN[7][70]MAIN[6][70]MAIN[6][73]MAIN[7][74]MAIN[7][75]MAIN[6][76]MAIN[6][79]OMUX[14]
Source
0000000000off
0001000001IMUX_CE[2]
0001000010IMUX_CE[3]
0001000100IMUX_G3_DATA[0]
0001001000IMUX_G3_DATA[1]
0001010000IMUX_G3_DATA[2]
0001100000IMUX_G3_DATA[3]
0010000100OUT_SEC[2]
0010001000OUT_SEC[3]
0010010000OUT_SEC[4]
0010100000OUT_SEC[5]
0100000001OUT_SEC[6]
0100000010OUT_SEC[7]
0100000100OUT_SEC[8]
0100001000OUT_SEC[9]
0100010000OUT_SEC[10]
0100100000OUT_SEC[11]
1000000001OUT_SEC[12]
1000000010OUT_SEC[13]
1000000100OUT_HALF1[17]
1000001000OUT_HALF1[16]
1000010000OUT_HALF1[15]
1000100000OUT_HALF1[14]
virtex2 INT_DCM_V2 switchbox INT muxes OMUX[15]
BitsDestination
MAIN[6][78]MAIN[7][77]MAIN[7][78]MAIN[7][79]MAIN[6][72]MAIN[7][73]MAIN[6][74]MAIN[6][75]MAIN[7][76]MAIN[6][77]OMUX[15]
Source
0000000000off
0001000001IMUX_CE[2]
0001000010IMUX_CE[3]
0001000100IMUX_G3_DATA[0]
0001001000IMUX_G3_DATA[1]
0001010000IMUX_G3_DATA[2]
0001100000IMUX_G3_DATA[3]
0010000100OUT_SEC[2]
0010001000OUT_SEC[3]
0010010000OUT_SEC[4]
0010100000OUT_SEC[5]
0100000001OUT_SEC[6]
0100000010OUT_SEC[7]
0100000100OUT_SEC[8]
0100001000OUT_SEC[9]
0100010000OUT_SEC[10]
0100100000OUT_SEC[11]
1000000001OUT_SEC[12]
1000000010OUT_SEC[13]
1000000100OUT_HALF1[17]
1000001000OUT_HALF1[16]
1000010000OUT_HALF1[15]
1000100000OUT_HALF1[14]
virtex2 INT_DCM_V2 switchbox INT muxes DBL_W0[0]
BitsDestination
MAIN[16][5]MAIN[16][6]MAIN[17][6]MAIN[17][5]MAIN[15][7]MAIN[14][5]MAIN[14][4]MAIN[15][6]DBL_W0[0]
Source
00000000off
00010001OMUX_S0
00010010HEX_E6[0]
00011000HEX_N6[0]
00100001OMUX_NW10
00100010HEX_S6[1]
00101000HEX_W6[0]
01000001DBL_W2[0]
01000010HEX_N3[0]
01000100HEX_S3[0]
01001000DBL_N3[9]
10000001DBL_W2_N[8]
10000010DBL_S1[0]
10000100DBL_S2[2]
10001000DBL_N1[0]
virtex2 INT_DCM_V2 switchbox INT muxes DBL_W0[1]
BitsDestination
MAIN[16][13]MAIN[16][14]MAIN[17][14]MAIN[17][13]MAIN[15][15]MAIN[14][13]MAIN[14][12]MAIN[15][14]DBL_W0[1]
Source
00000000off
00010001OMUX[2]
00010010HEX_E6[1]
00011000HEX_N6[1]
00100001OMUX_W1
00100010HEX_S6[2]
00101000HEX_W6[1]
01000001DBL_W2[1]
01000010HEX_N3[1]
01000100HEX_S3[1]
01001000DBL_N2[0]
10000001DBL_W2_N[9]
10000010DBL_S1[1]
10000100DBL_S2[3]
10001000DBL_N1[1]
virtex2 INT_DCM_V2 switchbox INT muxes DBL_W0[2]
BitsDestination
MAIN[15][23]MAIN[14][20]MAIN[15][22]MAIN[14][21]MAIN[16][22]MAIN[16][21]MAIN[17][22]MAIN[17][21]DBL_W0[2]
Source
00000000off
00010001OMUX[4]
00010100DBL_S2[4]
00011000HEX_S3[2]
00100001OMUX[6]
00100010OMUX_WN14
00100100DBL_W2[0]
00101000DBL_W2[2]
01000001HEX_E6[2]
01000010HEX_S6[3]
01000100DBL_S1[2]
01001000HEX_N3[2]
10000001HEX_N6[2]
10000010HEX_W6[2]
10000100DBL_N1[2]
10001000DBL_N2[1]
virtex2 INT_DCM_V2 switchbox INT muxes DBL_W0[3]
BitsDestination
MAIN[16][30]MAIN[16][29]MAIN[17][30]MAIN[17][29]MAIN[15][31]MAIN[14][29]MAIN[14][28]MAIN[15][30]DBL_W0[3]
Source
00000000off
00010001OMUX_W6
00010010HEX_E6[3]
00011000HEX_N6[3]
00100001OMUX_NW10
00100010HEX_S6[4]
00101000HEX_W6[3]
01000001DBL_W2[1]
01000010DBL_S1[3]
01000100DBL_S2[5]
01001000DBL_N1[3]
10000001DBL_W2[3]
10000010HEX_N3[3]
10000100HEX_S3[3]
10001000DBL_N2[2]
virtex2 INT_DCM_V2 switchbox INT muxes DBL_W0[4]
BitsDestination
MAIN[16][38]MAIN[16][37]MAIN[17][38]MAIN[17][37]MAIN[15][39]MAIN[14][37]MAIN[14][36]MAIN[15][38]DBL_W0[4]
Source
00000000off
00010001OMUX_WS1
00010010HEX_E6[4]
00011000HEX_N6[4]
00100001OMUX_N12
00100010HEX_S6[5]
00101000HEX_W6[4]
01000001DBL_W2[2]
01000010DBL_S1[4]
01000100DBL_S2[6]
01001000DBL_N1[4]
10000001DBL_W2[4]
10000010HEX_N3[4]
10000100HEX_S3[4]
10001000DBL_N2[3]
virtex2 INT_DCM_V2 switchbox INT muxes DBL_W0[5]
BitsDestination
MAIN[16][46]MAIN[16][45]MAIN[17][46]MAIN[17][45]MAIN[15][47]MAIN[14][45]MAIN[14][44]MAIN[15][46]DBL_W0[5]
Source
00000000off
00010001OMUX_S3
00010010HEX_E6[5]
00011000HEX_N6[5]
00100001OMUX_WN14
00100010HEX_S6[6]
00101000HEX_W6[5]
01000001DBL_W2[3]
01000010DBL_S1[5]
01000100DBL_S2[7]
01001000DBL_N1[5]
10000001DBL_W2[5]
10000010HEX_N3[5]
10000100HEX_S3[5]
10001000DBL_N2[4]
virtex2 INT_DCM_V2 switchbox INT muxes DBL_W0[6]
BitsDestination
MAIN[15][55]MAIN[14][52]MAIN[15][54]MAIN[14][53]MAIN[16][54]MAIN[16][53]MAIN[17][53]MAIN[17][54]DBL_W0[6]
Source
00000000off
00010001OMUX[11]
00010100DBL_S2[8]
00011000HEX_S3[6]
00100001OMUX_W9
00100010OMUX_SW5
00100100DBL_W2[4]
00101000DBL_W2[6]
01000001HEX_S6[7]
01000010HEX_E6[6]
01000100DBL_S1[6]
01001000HEX_N3[6]
10000001HEX_W6[6]
10000010HEX_N6[6]
10000100DBL_N1[6]
10001000DBL_N2[5]
virtex2 INT_DCM_V2 switchbox INT muxes DBL_W0[7]
BitsDestination
MAIN[16][62]MAIN[16][61]MAIN[17][61]MAIN[17][62]MAIN[15][63]MAIN[14][61]MAIN[14][60]MAIN[15][62]DBL_W0[7]
Source
00000000off
00010001OMUX[9]
00010010HEX_S6[8]
00011000HEX_W6[7]
00100001OMUX_WS1
00100010HEX_E6[7]
00101000HEX_N6[7]
01000001DBL_W2[5]
01000010DBL_S1[7]
01000100DBL_S2[9]
01001000DBL_N1[7]
10000001DBL_W2[7]
10000010HEX_N3[7]
10000100HEX_S3[7]
10001000DBL_N2[6]
virtex2 INT_DCM_V2 switchbox INT muxes DBL_W0[8]
BitsDestination
MAIN[16][70]MAIN[16][69]MAIN[17][69]MAIN[17][70]MAIN[15][71]MAIN[14][69]MAIN[14][68]MAIN[15][70]DBL_W0[8]
Source
00000000off
00010001OMUX[13]
00010010HEX_S6[9]
00011000HEX_W6[8]
00100001OMUX_W14
00100010HEX_E6[8]
00101000HEX_N6[8]
01000001DBL_W2[6]
01000010DBL_S1[8]
01000100DBL_S3[0]
01001000DBL_N1[8]
10000001DBL_W2[8]
10000010HEX_N3[8]
10000100HEX_S3[8]
10001000DBL_N2[7]
virtex2 INT_DCM_V2 switchbox INT muxes DBL_W0[9]
BitsDestination
MAIN[15][79]MAIN[14][76]MAIN[14][77]MAIN[15][78]MAIN[16][78]MAIN[16][77]MAIN[17][77]MAIN[17][78]DBL_W0[9]
Source
00000000off
00010001OMUX[13]
00010010OMUX_SW5
00010100DBL_W2[7]
00011000DBL_W2[9]
00100001OMUX_S0
00100010OMUX[15]
00100100DBL_S3[1]
00101000HEX_S3[9]
01000001HEX_S7[0]
01000010HEX_E6[9]
01000100DBL_S1[9]
01001000HEX_N3[9]
10000001HEX_W6[9]
10000010HEX_N6[9]
10000100DBL_N1[9]
10001000DBL_N2[8]
virtex2 INT_DCM_V2 switchbox INT muxes DBL_E0[0]
BitsDestination
MAIN[17][7]MAIN[17][4]MAIN[16][4]MAIN[16][7]MAIN[15][5]MAIN[14][7]MAIN[15][4]MAIN[14][6]DBL_E0[0]
Source
00000000off
00010001OMUX_E2
00010010HEX_S6[1]
00011000HEX_W6[0]
00100001OMUX_EN8
00100010HEX_E6[0]
00101000HEX_N6[0]
01000001DBL_E2[0]
01000010DBL_S1[0]
01000100DBL_S2[2]
01001000DBL_N1[0]
10000001DBL_E2[2]
10000010HEX_N3[0]
10000100HEX_S3[0]
10001000DBL_N3[9]
virtex2 INT_DCM_V2 switchbox INT muxes DBL_E0[1]
BitsDestination
MAIN[17][15]MAIN[17][12]MAIN[16][12]MAIN[16][15]MAIN[15][13]MAIN[14][15]MAIN[15][12]MAIN[14][14]DBL_E0[1]
Source
00000000off
00010001OMUX_S4
00010010HEX_S6[2]
00011000HEX_W6[1]
00100001OMUX_N10
00100010HEX_E6[1]
00101000HEX_N6[1]
01000001DBL_E2[1]
01000010DBL_S1[1]
01000100DBL_S2[3]
01001000DBL_N1[1]
10000001DBL_E2[3]
10000010HEX_N3[1]
10000100HEX_S3[1]
10001000DBL_N2[0]
virtex2 INT_DCM_V2 switchbox INT muxes DBL_E0[2]
BitsDestination
MAIN[15][21]MAIN[15][20]MAIN[14][22]MAIN[14][23]MAIN[17][23]MAIN[17][20]MAIN[16][23]MAIN[16][20]DBL_E0[2]
Source
00000000off
00010001OMUX[4]
00010100DBL_S2[4]
00011000HEX_S3[2]
00100001OMUX_NE12
00100010OMUX[6]
00100100DBL_E2[2]
00101000DBL_E2[4]
01000001HEX_E6[2]
01000010HEX_S6[3]
01000100DBL_S1[2]
01001000HEX_N3[2]
10000001HEX_N6[2]
10000010HEX_W6[2]
10000100DBL_N1[2]
10001000DBL_N2[1]
virtex2 INT_DCM_V2 switchbox INT muxes DBL_E0[3]
BitsDestination
MAIN[17][31]MAIN[17][28]MAIN[16][28]MAIN[16][31]MAIN[15][29]MAIN[14][31]MAIN[15][28]MAIN[14][30]DBL_E0[3]
Source
00000000off
00010001OMUX_SE3
00010010HEX_S6[4]
00011000HEX_W6[3]
00100001OMUX_EN8
00100010HEX_E6[3]
00101000HEX_N6[3]
01000001DBL_E2[3]
01000010DBL_S1[3]
01000100DBL_S2[5]
01001000DBL_N1[3]
10000001DBL_E2[5]
10000010HEX_N3[3]
10000100HEX_S3[3]
10001000DBL_N2[2]
virtex2 INT_DCM_V2 switchbox INT muxes DBL_E0[4]
BitsDestination
MAIN[17][39]MAIN[17][36]MAIN[16][39]MAIN[16][36]MAIN[15][37]MAIN[14][39]MAIN[15][36]MAIN[14][38]DBL_E0[4]
Source
00000000off
00010001OMUX_E7
00010010HEX_E6[4]
00011000HEX_N6[4]
00100001OMUX_E8
00100010HEX_S6[5]
00101000HEX_W6[4]
01000001DBL_E2[4]
01000010DBL_S1[4]
01000100DBL_S2[6]
01001000DBL_N1[4]
10000001DBL_E2[6]
10000010HEX_N3[4]
10000100HEX_S3[4]
10001000DBL_N2[3]
virtex2 INT_DCM_V2 switchbox INT muxes DBL_E0[5]
BitsDestination
MAIN[17][47]MAIN[17][44]MAIN[16][44]MAIN[16][47]MAIN[15][45]MAIN[14][47]MAIN[15][44]MAIN[14][46]DBL_E0[5]
Source
00000000off
00010001OMUX_ES7
00010010HEX_S6[6]
00011000HEX_W6[5]
00100001OMUX_NE12
00100010HEX_E6[5]
00101000HEX_N6[5]
01000001DBL_E2[5]
01000010DBL_S1[5]
01000100DBL_S2[7]
01001000DBL_N1[5]
10000001DBL_E2[7]
10000010HEX_N3[5]
10000100HEX_S3[5]
10001000DBL_N2[4]
virtex2 INT_DCM_V2 switchbox INT muxes DBL_E0[6]
BitsDestination
MAIN[17][55]MAIN[17][52]MAIN[16][55]MAIN[16][52]MAIN[15][53]MAIN[15][52]MAIN[14][55]MAIN[14][54]DBL_E0[6]
Source
00000000off
00010001OMUX[9]
00010100HEX_E6[6]
00011000HEX_N6[6]
00100001OMUX_SE3
00100010OMUX[11]
00100100HEX_S6[7]
00101000HEX_W6[6]
01000001DBL_E2[6]
01000010DBL_S2[8]
01000100DBL_S1[6]
01001000DBL_N1[6]
10000001DBL_E2[8]
10000010HEX_S3[6]
10000100HEX_N3[6]
10001000DBL_N2[5]
virtex2 INT_DCM_V2 switchbox INT muxes DBL_E0[7]
BitsDestination
MAIN[17][63]MAIN[17][60]MAIN[16][60]MAIN[16][63]MAIN[15][61]MAIN[14][63]MAIN[15][60]MAIN[14][62]DBL_E0[7]
Source
00000000off
00010001OMUX_S5
00010010HEX_S6[8]
00011000HEX_W6[7]
00100001OMUX_N11
00100010HEX_E6[7]
00101000HEX_N6[7]
01000001DBL_E2[7]
01000010DBL_S1[7]
01000100DBL_S2[9]
01001000DBL_N1[7]
10000001DBL_E2[9]
10000010HEX_N3[7]
10000100HEX_S3[7]
10001000DBL_N2[6]
virtex2 INT_DCM_V2 switchbox INT muxes DBL_E0[8]
BitsDestination
MAIN[17][71]MAIN[17][68]MAIN[16][68]MAIN[16][71]MAIN[15][69]MAIN[14][71]MAIN[15][68]MAIN[14][70]DBL_E0[8]
Source
00000000off
00010001OMUX_ES7
00010010HEX_S6[9]
00011000HEX_W6[8]
00100001OMUX_E13
00100010HEX_E6[8]
00101000HEX_N6[8]
01000001DBL_E2[8]
01000010DBL_S1[8]
01000100DBL_S3[0]
01001000DBL_N1[8]
10000001DBL_E2_S[0]
10000010HEX_N3[8]
10000100HEX_S3[8]
10001000DBL_N2[7]
virtex2 INT_DCM_V2 switchbox INT muxes DBL_E0[9]
BitsDestination
MAIN[17][79]MAIN[17][76]MAIN[16][79]MAIN[16][76]MAIN[15][77]MAIN[15][76]MAIN[14][78]MAIN[14][79]DBL_E0[9]
Source
00000000off
00010001OMUX[15]
00010010OMUX_N15
00010100HEX_E6[9]
00011000HEX_N6[9]
00100001OMUX_S0
00100010OMUX_S2
00100100HEX_S7[0]
00101000HEX_W6[9]
01000001DBL_S3[1]
01000010DBL_E2[9]
01000100DBL_S1[9]
01001000DBL_N1[9]
10000001HEX_S3[9]
10000010DBL_E2_S[1]
10000100HEX_N3[9]
10001000DBL_N2[8]
virtex2 INT_DCM_V2 switchbox INT muxes DBL_S0[0]
BitsDestination
MAIN[15][0]MAIN[15][1]MAIN[14][2]MAIN[14][3]MAIN[17][3]MAIN[17][0]MAIN[16][3]MAIN[16][0]DBL_S0[0]
Source
00000000off
00010001OMUX[0]
00010100DBL_E2[1]
00011000HEX_E3[0]
00100001OMUX[2]
00100010OMUX_S0
00100100DBL_S2[0]
00101000DBL_S2[2]
01000001HEX_W6_N[9]
01000010HEX_N6[0]
01000100DBL_W1[0]
01001000DBL_W2_N[8]
10000001HEX_S6[0]
10000010HEX_E6[0]
10000100DBL_E1[0]
10001000HEX_W3[0]
virtex2 INT_DCM_V2 switchbox INT muxes DBL_S0[1]
BitsDestination
MAIN[17][11]MAIN[17][8]MAIN[16][8]MAIN[16][11]MAIN[14][11]MAIN[15][8]MAIN[15][9]MAIN[14][10]DBL_S0[1]
Source
00000000off
00010001OMUX[2]
00010010HEX_N6[1]
00010100HEX_E6[1]
00100001OMUX_E2
00100010HEX_W6[0]
00100100HEX_S6[1]
01000001DBL_S2[1]
01000010DBL_W1[1]
01000100DBL_E1[1]
01001000DBL_E2[2]
10000001DBL_S2[3]
10000010DBL_W2_N[9]
10000100HEX_W3[1]
10001000HEX_E3[1]
virtex2 INT_DCM_V2 switchbox INT muxes DBL_S0[2]
BitsDestination
MAIN[15][16]MAIN[15][17]MAIN[14][18]MAIN[14][19]MAIN[17][19]MAIN[17][16]MAIN[16][16]MAIN[16][19]DBL_S0[2]
Source
00000000off
00010001OMUX[4]
00010100DBL_E2[3]
00011000HEX_E3[2]
00100001OMUX[6]
00100010OMUX_S4
00100100DBL_S2[2]
00101000DBL_S2[4]
01000001HEX_N6[2]
01000010HEX_W6[1]
01000100DBL_W1[2]
01001000DBL_W2[0]
10000001HEX_E6[2]
10000010HEX_S6[2]
10000100DBL_E1[2]
10001000HEX_W3[2]
virtex2 INT_DCM_V2 switchbox INT muxes DBL_S0[3]
BitsDestination
MAIN[17][27]MAIN[17][24]MAIN[16][27]MAIN[16][24]MAIN[14][27]MAIN[15][24]MAIN[15][25]MAIN[14][26]DBL_S0[3]
Source
00000000off
00010001OMUX[6]
00010010HEX_W6[2]
00010100HEX_S6[3]
00100001OMUX_W6
00100010HEX_N6[3]
00100100HEX_E6[3]
01000001DBL_S2[3]
01000010DBL_W1[3]
01000100DBL_E1[3]
01001000DBL_E2[4]
10000001DBL_S2[5]
10000010DBL_W2[1]
10000100HEX_W3[3]
10001000HEX_E3[3]
virtex2 INT_DCM_V2 switchbox INT muxes DBL_S0[4]
BitsDestination
MAIN[17][35]MAIN[17][32]MAIN[16][32]MAIN[16][35]MAIN[14][35]MAIN[15][32]MAIN[15][33]MAIN[14][34]DBL_S0[4]
Source
00000000off
00010001OMUX_WS1
00010010HEX_N6[4]
00010100HEX_E6[4]
00100001OMUX_SE3
00100010HEX_W6[3]
00100100HEX_S6[4]
01000001DBL_S2[4]
01000010DBL_W1[4]
01000100DBL_E1[4]
01001000DBL_E2[5]
10000001DBL_S2[6]
10000010DBL_W2[2]
10000100HEX_W3[4]
10001000HEX_E3[4]
virtex2 INT_DCM_V2 switchbox INT muxes DBL_S0[5]
BitsDestination
MAIN[17][43]MAIN[17][40]MAIN[16][40]MAIN[16][43]MAIN[14][43]MAIN[15][40]MAIN[15][41]MAIN[14][42]DBL_S0[5]
Source
00000000off
00010001OMUX_S3
00010010HEX_N6[5]
00010100HEX_E6[5]
00100001OMUX_E8
00100010HEX_W6[4]
00100100HEX_S6[5]
01000001DBL_S2[5]
01000010DBL_W1[5]
01000100DBL_E1[5]
01001000DBL_E2[6]
10000001DBL_S2[7]
10000010DBL_W2[3]
10000100HEX_W3[5]
10001000HEX_E3[5]
virtex2 INT_DCM_V2 switchbox INT muxes DBL_S0[6]
BitsDestination
MAIN[17][51]MAIN[17][48]MAIN[16][48]MAIN[16][51]MAIN[14][51]MAIN[15][48]MAIN[15][49]MAIN[14][50]DBL_S0[6]
Source
00000000off
00010001OMUX_SW5
00010010HEX_N6[6]
00010100HEX_E6[6]
00100001OMUX_ES7
00100010HEX_W6[5]
00100100HEX_S6[6]
01000001DBL_S2[6]
01000010DBL_W1[6]
01000100DBL_E1[6]
01001000DBL_E2[7]
10000001DBL_S2[8]
10000010DBL_W2[4]
10000100HEX_W3[6]
10001000HEX_E3[6]
virtex2 INT_DCM_V2 switchbox INT muxes DBL_S0[7]
BitsDestination
MAIN[15][56]MAIN[15][57]MAIN[14][58]MAIN[14][59]MAIN[17][59]MAIN[17][56]MAIN[16][59]MAIN[16][56]DBL_S0[7]
Source
00000000off
00010001OMUX[11]
00010100DBL_E2[8]
00011000HEX_E3[7]
00100001OMUX_SE3
00100010OMUX_WS1
00100100DBL_S2[7]
00101000DBL_S2[9]
01000001HEX_W6[6]
01000010HEX_N6[7]
01000100DBL_W1[7]
01001000DBL_W2[5]
10000001HEX_S6[7]
10000010HEX_E6[7]
10000100DBL_E1[7]
10001000HEX_W3[7]
virtex2 INT_DCM_V2 switchbox INT muxes DBL_S0[8]
BitsDestination
MAIN[17][67]MAIN[17][64]MAIN[16][67]MAIN[16][64]MAIN[14][67]MAIN[15][64]MAIN[15][65]MAIN[14][66]DBL_S0[8]
Source
00000000off
00010001OMUX_S5
00010010HEX_W6[7]
00010100HEX_S6[8]
00100001OMUX_W14
00100010HEX_N6[8]
00100100HEX_E6[8]
01000001DBL_S2[8]
01000010DBL_W1[8]
01000100DBL_E1[8]
01001000DBL_E2[9]
10000001DBL_S3[0]
10000010DBL_W2[6]
10000100HEX_W3[8]
10001000HEX_E3[8]
virtex2 INT_DCM_V2 switchbox INT muxes DBL_S0[9]
BitsDestination
MAIN[15][72]MAIN[15][73]MAIN[14][74]MAIN[14][75]MAIN[17][75]MAIN[17][72]MAIN[16][72]MAIN[16][75]DBL_S0[9]
Source
00000000off
00010001OMUX[15]
00010100DBL_E2_S[0]
00011000HEX_E3[9]
00100001OMUX_SW5
00100010OMUX_ES7
00100100DBL_S2[9]
00101000DBL_S3[1]
01000001HEX_N6[9]
01000010HEX_W6[8]
01000100DBL_W1[9]
01001000DBL_W2[7]
10000001HEX_E6[9]
10000010HEX_S6[9]
10000100DBL_E1[9]
10001000HEX_W3[9]
virtex2 INT_DCM_V2 switchbox INT muxes DBL_N0[0]
BitsDestination
MAIN[14][0]MAIN[15][3]MAIN[15][2]MAIN[14][1]MAIN[16][2]MAIN[16][1]MAIN[17][2]MAIN[17][1]DBL_N0[0]
Source
00000000off
00010001OMUX[0]
00010100DBL_E2[1]
00011000HEX_E3[0]
00100001OMUX_N13
00100010OMUX_EN8
00100100DBL_N3[8]
00101000DBL_N2[0]
01000001HEX_W6_N[9]
01000010HEX_N6[0]
01000100DBL_W1[0]
01001000DBL_W2_N[8]
10000001HEX_S6[0]
10000010HEX_E6[0]
10000100DBL_E1[0]
10001000HEX_W3[0]
virtex2 INT_DCM_V2 switchbox INT muxes DBL_N0[1]
BitsDestination
MAIN[16][10]MAIN[16][9]MAIN[17][9]MAIN[17][10]MAIN[14][9]MAIN[14][8]MAIN[15][11]MAIN[15][10]DBL_N0[1]
Source
00000000off
00010001OMUX_N10
00010010HEX_N6[1]
00010100HEX_E6[1]
00100001OMUX_NW10
00100010HEX_W6[0]
00100100HEX_S6[1]
01000001DBL_N3[9]
01000010DBL_W1[1]
01000100DBL_E1[1]
01001000DBL_E2[2]
10000001DBL_N2[1]
10000010DBL_W2_N[9]
10000100HEX_W3[1]
10001000HEX_E3[1]
virtex2 INT_DCM_V2 switchbox INT muxes DBL_N0[2]
BitsDestination
MAIN[14][16]MAIN[15][19]MAIN[15][18]MAIN[14][17]MAIN[16][18]MAIN[16][17]MAIN[17][17]MAIN[17][18]DBL_N0[2]
Source
00000000off
00010001OMUX[4]
00010100DBL_E2[3]
00011000HEX_E3[2]
00100001OMUX_NE12
00100010OMUX_W1
00100100DBL_N2[0]
00101000DBL_N2[2]
01000001HEX_N6[2]
01000010HEX_W6[1]
01000100DBL_W1[2]
01001000DBL_W2[0]
10000001HEX_E6[2]
10000010HEX_S6[2]
10000100DBL_E1[2]
10001000HEX_W3[2]
virtex2 INT_DCM_V2 switchbox INT muxes DBL_N0[3]
BitsDestination
MAIN[16][26]MAIN[16][25]MAIN[17][25]MAIN[17][26]MAIN[14][25]MAIN[14][24]MAIN[15][27]MAIN[15][26]DBL_N0[3]
Source
00000000off
00010001OMUX_EN8
00010010HEX_N6[3]
00010100HEX_E6[3]
00100001OMUX_WN14
00100010HEX_W6[2]
00100100HEX_S6[3]
01000001DBL_N2[1]
01000010DBL_W1[3]
01000100DBL_E1[3]
01001000DBL_E2[4]
10000001DBL_N2[3]
10000010DBL_W2[1]
10000100HEX_W3[3]
10001000HEX_E3[3]
virtex2 INT_DCM_V2 switchbox INT muxes DBL_N0[4]
BitsDestination
MAIN[16][34]MAIN[16][33]MAIN[17][33]MAIN[17][34]MAIN[14][33]MAIN[14][32]MAIN[15][35]MAIN[15][34]DBL_N0[4]
Source
00000000off
00010001OMUX_E7
00010010HEX_N6[4]
00010100HEX_E6[4]
00100001OMUX_NW10
00100010HEX_W6[3]
00100100HEX_S6[4]
01000001DBL_N2[2]
01000010DBL_W1[4]
01000100DBL_E1[4]
01001000DBL_E2[5]
10000001DBL_N2[4]
10000010DBL_W2[2]
10000100HEX_W3[4]
10001000HEX_E3[4]
virtex2 INT_DCM_V2 switchbox INT muxes DBL_N0[5]
BitsDestination
MAIN[16][42]MAIN[16][41]MAIN[17][42]MAIN[17][41]MAIN[14][41]MAIN[14][40]MAIN[15][43]MAIN[15][42]DBL_N0[5]
Source
00000000off
00010001OMUX_N12
00010010HEX_W6[4]
00010100HEX_S6[5]
00100001OMUX_NE12
00100010HEX_N6[5]
00100100HEX_E6[5]
01000001DBL_N2[3]
01000010DBL_W1[5]
01000100DBL_E1[5]
01001000DBL_E2[6]
10000001DBL_N2[5]
10000010DBL_W2[3]
10000100HEX_W3[5]
10001000HEX_E3[5]
virtex2 INT_DCM_V2 switchbox INT muxes DBL_N0[6]
BitsDestination
MAIN[16][50]MAIN[16][49]MAIN[17][49]MAIN[17][50]MAIN[14][49]MAIN[14][48]MAIN[15][51]MAIN[15][50]DBL_N0[6]
Source
00000000off
00010001OMUX[9]
00010010HEX_N6[6]
00010100HEX_E6[6]
00100001OMUX_WN14
00100010HEX_W6[5]
00100100HEX_S6[6]
01000001DBL_N2[4]
01000010DBL_W1[6]
01000100DBL_E1[6]
01001000DBL_E2[7]
10000001DBL_N2[6]
10000010DBL_W2[4]
10000100HEX_W3[6]
10001000HEX_E3[6]
virtex2 INT_DCM_V2 switchbox INT muxes DBL_N0[7]
BitsDestination
MAIN[14][56]MAIN[15][59]MAIN[15][58]MAIN[14][57]MAIN[16][58]MAIN[16][57]MAIN[17][58]MAIN[17][57]DBL_N0[7]
Source
00000000off
00010001OMUX[11]
00010100DBL_E2[8]
00011000HEX_E3[7]
00100001OMUX_W9
00100010OMUX_N11
00100100DBL_N2[5]
00101000DBL_N2[7]
01000001HEX_W6[6]
01000010HEX_N6[7]
01000100DBL_W1[7]
01001000DBL_W2[5]
10000001HEX_S6[7]
10000010HEX_E6[7]
10000100DBL_E1[7]
10001000HEX_W3[7]
virtex2 INT_DCM_V2 switchbox INT muxes DBL_N0[8]
BitsDestination
MAIN[16][66]MAIN[16][65]MAIN[17][66]MAIN[17][65]MAIN[14][65]MAIN[14][64]MAIN[15][67]MAIN[15][66]DBL_N0[8]
Source
00000000off
00010001OMUX[9]
00010010HEX_W6[7]
00010100HEX_S6[8]
00100001OMUX_E13
00100010HEX_N6[8]
00100100HEX_E6[8]
01000001DBL_N2[6]
01000010DBL_W1[8]
01000100DBL_E1[8]
01001000DBL_E2[9]
10000001DBL_N2[8]
10000010DBL_W2[6]
10000100HEX_W3[8]
10001000HEX_E3[8]
virtex2 INT_DCM_V2 switchbox INT muxes DBL_N0[9]
BitsDestination
MAIN[16][74]MAIN[16][73]MAIN[17][74]MAIN[17][73]MAIN[14][72]MAIN[15][75]MAIN[14][73]MAIN[15][74]DBL_N0[9]
Source
00000000off
00010001OMUX[13]
00010100HEX_W6[8]
00011000HEX_S6[9]
00100001OMUX_N15
00100010OMUX[15]
00100100HEX_N6[9]
00101000HEX_E6[9]
01000001DBL_N2[7]
01000010DBL_E2_S[0]
01000100DBL_W1[9]
01001000DBL_E1[9]
10000001DBL_N2[9]
10000010HEX_E3[9]
10000100DBL_W2[7]
10001000HEX_W3[9]
virtex2 INT_DCM_V2 switchbox INT muxes HEX_W0[0]
BitsDestination
MAIN[20][4]MAIN[20][6]MAIN[20][5]MAIN[18][4]MAIN[19][6]MAIN[18][6]MAIN[19][4]HEX_W0[0]
Source
0000000off
0010001OMUX_S0
0010010HEX_S3[0]
0010100HEX_N3[0]
0011000LH[6]
0100010OMUX_NW10
0100100HEX_W6[0]
0101000HEX_W6_N[8]
1000010LH[18]
1000100HEX_N7[9]
1001000HEX_S6[2]
virtex2 INT_DCM_V2 switchbox INT muxes HEX_W0[1]
BitsDestination
MAIN[21][12]MAIN[20][15]MAIN[21][14]MAIN[18][13]MAIN[19][15]MAIN[18][15]MAIN[19][13]HEX_W0[1]
Source
0000000off
0010001OMUX[2]
0010100HEX_W6[1]
0011000HEX_W6_N[9]
0100001LH[0]
0100010OMUX_W1
0100100HEX_S3[1]
0101000HEX_N3[1]
1000010LH[12]
1000100HEX_N6[0]
1001000HEX_S6[3]
virtex2 INT_DCM_V2 switchbox INT muxes HEX_W0[2]
BitsDestination
MAIN[19][22]MAIN[18][20]MAIN[18][22]MAIN[19][20]MAIN[20][22]MAIN[20][21]MAIN[20][20]HEX_W0[2]
Source
0000000off
0001001OMUX[4]
0001010OMUX[6]
0010001LH[18]
0010010HEX_S3[2]
0010100OMUX_WN14
0100001HEX_S6[4]
0100010LH[6]
0100100HEX_W6[0]
1000001HEX_N6[1]
1000010HEX_N3[2]
1000100HEX_W6[2]
virtex2 INT_DCM_V2 switchbox INT muxes HEX_W0[3]
BitsDestination
MAIN[21][28]MAIN[20][31]MAIN[21][30]MAIN[19][31]MAIN[18][29]MAIN[18][31]MAIN[19][29]HEX_W0[3]
Source
0000000off
0010001OMUX_W6
0010100HEX_W6[1]
0011000HEX_W6[3]
0100001LH[0]
0100010OMUX_NW10
0100100HEX_N3[3]
0101000HEX_S3[3]
1000010LH[12]
1000100HEX_S6[5]
1001000HEX_N6[2]
virtex2 INT_DCM_V2 switchbox INT muxes HEX_W0[4]
BitsDestination
MAIN[20][36]MAIN[20][38]MAIN[20][37]MAIN[19][38]MAIN[18][36]MAIN[18][38]MAIN[19][36]HEX_W0[4]
Source
0000000off
0010001OMUX_WS1
0010010HEX_S3[4]
0010100LH[6]
0011000HEX_N3[4]
0100010OMUX_N12
0100100HEX_W6[2]
0101000HEX_W6[4]
1000010LH[18]
1000100HEX_S6[6]
1001000HEX_N6[3]
virtex2 INT_DCM_V2 switchbox INT muxes HEX_W0[5]
BitsDestination
MAIN[21][44]MAIN[20][47]MAIN[21][46]MAIN[19][47]MAIN[18][45]MAIN[18][47]MAIN[19][45]HEX_W0[5]
Source
0000000off
0010001OMUX_S3
0010100HEX_W6[3]
0011000HEX_W6[5]
0100001LH[0]
0100010OMUX_WN14
0100100HEX_N3[5]
0101000HEX_S3[5]
1000010LH[12]
1000100HEX_S6[7]
1001000HEX_N6[4]
virtex2 INT_DCM_V2 switchbox INT muxes HEX_W0[6]
BitsDestination
MAIN[20][52]MAIN[20][53]MAIN[20][54]MAIN[19][54]MAIN[18][52]MAIN[18][54]MAIN[19][52]HEX_W0[6]
Source
0000000off
0010001OMUX[11]
0010010OMUX_W9
0010100HEX_W6[4]
0011000HEX_W6[6]
0100001OMUX_SW5
0100010HEX_S3[6]
0100100LH[6]
0101000HEX_N3[6]
1000010LH[18]
1000100HEX_S6[8]
1001000HEX_N6[5]
virtex2 INT_DCM_V2 switchbox INT muxes HEX_W0[7]
BitsDestination
MAIN[21][60]MAIN[21][62]MAIN[20][63]MAIN[19][63]MAIN[18][61]MAIN[19][61]MAIN[18][63]HEX_W0[7]
Source
0000000off
0010001OMUX[9]
0010010LH[0]
0010100HEX_N3[7]
0011000HEX_S3[7]
0100010OMUX_WS1
0100100HEX_W6[5]
0101000HEX_W6[7]
1000001LH[12]
1000100HEX_S6[9]
1001000HEX_N6[6]
virtex2 INT_DCM_V2 switchbox INT muxes HEX_W0[8]
BitsDestination
MAIN[20][68]MAIN[20][69]MAIN[20][70]MAIN[19][70]MAIN[18][68]MAIN[19][68]MAIN[18][70]HEX_W0[8]
Source
0000000off
0010001OMUX[13]
0010100HEX_W6[6]
0011000HEX_W6[8]
0100001HEX_S3[8]
0100010OMUX_W14
0100100LH[6]
0101000HEX_N3[8]
1000001LH[18]
1000100HEX_S7[0]
1001000HEX_N6[7]
virtex2 INT_DCM_V2 switchbox INT muxes HEX_W0[9]
BitsDestination
MAIN[21][78]MAIN[21][76]MAIN[20][79]MAIN[19][79]MAIN[18][77]MAIN[19][77]MAIN[18][79]HEX_W0[9]
Source
0000000off
0010001OMUX[13]
0010010LH[0]
0010100HEX_N3[9]
0011000HEX_S3[9]
0100001LH[12]
0100010OMUX[15]
0100100HEX_S7[1]
0101000HEX_N6[8]
1000001OMUX_S0
1000010OMUX_SW5
1000100HEX_W6[7]
1001000HEX_W6[9]
virtex2 INT_DCM_V2 switchbox INT muxes HEX_E0[0]
BitsDestination
MAIN[21][4]MAIN[21][6]MAIN[20][7]MAIN[19][7]MAIN[18][5]MAIN[19][5]MAIN[18][7]HEX_E0[0]
Source
0000000off
0010001OMUX_E2
0010010LH[6]
0010100HEX_N3[0]
0011000HEX_S3[0]
0100010OMUX_EN8
0100100HEX_E6[0]
0101000HEX_E6[2]
1000001LH[18]
1000100HEX_S6[2]
1001000HEX_N7[9]
virtex2 INT_DCM_V2 switchbox INT muxes HEX_E0[1]
BitsDestination
MAIN[20][12]MAIN[20][13]MAIN[20][14]MAIN[19][14]MAIN[18][12]MAIN[19][12]MAIN[18][14]HEX_E0[1]
Source
0000000off
0010001OMUX_S4
0010100HEX_E6[1]
0011000HEX_E6[3]
0100001HEX_S3[1]
0100010OMUX_N10
0100100LH[0]
0101000HEX_N3[1]
1000001LH[12]
1000100HEX_S6[3]
1001000HEX_N6[0]
virtex2 INT_DCM_V2 switchbox INT muxes HEX_E0[2]
BitsDestination
MAIN[21][22]MAIN[20][23]MAIN[21][20]MAIN[19][23]MAIN[18][21]MAIN[18][23]MAIN[19][21]HEX_E0[2]
Source
0000000off
0010001OMUX[4]
0010010LH[18]
0010100HEX_S6[4]
0011000HEX_N6[1]
0100001LH[6]
0100010OMUX[6]
0100100HEX_N3[2]
0101000HEX_S3[2]
1000001OMUX_NE12
1000100HEX_E6[2]
1001000HEX_E6[4]
virtex2 INT_DCM_V2 switchbox INT muxes HEX_E0[3]
BitsDestination
MAIN[20][28]MAIN[20][29]MAIN[20][30]MAIN[19][30]MAIN[18][28]MAIN[19][28]MAIN[18][30]HEX_E0[3]
Source
0000000off
0010001OMUX_SE3
0010100HEX_E6[3]
0011000HEX_E6[5]
0100001HEX_S3[3]
0100010OMUX_EN8
0100100LH[0]
0101000HEX_N3[3]
1000001LH[12]
1000100HEX_S6[5]
1001000HEX_N6[2]
virtex2 INT_DCM_V2 switchbox INT muxes HEX_E0[4]
BitsDestination
MAIN[21][36]MAIN[20][39]MAIN[21][38]MAIN[19][39]MAIN[18][37]MAIN[18][39]MAIN[19][37]HEX_E0[4]
Source
0000000off
0010001OMUX_E7
0010100HEX_E6[4]
0011000HEX_E6[6]
0100001LH[6]
0100010OMUX_E8
0100100HEX_N3[4]
0101000HEX_S3[4]
1000010LH[18]
1000100HEX_S6[6]
1001000HEX_N6[3]
virtex2 INT_DCM_V2 switchbox INT muxes HEX_E0[5]
BitsDestination
MAIN[20][44]MAIN[20][45]MAIN[20][46]MAIN[19][46]MAIN[18][44]MAIN[19][44]MAIN[18][46]HEX_E0[5]
Source
0000000off
0010001OMUX_ES7
0010100HEX_E6[5]
0011000HEX_E6[7]
0100001HEX_S3[5]
0100010OMUX_NE12
0100100LH[0]
0101000HEX_N3[5]
1000001LH[12]
1000100HEX_S6[7]
1001000HEX_N6[4]
virtex2 INT_DCM_V2 switchbox INT muxes HEX_E0[6]
BitsDestination
MAIN[21][52]MAIN[20][55]MAIN[21][54]MAIN[19][55]MAIN[18][53]MAIN[18][55]MAIN[19][53]HEX_E0[6]
Source
0000000off
0010001OMUX[9]
0010010OMUX[11]
0010100HEX_E6[6]
0011000HEX_E6[8]
0100001LH[6]
0100010OMUX_SE3
0100100HEX_N3[6]
0101000HEX_S3[6]
1000010LH[18]
1000100HEX_S6[8]
1001000HEX_N6[5]
virtex2 INT_DCM_V2 switchbox INT muxes HEX_E0[7]
BitsDestination
MAIN[20][60]MAIN[20][61]MAIN[20][62]MAIN[19][62]MAIN[18][60]MAIN[19][60]MAIN[18][62]HEX_E0[7]
Source
0000000off
0010001OMUX_S5
0010100HEX_E6[7]
0011000HEX_E6[9]
0100001HEX_S3[7]
0100010OMUX_N11
0100100LH[0]
0101000HEX_N3[7]
1000001LH[12]
1000100HEX_S6[9]
1001000HEX_N6[6]
virtex2 INT_DCM_V2 switchbox INT muxes HEX_E0[8]
BitsDestination
MAIN[21][68]MAIN[21][70]MAIN[20][71]MAIN[19][71]MAIN[18][69]MAIN[19][69]MAIN[18][71]HEX_E0[8]
Source
0000000off
0010001OMUX_ES7
0010010LH[6]
0010100HEX_N3[8]
0011000HEX_S3[8]
0100010OMUX_E13
0100100HEX_E6[8]
0101000HEX_E6_S[0]
1000001LH[18]
1000100HEX_S7[0]
1001000HEX_N6[7]
virtex2 INT_DCM_V2 switchbox INT muxes HEX_E0[9]
BitsDestination
MAIN[20][77]MAIN[20][78]MAIN[20][76]MAIN[19][78]MAIN[18][76]MAIN[18][78]MAIN[19][76]HEX_E0[9]
Source
0000000off
0010001OMUX[15]
0010010LH[12]
0010100HEX_S7[1]
0011000HEX_N6[8]
0100001OMUX_S0
0100010OMUX_S2
0100100HEX_E6[9]
0101000HEX_E6_S[1]
1000001OMUX_N15
1000010HEX_S3[9]
1000100LH[0]
1001000HEX_N3[9]
virtex2 INT_DCM_V2 switchbox INT muxes HEX_S0[0]
BitsDestination
MAIN[20][3]MAIN[21][2]MAIN[21][0]MAIN[19][3]MAIN[18][1]MAIN[18][3]MAIN[19][1]HEX_S0[0]
Source
0000000off
0010001OMUX[0]
0010010LV[0]
0010100HEX_E6[1]
0011000HEX_W6_N[8]
0100001OMUX[2]
0100100HEX_S6[0]
0101000HEX_S6[2]
1000001LV[12]
1000010OMUX_S0
1000100HEX_W3[0]
1001000HEX_E3[0]
virtex2 INT_DCM_V2 switchbox INT muxes HEX_S0[1]
BitsDestination
MAIN[20][8]MAIN[20][9]MAIN[20][10]MAIN[18][8]MAIN[19][10]MAIN[19][8]MAIN[18][10]HEX_S0[1]
Source
0000000off
0010001OMUX[2]
0010100HEX_S6[3]
0011000HEX_S6[1]
0100001HEX_E3[1]
0100010OMUX_E2
0100100HEX_W3[1]
0101000LV[18]
1000001LV[6]
1000100HEX_W6_N[9]
1001000HEX_E6[2]
virtex2 INT_DCM_V2 switchbox INT muxes HEX_S0[2]
BitsDestination
MAIN[21][16]MAIN[20][19]MAIN[21][18]MAIN[19][19]MAIN[18][17]MAIN[19][17]MAIN[18][19]HEX_S0[2]
Source
0000000off
0010001OMUX[4]
0010010OMUX_S4
0010100HEX_S6[2]
0011000HEX_S6[4]
0100001OMUX[6]
0100010LV[12]
0100100HEX_W3[2]
0101000HEX_E3[2]
1000001LV[0]
1000100HEX_E6[3]
1001000HEX_W6[0]
virtex2 INT_DCM_V2 switchbox INT muxes HEX_S0[3]
BitsDestination
MAIN[20][24]MAIN[20][26]MAIN[20][25]MAIN[18][24]MAIN[19][26]MAIN[18][26]MAIN[19][24]HEX_S0[3]
Source
0000000off
0010001OMUX[6]
0010010HEX_E3[3]
0010100HEX_W3[3]
0011000LV[18]
0100010OMUX_W6
0100100HEX_S6[5]
0101000HEX_S6[3]
1000010LV[6]
1000100HEX_W6[1]
1001000HEX_E6[4]
virtex2 INT_DCM_V2 switchbox INT muxes HEX_S0[4]
BitsDestination
MAIN[21][32]MAIN[21][34]MAIN[20][35]MAIN[19][35]MAIN[18][33]MAIN[19][33]MAIN[18][35]HEX_S0[4]
Source
0000000off
0010001OMUX_WS1
0010010LV[12]
0010100HEX_W3[4]
0011000HEX_E3[4]
0100010OMUX_SE3
0100100HEX_S6[4]
0101000HEX_S6[6]
1000001LV[0]
1000100HEX_E6[5]
1001000HEX_W6[2]
virtex2 INT_DCM_V2 switchbox INT muxes HEX_S0[5]
BitsDestination
MAIN[20][40]MAIN[20][41]MAIN[20][42]MAIN[18][40]MAIN[19][42]MAIN[19][40]MAIN[18][42]HEX_S0[5]
Source
0000000off
0010001OMUX_S3
0010100HEX_S6[7]
0011000HEX_S6[5]
0100001HEX_E3[5]
0100010OMUX_E8
0100100HEX_W3[5]
0101000LV[18]
1000001LV[6]
1000100HEX_W6[3]
1001000HEX_E6[6]
virtex2 INT_DCM_V2 switchbox INT muxes HEX_S0[6]
BitsDestination
MAIN[21][48]MAIN[21][50]MAIN[20][51]MAIN[19][51]MAIN[18][49]MAIN[19][49]MAIN[18][51]HEX_S0[6]
Source
0000000off
0010001OMUX_SW5
0010010LV[12]
0010100HEX_W3[6]
0011000HEX_E3[6]
0100010OMUX_ES7
0100100HEX_S6[6]
0101000HEX_S6[8]
1000001LV[0]
1000100HEX_E6[7]
1001000HEX_W6[4]
virtex2 INT_DCM_V2 switchbox INT muxes HEX_S0[7]
BitsDestination
MAIN[20][57]MAIN[20][58]MAIN[20][56]MAIN[18][56]MAIN[19][58]MAIN[18][58]MAIN[19][56]HEX_S0[7]
Source
0000000off
0010001OMUX[11]
0010010LV[6]
0010100HEX_W6[5]
0011000HEX_E6[8]
0100010OMUX_WS1
0100100HEX_S6[9]
0101000HEX_S6[7]
1000001OMUX_SE3
1000010HEX_E3[7]
1000100HEX_W3[7]
1001000LV[18]
virtex2 INT_DCM_V2 switchbox INT muxes HEX_S0[8]
BitsDestination
MAIN[21][64]MAIN[20][67]MAIN[21][66]MAIN[19][67]MAIN[18][65]MAIN[18][67]MAIN[19][65]HEX_S0[8]
Source
0000000off
0010001OMUX_S5
0010100HEX_S6[8]
0011000HEX_S7[0]
0100001LV[12]
0100010OMUX_W14
0100100HEX_W3[8]
0101000HEX_E3[8]
1000010LV[0]
1000100HEX_E6[9]
1001000HEX_W6[6]
virtex2 INT_DCM_V2 switchbox INT muxes HEX_S0[9]
BitsDestination
MAIN[20][72]MAIN[20][73]MAIN[20][74]MAIN[18][72]MAIN[19][74]MAIN[18][74]MAIN[19][72]HEX_S0[9]
Source
0000000off
0010001OMUX[15]
0010010OMUX_SW5
0010100HEX_S7[1]
0011000HEX_S6[9]
0100001OMUX_ES7
0100010HEX_E3[9]
0100100HEX_W3[9]
0101000LV[18]
1000010LV[6]
1000100HEX_W6[7]
1001000HEX_E6_S[0]
virtex2 INT_DCM_V2 switchbox INT muxes HEX_N0[0]
BitsDestination
MAIN[20][1]MAIN[20][2]MAIN[20][0]MAIN[18][0]MAIN[19][2]MAIN[18][2]MAIN[19][0]HEX_N0[0]
Source
0000000off
0010001OMUX[0]
0010010LV[0]
0010100HEX_W6_N[8]
0011000HEX_E6[1]
0100010OMUX_EN8
0100100HEX_N6[0]
0101000HEX_N7[8]
1000001OMUX_N13
1000010HEX_E3[0]
1000100HEX_W3[0]
1001000LV[12]
virtex2 INT_DCM_V2 switchbox INT muxes HEX_N0[1]
BitsDestination
MAIN[21][8]MAIN[21][10]MAIN[20][11]MAIN[19][11]MAIN[18][9]MAIN[19][9]MAIN[18][11]HEX_N0[1]
Source
0000000off
0010001OMUX_N10
0010010LV[18]
0010100HEX_W3[1]
0011000HEX_E3[1]
0100010OMUX_NW10
0100100HEX_N7[9]
0101000HEX_N6[1]
1000001LV[6]
1000100HEX_E6[2]
1001000HEX_W6_N[9]
virtex2 INT_DCM_V2 switchbox INT muxes HEX_N0[2]
BitsDestination
MAIN[20][16]MAIN[20][17]MAIN[20][18]MAIN[18][16]MAIN[19][18]MAIN[18][18]MAIN[19][16]HEX_N0[2]
Source
0000000off
0010001OMUX[4]
0010010OMUX_NE12
0010100HEX_N6[2]
0011000HEX_N6[0]
0100001OMUX_W1
0100010HEX_E3[2]
0100100HEX_W3[2]
0101000LV[12]
1000010LV[0]
1000100HEX_W6[0]
1001000HEX_E6[3]
virtex2 INT_DCM_V2 switchbox INT muxes HEX_N0[3]
BitsDestination
MAIN[21][24]MAIN[21][26]MAIN[20][27]MAIN[19][27]MAIN[18][25]MAIN[19][25]MAIN[18][27]HEX_N0[3]
Source
0000000off
0010001OMUX_EN8
0010010LV[18]
0010100HEX_W3[3]
0011000HEX_E3[3]
0100010OMUX_WN14
0100100HEX_N6[1]
0101000HEX_N6[3]
1000001LV[6]
1000100HEX_E6[4]
1001000HEX_W6[1]
virtex2 INT_DCM_V2 switchbox INT muxes HEX_N0[4]
BitsDestination
MAIN[20][32]MAIN[20][33]MAIN[20][34]MAIN[18][32]MAIN[19][34]MAIN[19][32]MAIN[18][34]HEX_N0[4]
Source
0000000off
0010001OMUX_E7
0010100HEX_N6[4]
0011000HEX_N6[2]
0100001HEX_E3[4]
0100010OMUX_NW10
0100100HEX_W3[4]
0101000LV[12]
1000001LV[0]
1000100HEX_W6[2]
1001000HEX_E6[5]
virtex2 INT_DCM_V2 switchbox INT muxes HEX_N0[5]
BitsDestination
MAIN[21][40]MAIN[20][43]MAIN[21][42]MAIN[19][43]MAIN[18][41]MAIN[18][43]MAIN[19][41]HEX_N0[5]
Source
0000000off
0010001OMUX_N12
0010100HEX_N6[3]
0011000HEX_N6[5]
0100001LV[18]
0100010OMUX_NE12
0100100HEX_W3[5]
0101000HEX_E3[5]
1000010LV[6]
1000100HEX_E6[6]
1001000HEX_W6[3]
virtex2 INT_DCM_V2 switchbox INT muxes HEX_N0[6]
BitsDestination
MAIN[20][48]MAIN[20][49]MAIN[20][50]MAIN[18][48]MAIN[19][50]MAIN[19][48]MAIN[18][50]HEX_N0[6]
Source
0000000off
0010001OMUX[9]
0010100HEX_N6[6]
0011000HEX_N6[4]
0100001HEX_E3[6]
0100010OMUX_WN14
0100100HEX_W3[6]
0101000LV[12]
1000001LV[0]
1000100HEX_W6[4]
1001000HEX_E6[7]
virtex2 INT_DCM_V2 switchbox INT muxes HEX_N0[7]
BitsDestination
MAIN[20][59]MAIN[21][58]MAIN[21][56]MAIN[19][59]MAIN[18][57]MAIN[18][59]MAIN[19][57]HEX_N0[7]
Source
0000000off
0010001OMUX[11]
0010010LV[6]
0010100HEX_E6[8]
0011000HEX_W6[5]
0100001OMUX_W9
0100100HEX_N6[5]
0101000HEX_N6[7]
1000001LV[18]
1000010OMUX_N11
1000100HEX_W3[7]
1001000HEX_E3[7]
virtex2 INT_DCM_V2 switchbox INT muxes HEX_N0[8]
BitsDestination
MAIN[20][64]MAIN[20][66]MAIN[20][65]MAIN[18][64]MAIN[19][66]MAIN[18][66]MAIN[19][64]HEX_N0[8]
Source
0000000off
0010001OMUX[9]
0010010HEX_E3[8]
0010100HEX_W3[8]
0011000LV[12]
0100010OMUX_E13
0100100HEX_N6[8]
0101000HEX_N6[6]
1000010LV[0]
1000100HEX_W6[6]
1001000HEX_E6[9]
virtex2 INT_DCM_V2 switchbox INT muxes HEX_N0[9]
BitsDestination
MAIN[21][72]MAIN[20][75]MAIN[21][74]MAIN[19][75]MAIN[18][73]MAIN[18][75]MAIN[19][73]HEX_N0[9]
Source
0000000off
0010001OMUX[13]
0010010OMUX[15]
0010100HEX_N6[7]
0011000HEX_N6[9]
0100001LV[18]
0100010OMUX_N15
0100100HEX_W3[9]
0101000HEX_E3[9]
1000010LV[6]
1000100HEX_E6_S[0]
1001000HEX_W6[7]
virtex2 INT_DCM_V2 switchbox INT muxes LH[0]
BitsDestination
MAIN[21][47]MAIN[21][49]MAIN[21][51]LH[0]
Source
000off
001DBL_W1[5]
011OMUX_S4
101DBL_E1[6]
111OMUX[11]
virtex2 INT_DCM_V2 switchbox INT muxes LH[6]
BitsDestination
MAIN[21][31]MAIN[21][33]MAIN[21][29]LH[6]
Source
000off
001OMUX[4]
011OMUX_N15
101DBL_E1[4]
111DBL_W1[3]
virtex2 INT_DCM_V2 switchbox INT muxes LH[12]
BitsDestination
MAIN[21][41]MAIN[21][45]MAIN[21][43]LH[12]
Source
000off
001DBL_W1[5]
011OMUX_S4
101DBL_E1[6]
111OMUX[11]
virtex2 INT_DCM_V2 switchbox INT muxes LH[18]
BitsDestination
MAIN[21][39]MAIN[21][37]MAIN[21][35]LH[18]
Source
000off
001OMUX[4]
011OMUX_N15
101DBL_E1[4]
111DBL_W1[3]
virtex2 INT_DCM_V2 switchbox INT muxes LV[0]
BitsDestination
MAIN[21][7]MAIN[21][9]MAIN[21][19]MAIN[21][25]MAIN[21][21]MAIN[21][11]MAIN[21][5]LV[0]
Source
0000000off
0000011HEX_E1[1]
0000101OMUX_E2
0001001DBL_W1[1]
0010001HEX_E6[1]
0100001HEX_E4[1]
1000011OMUX[0]
1000101HEX_E2[1]
1001001HEX_E5[1]
1010001DBL_E1[2]
1100001HEX_E3[1]
virtex2 INT_DCM_V2 switchbox INT muxes LV[6]
BitsDestination
MAIN[21][73]MAIN[21][61]MAIN[21][55]MAIN[21][69]MAIN[21][71]MAIN[21][65]MAIN[21][75]LV[6]
Source
0000000off
0000011OMUX_W9
0000101DBL_W1[7]
0001001HEX_W5[7]
0010001HEX_W3[7]
0100001HEX_W4[7]
1000011OMUX[15]
1000101HEX_W2[7]
1001001DBL_E1[8]
1010001HEX_W0[7]
1100001HEX_W1[7]
virtex2 INT_DCM_V2 switchbox INT muxes LV[12]
BitsDestination
MAIN[21][13]MAIN[21][1]MAIN[21][27]MAIN[21][23]MAIN[21][17]MAIN[21][3]MAIN[21][15]LV[12]
Source
0000000off
0000011HEX_E1[1]
0000101OMUX_E2
0001001DBL_W1[1]
0010001HEX_E6[1]
0100001HEX_E4[1]
1000011OMUX[0]
1000101HEX_E2[1]
1001001HEX_E5[1]
1010001DBL_E1[2]
1100001HEX_E3[1]
virtex2 INT_DCM_V2 switchbox INT muxes LV[18]
BitsDestination
MAIN[21][67]MAIN[21][53]MAIN[21][57]MAIN[21][77]MAIN[21][59]MAIN[21][79]MAIN[21][63]LV[18]
Source
0000000off
0000011OMUX_W9
0000101DBL_W1[7]
0001001HEX_W5[7]
0010001HEX_W3[7]
0100001HEX_W4[7]
1000011OMUX[15]
1000101HEX_W2[7]
1001001DBL_E1[8]
1010001HEX_W0[7]
1100001HEX_W1[7]
virtex2 INT_DCM_V2 switchbox INT muxes IMUX_DCM_CLK[0]
BitsDestination
MAIN[5][38]MAIN[5][39]MAIN[5][37]MAIN[4][39]MAIN[5][40]MAIN[5][42]MAIN[4][42]MAIN[4][40]MAIN[4][46]MAIN[5][48]MAIN[4][44]MAIN[5][44]IMUX_DCM_CLK[0]
Source
000000000000PULLUP
000100000001GCLK[0]
000100000010GCLK[1]
000100000100DCM_CLKPAD[0]
000100001000DCM_CLKPAD[1]
000100010000HEX_N3[6]
000100100000HEX_N0[6]
000101000000HEX_S6[6]
000110000000HEX_S3[6]
001000000001GCLK[2]
001000000010GCLK[3]
001000000100DCM_CLKPAD[2]
001000001000DCM_CLKPAD[3]
001000010000HEX_S2[6]
001000100000HEX_N1[6]
001001000000HEX_N4[6]
001010000000HEX_S4[6]
010000000001GCLK[4]
010000000010GCLK[5]
010000000100DCM_CLKPAD[4]
010000001000DCM_CLKPAD[5]
010000010000HEX_S1[6]
010000100000HEX_S5[6]
010001000000HEX_N5[6]
010010000000HEX_N2[6]
100000000001GCLK[7]
100000000010GCLK[6]
100000000100DCM_CLKPAD[6]
100000001000DCM_CLKPAD[7]
100000010000DBL_W1[5]
100000100000DBL_W2[5]
100001000000DBL_E0[5]
100010000000DBL_E1[5]
virtex2 INT_DCM_V2 switchbox INT muxes IMUX_DCM_CLK[1]
BitsDestination
MAIN[5][46]MAIN[5][47]MAIN[5][49]MAIN[4][47]MAIN[4][37]MAIN[4][41]MAIN[5][43]MAIN[5][41]MAIN[4][45]MAIN[4][49]MAIN[5][45]MAIN[4][43]IMUX_DCM_CLK[1]
Source
000000000000PULLUP
000100000001GCLK[0]
000100000010GCLK[1]
000100000100DCM_CLKPAD[0]
000100001000DCM_CLKPAD[1]
000100010000HEX_N3[6]
000100100000HEX_N0[6]
000101000000HEX_S6[6]
000110000000HEX_S3[6]
001000000001GCLK[2]
001000000010GCLK[3]
001000000100DCM_CLKPAD[2]
001000001000DCM_CLKPAD[3]
001000010000HEX_S2[6]
001000100000HEX_N1[6]
001001000000HEX_N4[6]
001010000000HEX_S4[6]
010000000001GCLK[4]
010000000010GCLK[5]
010000000100DCM_CLKPAD[4]
010000001000DCM_CLKPAD[5]
010000010000HEX_S1[6]
010000100000HEX_S5[6]
010001000000HEX_N5[6]
010010000000HEX_N2[6]
100000000001GCLK[7]
100000000010GCLK[6]
100000000100DCM_CLKPAD[6]
100000001000DCM_CLKPAD[7]
100000010000DBL_W1[5]
100000100000DBL_W2[5]
100001000000DBL_E0[5]
100010000000DBL_E1[5]
virtex2 INT_DCM_V2 switchbox INT muxes IMUX_DCM_CLK[2]
BitsDestination
MAIN[5][53]MAIN[5][52]MAIN[5][50]MAIN[4][52]MAIN[4][62]MAIN[4][58]MAIN[5][56]MAIN[5][58]MAIN[4][54]MAIN[4][50]MAIN[5][54]MAIN[4][56]IMUX_DCM_CLK[2]
Source
000000000000PULLUP
000100000001GCLK[0]
000100000010GCLK[1]
000100000100DCM_CLKPAD[0]
000100001000DCM_CLKPAD[1]
000100010000HEX_S6[6]
000100100000HEX_N3[6]
000101000000HEX_N0[6]
000110000000HEX_S4[6]
001000000001GCLK[2]
001000000010GCLK[3]
001000000100DCM_CLKPAD[2]
001000001000DCM_CLKPAD[3]
001000010000HEX_N5[6]
001000100000HEX_S3[6]
001001000000HEX_S2[6]
001010000000HEX_N2[6]
010000000001GCLK[4]
010000000010GCLK[5]
010000000100DCM_CLKPAD[4]
010000001000DCM_CLKPAD[5]
010000010000HEX_S1[6]
010000100000HEX_S5[6]
010001000000HEX_N4[6]
010010000000HEX_N1[6]
100000000001GCLK[7]
100000000010GCLK[6]
100000000100DCM_CLKPAD[6]
100000001000DCM_CLKPAD[7]
100000010000DBL_W1[6]
100000100000DBL_W2[6]
100001000000DBL_E0[6]
100010000000DBL_E1[6]
virtex2 INT_DCM_V2 switchbox INT muxes IMUX_SR[0]
BitsDestination
MAIN[5][3]MAIN[4][3]MAIN[5][5]MAIN[4][5]MAIN[5][1]MAIN[5][2]MAIN[4][2]MAIN[5][0]IMUX_SR[0]
Source
00000000PULLUP
00010001DBL_W1[0]
00010010HEX_N1[0]
00010100HEX_N5[0]
00011000HEX_S4[0]
00100001DBL_W2[0]
00100010HEX_S5[0]
00100100HEX_S1[0]
00101000HEX_N3[0]
01000001HEX_N2[0]
01000010DBL_E0[0]
01000100HEX_S2[0]
01001000HEX_N0[0]
10000001HEX_S3[0]
10000010DBL_E1[0]
10000100HEX_N4[0]
10001000HEX_S6[0]
virtex2 INT_DCM_V2 switchbox INT muxes IMUX_SR[1]
BitsDestination
MAIN[4][12]MAIN[5][12]MAIN[5][14]MAIN[4][14]MAIN[5][16]MAIN[5][15]MAIN[5][17]MAIN[4][15]IMUX_SR[1]
Source
00000000PULLUP
00010001DBL_W1[1]
00010010HEX_N2[0]
00010100HEX_S2[0]
00011000HEX_N0[0]
00100001DBL_W2[1]
00100010HEX_S3[0]
00100100HEX_N4[0]
00101000HEX_S6[0]
01000001HEX_S5[0]
01000010DBL_E0[1]
01000100HEX_S1[0]
01001000HEX_N3[0]
10000001HEX_N1[0]
10000010DBL_E1[1]
10000100HEX_N5[0]
10001000HEX_S4[0]
virtex2 INT_DCM_V2 switchbox INT muxes IMUX_SR[2]
BitsDestination
MAIN[4][0]MAIN[4][4]MAIN[4][8]MAIN[5][4]MAIN[5][7]MAIN[5][8]MAIN[4][6]MAIN[5][6]IMUX_SR[2]
Source
00000000PULLUP
00010001DBL_W1[0]
00010010HEX_N1[0]
00010100HEX_N5[0]
00011000HEX_S4[0]
00100001DBL_W2[0]
00100010HEX_S5[0]
00100100HEX_S1[0]
00101000HEX_N3[0]
01000001HEX_N2[0]
01000010DBL_E0[0]
01000100HEX_S2[0]
01001000HEX_N0[0]
10000001HEX_S3[0]
10000010DBL_E1[0]
10000100HEX_N4[0]
10001000HEX_S6[0]
virtex2 INT_DCM_V2 switchbox INT muxes IMUX_SR[3]
BitsDestination
MAIN[5][13]MAIN[4][9]MAIN[4][17]MAIN[4][13]MAIN[5][10]MAIN[5][9]MAIN[5][11]MAIN[4][11]IMUX_SR[3]
Source
00000000PULLUP
00010001DBL_W1[1]
00010010HEX_N2[0]
00010100HEX_S2[0]
00011000HEX_N0[0]
00100001DBL_W2[1]
00100010HEX_S3[0]
00100100HEX_N4[0]
00101000HEX_S6[0]
01000001HEX_S5[0]
01000010DBL_E0[1]
01000100HEX_S1[0]
01001000HEX_N3[0]
10000001HEX_N1[0]
10000010DBL_E1[1]
10000100HEX_N5[0]
10001000HEX_S4[0]
virtex2 INT_DCM_V2 switchbox INT muxes IMUX_CE[2]
BitsDestination
MAIN[5][75]MAIN[4][71]MAIN[4][79]MAIN[4][75]MAIN[5][72]MAIN[5][71]MAIN[5][73]MAIN[4][73]IMUX_CE[2]
Source
00000000PULLUP
00010001DBL_W1[9]
00010010HEX_S1[9]
00010100HEX_S2[9]
00011000HEX_S5[9]
00100001DBL_W2[9]
00100010HEX_N5[9]
00100100HEX_N4[9]
00101000HEX_N1[9]
01000001HEX_S6[9]
01000010DBL_E0[9]
01000100HEX_S4[9]
01001000HEX_S3[9]
10000001HEX_N0[9]
10000010DBL_E1[9]
10000100HEX_N2[9]
10001000HEX_N3[9]
virtex2 INT_DCM_V2 switchbox INT muxes IMUX_CE[3]
BitsDestination
MAIN[4][74]MAIN[5][74]MAIN[5][76]MAIN[4][76]MAIN[5][78]MAIN[5][77]MAIN[5][79]MAIN[4][77]IMUX_CE[3]
Source
00000000PULLUP
00010001DBL_W1[9]
00010010HEX_S1[9]
00010100HEX_S2[9]
00011000HEX_S5[9]
00100001DBL_W2[9]
00100010HEX_N5[9]
00100100HEX_N4[9]
00101000HEX_N1[9]
01000001HEX_S6[9]
01000010DBL_E0[9]
01000100HEX_S4[9]
01001000HEX_S3[9]
10000001HEX_N0[9]
10000010DBL_E1[9]
10000100HEX_N2[9]
10001000HEX_N3[9]
virtex2 INT_DCM_V2 switchbox INT muxes IMUX_TI[0]
BitsDestination
MAIN[5][18]MAIN[5][19]MAIN[4][20]MAIN[5][20]MAIN[5][27]MAIN[4][25]MAIN[4][23]MAIN[5][23]MAIN[4][21]MAIN[5][21]IMUX_TI[0]
Source
0000000000PULLUP
0001000001OMUX[2]
0001000010OMUX[3]
0001000100HEX_N5[3]
0001001000HEX_N2[3]
0001010000HEX_S5[3]
0001100000HEX_S2[3]
0010000001OMUX[4]
0010000010HEX_N0[3]
0010000100DBL_W1[2]
0010001000DBL_W2[2]
0010010000HEX_N3[3]
0010100000HEX_S4[3]
0100000001OMUX[5]
0100000010DBL_W2[3]
0100000100DBL_W1[3]
0100001000DBL_E1[3]
0100010000DBL_E0[3]
0100100000HEX_S1[3]
1000000001DBL_E0[2]
1000000010HEX_S6[3]
1000000100DBL_E1[2]
1000001000HEX_S3[3]
1000010000HEX_N1[3]
1000100000HEX_N4[3]
virtex2 INT_DCM_V2 switchbox INT muxes IMUX_TI[1]
BitsDestination
MAIN[5][28]MAIN[5][25]MAIN[4][26]MAIN[5][26]MAIN[4][28]MAIN[4][24]MAIN[5][22]MAIN[5][24]MAIN[4][22]MAIN[4][18]IMUX_TI[1]
Source
0000000000PULLUP
0001000001OMUX[2]
0001000010OMUX[3]
0001000100HEX_N5[3]
0001001000HEX_N2[3]
0001010000HEX_S5[3]
0001100000HEX_S2[3]
0010000001OMUX[4]
0010000010HEX_N0[3]
0010000100DBL_W1[2]
0010001000DBL_W2[2]
0010010000HEX_N3[3]
0010100000HEX_S4[3]
0100000001OMUX[5]
0100000010DBL_W2[3]
0100000100DBL_W1[3]
0100001000DBL_E1[3]
0100010000DBL_E0[3]
0100100000HEX_S1[3]
1000000001DBL_E0[2]
1000000010HEX_S6[3]
1000000100DBL_E1[2]
1000001000HEX_S3[3]
1000010000HEX_N1[3]
1000100000HEX_N4[3]
virtex2 INT_DCM_V2 switchbox INT muxes IMUX_G0_FAN[0]
BitsDestination
MAIN[9][16]MAIN[9][19]MAIN[8][19]MAIN[8][16]MAIN[10][17]MAIN[10][19]MAIN[11][19]MAIN[11][17]MAIN[13][17]MAIN[12][19]MAIN[13][19]MAIN[12][17]IMUX_G0_FAN[0]
Source
000000000000PULLUP
000100000001OMUX_W1
000100000010OMUX_E2
000100000100OMUX_NW10
000100001000OMUX_N10
000100010000DBL_S1[0]
000100100000IMUX_G1_FAN[0]
000101000000DBL_N2[0]
000110000000IMUX_G2_FAN[0]
001000000001DBL_E0[1]
001000000010DBL_S0[0]
001000000100OMUX_EN8
001000001000DBL_W0[0]
001000010000DBL_N1[1]
001000100000DBL_S1[2]
001001000000DBL_W2[1]
001010000000DBL_S1[1]
010000000001DBL_E2[1]
010000000010DBL_S0[2]
010000000100DBL_E2[0]
010000001000DBL_E2[2]
010000010000DBL_W1[0]
010000100000DBL_E1[2]
010001000000DBL_E1[1]
010010000000DBL_N2[1]
100000000001DBL_S2[0]
100000000010DBL_S2[2]
100000000100DBL_N0[1]
100000001000DBL_S2[1]
100000010000DBL_E1[0]
100000100000DBL_W1[1]
100001000000DBL_W2[0]
100010000000DBL_N1[0]
virtex2 INT_DCM_V2 switchbox INT muxes IMUX_G0_FAN[1]
BitsDestination
MAIN[9][17]MAIN[9][18]MAIN[8][18]MAIN[8][17]MAIN[10][16]MAIN[10][18]MAIN[11][18]MAIN[11][16]MAIN[13][16]MAIN[12][18]MAIN[13][18]MAIN[12][16]IMUX_G0_FAN[1]
Source
000000000000PULLUP
000100000001OMUX_W1
000100000010OMUX_E2
000100000100OMUX_NW10
000100001000OMUX_N10
000100010000DBL_S1[0]
000100100000IMUX_G1_FAN[0]
000101000000DBL_N2[0]
000110000000IMUX_G2_FAN[0]
001000000001DBL_E0[1]
001000000010DBL_S0[0]
001000000100OMUX_EN8
001000001000DBL_W0[0]
001000010000DBL_N1[1]
001000100000DBL_S1[2]
001001000000DBL_W2[1]
001010000000DBL_S1[1]
010000000001DBL_E2[1]
010000000010DBL_S0[2]
010000000100DBL_E2[0]
010000001000DBL_E2[2]
010000010000DBL_W1[0]
010000100000DBL_E1[2]
010001000000DBL_E1[1]
010010000000DBL_N2[1]
100000000001DBL_S2[0]
100000000010DBL_S2[2]
100000000100DBL_N0[1]
100000001000DBL_S2[1]
100000010000DBL_E1[0]
100000100000DBL_W1[1]
100001000000DBL_W2[0]
100010000000DBL_N1[0]
virtex2 INT_DCM_V2 switchbox INT muxes IMUX_G0_DATA[0]
BitsDestination
MAIN[9][0]MAIN[9][3]MAIN[8][3]MAIN[8][0]MAIN[10][1]MAIN[10][3]MAIN[11][3]MAIN[11][1]MAIN[13][1]MAIN[12][3]MAIN[13][3]MAIN[12][1]IMUX_G0_DATA[0]
Source
000000000000PULLUP
000100000001OMUX_W1
000100000010OMUX_E2
000100000100OMUX_NW10
000100001000OMUX_N10
000100010000DBL_S1[0]
000100100000IMUX_G1_FAN[0]
000101000000DBL_N2[0]
000110000000IMUX_G2_FAN[0]
001000000001DBL_E0[1]
001000000010DBL_S0[0]
001000000100OMUX_EN8
001000001000DBL_W0[0]
001000010000DBL_N1[1]
001000100000DBL_S1[2]
001001000000DBL_W2[1]
001010000000DBL_S1[1]
010000000001DBL_E2[1]
010000000010DBL_S0[2]
010000000100DBL_E2[0]
010000001000DBL_E2[2]
010000010000DBL_W1[0]
010000100000DBL_E1[2]
010001000000DBL_E1[1]
010010000000DBL_N2[1]
100000000001DBL_S2[0]
100000000010DBL_S2[2]
100000000100DBL_N0[1]
100000001000DBL_S2[1]
100000010000DBL_E1[0]
100000100000DBL_W1[1]
100001000000DBL_W2[0]
100010000000DBL_N1[0]
virtex2 INT_DCM_V2 switchbox INT muxes IMUX_G0_DATA[1]
BitsDestination
MAIN[9][1]MAIN[9][2]MAIN[8][2]MAIN[8][1]MAIN[10][0]MAIN[10][2]MAIN[11][2]MAIN[11][0]MAIN[13][0]MAIN[12][2]MAIN[13][2]MAIN[12][0]IMUX_G0_DATA[1]
Source
000000000000PULLUP
000100000001OMUX_W1
000100000010OMUX_E2
000100000100OMUX_NW10
000100001000OMUX_N10
000100010000DBL_S1[0]
000100100000IMUX_G1_FAN[0]
000101000000DBL_N2[0]
000110000000IMUX_G2_FAN[0]
001000000001DBL_E0[1]
001000000010DBL_S0[0]
001000000100OMUX_EN8
001000001000DBL_W0[0]
001000010000DBL_N1[1]
001000100000DBL_S1[2]
001001000000DBL_W2[1]
001010000000DBL_S1[1]
010000000001DBL_E2[1]
010000000010DBL_S0[2]
010000000100DBL_E2[0]
010000001000DBL_E2[2]
010000010000DBL_W1[0]
010000100000DBL_E1[2]
010001000000DBL_E1[1]
010010000000DBL_N2[1]
100000000001DBL_S2[0]
100000000010DBL_S2[2]
100000000100DBL_N0[1]
100000001000DBL_S2[1]
100000010000DBL_E1[0]
100000100000DBL_W1[1]
100001000000DBL_W2[0]
100010000000DBL_N1[0]
virtex2 INT_DCM_V2 switchbox INT muxes IMUX_G0_DATA[2]
BitsDestination
MAIN[9][7]MAIN[9][4]MAIN[8][4]MAIN[8][7]MAIN[10][6]MAIN[10][4]MAIN[11][4]MAIN[11][6]MAIN[13][6]MAIN[12][4]MAIN[13][4]MAIN[12][6]IMUX_G0_DATA[2]
Source
000000000000PULLUP
000100000001OMUX_W1
000100000010OMUX_E2
000100000100OMUX_NW10
000100001000OMUX_N10
000100010000DBL_S1[0]
000100100000IMUX_G1_FAN[0]
000101000000DBL_N2[0]
000110000000IMUX_G2_FAN[0]
001000000001DBL_E0[1]
001000000010DBL_S0[0]
001000000100OMUX_EN8
001000001000DBL_W0[0]
001000010000DBL_N1[1]
001000100000DBL_S1[2]
001001000000DBL_W2[1]
001010000000DBL_S1[1]
010000000001DBL_E2[1]
010000000010DBL_S0[2]
010000000100DBL_E2[0]
010000001000DBL_E2[2]
010000010000DBL_W1[0]
010000100000DBL_E1[2]
010001000000DBL_E1[1]
010010000000DBL_N2[1]
100000000001DBL_S2[0]
100000000010DBL_S2[2]
100000000100DBL_N0[1]
100000001000DBL_S2[1]
100000010000DBL_E1[0]
100000100000DBL_W1[1]
100001000000DBL_W2[0]
100010000000DBL_N1[0]
virtex2 INT_DCM_V2 switchbox INT muxes IMUX_G0_DATA[3]
BitsDestination
MAIN[9][6]MAIN[9][5]MAIN[8][5]MAIN[8][6]MAIN[10][7]MAIN[10][5]MAIN[11][5]MAIN[11][7]MAIN[13][7]MAIN[12][5]MAIN[13][5]MAIN[12][7]IMUX_G0_DATA[3]
Source
000000000000PULLUP
000100000001OMUX_W1
000100000010OMUX_E2
000100000100OMUX_NW10
000100001000OMUX_N10
000100010000DBL_S1[0]
000100100000IMUX_G1_FAN[0]
000101000000DBL_N2[0]
000110000000IMUX_G2_FAN[0]
001000000001DBL_E0[1]
001000000010DBL_S0[0]
001000000100OMUX_EN8
001000001000DBL_W0[0]
001000010000DBL_N1[1]
001000100000DBL_S1[2]
001001000000DBL_W2[1]
001010000000DBL_S1[1]
010000000001DBL_E2[1]
010000000010DBL_S0[2]
010000000100DBL_E2[0]
010000001000DBL_E2[2]
010000010000DBL_W1[0]
010000100000DBL_E1[2]
010001000000DBL_E1[1]
010010000000DBL_N2[1]
100000000001DBL_S2[0]
100000000010DBL_S2[2]
100000000100DBL_N0[1]
100000001000DBL_S2[1]
100000010000DBL_E1[0]
100000100000DBL_W1[1]
100001000000DBL_W2[0]
100010000000DBL_N1[0]
virtex2 INT_DCM_V2 switchbox INT muxes IMUX_G0_DATA[4]
BitsDestination
MAIN[9][8]MAIN[9][11]MAIN[8][11]MAIN[8][8]MAIN[10][9]MAIN[10][11]MAIN[11][11]MAIN[11][9]MAIN[13][9]MAIN[12][11]MAIN[13][11]MAIN[12][9]IMUX_G0_DATA[4]
Source
000000000000PULLUP
000100000001OMUX_W1
000100000010OMUX_E2
000100000100OMUX_NW10
000100001000OMUX_N10
000100010000DBL_S1[0]
000100100000IMUX_G1_FAN[0]
000101000000DBL_N2[0]
000110000000IMUX_G2_FAN[0]
001000000001DBL_E0[1]
001000000010DBL_S0[0]
001000000100OMUX_EN8
001000001000DBL_W0[0]
001000010000DBL_N1[1]
001000100000DBL_S1[2]
001001000000DBL_W2[1]
001010000000DBL_S1[1]
010000000001DBL_E2[1]
010000000010DBL_S0[2]
010000000100DBL_E2[0]
010000001000DBL_E2[2]
010000010000DBL_W1[0]
010000100000DBL_E1[2]
010001000000DBL_E1[1]
010010000000DBL_N2[1]
100000000001DBL_S2[0]
100000000010DBL_S2[2]
100000000100DBL_N0[1]
100000001000DBL_S2[1]
100000010000DBL_E1[0]
100000100000DBL_W1[1]
100001000000DBL_W2[0]
100010000000DBL_N1[0]
virtex2 INT_DCM_V2 switchbox INT muxes IMUX_G0_DATA[5]
BitsDestination
MAIN[9][9]MAIN[9][10]MAIN[8][10]MAIN[8][9]MAIN[10][8]MAIN[10][10]MAIN[11][10]MAIN[11][8]MAIN[13][8]MAIN[12][10]MAIN[13][10]MAIN[12][8]IMUX_G0_DATA[5]
Source
000000000000PULLUP
000100000001OMUX_W1
000100000010OMUX_E2
000100000100OMUX_NW10
000100001000OMUX_N10
000100010000DBL_S1[0]
000100100000IMUX_G1_FAN[0]
000101000000DBL_N2[0]
000110000000IMUX_G2_FAN[0]
001000000001DBL_E0[1]
001000000010DBL_S0[0]
001000000100OMUX_EN8
001000001000DBL_W0[0]
001000010000DBL_N1[1]
001000100000DBL_S1[2]
001001000000DBL_W2[1]
001010000000DBL_S1[1]
010000000001DBL_E2[1]
010000000010DBL_S0[2]
010000000100DBL_E2[0]
010000001000DBL_E2[2]
010000010000DBL_W1[0]
010000100000DBL_E1[2]
010001000000DBL_E1[1]
010010000000DBL_N2[1]
100000000001DBL_S2[0]
100000000010DBL_S2[2]
100000000100DBL_N0[1]
100000001000DBL_S2[1]
100000010000DBL_E1[0]
100000100000DBL_W1[1]
100001000000DBL_W2[0]
100010000000DBL_N1[0]
virtex2 INT_DCM_V2 switchbox INT muxes IMUX_G0_DATA[6]
BitsDestination
MAIN[9][15]MAIN[9][12]MAIN[8][12]MAIN[8][15]MAIN[10][14]MAIN[10][12]MAIN[11][12]MAIN[11][14]MAIN[13][14]MAIN[12][12]MAIN[13][12]MAIN[12][14]IMUX_G0_DATA[6]
Source
000000000000PULLUP
000100000001OMUX_W1
000100000010OMUX_E2
000100000100OMUX_NW10
000100001000OMUX_N10
000100010000DBL_S1[0]
000100100000IMUX_G1_FAN[0]
000101000000DBL_N2[0]
000110000000IMUX_G2_FAN[0]
001000000001DBL_E0[1]
001000000010DBL_S0[0]
001000000100OMUX_EN8
001000001000DBL_W0[0]
001000010000DBL_N1[1]
001000100000DBL_S1[2]
001001000000DBL_W2[1]
001010000000DBL_S1[1]
010000000001DBL_E2[1]
010000000010DBL_S0[2]
010000000100DBL_E2[0]
010000001000DBL_E2[2]
010000010000DBL_W1[0]
010000100000DBL_E1[2]
010001000000DBL_E1[1]
010010000000DBL_N2[1]
100000000001DBL_S2[0]
100000000010DBL_S2[2]
100000000100DBL_N0[1]
100000001000DBL_S2[1]
100000010000DBL_E1[0]
100000100000DBL_W1[1]
100001000000DBL_W2[0]
100010000000DBL_N1[0]
virtex2 INT_DCM_V2 switchbox INT muxes IMUX_G0_DATA[7]
BitsDestination
MAIN[9][14]MAIN[9][13]MAIN[8][13]MAIN[8][14]MAIN[10][15]MAIN[10][13]MAIN[11][13]MAIN[11][15]MAIN[13][15]MAIN[12][13]MAIN[13][13]MAIN[12][15]IMUX_G0_DATA[7]
Source
000000000000PULLUP
000100000001OMUX_W1
000100000010OMUX_E2
000100000100OMUX_NW10
000100001000OMUX_N10
000100010000DBL_S1[0]
000100100000IMUX_G1_FAN[0]
000101000000DBL_N2[0]
000110000000IMUX_G2_FAN[0]
001000000001DBL_E0[1]
001000000010DBL_S0[0]
001000000100OMUX_EN8
001000001000DBL_W0[0]
001000010000DBL_N1[1]
001000100000DBL_S1[2]
001001000000DBL_W2[1]
001010000000DBL_S1[1]
010000000001DBL_E2[1]
010000000010DBL_S0[2]
010000000100DBL_E2[0]
010000001000DBL_E2[2]
010000010000DBL_W1[0]
010000100000DBL_E1[2]
010001000000DBL_E1[1]
010010000000DBL_N2[1]
100000000001DBL_S2[0]
100000000010DBL_S2[2]
100000000100DBL_N0[1]
100000001000DBL_S2[1]
100000010000DBL_E1[0]
100000100000DBL_W1[1]
100001000000DBL_W2[0]
100010000000DBL_N1[0]
virtex2 INT_DCM_V2 switchbox INT muxes IMUX_G1_FAN[0]
BitsDestination
MAIN[9][23]MAIN[9][20]MAIN[8][23]MAIN[8][20]MAIN[10][22]MAIN[10][20]MAIN[11][22]MAIN[11][20]MAIN[13][20]MAIN[13][22]MAIN[12][22]MAIN[12][20]IMUX_G1_FAN[0]
Source
000000000000PULLUP
000100000001OMUX_W6
000100000010DBL_S0[4]
000100000100DBL_W0[4]
000100001000DBL_E0[3]
000100010000DBL_W1[2]
000100100000DBL_N1[4]
000101000000DBL_W2[4]
000110000000DBL_N2[4]
001000000001OMUX_N12
001000000010OMUX_E7
001000000100OMUX_NE12
001000001000OMUX_WN14
001000010000IMUX_G3_FAN[1]
001000100000DBL_S1[3]
001001000000DBL_E1[4]
001010000000IMUX_G0_FAN[1]
010000000001DBL_E2[4]
010000000010DBL_E2[3]
010000000100DBL_W2[3]
010000001000DBL_W0[2]
010000010000DBL_N1[2]
010000100000DBL_W1[3]
010001000000DBL_W1[4]
010010000000DBL_N2[3]
100000000001DBL_N0[3]
100000000010DBL_S2[4]
100000000100DBL_S2[3]
100000001000DBL_W2[2]
100000010000DBL_S1[4]
100000100000DBL_E1[3]
100001000000DBL_N2[2]
100010000000DBL_N1[3]
virtex2 INT_DCM_V2 switchbox INT muxes IMUX_G1_FAN[1]
BitsDestination
MAIN[9][22]MAIN[9][21]MAIN[8][22]MAIN[8][21]MAIN[10][23]MAIN[10][21]MAIN[11][23]MAIN[11][21]MAIN[13][21]MAIN[13][23]MAIN[12][23]MAIN[12][21]IMUX_G1_FAN[1]
Source
000000000000PULLUP
000100000001OMUX_W6
000100000010DBL_S0[4]
000100000100DBL_W0[4]
000100001000DBL_E0[3]
000100010000DBL_W1[2]
000100100000DBL_N1[4]
000101000000DBL_W2[4]
000110000000DBL_N2[4]
001000000001OMUX_N12
001000000010OMUX_E7
001000000100OMUX_NE12
001000001000OMUX_WN14
001000010000IMUX_G3_FAN[1]
001000100000DBL_S1[3]
001001000000DBL_E1[4]
001010000000IMUX_G0_FAN[1]
010000000001DBL_E2[4]
010000000010DBL_E2[3]
010000000100DBL_W2[3]
010000001000DBL_W0[2]
010000010000DBL_N1[2]
010000100000DBL_W1[3]
010001000000DBL_W1[4]
010010000000DBL_N2[3]
100000000001DBL_N0[3]
100000000010DBL_S2[4]
100000000100DBL_S2[3]
100000001000DBL_W2[2]
100000010000DBL_S1[4]
100000100000DBL_E1[3]
100001000000DBL_N2[2]
100010000000DBL_N1[3]
virtex2 INT_DCM_V2 switchbox INT muxes IMUX_G1_DATA[0]
BitsDestination
MAIN[9][39]MAIN[9][36]MAIN[8][39]MAIN[8][36]MAIN[10][38]MAIN[10][36]MAIN[11][38]MAIN[11][36]MAIN[13][36]MAIN[13][38]MAIN[12][38]MAIN[12][36]IMUX_G1_DATA[0]
Source
000000000000PULLUP
000100000001OMUX_W6
000100000010DBL_S0[4]
000100000100DBL_W0[4]
000100001000DBL_E0[3]
000100010000DBL_W1[2]
000100100000DBL_N1[4]
000101000000DBL_W2[4]
000110000000DBL_N2[4]
001000000001OMUX_N12
001000000010OMUX_E7
001000000100OMUX_NE12
001000001000OMUX_WN14
001000010000IMUX_G3_FAN[1]
001000100000DBL_S1[3]
001001000000DBL_E1[4]
001010000000IMUX_G0_FAN[1]
010000000001DBL_E2[4]
010000000010DBL_E2[3]
010000000100DBL_W2[3]
010000001000DBL_W0[2]
010000010000DBL_N1[2]
010000100000DBL_W1[3]
010001000000DBL_W1[4]
010010000000DBL_N2[3]
100000000001DBL_N0[3]
100000000010DBL_S2[4]
100000000100DBL_S2[3]
100000001000DBL_W2[2]
100000010000DBL_S1[4]
100000100000DBL_E1[3]
100001000000DBL_N2[2]
100010000000DBL_N1[3]
virtex2 INT_DCM_V2 switchbox INT muxes IMUX_G1_DATA[1]
BitsDestination
MAIN[9][38]MAIN[9][37]MAIN[8][38]MAIN[8][37]MAIN[10][39]MAIN[10][37]MAIN[11][39]MAIN[11][37]MAIN[13][37]MAIN[13][39]MAIN[12][39]MAIN[12][37]IMUX_G1_DATA[1]
Source
000000000000PULLUP
000100000001OMUX_W6
000100000010DBL_S0[4]
000100000100DBL_W0[4]
000100001000DBL_E0[3]
000100010000DBL_W1[2]
000100100000DBL_N1[4]
000101000000DBL_W2[4]
000110000000DBL_N2[4]
001000000001OMUX_N12
001000000010OMUX_E7
001000000100OMUX_NE12
001000001000OMUX_WN14
001000010000IMUX_G3_FAN[1]
001000100000DBL_S1[3]
001001000000DBL_E1[4]
001010000000IMUX_G0_FAN[1]
010000000001DBL_E2[4]
010000000010DBL_E2[3]
010000000100DBL_W2[3]
010000001000DBL_W0[2]
010000010000DBL_N1[2]
010000100000DBL_W1[3]
010001000000DBL_W1[4]
010010000000DBL_N2[3]
100000000001DBL_N0[3]
100000000010DBL_S2[4]
100000000100DBL_S2[3]
100000001000DBL_W2[2]
100000010000DBL_S1[4]
100000100000DBL_E1[3]
100001000000DBL_N2[2]
100010000000DBL_N1[3]
virtex2 INT_DCM_V2 switchbox INT muxes IMUX_G1_DATA[2]
BitsDestination
MAIN[9][32]MAIN[9][35]MAIN[8][32]MAIN[8][35]MAIN[10][33]MAIN[10][35]MAIN[11][33]MAIN[11][35]MAIN[13][35]MAIN[13][33]MAIN[12][33]MAIN[12][35]IMUX_G1_DATA[2]
Source
000000000000PULLUP
000100000001OMUX_W6
000100000010DBL_S0[4]
000100000100DBL_W0[4]
000100001000DBL_E0[3]
000100010000DBL_W1[2]
000100100000DBL_N1[4]
000101000000DBL_W2[4]
000110000000DBL_N2[4]
001000000001OMUX_N12
001000000010OMUX_E7
001000000100OMUX_NE12
001000001000OMUX_WN14
001000010000IMUX_G3_FAN[1]
001000100000DBL_S1[3]
001001000000DBL_E1[4]
001010000000IMUX_G0_FAN[1]
010000000001DBL_E2[4]
010000000010DBL_E2[3]
010000000100DBL_W2[3]
010000001000DBL_W0[2]
010000010000DBL_N1[2]
010000100000DBL_W1[3]
010001000000DBL_W1[4]
010010000000DBL_N2[3]
100000000001DBL_N0[3]
100000000010DBL_S2[4]
100000000100DBL_S2[3]
100000001000DBL_W2[2]
100000010000DBL_S1[4]
100000100000DBL_E1[3]
100001000000DBL_N2[2]
100010000000DBL_N1[3]
virtex2 INT_DCM_V2 switchbox INT muxes IMUX_G1_DATA[3]
BitsDestination
MAIN[9][33]MAIN[9][34]MAIN[8][33]MAIN[8][34]MAIN[10][32]MAIN[10][34]MAIN[11][32]MAIN[11][34]MAIN[13][34]MAIN[13][32]MAIN[12][32]MAIN[12][34]IMUX_G1_DATA[3]
Source
000000000000PULLUP
000100000001OMUX_W6
000100000010DBL_S0[4]
000100000100DBL_W0[4]
000100001000DBL_E0[3]
000100010000DBL_W1[2]
000100100000DBL_N1[4]
000101000000DBL_W2[4]
000110000000DBL_N2[4]
001000000001OMUX_N12
001000000010OMUX_E7
001000000100OMUX_NE12
001000001000OMUX_WN14
001000010000IMUX_G3_FAN[1]
001000100000DBL_S1[3]
001001000000DBL_E1[4]
001010000000IMUX_G0_FAN[1]
010000000001DBL_E2[4]
010000000010DBL_E2[3]
010000000100DBL_W2[3]
010000001000DBL_W0[2]
010000010000DBL_N1[2]
010000100000DBL_W1[3]
010001000000DBL_W1[4]
010010000000DBL_N2[3]
100000000001DBL_N0[3]
100000000010DBL_S2[4]
100000000100DBL_S2[3]
100000001000DBL_W2[2]
100000010000DBL_S1[4]
100000100000DBL_E1[3]
100001000000DBL_N2[2]
100010000000DBL_N1[3]
virtex2 INT_DCM_V2 switchbox INT muxes IMUX_G1_DATA[4]
BitsDestination
MAIN[9][31]MAIN[9][28]MAIN[8][31]MAIN[8][28]MAIN[10][30]MAIN[10][28]MAIN[11][30]MAIN[11][28]MAIN[13][28]MAIN[13][30]MAIN[12][30]MAIN[12][28]IMUX_G1_DATA[4]
Source
000000000000PULLUP
000100000001OMUX_W6
000100000010DBL_S0[4]
000100000100DBL_W0[4]
000100001000DBL_E0[3]
000100010000DBL_W1[2]
000100100000DBL_N1[4]
000101000000DBL_W2[4]
000110000000DBL_N2[4]
001000000001OMUX_N12
001000000010OMUX_E7
001000000100OMUX_NE12
001000001000OMUX_WN14
001000010000IMUX_G3_FAN[1]
001000100000DBL_S1[3]
001001000000DBL_E1[4]
001010000000IMUX_G0_FAN[1]
010000000001DBL_E2[4]
010000000010DBL_E2[3]
010000000100DBL_W2[3]
010000001000DBL_W0[2]
010000010000DBL_N1[2]
010000100000DBL_W1[3]
010001000000DBL_W1[4]
010010000000DBL_N2[3]
100000000001DBL_N0[3]
100000000010DBL_S2[4]
100000000100DBL_S2[3]
100000001000DBL_W2[2]
100000010000DBL_S1[4]
100000100000DBL_E1[3]
100001000000DBL_N2[2]
100010000000DBL_N1[3]
virtex2 INT_DCM_V2 switchbox INT muxes IMUX_G1_DATA[5]
BitsDestination
MAIN[9][30]MAIN[9][29]MAIN[8][30]MAIN[8][29]MAIN[10][31]MAIN[10][29]MAIN[11][31]MAIN[11][29]MAIN[13][29]MAIN[13][31]MAIN[12][31]MAIN[12][29]IMUX_G1_DATA[5]
Source
000000000000PULLUP
000100000001OMUX_W6
000100000010DBL_S0[4]
000100000100DBL_W0[4]
000100001000DBL_E0[3]
000100010000DBL_W1[2]
000100100000DBL_N1[4]
000101000000DBL_W2[4]
000110000000DBL_N2[4]
001000000001OMUX_N12
001000000010OMUX_E7
001000000100OMUX_NE12
001000001000OMUX_WN14
001000010000IMUX_G3_FAN[1]
001000100000DBL_S1[3]
001001000000DBL_E1[4]
001010000000IMUX_G0_FAN[1]
010000000001DBL_E2[4]
010000000010DBL_E2[3]
010000000100DBL_W2[3]
010000001000DBL_W0[2]
010000010000DBL_N1[2]
010000100000DBL_W1[3]
010001000000DBL_W1[4]
010010000000DBL_N2[3]
100000000001DBL_N0[3]
100000000010DBL_S2[4]
100000000100DBL_S2[3]
100000001000DBL_W2[2]
100000010000DBL_S1[4]
100000100000DBL_E1[3]
100001000000DBL_N2[2]
100010000000DBL_N1[3]
virtex2 INT_DCM_V2 switchbox INT muxes IMUX_G1_DATA[6]
BitsDestination
MAIN[9][24]MAIN[9][27]MAIN[8][24]MAIN[8][27]MAIN[10][25]MAIN[10][27]MAIN[11][25]MAIN[11][27]MAIN[13][27]MAIN[13][25]MAIN[12][25]MAIN[12][27]IMUX_G1_DATA[6]
Source
000000000000PULLUP
000100000001OMUX_W6
000100000010DBL_S0[4]
000100000100DBL_W0[4]
000100001000DBL_E0[3]
000100010000DBL_W1[2]
000100100000DBL_N1[4]
000101000000DBL_W2[4]
000110000000DBL_N2[4]
001000000001OMUX_N12
001000000010OMUX_E7
001000000100OMUX_NE12
001000001000OMUX_WN14
001000010000IMUX_G3_FAN[1]
001000100000DBL_S1[3]
001001000000DBL_E1[4]
001010000000IMUX_G0_FAN[1]
010000000001DBL_E2[4]
010000000010DBL_E2[3]
010000000100DBL_W2[3]
010000001000DBL_W0[2]
010000010000DBL_N1[2]
010000100000DBL_W1[3]
010001000000DBL_W1[4]
010010000000DBL_N2[3]
100000000001DBL_N0[3]
100000000010DBL_S2[4]
100000000100DBL_S2[3]
100000001000DBL_W2[2]
100000010000DBL_S1[4]
100000100000DBL_E1[3]
100001000000DBL_N2[2]
100010000000DBL_N1[3]
virtex2 INT_DCM_V2 switchbox INT muxes IMUX_G1_DATA[7]
BitsDestination
MAIN[9][25]MAIN[9][26]MAIN[8][25]MAIN[8][26]MAIN[10][24]MAIN[10][26]MAIN[11][24]MAIN[11][26]MAIN[13][26]MAIN[13][24]MAIN[12][24]MAIN[12][26]IMUX_G1_DATA[7]
Source
000000000000PULLUP
000100000001OMUX_W6
000100000010DBL_S0[4]
000100000100DBL_W0[4]
000100001000DBL_E0[3]
000100010000DBL_W1[2]
000100100000DBL_N1[4]
000101000000DBL_W2[4]
000110000000DBL_N2[4]
001000000001OMUX_N12
001000000010OMUX_E7
001000000100OMUX_NE12
001000001000OMUX_WN14
001000010000IMUX_G3_FAN[1]
001000100000DBL_S1[3]
001001000000DBL_E1[4]
001010000000IMUX_G0_FAN[1]
010000000001DBL_E2[4]
010000000010DBL_E2[3]
010000000100DBL_W2[3]
010000001000DBL_W0[2]
010000010000DBL_N1[2]
010000100000DBL_W1[3]
010001000000DBL_W1[4]
010010000000DBL_N2[3]
100000000001DBL_N0[3]
100000000010DBL_S2[4]
100000000100DBL_S2[3]
100000001000DBL_W2[2]
100000010000DBL_S1[4]
100000100000DBL_E1[3]
100001000000DBL_N2[2]
100010000000DBL_N1[3]
virtex2 INT_DCM_V2 switchbox INT muxes IMUX_G2_FAN[0]
BitsDestination
MAIN[9][56]MAIN[9][59]MAIN[8][59]MAIN[8][56]MAIN[10][57]MAIN[10][59]MAIN[11][59]MAIN[11][57]MAIN[13][59]MAIN[13][57]MAIN[12][59]MAIN[12][57]IMUX_G2_FAN[0]
Source
000000000000PULLUP
000100000001OMUX_WS1
000100000010OMUX_E8
000100000100OMUX_SE3
000100001000OMUX_W9
000100010000DBL_S1[5]
000100100000IMUX_G3_FAN[0]
000101000000DBL_N2[5]
000110000000IMUX_G0_FAN[0]
001000000001DBL_E0[5]
001000000010OMUX_S3
001000000100DBL_W0[6]
001000001000DBL_S0[6]
001000010000DBL_N1[6]
001000100000DBL_S1[7]
001001000000DBL_W2[6]
001010000000DBL_S1[6]
010000000001DBL_E2[6]
010000000010DBL_E2[5]
010000000100DBL_E2[7]
010000001000DBL_E0[7]
010000010000DBL_W1[5]
010000100000DBL_E1[7]
010001000000DBL_E1[6]
010010000000DBL_N2[6]
100000000001DBL_S2[5]
100000000010DBL_N0[5]
100000000100DBL_S2[6]
100000001000DBL_S2[7]
100000010000DBL_E1[5]
100000100000DBL_W1[6]
100001000000DBL_W2[5]
100010000000DBL_N1[5]
virtex2 INT_DCM_V2 switchbox INT muxes IMUX_G2_FAN[1]
BitsDestination
MAIN[9][57]MAIN[9][58]MAIN[8][58]MAIN[8][57]MAIN[10][56]MAIN[10][58]MAIN[11][58]MAIN[11][56]MAIN[13][58]MAIN[13][56]MAIN[12][58]MAIN[12][56]IMUX_G2_FAN[1]
Source
000000000000PULLUP
000100000001OMUX_WS1
000100000010OMUX_E8
000100000100OMUX_SE3
000100001000OMUX_W9
000100010000DBL_S1[5]
000100100000IMUX_G3_FAN[0]
000101000000DBL_N2[5]
000110000000IMUX_G0_FAN[0]
001000000001DBL_E0[5]
001000000010OMUX_S3
001000000100DBL_W0[6]
001000001000DBL_S0[6]
001000010000DBL_N1[6]
001000100000DBL_S1[7]
001001000000DBL_W2[6]
001010000000DBL_S1[6]
010000000001DBL_E2[6]
010000000010DBL_E2[5]
010000000100DBL_E2[7]
010000001000DBL_E0[7]
010000010000DBL_W1[5]
010000100000DBL_E1[7]
010001000000DBL_E1[6]
010010000000DBL_N2[6]
100000000001DBL_S2[5]
100000000010DBL_N0[5]
100000000100DBL_S2[6]
100000001000DBL_S2[7]
100000010000DBL_E1[5]
100000100000DBL_W1[6]
100001000000DBL_W2[5]
100010000000DBL_N1[5]
virtex2 INT_DCM_V2 switchbox INT muxes IMUX_G2_DATA[0]
BitsDestination
MAIN[9][40]MAIN[9][43]MAIN[8][43]MAIN[8][40]MAIN[10][41]MAIN[10][43]MAIN[11][43]MAIN[11][41]MAIN[13][43]MAIN[13][41]MAIN[12][43]MAIN[12][41]IMUX_G2_DATA[0]
Source
000000000000PULLUP
000100000001OMUX_WS1
000100000010OMUX_E8
000100000100OMUX_SE3
000100001000OMUX_W9
000100010000DBL_S1[5]
000100100000IMUX_G3_FAN[0]
000101000000DBL_N2[5]
000110000000IMUX_G0_FAN[0]
001000000001DBL_E0[5]
001000000010OMUX_S3
001000000100DBL_W0[6]
001000001000DBL_S0[6]
001000010000DBL_N1[6]
001000100000DBL_S1[7]
001001000000DBL_W2[6]
001010000000DBL_S1[6]
010000000001DBL_E2[6]
010000000010DBL_E2[5]
010000000100DBL_E2[7]
010000001000DBL_E0[7]
010000010000DBL_W1[5]
010000100000DBL_E1[7]
010001000000DBL_E1[6]
010010000000DBL_N2[6]
100000000001DBL_S2[5]
100000000010DBL_N0[5]
100000000100DBL_S2[6]
100000001000DBL_S2[7]
100000010000DBL_E1[5]
100000100000DBL_W1[6]
100001000000DBL_W2[5]
100010000000DBL_N1[5]
virtex2 INT_DCM_V2 switchbox INT muxes IMUX_G2_DATA[1]
BitsDestination
MAIN[9][41]MAIN[9][42]MAIN[8][42]MAIN[8][41]MAIN[10][40]MAIN[10][42]MAIN[11][42]MAIN[11][40]MAIN[13][42]MAIN[13][40]MAIN[12][42]MAIN[12][40]IMUX_G2_DATA[1]
Source
000000000000PULLUP
000100000001OMUX_WS1
000100000010OMUX_E8
000100000100OMUX_SE3
000100001000OMUX_W9
000100010000DBL_S1[5]
000100100000IMUX_G3_FAN[0]
000101000000DBL_N2[5]
000110000000IMUX_G0_FAN[0]
001000000001DBL_E0[5]
001000000010OMUX_S3
001000000100DBL_W0[6]
001000001000DBL_S0[6]
001000010000DBL_N1[6]
001000100000DBL_S1[7]
001001000000DBL_W2[6]
001010000000DBL_S1[6]
010000000001DBL_E2[6]
010000000010DBL_E2[5]
010000000100DBL_E2[7]
010000001000DBL_E0[7]
010000010000DBL_W1[5]
010000100000DBL_E1[7]
010001000000DBL_E1[6]
010010000000DBL_N2[6]
100000000001DBL_S2[5]
100000000010DBL_N0[5]
100000000100DBL_S2[6]
100000001000DBL_S2[7]
100000010000DBL_E1[5]
100000100000DBL_W1[6]
100001000000DBL_W2[5]
100010000000DBL_N1[5]
virtex2 INT_DCM_V2 switchbox INT muxes IMUX_G2_DATA[2]
BitsDestination
MAIN[9][47]MAIN[9][44]MAIN[8][44]MAIN[8][47]MAIN[10][46]MAIN[10][44]MAIN[11][44]MAIN[11][46]MAIN[13][44]MAIN[13][46]MAIN[12][44]MAIN[12][46]IMUX_G2_DATA[2]
Source
000000000000PULLUP
000100000001OMUX_WS1
000100000010OMUX_E8
000100000100OMUX_SE3
000100001000OMUX_W9
000100010000DBL_S1[5]
000100100000IMUX_G3_FAN[0]
000101000000DBL_N2[5]
000110000000IMUX_G0_FAN[0]
001000000001DBL_E0[5]
001000000010OMUX_S3
001000000100DBL_W0[6]
001000001000DBL_S0[6]
001000010000DBL_N1[6]
001000100000DBL_S1[7]
001001000000DBL_W2[6]
001010000000DBL_S1[6]
010000000001DBL_E2[6]
010000000010DBL_E2[5]
010000000100DBL_E2[7]
010000001000DBL_E0[7]
010000010000DBL_W1[5]
010000100000DBL_E1[7]
010001000000DBL_E1[6]
010010000000DBL_N2[6]
100000000001DBL_S2[5]
100000000010DBL_N0[5]
100000000100DBL_S2[6]
100000001000DBL_S2[7]
100000010000DBL_E1[5]
100000100000DBL_W1[6]
100001000000DBL_W2[5]
100010000000DBL_N1[5]
virtex2 INT_DCM_V2 switchbox INT muxes IMUX_G2_DATA[3]
BitsDestination
MAIN[9][46]MAIN[9][45]MAIN[8][45]MAIN[8][46]MAIN[10][47]MAIN[10][45]MAIN[11][45]MAIN[11][47]MAIN[13][45]MAIN[13][47]MAIN[12][45]MAIN[12][47]IMUX_G2_DATA[3]
Source
000000000000PULLUP
000100000001OMUX_WS1
000100000010OMUX_E8
000100000100OMUX_SE3
000100001000OMUX_W9
000100010000DBL_S1[5]
000100100000IMUX_G3_FAN[0]
000101000000DBL_N2[5]
000110000000IMUX_G0_FAN[0]
001000000001DBL_E0[5]
001000000010OMUX_S3
001000000100DBL_W0[6]
001000001000DBL_S0[6]
001000010000DBL_N1[6]
001000100000DBL_S1[7]
001001000000DBL_W2[6]
001010000000DBL_S1[6]
010000000001DBL_E2[6]
010000000010DBL_E2[5]
010000000100DBL_E2[7]
010000001000DBL_E0[7]
010000010000DBL_W1[5]
010000100000DBL_E1[7]
010001000000DBL_E1[6]
010010000000DBL_N2[6]
100000000001DBL_S2[5]
100000000010DBL_N0[5]
100000000100DBL_S2[6]
100000001000DBL_S2[7]
100000010000DBL_E1[5]
100000100000DBL_W1[6]
100001000000DBL_W2[5]
100010000000DBL_N1[5]
virtex2 INT_DCM_V2 switchbox INT muxes IMUX_G2_DATA[4]
BitsDestination
MAIN[9][48]MAIN[9][51]MAIN[8][51]MAIN[8][48]MAIN[10][49]MAIN[10][51]MAIN[11][51]MAIN[11][49]MAIN[13][51]MAIN[13][49]MAIN[12][51]MAIN[12][49]IMUX_G2_DATA[4]
Source
000000000000PULLUP
000100000001OMUX_WS1
000100000010OMUX_E8
000100000100OMUX_SE3
000100001000OMUX_W9
000100010000DBL_S1[5]
000100100000IMUX_G3_FAN[0]
000101000000DBL_N2[5]
000110000000IMUX_G0_FAN[0]
001000000001DBL_E0[5]
001000000010OMUX_S3
001000000100DBL_W0[6]
001000001000DBL_S0[6]
001000010000DBL_N1[6]
001000100000DBL_S1[7]
001001000000DBL_W2[6]
001010000000DBL_S1[6]
010000000001DBL_E2[6]
010000000010DBL_E2[5]
010000000100DBL_E2[7]
010000001000DBL_E0[7]
010000010000DBL_W1[5]
010000100000DBL_E1[7]
010001000000DBL_E1[6]
010010000000DBL_N2[6]
100000000001DBL_S2[5]
100000000010DBL_N0[5]
100000000100DBL_S2[6]
100000001000DBL_S2[7]
100000010000DBL_E1[5]
100000100000DBL_W1[6]
100001000000DBL_W2[5]
100010000000DBL_N1[5]
virtex2 INT_DCM_V2 switchbox INT muxes IMUX_G2_DATA[5]
BitsDestination
MAIN[9][49]MAIN[9][50]MAIN[8][50]MAIN[8][49]MAIN[10][48]MAIN[10][50]MAIN[11][50]MAIN[11][48]MAIN[13][50]MAIN[13][48]MAIN[12][50]MAIN[12][48]IMUX_G2_DATA[5]
Source
000000000000PULLUP
000100000001OMUX_WS1
000100000010OMUX_E8
000100000100OMUX_SE3
000100001000OMUX_W9
000100010000DBL_S1[5]
000100100000IMUX_G3_FAN[0]
000101000000DBL_N2[5]
000110000000IMUX_G0_FAN[0]
001000000001DBL_E0[5]
001000000010OMUX_S3
001000000100DBL_W0[6]
001000001000DBL_S0[6]
001000010000DBL_N1[6]
001000100000DBL_S1[7]
001001000000DBL_W2[6]
001010000000DBL_S1[6]
010000000001DBL_E2[6]
010000000010DBL_E2[5]
010000000100DBL_E2[7]
010000001000DBL_E0[7]
010000010000DBL_W1[5]
010000100000DBL_E1[7]
010001000000DBL_E1[6]
010010000000DBL_N2[6]
100000000001DBL_S2[5]
100000000010DBL_N0[5]
100000000100DBL_S2[6]
100000001000DBL_S2[7]
100000010000DBL_E1[5]
100000100000DBL_W1[6]
100001000000DBL_W2[5]
100010000000DBL_N1[5]
virtex2 INT_DCM_V2 switchbox INT muxes IMUX_G2_DATA[6]
BitsDestination
MAIN[9][55]MAIN[9][52]MAIN[8][52]MAIN[8][55]MAIN[10][54]MAIN[10][52]MAIN[11][52]MAIN[11][54]MAIN[13][52]MAIN[13][54]MAIN[12][52]MAIN[12][54]IMUX_G2_DATA[6]
Source
000000000000PULLUP
000100000001OMUX_WS1
000100000010OMUX_E8
000100000100OMUX_SE3
000100001000OMUX_W9
000100010000DBL_S1[5]
000100100000IMUX_G3_FAN[0]
000101000000DBL_N2[5]
000110000000IMUX_G0_FAN[0]
001000000001DBL_E0[5]
001000000010OMUX_S3
001000000100DBL_W0[6]
001000001000DBL_S0[6]
001000010000DBL_N1[6]
001000100000DBL_S1[7]
001001000000DBL_W2[6]
001010000000DBL_S1[6]
010000000001DBL_E2[6]
010000000010DBL_E2[5]
010000000100DBL_E2[7]
010000001000DBL_E0[7]
010000010000DBL_W1[5]
010000100000DBL_E1[7]
010001000000DBL_E1[6]
010010000000DBL_N2[6]
100000000001DBL_S2[5]
100000000010DBL_N0[5]
100000000100DBL_S2[6]
100000001000DBL_S2[7]
100000010000DBL_E1[5]
100000100000DBL_W1[6]
100001000000DBL_W2[5]
100010000000DBL_N1[5]
virtex2 INT_DCM_V2 switchbox INT muxes IMUX_G2_DATA[7]
BitsDestination
MAIN[9][54]MAIN[9][53]MAIN[8][53]MAIN[8][54]MAIN[10][55]MAIN[10][53]MAIN[11][53]MAIN[11][55]MAIN[13][53]MAIN[13][55]MAIN[12][53]MAIN[12][55]IMUX_G2_DATA[7]
Source
000000000000PULLUP
000100000001OMUX_WS1
000100000010OMUX_E8
000100000100OMUX_SE3
000100001000OMUX_W9
000100010000DBL_S1[5]
000100100000IMUX_G3_FAN[0]
000101000000DBL_N2[5]
000110000000IMUX_G0_FAN[0]
001000000001DBL_E0[5]
001000000010OMUX_S3
001000000100DBL_W0[6]
001000001000DBL_S0[6]
001000010000DBL_N1[6]
001000100000DBL_S1[7]
001001000000DBL_W2[6]
001010000000DBL_S1[6]
010000000001DBL_E2[6]
010000000010DBL_E2[5]
010000000100DBL_E2[7]
010000001000DBL_E0[7]
010000010000DBL_W1[5]
010000100000DBL_E1[7]
010001000000DBL_E1[6]
010010000000DBL_N2[6]
100000000001DBL_S2[5]
100000000010DBL_N0[5]
100000000100DBL_S2[6]
100000001000DBL_S2[7]
100000010000DBL_E1[5]
100000100000DBL_W1[6]
100001000000DBL_W2[5]
100010000000DBL_N1[5]
virtex2 INT_DCM_V2 switchbox INT muxes IMUX_G3_FAN[0]
BitsDestination
MAIN[9][63]MAIN[9][60]MAIN[8][60]MAIN[8][63]MAIN[10][62]MAIN[10][60]MAIN[11][62]MAIN[11][60]MAIN[13][62]MAIN[12][62]MAIN[12][60]MAIN[13][60]IMUX_G3_FAN[0]
Source
000000000000PULLUP
000100000001OMUX_S5
000100000010OMUX_W14
000100000100OMUX_ES7
000100001000OMUX_E13
000100010000IMUX_G1_FAN[1]
000100100000DBL_S1[8]
000101000000DBL_E1[9]
000110000000IMUX_G2_FAN[1]
001000000001DBL_W0[8]
001000000010OMUX_SW5
001000000100DBL_S0[8]
001000001000DBL_E0[9]
001000010000DBL_W1[7]
001000100000DBL_N1[9]
001001000000DBL_W2[9]
001010000000DBL_N2[9]
010000000001DBL_N0[7]
010000000010DBL_E2[9]
010000000100DBL_E2[8]
010000001000DBL_W2[8]
010000010000DBL_N1[7]
010000100000DBL_W1[8]
010001000000DBL_W1[9]
010010000000DBL_N2[8]
100000000001DBL_W2[7]
100000000010DBL_N0[9]
100000000100DBL_S2[9]
100000001000DBL_S2[8]
100000010000DBL_S1[9]
100000100000DBL_E1[8]
100001000000DBL_N2[7]
100010000000DBL_N1[8]
virtex2 INT_DCM_V2 switchbox INT muxes IMUX_G3_FAN[1]
BitsDestination
MAIN[9][62]MAIN[9][61]MAIN[8][61]MAIN[8][62]MAIN[10][63]MAIN[10][61]MAIN[11][63]MAIN[11][61]MAIN[13][63]MAIN[12][63]MAIN[12][61]MAIN[13][61]IMUX_G3_FAN[1]
Source
000000000000PULLUP
000100000001OMUX_S5
000100000010OMUX_W14
000100000100OMUX_ES7
000100001000OMUX_E13
000100010000IMUX_G1_FAN[1]
000100100000DBL_S1[8]
000101000000DBL_E1[9]
000110000000IMUX_G2_FAN[1]
001000000001DBL_W0[8]
001000000010OMUX_SW5
001000000100DBL_S0[8]
001000001000DBL_E0[9]
001000010000DBL_W1[7]
001000100000DBL_N1[9]
001001000000DBL_W2[9]
001010000000DBL_N2[9]
010000000001DBL_N0[7]
010000000010DBL_E2[9]
010000000100DBL_E2[8]
010000001000DBL_W2[8]
010000010000DBL_N1[7]
010000100000DBL_W1[8]
010001000000DBL_W1[9]
010010000000DBL_N2[8]
100000000001DBL_W2[7]
100000000010DBL_N0[9]
100000000100DBL_S2[9]
100000001000DBL_S2[8]
100000010000DBL_S1[9]
100000100000DBL_E1[8]
100001000000DBL_N2[7]
100010000000DBL_N1[8]
virtex2 INT_DCM_V2 switchbox INT muxes IMUX_G3_DATA[0]
BitsDestination
MAIN[9][79]MAIN[9][76]MAIN[8][76]MAIN[8][79]MAIN[10][78]MAIN[10][76]MAIN[11][78]MAIN[11][76]MAIN[13][78]MAIN[12][78]MAIN[12][76]MAIN[13][76]IMUX_G3_DATA[0]
Source
000000000000PULLUP
000100000001OMUX_S5
000100000010OMUX_W14
000100000100OMUX_ES7
000100001000OMUX_E13
000100010000IMUX_G1_FAN[1]
000100100000DBL_S1[8]
000101000000DBL_E1[9]
000110000000IMUX_G2_FAN[1]
001000000001DBL_W0[8]
001000000010OMUX_SW5
001000000100DBL_S0[8]
001000001000DBL_E0[9]
001000010000DBL_W1[7]
001000100000DBL_N1[9]
001001000000DBL_W2[9]
001010000000DBL_N2[9]
010000000001DBL_N0[7]
010000000010DBL_E2[9]
010000000100DBL_E2[8]
010000001000DBL_W2[8]
010000010000DBL_N1[7]
010000100000DBL_W1[8]
010001000000DBL_W1[9]
010010000000DBL_N2[8]
100000000001DBL_W2[7]
100000000010DBL_N0[9]
100000000100DBL_S2[9]
100000001000DBL_S2[8]
100000010000DBL_S1[9]
100000100000DBL_E1[8]
100001000000DBL_N2[7]
100010000000DBL_N1[8]
virtex2 INT_DCM_V2 switchbox INT muxes IMUX_G3_DATA[1]
BitsDestination
MAIN[9][78]MAIN[9][77]MAIN[8][77]MAIN[8][78]MAIN[10][79]MAIN[10][77]MAIN[11][79]MAIN[11][77]MAIN[13][79]MAIN[12][79]MAIN[12][77]MAIN[13][77]IMUX_G3_DATA[1]
Source
000000000000PULLUP
000100000001OMUX_S5
000100000010OMUX_W14
000100000100OMUX_ES7
000100001000OMUX_E13
000100010000IMUX_G1_FAN[1]
000100100000DBL_S1[8]
000101000000DBL_E1[9]
000110000000IMUX_G2_FAN[1]
001000000001DBL_W0[8]
001000000010OMUX_SW5
001000000100DBL_S0[8]
001000001000DBL_E0[9]
001000010000DBL_W1[7]
001000100000DBL_N1[9]
001001000000DBL_W2[9]
001010000000DBL_N2[9]
010000000001DBL_N0[7]
010000000010DBL_E2[9]
010000000100DBL_E2[8]
010000001000DBL_W2[8]
010000010000DBL_N1[7]
010000100000DBL_W1[8]
010001000000DBL_W1[9]
010010000000DBL_N2[8]
100000000001DBL_W2[7]
100000000010DBL_N0[9]
100000000100DBL_S2[9]
100000001000DBL_S2[8]
100000010000DBL_S1[9]
100000100000DBL_E1[8]
100001000000DBL_N2[7]
100010000000DBL_N1[8]
virtex2 INT_DCM_V2 switchbox INT muxes IMUX_G3_DATA[2]
BitsDestination
MAIN[9][72]MAIN[9][75]MAIN[8][75]MAIN[8][72]MAIN[10][73]MAIN[10][75]MAIN[11][73]MAIN[11][75]MAIN[13][73]MAIN[12][73]MAIN[12][75]MAIN[13][75]IMUX_G3_DATA[2]
Source
000000000000PULLUP
000100000001OMUX_S5
000100000010OMUX_W14
000100000100OMUX_ES7
000100001000OMUX_E13
000100010000IMUX_G1_FAN[1]
000100100000DBL_S1[8]
000101000000DBL_E1[9]
000110000000IMUX_G2_FAN[1]
001000000001DBL_W0[8]
001000000010OMUX_SW5
001000000100DBL_S0[8]
001000001000DBL_E0[9]
001000010000DBL_W1[7]
001000100000DBL_N1[9]
001001000000DBL_W2[9]
001010000000DBL_N2[9]
010000000001DBL_N0[7]
010000000010DBL_E2[9]
010000000100DBL_E2[8]
010000001000DBL_W2[8]
010000010000DBL_N1[7]
010000100000DBL_W1[8]
010001000000DBL_W1[9]
010010000000DBL_N2[8]
100000000001DBL_W2[7]
100000000010DBL_N0[9]
100000000100DBL_S2[9]
100000001000DBL_S2[8]
100000010000DBL_S1[9]
100000100000DBL_E1[8]
100001000000DBL_N2[7]
100010000000DBL_N1[8]
virtex2 INT_DCM_V2 switchbox INT muxes IMUX_G3_DATA[3]
BitsDestination
MAIN[9][73]MAIN[9][74]MAIN[8][74]MAIN[8][73]MAIN[10][72]MAIN[10][74]MAIN[11][72]MAIN[11][74]MAIN[13][72]MAIN[12][72]MAIN[12][74]MAIN[13][74]IMUX_G3_DATA[3]
Source
000000000000PULLUP
000100000001OMUX_S5
000100000010OMUX_W14
000100000100OMUX_ES7
000100001000OMUX_E13
000100010000IMUX_G1_FAN[1]
000100100000DBL_S1[8]
000101000000DBL_E1[9]
000110000000IMUX_G2_FAN[1]
001000000001DBL_W0[8]
001000000010OMUX_SW5
001000000100DBL_S0[8]
001000001000DBL_E0[9]
001000010000DBL_W1[7]
001000100000DBL_N1[9]
001001000000DBL_W2[9]
001010000000DBL_N2[9]
010000000001DBL_N0[7]
010000000010DBL_E2[9]
010000000100DBL_E2[8]
010000001000DBL_W2[8]
010000010000DBL_N1[7]
010000100000DBL_W1[8]
010001000000DBL_W1[9]
010010000000DBL_N2[8]
100000000001DBL_W2[7]
100000000010DBL_N0[9]
100000000100DBL_S2[9]
100000001000DBL_S2[8]
100000010000DBL_S1[9]
100000100000DBL_E1[8]
100001000000DBL_N2[7]
100010000000DBL_N1[8]
virtex2 INT_DCM_V2 switchbox INT muxes IMUX_G3_DATA[4]
BitsDestination
MAIN[9][71]MAIN[9][68]MAIN[8][68]MAIN[8][71]MAIN[10][70]MAIN[10][68]MAIN[11][70]MAIN[11][68]MAIN[13][70]MAIN[12][70]MAIN[12][68]MAIN[13][68]IMUX_G3_DATA[4]
Source
000000000000PULLUP
000100000001OMUX_S5
000100000010OMUX_W14
000100000100OMUX_ES7
000100001000OMUX_E13
000100010000IMUX_G1_FAN[1]
000100100000DBL_S1[8]
000101000000DBL_E1[9]
000110000000IMUX_G2_FAN[1]
001000000001DBL_W0[8]
001000000010OMUX_SW5
001000000100DBL_S0[8]
001000001000DBL_E0[9]
001000010000DBL_W1[7]
001000100000DBL_N1[9]
001001000000DBL_W2[9]
001010000000DBL_N2[9]
010000000001DBL_N0[7]
010000000010DBL_E2[9]
010000000100DBL_E2[8]
010000001000DBL_W2[8]
010000010000DBL_N1[7]
010000100000DBL_W1[8]
010001000000DBL_W1[9]
010010000000DBL_N2[8]
100000000001DBL_W2[7]
100000000010DBL_N0[9]
100000000100DBL_S2[9]
100000001000DBL_S2[8]
100000010000DBL_S1[9]
100000100000DBL_E1[8]
100001000000DBL_N2[7]
100010000000DBL_N1[8]
virtex2 INT_DCM_V2 switchbox INT muxes IMUX_G3_DATA[5]
BitsDestination
MAIN[9][70]MAIN[9][69]MAIN[8][69]MAIN[8][70]MAIN[10][71]MAIN[10][69]MAIN[11][71]MAIN[11][69]MAIN[13][71]MAIN[12][71]MAIN[12][69]MAIN[13][69]IMUX_G3_DATA[5]
Source
000000000000PULLUP
000100000001OMUX_S5
000100000010OMUX_W14
000100000100OMUX_ES7
000100001000OMUX_E13
000100010000IMUX_G1_FAN[1]
000100100000DBL_S1[8]
000101000000DBL_E1[9]
000110000000IMUX_G2_FAN[1]
001000000001DBL_W0[8]
001000000010OMUX_SW5
001000000100DBL_S0[8]
001000001000DBL_E0[9]
001000010000DBL_W1[7]
001000100000DBL_N1[9]
001001000000DBL_W2[9]
001010000000DBL_N2[9]
010000000001DBL_N0[7]
010000000010DBL_E2[9]
010000000100DBL_E2[8]
010000001000DBL_W2[8]
010000010000DBL_N1[7]
010000100000DBL_W1[8]
010001000000DBL_W1[9]
010010000000DBL_N2[8]
100000000001DBL_W2[7]
100000000010DBL_N0[9]
100000000100DBL_S2[9]
100000001000DBL_S2[8]
100000010000DBL_S1[9]
100000100000DBL_E1[8]
100001000000DBL_N2[7]
100010000000DBL_N1[8]
virtex2 INT_DCM_V2 switchbox INT muxes IMUX_G3_DATA[6]
BitsDestination
MAIN[9][64]MAIN[9][67]MAIN[8][67]MAIN[8][64]MAIN[10][65]MAIN[10][67]MAIN[11][65]MAIN[11][67]MAIN[13][65]MAIN[12][65]MAIN[12][67]MAIN[13][67]IMUX_G3_DATA[6]
Source
000000000000PULLUP
000100000001OMUX_S5
000100000010OMUX_W14
000100000100OMUX_ES7
000100001000OMUX_E13
000100010000IMUX_G1_FAN[1]
000100100000DBL_S1[8]
000101000000DBL_E1[9]
000110000000IMUX_G2_FAN[1]
001000000001DBL_W0[8]
001000000010OMUX_SW5
001000000100DBL_S0[8]
001000001000DBL_E0[9]
001000010000DBL_W1[7]
001000100000DBL_N1[9]
001001000000DBL_W2[9]
001010000000DBL_N2[9]
010000000001DBL_N0[7]
010000000010DBL_E2[9]
010000000100DBL_E2[8]
010000001000DBL_W2[8]
010000010000DBL_N1[7]
010000100000DBL_W1[8]
010001000000DBL_W1[9]
010010000000DBL_N2[8]
100000000001DBL_W2[7]
100000000010DBL_N0[9]
100000000100DBL_S2[9]
100000001000DBL_S2[8]
100000010000DBL_S1[9]
100000100000DBL_E1[8]
100001000000DBL_N2[7]
100010000000DBL_N1[8]
virtex2 INT_DCM_V2 switchbox INT muxes IMUX_G3_DATA[7]
BitsDestination
MAIN[9][65]MAIN[9][66]MAIN[8][66]MAIN[8][65]MAIN[10][64]MAIN[10][66]MAIN[11][64]MAIN[11][66]MAIN[13][64]MAIN[12][64]MAIN[12][66]MAIN[13][66]IMUX_G3_DATA[7]
Source
000000000000PULLUP
000100000001OMUX_S5
000100000010OMUX_W14
000100000100OMUX_ES7
000100001000OMUX_E13
000100010000IMUX_G1_FAN[1]
000100100000DBL_S1[8]
000101000000DBL_E1[9]
000110000000IMUX_G2_FAN[1]
001000000001DBL_W0[8]
001000000010OMUX_SW5
001000000100DBL_S0[8]
001000001000DBL_E0[9]
001000010000DBL_W1[7]
001000100000DBL_N1[9]
001001000000DBL_W2[9]
001010000000DBL_N2[9]
010000000001DBL_N0[7]
010000000010DBL_E2[9]
010000000100DBL_E2[8]
010000001000DBL_W2[8]
010000010000DBL_N1[7]
010000100000DBL_W1[8]
010001000000DBL_W1[9]
010010000000DBL_N2[8]
100000000001DBL_W2[7]
100000000010DBL_N0[9]
100000000100DBL_S2[9]
100000001000DBL_S2[8]
100000010000DBL_S1[9]
100000100000DBL_E1[8]
100001000000DBL_N2[7]
100010000000DBL_N1[8]

Bitstream

virtex2 INT_DCM_V2 rect MAIN
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21
B79 - - - - INT: mux IMUX_CE[2] bit 5 INT: mux IMUX_CE[3] bit 1 INT: mux OMUX[14] bit 0 INT: mux OMUX[15] bit 6 INT: mux IMUX_G3_DATA[0] bit 8 INT: mux IMUX_G3_DATA[0] bit 11 INT: mux IMUX_G3_DATA[1] bit 7 INT: mux IMUX_G3_DATA[1] bit 5 INT: mux IMUX_G3_DATA[1] bit 2 INT: mux IMUX_G3_DATA[1] bit 3 INT: mux DBL_E0[9] bit 0 INT: mux DBL_W0[9] bit 7 INT: mux DBL_E0[9] bit 5 INT: mux DBL_E0[9] bit 7 INT: mux HEX_W0[9] bit 0 INT: mux HEX_W0[9] bit 3 INT: mux HEX_W0[9] bit 4 INT: mux LV[18] bit 1
B78 - - - - INT: !invert IMUX_CE_OPTINV[3] ← IMUX_CE[3] INT: mux IMUX_CE[3] bit 3 INT: mux OMUX[15] bit 9 INT: mux OMUX[15] bit 7 INT: mux IMUX_G3_DATA[1] bit 8 INT: mux IMUX_G3_DATA[1] bit 11 INT: mux IMUX_G3_DATA[0] bit 7 INT: mux IMUX_G3_DATA[0] bit 5 INT: mux IMUX_G3_DATA[0] bit 2 INT: mux IMUX_G3_DATA[0] bit 3 INT: mux DBL_E0[9] bit 1 INT: mux DBL_W0[9] bit 4 INT: mux DBL_W0[9] bit 3 INT: mux DBL_W0[9] bit 0 INT: mux HEX_E0[9] bit 1 INT: mux HEX_E0[9] bit 3 INT: mux HEX_E0[9] bit 5 INT: mux HEX_W0[9] bit 6
B77 - - - - INT: mux IMUX_CE[3] bit 0 INT: mux IMUX_CE[3] bit 2 INT: mux OMUX[15] bit 0 INT: mux OMUX[15] bit 8 INT: mux IMUX_G3_DATA[1] bit 9 INT: mux IMUX_G3_DATA[1] bit 10 INT: mux IMUX_G3_DATA[1] bit 6 INT: mux IMUX_G3_DATA[1] bit 4 INT: mux IMUX_G3_DATA[1] bit 1 INT: mux IMUX_G3_DATA[1] bit 0 INT: mux DBL_W0[9] bit 5 INT: mux DBL_E0[9] bit 3 INT: mux DBL_W0[9] bit 2 INT: mux DBL_W0[9] bit 1 INT: mux HEX_W0[9] bit 2 INT: mux HEX_W0[9] bit 1 INT: mux HEX_E0[9] bit 6 INT: mux LV[18] bit 3
B76 - - - - INT: mux IMUX_CE[3] bit 4 INT: mux IMUX_CE[3] bit 5 INT: mux OMUX[14] bit 1 INT: mux OMUX[15] bit 1 INT: mux IMUX_G3_DATA[0] bit 9 INT: mux IMUX_G3_DATA[0] bit 10 INT: mux IMUX_G3_DATA[0] bit 6 INT: mux IMUX_G3_DATA[0] bit 4 INT: mux IMUX_G3_DATA[0] bit 1 INT: mux IMUX_G3_DATA[0] bit 0 INT: mux DBL_W0[9] bit 6 INT: mux DBL_E0[9] bit 2 INT: mux DBL_E0[9] bit 4 INT: mux DBL_E0[9] bit 6 INT: mux HEX_E0[9] bit 2 INT: mux HEX_E0[9] bit 0 INT: mux HEX_E0[9] bit 4 INT: mux HEX_W0[9] bit 5
B75 - - - - INT: mux IMUX_CE[2] bit 4 INT: mux IMUX_CE[2] bit 7 INT: mux OMUX[15] bit 2 INT: mux OMUX[14] bit 2 INT: mux IMUX_G3_DATA[2] bit 9 INT: mux IMUX_G3_DATA[2] bit 10 INT: mux IMUX_G3_DATA[2] bit 6 INT: mux IMUX_G3_DATA[2] bit 4 INT: mux IMUX_G3_DATA[2] bit 1 INT: mux IMUX_G3_DATA[2] bit 0 INT: mux DBL_S0[9] bit 4 INT: mux DBL_N0[9] bit 2 INT: mux DBL_S0[9] bit 0 INT: mux DBL_S0[9] bit 3 INT: mux HEX_N0[9] bit 1 INT: mux HEX_N0[9] bit 3 INT: mux HEX_N0[9] bit 5 INT: mux LV[6] bit 0
B74 - - - - INT: mux IMUX_CE[3] bit 7 INT: mux IMUX_CE[3] bit 6 INT: mux OMUX[15] bit 3 INT: mux OMUX[14] bit 3 INT: mux IMUX_G3_DATA[3] bit 9 INT: mux IMUX_G3_DATA[3] bit 10 INT: mux IMUX_G3_DATA[3] bit 6 INT: mux IMUX_G3_DATA[3] bit 4 INT: mux IMUX_G3_DATA[3] bit 1 INT: mux IMUX_G3_DATA[3] bit 0 INT: mux DBL_S0[9] bit 5 INT: mux DBL_N0[9] bit 0 INT: mux DBL_N0[9] bit 7 INT: mux DBL_N0[9] bit 5 INT: mux HEX_S0[9] bit 1 INT: mux HEX_S0[9] bit 2 INT: mux HEX_S0[9] bit 4 INT: mux HEX_N0[9] bit 4
B73 - - - - INT: mux IMUX_CE[2] bit 0 INT: mux IMUX_CE[2] bit 1 INT: mux OMUX[14] bit 4 INT: mux OMUX[15] bit 4 INT: mux IMUX_G3_DATA[3] bit 8 INT: mux IMUX_G3_DATA[3] bit 11 INT: mux IMUX_G3_DATA[2] bit 7 INT: mux IMUX_G3_DATA[2] bit 5 INT: mux IMUX_G3_DATA[2] bit 2 INT: mux IMUX_G3_DATA[2] bit 3 INT: mux DBL_N0[9] bit 1 INT: mux DBL_S0[9] bit 6 INT: mux DBL_N0[9] bit 6 INT: mux DBL_N0[9] bit 4 INT: mux HEX_N0[9] bit 2 INT: mux HEX_N0[9] bit 0 INT: mux HEX_S0[9] bit 5 INT: mux LV[6] bit 6
B72 - - - - INT: !invert IMUX_CE_OPTINV[2] ← IMUX_CE[2] INT: mux IMUX_CE[2] bit 3 INT: mux OMUX[15] bit 5 INT: mux OMUX[14] bit 8 INT: mux IMUX_G3_DATA[2] bit 8 INT: mux IMUX_G3_DATA[2] bit 11 INT: mux IMUX_G3_DATA[3] bit 7 INT: mux IMUX_G3_DATA[3] bit 5 INT: mux IMUX_G3_DATA[3] bit 2 INT: mux IMUX_G3_DATA[3] bit 3 INT: mux DBL_N0[9] bit 3 INT: mux DBL_S0[9] bit 7 INT: mux DBL_S0[9] bit 1 INT: mux DBL_S0[9] bit 2 INT: mux HEX_S0[9] bit 3 INT: mux HEX_S0[9] bit 0 INT: mux HEX_S0[9] bit 6 INT: mux HEX_N0[9] bit 6
B71 - - - - INT: mux IMUX_CE[2] bit 6 INT: mux IMUX_CE[2] bit 2 INT: mux OMUX[14] bit 9 INT: mux OMUX[14] bit 7 INT: mux IMUX_G3_DATA[4] bit 8 INT: mux IMUX_G3_DATA[4] bit 11 INT: mux IMUX_G3_DATA[5] bit 7 INT: mux IMUX_G3_DATA[5] bit 5 INT: mux IMUX_G3_DATA[5] bit 2 INT: mux IMUX_G3_DATA[5] bit 3 INT: mux DBL_E0[8] bit 2 INT: mux DBL_W0[8] bit 3 INT: mux DBL_E0[8] bit 4 INT: mux DBL_E0[8] bit 7 INT: mux HEX_E0[8] bit 0 INT: mux HEX_E0[8] bit 3 INT: mux HEX_E0[8] bit 4 INT: mux LV[6] bit 2
B70 - - - - - - INT: mux OMUX[14] bit 5 INT: mux OMUX[14] bit 6 INT: mux IMUX_G3_DATA[5] bit 8 INT: mux IMUX_G3_DATA[5] bit 11 INT: mux IMUX_G3_DATA[4] bit 7 INT: mux IMUX_G3_DATA[4] bit 5 INT: mux IMUX_G3_DATA[4] bit 2 INT: mux IMUX_G3_DATA[4] bit 3 INT: mux DBL_E0[8] bit 0 INT: mux DBL_W0[8] bit 0 INT: mux DBL_W0[8] bit 7 INT: mux DBL_W0[8] bit 4 INT: mux HEX_W0[8] bit 0 INT: mux HEX_W0[8] bit 3 INT: mux HEX_W0[8] bit 4 INT: mux HEX_E0[8] bit 5
B69 - - - - - - INT: mux OMUX[12] bit 4 INT: mux OMUX[13] bit 6 INT: mux IMUX_G3_DATA[5] bit 9 INT: mux IMUX_G3_DATA[5] bit 10 INT: mux IMUX_G3_DATA[5] bit 6 INT: mux IMUX_G3_DATA[5] bit 4 INT: mux IMUX_G3_DATA[5] bit 1 INT: mux IMUX_G3_DATA[5] bit 0 INT: mux DBL_W0[8] bit 2 INT: mux DBL_E0[8] bit 3 INT: mux DBL_W0[8] bit 6 INT: mux DBL_W0[8] bit 5 INT: mux HEX_E0[8] bit 2 INT: mux HEX_E0[8] bit 1 INT: mux HEX_W0[8] bit 5 INT: mux LV[6] bit 3
B68 - - - - - - INT: mux OMUX[13] bit 9 INT: mux OMUX[13] bit 7 INT: mux IMUX_G3_DATA[4] bit 9 INT: mux IMUX_G3_DATA[4] bit 10 INT: mux IMUX_G3_DATA[4] bit 6 INT: mux IMUX_G3_DATA[4] bit 4 INT: mux IMUX_G3_DATA[4] bit 1 INT: mux IMUX_G3_DATA[4] bit 0 INT: mux DBL_W0[8] bit 1 INT: mux DBL_E0[8] bit 1 INT: mux DBL_E0[8] bit 5 INT: mux DBL_E0[8] bit 6 INT: mux HEX_W0[8] bit 2 INT: mux HEX_W0[8] bit 1 INT: mux HEX_W0[8] bit 6 INT: mux HEX_E0[8] bit 6
B67 - - - - - - INT: mux OMUX[13] bit 4 INT: mux OMUX[13] bit 8 INT: mux IMUX_G3_DATA[6] bit 9 INT: mux IMUX_G3_DATA[6] bit 10 INT: mux IMUX_G3_DATA[6] bit 6 INT: mux IMUX_G3_DATA[6] bit 4 INT: mux IMUX_G3_DATA[6] bit 1 INT: mux IMUX_G3_DATA[6] bit 0 INT: mux DBL_S0[8] bit 3 INT: mux DBL_N0[8] bit 1 INT: mux DBL_S0[8] bit 5 INT: mux DBL_S0[8] bit 7 INT: mux HEX_S0[8] bit 1 INT: mux HEX_S0[8] bit 3 INT: mux HEX_S0[8] bit 5 INT: mux LV[18] bit 6
B66 - - - - - - INT: mux OMUX[12] bit 5 INT: mux OMUX[13] bit 5 INT: mux IMUX_G3_DATA[7] bit 9 INT: mux IMUX_G3_DATA[7] bit 10 INT: mux IMUX_G3_DATA[7] bit 6 INT: mux IMUX_G3_DATA[7] bit 4 INT: mux IMUX_G3_DATA[7] bit 1 INT: mux IMUX_G3_DATA[7] bit 0 INT: mux DBL_S0[8] bit 0 INT: mux DBL_N0[8] bit 0 INT: mux DBL_N0[8] bit 7 INT: mux DBL_N0[8] bit 5 INT: mux HEX_N0[8] bit 1 INT: mux HEX_N0[8] bit 2 INT: mux HEX_N0[8] bit 5 INT: mux HEX_S0[8] bit 4
B65 - - - - - - INT: mux OMUX[13] bit 0 INT: mux OMUX[12] bit 0 INT: mux IMUX_G3_DATA[7] bit 8 INT: mux IMUX_G3_DATA[7] bit 11 INT: mux IMUX_G3_DATA[6] bit 7 INT: mux IMUX_G3_DATA[6] bit 5 INT: mux IMUX_G3_DATA[6] bit 2 INT: mux IMUX_G3_DATA[6] bit 3 INT: mux DBL_N0[8] bit 3 INT: mux DBL_S0[8] bit 1 INT: mux DBL_N0[8] bit 6 INT: mux DBL_N0[8] bit 4 INT: mux HEX_S0[8] bit 2 INT: mux HEX_S0[8] bit 0 INT: mux HEX_N0[8] bit 4 INT: mux LV[6] bit 1
B64 - - - - - - INT: mux OMUX[13] bit 1 INT: mux OMUX[12] bit 1 INT: mux IMUX_G3_DATA[6] bit 8 INT: mux IMUX_G3_DATA[6] bit 11 INT: mux IMUX_G3_DATA[7] bit 7 INT: mux IMUX_G3_DATA[7] bit 5 INT: mux IMUX_G3_DATA[7] bit 2 INT: mux IMUX_G3_DATA[7] bit 3 INT: mux DBL_N0[8] bit 2 INT: mux DBL_S0[8] bit 2 INT: mux DBL_S0[8] bit 4 INT: mux DBL_S0[8] bit 6 INT: mux HEX_N0[8] bit 3 INT: mux HEX_N0[8] bit 0 INT: mux HEX_N0[8] bit 6 INT: mux HEX_S0[8] bit 6
B63 - - - - - - INT: mux OMUX[12] bit 2 INT: mux OMUX[13] bit 2 INT: mux IMUX_G3_FAN[0] bit 8 INT: mux IMUX_G3_FAN[0] bit 11 INT: mux IMUX_G3_FAN[1] bit 7 INT: mux IMUX_G3_FAN[1] bit 5 INT: mux IMUX_G3_FAN[1] bit 2 INT: mux IMUX_G3_FAN[1] bit 3 INT: mux DBL_E0[7] bit 2 INT: mux DBL_W0[7] bit 3 INT: mux DBL_E0[7] bit 4 INT: mux DBL_E0[7] bit 7 INT: mux HEX_W0[7] bit 0 INT: mux HEX_W0[7] bit 3 INT: mux HEX_W0[7] bit 4 INT: mux LV[18] bit 0
B62 - - - - INT: mux IMUX_DCM_CLK[2] bit 7 - INT: mux OMUX[13] bit 3 INT: mux OMUX[12] bit 8 INT: mux IMUX_G3_FAN[1] bit 8 INT: mux IMUX_G3_FAN[1] bit 11 INT: mux IMUX_G3_FAN[0] bit 7 INT: mux IMUX_G3_FAN[0] bit 5 INT: mux IMUX_G3_FAN[0] bit 2 INT: mux IMUX_G3_FAN[0] bit 3 INT: mux DBL_E0[7] bit 0 INT: mux DBL_W0[7] bit 0 INT: mux DBL_W0[7] bit 7 INT: mux DBL_W0[7] bit 4 INT: mux HEX_E0[7] bit 0 INT: mux HEX_E0[7] bit 3 INT: mux HEX_E0[7] bit 4 INT: mux HEX_W0[7] bit 5
B61 - - - - - - INT: mux OMUX[12] bit 9 INT: mux OMUX[12] bit 7 INT: mux IMUX_G3_FAN[1] bit 9 INT: mux IMUX_G3_FAN[1] bit 10 INT: mux IMUX_G3_FAN[1] bit 6 INT: mux IMUX_G3_FAN[1] bit 4 INT: mux IMUX_G3_FAN[1] bit 1 INT: mux IMUX_G3_FAN[1] bit 0 INT: mux DBL_W0[7] bit 2 INT: mux DBL_E0[7] bit 3 INT: mux DBL_W0[7] bit 6 INT: mux DBL_W0[7] bit 5 INT: mux HEX_W0[7] bit 2 INT: mux HEX_W0[7] bit 1 INT: mux HEX_E0[7] bit 5 INT: mux LV[6] bit 5
B60 - - - - - - INT: mux OMUX[12] bit 3 INT: mux OMUX[12] bit 6 INT: mux IMUX_G3_FAN[0] bit 9 INT: mux IMUX_G3_FAN[0] bit 10 INT: mux IMUX_G3_FAN[0] bit 6 INT: mux IMUX_G3_FAN[0] bit 4 INT: mux IMUX_G3_FAN[0] bit 1 INT: mux IMUX_G3_FAN[0] bit 0 INT: mux DBL_W0[7] bit 1 INT: mux DBL_E0[7] bit 1 INT: mux DBL_E0[7] bit 5 INT: mux DBL_E0[7] bit 6 INT: mux HEX_E0[7] bit 2 INT: mux HEX_E0[7] bit 1 INT: mux HEX_E0[7] bit 6 INT: mux HEX_W0[7] bit 6
B59 - - - - - - INT: mux OMUX[10] bit 5 INT: mux OMUX[11] bit 6 INT: mux IMUX_G2_FAN[0] bit 9 INT: mux IMUX_G2_FAN[0] bit 10 INT: mux IMUX_G2_FAN[0] bit 6 INT: mux IMUX_G2_FAN[0] bit 5 INT: mux IMUX_G2_FAN[0] bit 1 INT: mux IMUX_G2_FAN[0] bit 3 INT: mux DBL_S0[7] bit 4 INT: mux DBL_N0[7] bit 6 INT: mux DBL_S0[7] bit 1 INT: mux DBL_S0[7] bit 3 INT: mux HEX_N0[7] bit 1 INT: mux HEX_N0[7] bit 3 INT: mux HEX_N0[7] bit 6 INT: mux LV[18] bit 2
B58 - - - - INT: mux IMUX_DCM_CLK[2] bit 6 INT: mux IMUX_DCM_CLK[2] bit 4 INT: mux OMUX[11] bit 9 INT: mux OMUX[11] bit 7 INT: mux IMUX_G2_FAN[1] bit 9 INT: mux IMUX_G2_FAN[1] bit 10 INT: mux IMUX_G2_FAN[1] bit 6 INT: mux IMUX_G2_FAN[1] bit 5 INT: mux IMUX_G2_FAN[1] bit 1 INT: mux IMUX_G2_FAN[1] bit 3 INT: mux DBL_S0[7] bit 5 INT: mux DBL_N0[7] bit 5 INT: mux DBL_N0[7] bit 3 INT: mux DBL_N0[7] bit 1 INT: mux HEX_S0[7] bit 1 INT: mux HEX_S0[7] bit 2 INT: mux HEX_S0[7] bit 5 INT: mux HEX_N0[7] bit 5
B57 - - - - - - INT: mux OMUX[11] bit 5 INT: mux OMUX[11] bit 8 INT: mux IMUX_G2_FAN[1] bit 8 INT: mux IMUX_G2_FAN[1] bit 11 INT: mux IMUX_G2_FAN[0] bit 7 INT: mux IMUX_G2_FAN[0] bit 4 INT: mux IMUX_G2_FAN[0] bit 0 INT: mux IMUX_G2_FAN[0] bit 2 INT: mux DBL_N0[7] bit 4 INT: mux DBL_S0[7] bit 6 INT: mux DBL_N0[7] bit 2 INT: mux DBL_N0[7] bit 0 INT: mux HEX_N0[7] bit 2 INT: mux HEX_N0[7] bit 0 INT: mux HEX_S0[7] bit 6 INT: mux LV[18] bit 4
B56 - - - - INT: mux IMUX_DCM_CLK[2] bit 0 INT: mux IMUX_DCM_CLK[2] bit 5 INT: mux OMUX[10] bit 0 INT: mux OMUX[11] bit 0 INT: mux IMUX_G2_FAN[0] bit 8 INT: mux IMUX_G2_FAN[0] bit 11 INT: mux IMUX_G2_FAN[1] bit 7 INT: mux IMUX_G2_FAN[1] bit 4 INT: mux IMUX_G2_FAN[1] bit 0 INT: mux IMUX_G2_FAN[1] bit 2 INT: mux DBL_N0[7] bit 7 INT: mux DBL_S0[7] bit 7 INT: mux DBL_S0[7] bit 0 INT: mux DBL_S0[7] bit 2 INT: mux HEX_S0[7] bit 3 INT: mux HEX_S0[7] bit 0 INT: mux HEX_S0[7] bit 4 INT: mux HEX_N0[7] bit 4
B55 - - - - - - INT: mux OMUX[11] bit 1 INT: mux OMUX[10] bit 1 INT: mux IMUX_G2_DATA[6] bit 8 INT: mux IMUX_G2_DATA[6] bit 11 INT: mux IMUX_G2_DATA[7] bit 7 INT: mux IMUX_G2_DATA[7] bit 4 INT: mux IMUX_G2_DATA[7] bit 0 INT: mux IMUX_G2_DATA[7] bit 2 INT: mux DBL_E0[6] bit 1 INT: mux DBL_W0[6] bit 7 INT: mux DBL_E0[6] bit 5 INT: mux DBL_E0[6] bit 7 INT: mux HEX_E0[6] bit 1 INT: mux HEX_E0[6] bit 3 INT: mux HEX_E0[6] bit 5 INT: mux LV[6] bit 4
B54 - - - - INT: mux IMUX_DCM_CLK[2] bit 3 INT: mux IMUX_DCM_CLK[2] bit 1 INT: mux OMUX[11] bit 2 INT: mux OMUX[10] bit 2 INT: mux IMUX_G2_DATA[7] bit 8 INT: mux IMUX_G2_DATA[7] bit 11 INT: mux IMUX_G2_DATA[6] bit 7 INT: mux IMUX_G2_DATA[6] bit 4 INT: mux IMUX_G2_DATA[6] bit 0 INT: mux IMUX_G2_DATA[6] bit 2 INT: mux DBL_E0[6] bit 0 INT: mux DBL_W0[6] bit 5 INT: mux DBL_W0[6] bit 3 INT: mux DBL_W0[6] bit 0 INT: mux HEX_W0[6] bit 1 INT: mux HEX_W0[6] bit 3 INT: mux HEX_W0[6] bit 4 INT: mux HEX_E0[6] bit 4
B53 - - - - - INT: mux IMUX_DCM_CLK[2] bit 11 INT: mux OMUX[10] bit 3 INT: mux OMUX[11] bit 3 INT: mux IMUX_G2_DATA[7] bit 9 INT: mux IMUX_G2_DATA[7] bit 10 INT: mux IMUX_G2_DATA[7] bit 6 INT: mux IMUX_G2_DATA[7] bit 5 INT: mux IMUX_G2_DATA[7] bit 1 INT: mux IMUX_G2_DATA[7] bit 3 INT: mux DBL_W0[6] bit 4 INT: mux DBL_E0[6] bit 3 INT: mux DBL_W0[6] bit 2 INT: mux DBL_W0[6] bit 1 INT: mux HEX_E0[6] bit 2 INT: mux HEX_E0[6] bit 0 INT: mux HEX_W0[6] bit 5 INT: mux LV[18] bit 5
B52 - - - - INT: mux IMUX_DCM_CLK[2] bit 8 INT: mux IMUX_DCM_CLK[2] bit 10 INT: mux OMUX[11] bit 4 INT: mux OMUX[10] bit 8 INT: mux IMUX_G2_DATA[6] bit 9 INT: mux IMUX_G2_DATA[6] bit 10 INT: mux IMUX_G2_DATA[6] bit 6 INT: mux IMUX_G2_DATA[6] bit 5 INT: mux IMUX_G2_DATA[6] bit 1 INT: mux IMUX_G2_DATA[6] bit 3 INT: mux DBL_W0[6] bit 6 INT: mux DBL_E0[6] bit 2 INT: mux DBL_E0[6] bit 4 INT: mux DBL_E0[6] bit 6 INT: mux HEX_W0[6] bit 2 INT: mux HEX_W0[6] bit 0 INT: mux HEX_W0[6] bit 6 INT: mux HEX_E0[6] bit 6
B51 - - - - INT: invert IMUX_DCM_CLK_OPTINV[2] ← IMUX_DCM_CLK[2] - INT: mux OMUX[10] bit 9 INT: mux OMUX[10] bit 7 INT: mux IMUX_G2_DATA[4] bit 9 INT: mux IMUX_G2_DATA[4] bit 10 INT: mux IMUX_G2_DATA[4] bit 6 INT: mux IMUX_G2_DATA[4] bit 5 INT: mux IMUX_G2_DATA[4] bit 1 INT: mux IMUX_G2_DATA[4] bit 3 INT: mux DBL_S0[6] bit 3 INT: mux DBL_N0[6] bit 1 INT: mux DBL_S0[6] bit 4 INT: mux DBL_S0[6] bit 7 INT: mux HEX_S0[6] bit 0 INT: mux HEX_S0[6] bit 3 INT: mux HEX_S0[6] bit 4 INT: mux LH[0] bit 0
B50 - - - - INT: mux IMUX_DCM_CLK[2] bit 2 INT: mux IMUX_DCM_CLK[2] bit 9 INT: mux OMUX[10] bit 4 INT: mux OMUX[10] bit 6 INT: mux IMUX_G2_DATA[5] bit 9 INT: mux IMUX_G2_DATA[5] bit 10 INT: mux IMUX_G2_DATA[5] bit 6 INT: mux IMUX_G2_DATA[5] bit 5 INT: mux IMUX_G2_DATA[5] bit 1 INT: mux IMUX_G2_DATA[5] bit 3 INT: mux DBL_S0[6] bit 0 INT: mux DBL_N0[6] bit 0 INT: mux DBL_N0[6] bit 7 INT: mux DBL_N0[6] bit 4 INT: mux HEX_N0[6] bit 0 INT: mux HEX_N0[6] bit 2 INT: mux HEX_N0[6] bit 4 INT: mux HEX_S0[6] bit 5
B49 - - - - INT: mux IMUX_DCM_CLK[1] bit 2 INT: mux IMUX_DCM_CLK[1] bit 9 INT: mux OMUX[8] bit 0 INT: mux OMUX[9] bit 6 INT: mux IMUX_G2_DATA[5] bit 8 INT: mux IMUX_G2_DATA[5] bit 11 INT: mux IMUX_G2_DATA[4] bit 7 INT: mux IMUX_G2_DATA[4] bit 4 INT: mux IMUX_G2_DATA[4] bit 0 INT: mux IMUX_G2_DATA[4] bit 2 INT: mux DBL_N0[6] bit 3 INT: mux DBL_S0[6] bit 1 INT: mux DBL_N0[6] bit 6 INT: mux DBL_N0[6] bit 5 INT: mux HEX_S0[6] bit 2 INT: mux HEX_S0[6] bit 1 INT: mux HEX_N0[6] bit 5 INT: mux LH[0] bit 1
B48 - - - - INT: invert IMUX_DCM_CLK_OPTINV[1] ← IMUX_DCM_CLK[1] INT: mux IMUX_DCM_CLK[0] bit 2 INT: mux OMUX[9] bit 9 INT: mux OMUX[9] bit 7 INT: mux IMUX_G2_DATA[4] bit 8 INT: mux IMUX_G2_DATA[4] bit 11 INT: mux IMUX_G2_DATA[5] bit 7 INT: mux IMUX_G2_DATA[5] bit 4 INT: mux IMUX_G2_DATA[5] bit 0 INT: mux IMUX_G2_DATA[5] bit 2 INT: mux DBL_N0[6] bit 2 INT: mux DBL_S0[6] bit 2 INT: mux DBL_S0[6] bit 5 INT: mux DBL_S0[6] bit 6 INT: mux HEX_N0[6] bit 3 INT: mux HEX_N0[6] bit 1 INT: mux HEX_N0[6] bit 6 INT: mux HEX_S0[6] bit 6
B47 - - - - INT: mux IMUX_DCM_CLK[1] bit 8 INT: mux IMUX_DCM_CLK[1] bit 10 INT: mux OMUX[9] bit 0 INT: mux OMUX[9] bit 8 INT: mux IMUX_G2_DATA[2] bit 8 INT: mux IMUX_G2_DATA[2] bit 11 INT: mux IMUX_G2_DATA[3] bit 7 INT: mux IMUX_G2_DATA[3] bit 4 INT: mux IMUX_G2_DATA[3] bit 0 INT: mux IMUX_G2_DATA[3] bit 2 INT: mux DBL_E0[5] bit 2 INT: mux DBL_W0[5] bit 3 INT: mux DBL_E0[5] bit 4 INT: mux DBL_E0[5] bit 7 INT: mux HEX_W0[5] bit 1 INT: mux HEX_W0[5] bit 3 INT: mux HEX_W0[5] bit 5 INT: mux LH[0] bit 2
B46 - - - - INT: mux IMUX_DCM_CLK[0] bit 3 INT: mux IMUX_DCM_CLK[1] bit 11 INT: mux OMUX[8] bit 1 INT: mux OMUX[9] bit 1 INT: mux IMUX_G2_DATA[3] bit 8 INT: mux IMUX_G2_DATA[3] bit 11 INT: mux IMUX_G2_DATA[2] bit 7 INT: mux IMUX_G2_DATA[2] bit 4 INT: mux IMUX_G2_DATA[2] bit 0 INT: mux IMUX_G2_DATA[2] bit 2 INT: mux DBL_E0[5] bit 0 INT: mux DBL_W0[5] bit 0 INT: mux DBL_W0[5] bit 7 INT: mux DBL_W0[5] bit 5 INT: mux HEX_E0[5] bit 0 INT: mux HEX_E0[5] bit 3 INT: mux HEX_E0[5] bit 4 INT: mux HEX_W0[5] bit 4
B45 - - - - INT: mux IMUX_DCM_CLK[1] bit 3 INT: mux IMUX_DCM_CLK[1] bit 1 INT: mux OMUX[9] bit 2 INT: mux OMUX[8] bit 2 INT: mux IMUX_G2_DATA[3] bit 9 INT: mux IMUX_G2_DATA[3] bit 10 INT: mux IMUX_G2_DATA[3] bit 6 INT: mux IMUX_G2_DATA[3] bit 5 INT: mux IMUX_G2_DATA[3] bit 1 INT: mux IMUX_G2_DATA[3] bit 3 INT: mux DBL_W0[5] bit 2 INT: mux DBL_E0[5] bit 3 INT: mux DBL_W0[5] bit 6 INT: mux DBL_W0[5] bit 4 INT: mux HEX_W0[5] bit 2 INT: mux HEX_W0[5] bit 0 INT: mux HEX_E0[5] bit 5 INT: mux LH[12] bit 1
B44 - - - - INT: mux IMUX_DCM_CLK[0] bit 1 INT: mux IMUX_DCM_CLK[0] bit 0 INT: mux OMUX[9] bit 3 INT: mux OMUX[8] bit 3 INT: mux IMUX_G2_DATA[2] bit 9 INT: mux IMUX_G2_DATA[2] bit 10 INT: mux IMUX_G2_DATA[2] bit 6 INT: mux IMUX_G2_DATA[2] bit 5 INT: mux IMUX_G2_DATA[2] bit 1 INT: mux IMUX_G2_DATA[2] bit 3 INT: mux DBL_W0[5] bit 1 INT: mux DBL_E0[5] bit 1 INT: mux DBL_E0[5] bit 5 INT: mux DBL_E0[5] bit 6 INT: mux HEX_E0[5] bit 2 INT: mux HEX_E0[5] bit 1 INT: mux HEX_E0[5] bit 6 INT: mux HEX_W0[5] bit 6
B43 - - - - INT: mux IMUX_DCM_CLK[1] bit 0 INT: mux IMUX_DCM_CLK[1] bit 5 INT: mux OMUX[8] bit 4 INT: mux OMUX[9] bit 4 INT: mux IMUX_G2_DATA[0] bit 9 INT: mux IMUX_G2_DATA[0] bit 10 INT: mux IMUX_G2_DATA[0] bit 6 INT: mux IMUX_G2_DATA[0] bit 5 INT: mux IMUX_G2_DATA[0] bit 1 INT: mux IMUX_G2_DATA[0] bit 3 INT: mux DBL_S0[5] bit 3 INT: mux DBL_N0[5] bit 1 INT: mux DBL_S0[5] bit 4 INT: mux DBL_S0[5] bit 7 INT: mux HEX_N0[5] bit 1 INT: mux HEX_N0[5] bit 3 INT: mux HEX_N0[5] bit 5 INT: mux LH[12] bit 0
B42 - - - - INT: mux IMUX_DCM_CLK[0] bit 5 INT: mux IMUX_DCM_CLK[0] bit 6 INT: mux OMUX[9] bit 5 INT: mux OMUX[8] bit 8 INT: mux IMUX_G2_DATA[1] bit 9 INT: mux IMUX_G2_DATA[1] bit 10 INT: mux IMUX_G2_DATA[1] bit 6 INT: mux IMUX_G2_DATA[1] bit 5 INT: mux IMUX_G2_DATA[1] bit 1 INT: mux IMUX_G2_DATA[1] bit 3 INT: mux DBL_S0[5] bit 0 INT: mux DBL_N0[5] bit 0 INT: mux DBL_N0[5] bit 7 INT: mux DBL_N0[5] bit 5 INT: mux HEX_S0[5] bit 0 INT: mux HEX_S0[5] bit 2 INT: mux HEX_S0[5] bit 4 INT: mux HEX_N0[5] bit 4
B41 - - - - INT: mux IMUX_DCM_CLK[1] bit 6 INT: mux IMUX_DCM_CLK[1] bit 4 INT: mux OMUX[8] bit 9 INT: mux OMUX[8] bit 7 INT: mux IMUX_G2_DATA[1] bit 8 INT: mux IMUX_G2_DATA[1] bit 11 INT: mux IMUX_G2_DATA[0] bit 7 INT: mux IMUX_G2_DATA[0] bit 4 INT: mux IMUX_G2_DATA[0] bit 0 INT: mux IMUX_G2_DATA[0] bit 2 INT: mux DBL_N0[5] bit 3 INT: mux DBL_S0[5] bit 1 INT: mux DBL_N0[5] bit 6 INT: mux DBL_N0[5] bit 4 INT: mux HEX_N0[5] bit 2 INT: mux HEX_N0[5] bit 0 INT: mux HEX_S0[5] bit 5 INT: mux LH[12] bit 2
B40 - - - - INT: mux IMUX_DCM_CLK[0] bit 4 INT: mux IMUX_DCM_CLK[0] bit 7 INT: mux OMUX[8] bit 5 INT: mux OMUX[8] bit 6 INT: mux IMUX_G2_DATA[0] bit 8 INT: mux IMUX_G2_DATA[0] bit 11 INT: mux IMUX_G2_DATA[1] bit 7 INT: mux IMUX_G2_DATA[1] bit 4 INT: mux IMUX_G2_DATA[1] bit 0 INT: mux IMUX_G2_DATA[1] bit 2 INT: mux DBL_N0[5] bit 2 INT: mux DBL_S0[5] bit 2 INT: mux DBL_S0[5] bit 5 INT: mux DBL_S0[5] bit 6 INT: mux HEX_S0[5] bit 3 INT: mux HEX_S0[5] bit 1 INT: mux HEX_S0[5] bit 6 INT: mux HEX_N0[5] bit 6
B39 - - - - INT: mux IMUX_DCM_CLK[0] bit 8 INT: mux IMUX_DCM_CLK[0] bit 10 INT: mux OMUX[6] bit 4 INT: mux OMUX[7] bit 6 INT: mux IMUX_G1_DATA[0] bit 9 INT: mux IMUX_G1_DATA[0] bit 11 INT: mux IMUX_G1_DATA[1] bit 7 INT: mux IMUX_G1_DATA[1] bit 5 INT: mux IMUX_G1_DATA[1] bit 1 INT: mux IMUX_G1_DATA[1] bit 2 INT: mux DBL_E0[4] bit 2 INT: mux DBL_W0[4] bit 3 INT: mux DBL_E0[4] bit 5 INT: mux DBL_E0[4] bit 7 INT: mux HEX_E0[4] bit 1 INT: mux HEX_E0[4] bit 3 INT: mux HEX_E0[4] bit 5 INT: mux LH[18] bit 2
B38 - - - - INT: invert IMUX_DCM_CLK_OPTINV[0] ← IMUX_DCM_CLK[0] INT: mux IMUX_DCM_CLK[0] bit 11 INT: mux OMUX[7] bit 9 INT: mux OMUX[7] bit 7 INT: mux IMUX_G1_DATA[1] bit 9 INT: mux IMUX_G1_DATA[1] bit 11 INT: mux IMUX_G1_DATA[0] bit 7 INT: mux IMUX_G1_DATA[0] bit 5 INT: mux IMUX_G1_DATA[0] bit 1 INT: mux IMUX_G1_DATA[0] bit 2 INT: mux DBL_E0[4] bit 0 INT: mux DBL_W0[4] bit 0 INT: mux DBL_W0[4] bit 7 INT: mux DBL_W0[4] bit 5 INT: mux HEX_W0[4] bit 1 INT: mux HEX_W0[4] bit 3 INT: mux HEX_W0[4] bit 5 INT: mux HEX_E0[4] bit 4
B37 - - - - INT: mux IMUX_DCM_CLK[1] bit 7 INT: mux IMUX_DCM_CLK[0] bit 9 INT: mux OMUX[7] bit 4 INT: mux OMUX[7] bit 8 INT: mux IMUX_G1_DATA[1] bit 8 INT: mux IMUX_G1_DATA[1] bit 10 INT: mux IMUX_G1_DATA[1] bit 6 INT: mux IMUX_G1_DATA[1] bit 4 INT: mux IMUX_G1_DATA[1] bit 0 INT: mux IMUX_G1_DATA[1] bit 3 INT: mux DBL_W0[4] bit 2 INT: mux DBL_E0[4] bit 3 INT: mux DBL_W0[4] bit 6 INT: mux DBL_W0[4] bit 4 INT: mux HEX_E0[4] bit 2 INT: mux HEX_E0[4] bit 0 INT: mux HEX_W0[4] bit 4 INT: mux LH[18] bit 1
B36 - - - - - - INT: mux OMUX[6] bit 5 INT: mux OMUX[7] bit 5 INT: mux IMUX_G1_DATA[0] bit 8 INT: mux IMUX_G1_DATA[0] bit 10 INT: mux IMUX_G1_DATA[0] bit 6 INT: mux IMUX_G1_DATA[0] bit 4 INT: mux IMUX_G1_DATA[0] bit 0 INT: mux IMUX_G1_DATA[0] bit 3 INT: mux DBL_W0[4] bit 1 INT: mux DBL_E0[4] bit 1 INT: mux DBL_E0[4] bit 4 INT: mux DBL_E0[4] bit 6 INT: mux HEX_W0[4] bit 2 INT: mux HEX_W0[4] bit 0 INT: mux HEX_W0[4] bit 6 INT: mux HEX_E0[4] bit 6
B35 - - - - - - INT: mux OMUX[7] bit 0 INT: mux OMUX[6] bit 0 INT: mux IMUX_G1_DATA[2] bit 8 INT: mux IMUX_G1_DATA[2] bit 10 INT: mux IMUX_G1_DATA[2] bit 6 INT: mux IMUX_G1_DATA[2] bit 4 INT: mux IMUX_G1_DATA[2] bit 0 INT: mux IMUX_G1_DATA[2] bit 3 INT: mux DBL_S0[4] bit 3 INT: mux DBL_N0[4] bit 1 INT: mux DBL_S0[4] bit 4 INT: mux DBL_S0[4] bit 7 INT: mux HEX_S0[4] bit 0 INT: mux HEX_S0[4] bit 3 INT: mux HEX_S0[4] bit 4 INT: mux LH[18] bit 0
B34 - - - - - - INT: mux OMUX[7] bit 1 INT: mux OMUX[6] bit 1 INT: mux IMUX_G1_DATA[3] bit 8 INT: mux IMUX_G1_DATA[3] bit 10 INT: mux IMUX_G1_DATA[3] bit 6 INT: mux IMUX_G1_DATA[3] bit 4 INT: mux IMUX_G1_DATA[3] bit 0 INT: mux IMUX_G1_DATA[3] bit 3 INT: mux DBL_S0[4] bit 0 INT: mux DBL_N0[4] bit 0 INT: mux DBL_N0[4] bit 7 INT: mux DBL_N0[4] bit 4 INT: mux HEX_N0[4] bit 0 INT: mux HEX_N0[4] bit 2 INT: mux HEX_N0[4] bit 4 INT: mux HEX_S0[4] bit 5
B33 - - - - - - INT: mux OMUX[6] bit 2 INT: mux OMUX[7] bit 2 INT: mux IMUX_G1_DATA[3] bit 9 INT: mux IMUX_G1_DATA[3] bit 11 INT: mux IMUX_G1_DATA[2] bit 7 INT: mux IMUX_G1_DATA[2] bit 5 INT: mux IMUX_G1_DATA[2] bit 1 INT: mux IMUX_G1_DATA[2] bit 2 INT: mux DBL_N0[4] bit 3 INT: mux DBL_S0[4] bit 1 INT: mux DBL_N0[4] bit 6 INT: mux DBL_N0[4] bit 5 INT: mux HEX_S0[4] bit 2 INT: mux HEX_S0[4] bit 1 INT: mux HEX_N0[4] bit 5 INT: mux LH[6] bit 1
B32 - - - - - - INT: mux OMUX[7] bit 3 INT: mux OMUX[6] bit 8 INT: mux IMUX_G1_DATA[2] bit 9 INT: mux IMUX_G1_DATA[2] bit 11 INT: mux IMUX_G1_DATA[3] bit 7 INT: mux IMUX_G1_DATA[3] bit 5 INT: mux IMUX_G1_DATA[3] bit 1 INT: mux IMUX_G1_DATA[3] bit 2 INT: mux DBL_N0[4] bit 2 INT: mux DBL_S0[4] bit 2 INT: mux DBL_S0[4] bit 5 INT: mux DBL_S0[4] bit 6 INT: mux HEX_N0[4] bit 3 INT: mux HEX_N0[4] bit 1 INT: mux HEX_N0[4] bit 6 INT: mux HEX_S0[4] bit 6
B31 - - - - - - INT: mux OMUX[6] bit 9 INT: mux OMUX[6] bit 7 INT: mux IMUX_G1_DATA[4] bit 9 INT: mux IMUX_G1_DATA[4] bit 11 INT: mux IMUX_G1_DATA[5] bit 7 INT: mux IMUX_G1_DATA[5] bit 5 INT: mux IMUX_G1_DATA[5] bit 1 INT: mux IMUX_G1_DATA[5] bit 2 INT: mux DBL_E0[3] bit 2 INT: mux DBL_W0[3] bit 3 INT: mux DBL_E0[3] bit 4 INT: mux DBL_E0[3] bit 7 INT: mux HEX_W0[3] bit 1 INT: mux HEX_W0[3] bit 3 INT: mux HEX_W0[3] bit 5 INT: mux LH[6] bit 2
B30 - - - - - - INT: mux OMUX[6] bit 3 INT: mux OMUX[6] bit 6 INT: mux IMUX_G1_DATA[5] bit 9 INT: mux IMUX_G1_DATA[5] bit 11 INT: mux IMUX_G1_DATA[4] bit 7 INT: mux IMUX_G1_DATA[4] bit 5 INT: mux IMUX_G1_DATA[4] bit 1 INT: mux IMUX_G1_DATA[4] bit 2 INT: mux DBL_E0[3] bit 0 INT: mux DBL_W0[3] bit 0 INT: mux DBL_W0[3] bit 7 INT: mux DBL_W0[3] bit 5 INT: mux HEX_E0[3] bit 0 INT: mux HEX_E0[3] bit 3 INT: mux HEX_E0[3] bit 4 INT: mux HEX_W0[3] bit 4
B29 - - - - - - INT: mux OMUX[4] bit 0 INT: mux OMUX[5] bit 6 INT: mux IMUX_G1_DATA[5] bit 8 INT: mux IMUX_G1_DATA[5] bit 10 INT: mux IMUX_G1_DATA[5] bit 6 INT: mux IMUX_G1_DATA[5] bit 4 INT: mux IMUX_G1_DATA[5] bit 0 INT: mux IMUX_G1_DATA[5] bit 3 INT: mux DBL_W0[3] bit 2 INT: mux DBL_E0[3] bit 3 INT: mux DBL_W0[3] bit 6 INT: mux DBL_W0[3] bit 4 INT: mux HEX_W0[3] bit 2 INT: mux HEX_W0[3] bit 0 INT: mux HEX_E0[3] bit 5 INT: mux LH[6] bit 0
B28 - - - - INT: mux IMUX_TI[1] bit 5 INT: mux IMUX_TI[1] bit 9 INT: mux OMUX[5] bit 9 INT: mux OMUX[5] bit 7 INT: mux IMUX_G1_DATA[4] bit 8 INT: mux IMUX_G1_DATA[4] bit 10 INT: mux IMUX_G1_DATA[4] bit 6 INT: mux IMUX_G1_DATA[4] bit 4 INT: mux IMUX_G1_DATA[4] bit 0 INT: mux IMUX_G1_DATA[4] bit 3 INT: mux DBL_W0[3] bit 1 INT: mux DBL_E0[3] bit 1 INT: mux DBL_E0[3] bit 5 INT: mux DBL_E0[3] bit 6 INT: mux HEX_E0[3] bit 2 INT: mux HEX_E0[3] bit 1 INT: mux HEX_E0[3] bit 6 INT: mux HEX_W0[3] bit 6
B27 - - - - INT: !invert IMUX_TI_OPTINV[1] ← IMUX_TI[1] INT: mux IMUX_TI[0] bit 5 INT: mux OMUX[5] bit 0 INT: mux OMUX[5] bit 8 INT: mux IMUX_G1_DATA[6] bit 8 INT: mux IMUX_G1_DATA[6] bit 10 INT: mux IMUX_G1_DATA[6] bit 6 INT: mux IMUX_G1_DATA[6] bit 4 INT: mux IMUX_G1_DATA[6] bit 0 INT: mux IMUX_G1_DATA[6] bit 3 INT: mux DBL_S0[3] bit 3 INT: mux DBL_N0[3] bit 1 INT: mux DBL_S0[3] bit 5 INT: mux DBL_S0[3] bit 7 INT: mux HEX_N0[3] bit 0 INT: mux HEX_N0[3] bit 3 INT: mux HEX_N0[3] bit 4 INT: mux LV[12] bit 4
B26 - - - - INT: mux IMUX_TI[1] bit 7 INT: mux IMUX_TI[1] bit 6 INT: mux OMUX[4] bit 1 INT: mux OMUX[5] bit 1 INT: mux IMUX_G1_DATA[7] bit 8 INT: mux IMUX_G1_DATA[7] bit 10 INT: mux IMUX_G1_DATA[7] bit 6 INT: mux IMUX_G1_DATA[7] bit 4 INT: mux IMUX_G1_DATA[7] bit 0 INT: mux IMUX_G1_DATA[7] bit 3 INT: mux DBL_S0[3] bit 0 INT: mux DBL_N0[3] bit 0 INT: mux DBL_N0[3] bit 7 INT: mux DBL_N0[3] bit 4 INT: mux HEX_S0[3] bit 1 INT: mux HEX_S0[3] bit 2 INT: mux HEX_S0[3] bit 5 INT: mux HEX_N0[3] bit 5
B25 - - - - INT: mux IMUX_TI[0] bit 4 INT: mux IMUX_TI[1] bit 8 INT: mux OMUX[5] bit 2 INT: mux OMUX[4] bit 2 INT: mux IMUX_G1_DATA[7] bit 9 INT: mux IMUX_G1_DATA[7] bit 11 INT: mux IMUX_G1_DATA[6] bit 7 INT: mux IMUX_G1_DATA[6] bit 5 INT: mux IMUX_G1_DATA[6] bit 1 INT: mux IMUX_G1_DATA[6] bit 2 INT: mux DBL_N0[3] bit 3 INT: mux DBL_S0[3] bit 1 INT: mux DBL_N0[3] bit 6 INT: mux DBL_N0[3] bit 5 INT: mux HEX_N0[3] bit 2 INT: mux HEX_N0[3] bit 1 INT: mux HEX_S0[3] bit 4 INT: mux LV[0] bit 3
B24 - - - - INT: mux IMUX_TI[1] bit 4 INT: mux IMUX_TI[1] bit 2 INT: mux OMUX[5] bit 3 INT: mux OMUX[4] bit 3 INT: mux IMUX_G1_DATA[6] bit 9 INT: mux IMUX_G1_DATA[6] bit 11 INT: mux IMUX_G1_DATA[7] bit 7 INT: mux IMUX_G1_DATA[7] bit 5 INT: mux IMUX_G1_DATA[7] bit 1 INT: mux IMUX_G1_DATA[7] bit 2 INT: mux DBL_N0[3] bit 2 INT: mux DBL_S0[3] bit 2 INT: mux DBL_S0[3] bit 4 INT: mux DBL_S0[3] bit 6 INT: mux HEX_S0[3] bit 3 INT: mux HEX_S0[3] bit 0 INT: mux HEX_S0[3] bit 6 INT: mux HEX_N0[3] bit 6
B23 - - - - INT: mux IMUX_TI[0] bit 3 INT: mux IMUX_TI[0] bit 2 INT: mux OMUX[4] bit 4 INT: mux OMUX[5] bit 4 INT: mux IMUX_G1_FAN[0] bit 9 INT: mux IMUX_G1_FAN[0] bit 11 INT: mux IMUX_G1_FAN[1] bit 7 INT: mux IMUX_G1_FAN[1] bit 5 INT: mux IMUX_G1_FAN[1] bit 1 INT: mux IMUX_G1_FAN[1] bit 2 INT: mux DBL_E0[2] bit 4 INT: mux DBL_W0[2] bit 7 INT: mux DBL_E0[2] bit 1 INT: mux DBL_E0[2] bit 3 INT: mux HEX_E0[2] bit 1 INT: mux HEX_E0[2] bit 3 INT: mux HEX_E0[2] bit 5 INT: mux LV[12] bit 3
B22 - - - - INT: mux IMUX_TI[1] bit 1 INT: mux IMUX_TI[1] bit 3 INT: mux OMUX[5] bit 5 INT: mux OMUX[4] bit 8 INT: mux IMUX_G1_FAN[1] bit 9 INT: mux IMUX_G1_FAN[1] bit 11 INT: mux IMUX_G1_FAN[0] bit 7 INT: mux IMUX_G1_FAN[0] bit 5 INT: mux IMUX_G1_FAN[0] bit 1 INT: mux IMUX_G1_FAN[0] bit 2 INT: mux DBL_E0[2] bit 5 INT: mux DBL_W0[2] bit 5 INT: mux DBL_W0[2] bit 3 INT: mux DBL_W0[2] bit 1 INT: mux HEX_W0[2] bit 4 INT: mux HEX_W0[2] bit 6 INT: mux HEX_W0[2] bit 2 INT: mux HEX_E0[2] bit 6
B21 - - - - INT: mux IMUX_TI[0] bit 1 INT: mux IMUX_TI[0] bit 0 INT: mux OMUX[4] bit 9 INT: mux OMUX[4] bit 7 INT: mux IMUX_G1_FAN[1] bit 8 INT: mux IMUX_G1_FAN[1] bit 10 INT: mux IMUX_G1_FAN[1] bit 6 INT: mux IMUX_G1_FAN[1] bit 4 INT: mux IMUX_G1_FAN[1] bit 0 INT: mux IMUX_G1_FAN[1] bit 3 INT: mux DBL_W0[2] bit 4 INT: mux DBL_E0[2] bit 7 INT: mux DBL_W0[2] bit 2 INT: mux DBL_W0[2] bit 0 INT: mux HEX_E0[2] bit 2 INT: mux HEX_E0[2] bit 0 INT: mux HEX_W0[2] bit 1 INT: mux LV[0] bit 2
B20 - - - - INT: mux IMUX_TI[0] bit 7 INT: mux IMUX_TI[0] bit 6 INT: mux OMUX[4] bit 5 INT: mux OMUX[4] bit 6 INT: mux IMUX_G1_FAN[0] bit 8 INT: mux IMUX_G1_FAN[0] bit 10 INT: mux IMUX_G1_FAN[0] bit 6 INT: mux IMUX_G1_FAN[0] bit 4 INT: mux IMUX_G1_FAN[0] bit 0 INT: mux IMUX_G1_FAN[0] bit 3 INT: mux DBL_W0[2] bit 6 INT: mux DBL_E0[2] bit 6 INT: mux DBL_E0[2] bit 0 INT: mux DBL_E0[2] bit 2 INT: mux HEX_W0[2] bit 5 INT: mux HEX_W0[2] bit 3 INT: mux HEX_W0[2] bit 0 INT: mux HEX_E0[2] bit 4
B19 - - - - INT: !invert IMUX_TI_OPTINV[0] ← IMUX_TI[0] INT: mux IMUX_TI[0] bit 8 INT: mux OMUX[2] bit 0 INT: mux OMUX[3] bit 6 INT: mux IMUX_G0_FAN[0] bit 9 INT: mux IMUX_G0_FAN[0] bit 10 INT: mux IMUX_G0_FAN[0] bit 6 INT: mux IMUX_G0_FAN[0] bit 5 INT: mux IMUX_G0_FAN[0] bit 2 INT: mux IMUX_G0_FAN[0] bit 1 INT: mux DBL_S0[2] bit 4 INT: mux DBL_N0[2] bit 6 INT: mux DBL_S0[2] bit 0 INT: mux DBL_S0[2] bit 3 INT: mux HEX_S0[2] bit 0 INT: mux HEX_S0[2] bit 3 INT: mux HEX_S0[2] bit 5 INT: mux LV[0] bit 4
B18 - - - - INT: mux IMUX_TI[1] bit 0 INT: mux IMUX_TI[0] bit 9 INT: mux OMUX[3] bit 9 INT: mux OMUX[3] bit 7 INT: mux IMUX_G0_FAN[1] bit 9 INT: mux IMUX_G0_FAN[1] bit 10 INT: mux IMUX_G0_FAN[1] bit 6 INT: mux IMUX_G0_FAN[1] bit 5 INT: mux IMUX_G0_FAN[1] bit 2 INT: mux IMUX_G0_FAN[1] bit 1 INT: mux DBL_S0[2] bit 5 INT: mux DBL_N0[2] bit 5 INT: mux DBL_N0[2] bit 3 INT: mux DBL_N0[2] bit 0 INT: mux HEX_N0[2] bit 1 INT: mux HEX_N0[2] bit 2 INT: mux HEX_N0[2] bit 4 INT: mux HEX_S0[2] bit 4
B17 - - - - INT: mux IMUX_SR[3] bit 5 INT: mux IMUX_SR[1] bit 1 INT: mux OMUX[3] bit 0 INT: mux OMUX[3] bit 8 INT: mux IMUX_G0_FAN[1] bit 8 INT: mux IMUX_G0_FAN[1] bit 11 INT: mux IMUX_G0_FAN[0] bit 7 INT: mux IMUX_G0_FAN[0] bit 4 INT: mux IMUX_G0_FAN[0] bit 0 INT: mux IMUX_G0_FAN[0] bit 3 INT: mux DBL_N0[2] bit 4 INT: mux DBL_S0[2] bit 6 INT: mux DBL_N0[2] bit 2 INT: mux DBL_N0[2] bit 1 INT: mux HEX_S0[2] bit 2 INT: mux HEX_S0[2] bit 1 INT: mux HEX_N0[2] bit 5 INT: mux LV[12] bit 2
B16 - - - - INT: !invert IMUX_SR_OPTINV[1] ← IMUX_SR[1] INT: mux IMUX_SR[1] bit 3 INT: mux OMUX[2] bit 1 INT: mux OMUX[3] bit 1 INT: mux IMUX_G0_FAN[0] bit 8 INT: mux IMUX_G0_FAN[0] bit 11 INT: mux IMUX_G0_FAN[1] bit 7 INT: mux IMUX_G0_FAN[1] bit 4 INT: mux IMUX_G0_FAN[1] bit 0 INT: mux IMUX_G0_FAN[1] bit 3 INT: mux DBL_N0[2] bit 7 INT: mux DBL_S0[2] bit 7 INT: mux DBL_S0[2] bit 1 INT: mux DBL_S0[2] bit 2 INT: mux HEX_N0[2] bit 3 INT: mux HEX_N0[2] bit 0 INT: mux HEX_N0[2] bit 6 INT: mux HEX_S0[2] bit 6
B15 - - - - INT: mux IMUX_SR[1] bit 0 INT: mux IMUX_SR[1] bit 2 INT: mux OMUX[3] bit 2 INT: mux OMUX[2] bit 2 INT: mux IMUX_G0_DATA[6] bit 8 INT: mux IMUX_G0_DATA[6] bit 11 INT: mux IMUX_G0_DATA[7] bit 7 INT: mux IMUX_G0_DATA[7] bit 4 INT: mux IMUX_G0_DATA[7] bit 0 INT: mux IMUX_G0_DATA[7] bit 3 INT: mux DBL_E0[1] bit 2 INT: mux DBL_W0[1] bit 3 INT: mux DBL_E0[1] bit 4 INT: mux DBL_E0[1] bit 7 INT: mux HEX_W0[1] bit 1 INT: mux HEX_W0[1] bit 2 INT: mux HEX_W0[1] bit 5 INT: mux LV[12] bit 0
B14 - - - - INT: mux IMUX_SR[1] bit 4 INT: mux IMUX_SR[1] bit 5 INT: mux OMUX[3] bit 3 INT: mux OMUX[2] bit 3 INT: mux IMUX_G0_DATA[7] bit 8 INT: mux IMUX_G0_DATA[7] bit 11 INT: mux IMUX_G0_DATA[6] bit 7 INT: mux IMUX_G0_DATA[6] bit 4 INT: mux IMUX_G0_DATA[6] bit 0 INT: mux IMUX_G0_DATA[6] bit 3 INT: mux DBL_E0[1] bit 0 INT: mux DBL_W0[1] bit 0 INT: mux DBL_W0[1] bit 6 INT: mux DBL_W0[1] bit 5 INT: mux HEX_E0[1] bit 0 INT: mux HEX_E0[1] bit 3 INT: mux HEX_E0[1] bit 4 INT: mux HEX_W0[1] bit 4
B13 - - - - INT: mux IMUX_SR[3] bit 4 INT: mux IMUX_SR[3] bit 7 INT: mux OMUX[2] bit 4 INT: mux OMUX[3] bit 4 INT: mux IMUX_G0_DATA[7] bit 9 INT: mux IMUX_G0_DATA[7] bit 10 INT: mux IMUX_G0_DATA[7] bit 6 INT: mux IMUX_G0_DATA[7] bit 5 INT: mux IMUX_G0_DATA[7] bit 2 INT: mux IMUX_G0_DATA[7] bit 1 INT: mux DBL_W0[1] bit 2 INT: mux DBL_E0[1] bit 3 INT: mux DBL_W0[1] bit 7 INT: mux DBL_W0[1] bit 4 INT: mux HEX_W0[1] bit 3 INT: mux HEX_W0[1] bit 0 INT: mux HEX_E0[1] bit 5 INT: mux LV[12] bit 6
B12 - - - - INT: mux IMUX_SR[1] bit 7 INT: mux IMUX_SR[1] bit 6 INT: mux OMUX[3] bit 5 INT: mux OMUX[2] bit 8 INT: mux IMUX_G0_DATA[6] bit 9 INT: mux IMUX_G0_DATA[6] bit 10 INT: mux IMUX_G0_DATA[6] bit 6 INT: mux IMUX_G0_DATA[6] bit 5 INT: mux IMUX_G0_DATA[6] bit 2 INT: mux IMUX_G0_DATA[6] bit 1 INT: mux DBL_W0[1] bit 1 INT: mux DBL_E0[1] bit 1 INT: mux DBL_E0[1] bit 5 INT: mux DBL_E0[1] bit 6 INT: mux HEX_E0[1] bit 2 INT: mux HEX_E0[1] bit 1 INT: mux HEX_E0[1] bit 6 INT: mux HEX_W0[1] bit 6
B11 - - - - INT: mux IMUX_SR[3] bit 0 INT: mux IMUX_SR[3] bit 1 INT: mux OMUX[2] bit 9 INT: mux OMUX[2] bit 7 INT: mux IMUX_G0_DATA[4] bit 9 INT: mux IMUX_G0_DATA[4] bit 10 INT: mux IMUX_G0_DATA[4] bit 6 INT: mux IMUX_G0_DATA[4] bit 5 INT: mux IMUX_G0_DATA[4] bit 2 INT: mux IMUX_G0_DATA[4] bit 1 INT: mux DBL_S0[1] bit 3 INT: mux DBL_N0[1] bit 1 INT: mux DBL_S0[1] bit 4 INT: mux DBL_S0[1] bit 7 INT: mux HEX_N0[1] bit 0 INT: mux HEX_N0[1] bit 3 INT: mux HEX_N0[1] bit 4 INT: mux LV[0] bit 1
B10 - - - - INT: !invert IMUX_SR_OPTINV[3] ← IMUX_SR[3] INT: mux IMUX_SR[3] bit 3 INT: mux OMUX[2] bit 5 INT: mux OMUX[2] bit 6 INT: mux IMUX_G0_DATA[5] bit 9 INT: mux IMUX_G0_DATA[5] bit 10 INT: mux IMUX_G0_DATA[5] bit 6 INT: mux IMUX_G0_DATA[5] bit 5 INT: mux IMUX_G0_DATA[5] bit 2 INT: mux IMUX_G0_DATA[5] bit 1 INT: mux DBL_S0[1] bit 0 INT: mux DBL_N0[1] bit 0 INT: mux DBL_N0[1] bit 7 INT: mux DBL_N0[1] bit 4 INT: mux HEX_S0[1] bit 0 INT: mux HEX_S0[1] bit 2 INT: mux HEX_S0[1] bit 4 INT: mux HEX_N0[1] bit 5
B9 - - - - INT: mux IMUX_SR[3] bit 6 INT: mux IMUX_SR[3] bit 2 INT: mux OMUX[0] bit 0 INT: mux OMUX[1] bit 6 INT: mux IMUX_G0_DATA[5] bit 8 INT: mux IMUX_G0_DATA[5] bit 11 INT: mux IMUX_G0_DATA[4] bit 7 INT: mux IMUX_G0_DATA[4] bit 4 INT: mux IMUX_G0_DATA[4] bit 0 INT: mux IMUX_G0_DATA[4] bit 3 INT: mux DBL_N0[1] bit 3 INT: mux DBL_S0[1] bit 1 INT: mux DBL_N0[1] bit 6 INT: mux DBL_N0[1] bit 5 INT: mux HEX_N0[1] bit 2 INT: mux HEX_N0[1] bit 1 INT: mux HEX_S0[1] bit 5 INT: mux LV[0] bit 5
B8 - - - - INT: mux IMUX_SR[2] bit 5 INT: mux IMUX_SR[2] bit 2 INT: mux OMUX[1] bit 9 INT: mux OMUX[1] bit 7 INT: mux IMUX_G0_DATA[4] bit 8 INT: mux IMUX_G0_DATA[4] bit 11 INT: mux IMUX_G0_DATA[5] bit 7 INT: mux IMUX_G0_DATA[5] bit 4 INT: mux IMUX_G0_DATA[5] bit 0 INT: mux IMUX_G0_DATA[5] bit 3 INT: mux DBL_N0[1] bit 2 INT: mux DBL_S0[1] bit 2 INT: mux DBL_S0[1] bit 5 INT: mux DBL_S0[1] bit 6 INT: mux HEX_S0[1] bit 3 INT: mux HEX_S0[1] bit 1 INT: mux HEX_S0[1] bit 6 INT: mux HEX_N0[1] bit 6
B7 - - - - INT: !invert IMUX_SR_OPTINV[2] ← IMUX_SR[2] INT: mux IMUX_SR[2] bit 3 INT: mux OMUX[1] bit 0 INT: mux OMUX[1] bit 8 INT: mux IMUX_G0_DATA[2] bit 8 INT: mux IMUX_G0_DATA[2] bit 11 INT: mux IMUX_G0_DATA[3] bit 7 INT: mux IMUX_G0_DATA[3] bit 4 INT: mux IMUX_G0_DATA[3] bit 0 INT: mux IMUX_G0_DATA[3] bit 3 INT: mux DBL_E0[0] bit 2 INT: mux DBL_W0[0] bit 3 INT: mux DBL_E0[0] bit 4 INT: mux DBL_E0[0] bit 7 INT: mux HEX_E0[0] bit 0 INT: mux HEX_E0[0] bit 3 INT: mux HEX_E0[0] bit 4 INT: mux LV[0] bit 6
B6 - - - - INT: mux IMUX_SR[2] bit 1 INT: mux IMUX_SR[2] bit 0 INT: mux OMUX[0] bit 1 INT: mux OMUX[1] bit 1 INT: mux IMUX_G0_DATA[3] bit 8 INT: mux IMUX_G0_DATA[3] bit 11 INT: mux IMUX_G0_DATA[2] bit 7 INT: mux IMUX_G0_DATA[2] bit 4 INT: mux IMUX_G0_DATA[2] bit 0 INT: mux IMUX_G0_DATA[2] bit 3 INT: mux DBL_E0[0] bit 0 INT: mux DBL_W0[0] bit 0 INT: mux DBL_W0[0] bit 6 INT: mux DBL_W0[0] bit 5 INT: mux HEX_W0[0] bit 1 INT: mux HEX_W0[0] bit 2 INT: mux HEX_W0[0] bit 5 INT: mux HEX_E0[0] bit 5
B5 - - - - INT: mux IMUX_SR[0] bit 4 INT: mux IMUX_SR[0] bit 5 INT: mux OMUX[1] bit 2 INT: mux OMUX[0] bit 2 INT: mux IMUX_G0_DATA[3] bit 9 INT: mux IMUX_G0_DATA[3] bit 10 INT: mux IMUX_G0_DATA[3] bit 6 INT: mux IMUX_G0_DATA[3] bit 5 INT: mux IMUX_G0_DATA[3] bit 2 INT: mux IMUX_G0_DATA[3] bit 1 INT: mux DBL_W0[0] bit 2 INT: mux DBL_E0[0] bit 3 INT: mux DBL_W0[0] bit 7 INT: mux DBL_W0[0] bit 4 INT: mux HEX_E0[0] bit 2 INT: mux HEX_E0[0] bit 1 INT: mux HEX_W0[0] bit 4 INT: mux LV[0] bit 0
B4 - - - - INT: mux IMUX_SR[2] bit 6 INT: mux IMUX_SR[2] bit 4 INT: mux OMUX[1] bit 3 INT: mux OMUX[0] bit 3 INT: mux IMUX_G0_DATA[2] bit 9 INT: mux IMUX_G0_DATA[2] bit 10 INT: mux IMUX_G0_DATA[2] bit 6 INT: mux IMUX_G0_DATA[2] bit 5 INT: mux IMUX_G0_DATA[2] bit 2 INT: mux IMUX_G0_DATA[2] bit 1 INT: mux DBL_W0[0] bit 1 INT: mux DBL_E0[0] bit 1 INT: mux DBL_E0[0] bit 5 INT: mux DBL_E0[0] bit 6 INT: mux HEX_W0[0] bit 3 INT: mux HEX_W0[0] bit 0 INT: mux HEX_W0[0] bit 6 INT: mux HEX_E0[0] bit 6
B3 - - - - INT: mux IMUX_SR[0] bit 6 INT: mux IMUX_SR[0] bit 7 INT: mux OMUX[0] bit 4 INT: mux OMUX[1] bit 4 INT: mux IMUX_G0_DATA[0] bit 9 INT: mux IMUX_G0_DATA[0] bit 10 INT: mux IMUX_G0_DATA[0] bit 6 INT: mux IMUX_G0_DATA[0] bit 5 INT: mux IMUX_G0_DATA[0] bit 2 INT: mux IMUX_G0_DATA[0] bit 1 INT: mux DBL_S0[0] bit 4 INT: mux DBL_N0[0] bit 6 INT: mux DBL_S0[0] bit 1 INT: mux DBL_S0[0] bit 3 INT: mux HEX_S0[0] bit 1 INT: mux HEX_S0[0] bit 3 INT: mux HEX_S0[0] bit 6 INT: mux LV[12] bit 1
B2 - - - - INT: mux IMUX_SR[0] bit 1 INT: mux IMUX_SR[0] bit 2 INT: mux OMUX[1] bit 5 INT: mux OMUX[0] bit 8 INT: mux IMUX_G0_DATA[1] bit 9 INT: mux IMUX_G0_DATA[1] bit 10 INT: mux IMUX_G0_DATA[1] bit 6 INT: mux IMUX_G0_DATA[1] bit 5 INT: mux IMUX_G0_DATA[1] bit 2 INT: mux IMUX_G0_DATA[1] bit 1 INT: mux DBL_S0[0] bit 5 INT: mux DBL_N0[0] bit 5 INT: mux DBL_N0[0] bit 3 INT: mux DBL_N0[0] bit 1 INT: mux HEX_N0[0] bit 1 INT: mux HEX_N0[0] bit 2 INT: mux HEX_N0[0] bit 5 INT: mux HEX_S0[0] bit 5
B1 - - - - INT: !invert IMUX_SR_OPTINV[0] ← IMUX_SR[0] INT: mux IMUX_SR[0] bit 3 INT: mux OMUX[0] bit 9 INT: mux OMUX[0] bit 7 INT: mux IMUX_G0_DATA[1] bit 8 INT: mux IMUX_G0_DATA[1] bit 11 INT: mux IMUX_G0_DATA[0] bit 7 INT: mux IMUX_G0_DATA[0] bit 4 INT: mux IMUX_G0_DATA[0] bit 0 INT: mux IMUX_G0_DATA[0] bit 3 INT: mux DBL_N0[0] bit 4 INT: mux DBL_S0[0] bit 6 INT: mux DBL_N0[0] bit 2 INT: mux DBL_N0[0] bit 0 INT: mux HEX_S0[0] bit 2 INT: mux HEX_S0[0] bit 0 INT: mux HEX_N0[0] bit 6 INT: mux LV[12] bit 5
B0 - - - - INT: mux IMUX_SR[2] bit 7 INT: mux IMUX_SR[0] bit 0 INT: mux OMUX[0] bit 5 INT: mux OMUX[0] bit 6 INT: mux IMUX_G0_DATA[0] bit 8 INT: mux IMUX_G0_DATA[0] bit 11 INT: mux IMUX_G0_DATA[1] bit 7 INT: mux IMUX_G0_DATA[1] bit 4 INT: mux IMUX_G0_DATA[1] bit 0 INT: mux IMUX_G0_DATA[1] bit 3 INT: mux DBL_N0[0] bit 7 INT: mux DBL_S0[0] bit 7 INT: mux DBL_S0[0] bit 0 INT: mux DBL_S0[0] bit 2 INT: mux HEX_N0[0] bit 3 INT: mux HEX_N0[0] bit 0 INT: mux HEX_N0[0] bit 4 INT: mux HEX_S0[0] bit 4

INT_DCM_V2P

Used with the Virtex 2 Pro DCM_V2P tile.

Tile INT_DCM_V2P

Cells: 1

Switchbox INT

virtex2 INT_DCM_V2P switchbox INT programmable inverters
DestinationSourceBit
IMUX_DCM_CLK_OPTINV[0]IMUX_DCM_CLK[0]MAIN[4][38]
IMUX_DCM_CLK_OPTINV[1]IMUX_DCM_CLK[1]MAIN[4][48]
IMUX_DCM_CLK_OPTINV[2]IMUX_DCM_CLK[2]MAIN[4][51]
IMUX_SR_OPTINV[0]IMUX_SR[0]!MAIN[4][1]
IMUX_SR_OPTINV[1]IMUX_SR[1]!MAIN[4][16]
IMUX_SR_OPTINV[2]IMUX_SR[2]!MAIN[4][7]
IMUX_SR_OPTINV[3]IMUX_SR[3]!MAIN[4][10]
IMUX_CE_OPTINV[2]IMUX_CE[2]!MAIN[4][72]
IMUX_CE_OPTINV[3]IMUX_CE[3]!MAIN[4][78]
IMUX_TI_OPTINV[0]IMUX_TI[0]!MAIN[4][19]
IMUX_TI_OPTINV[1]IMUX_TI[1]!MAIN[4][27]
virtex2 INT_DCM_V2P switchbox INT muxes OMUX[0]
BitsDestination
MAIN[6][1]MAIN[7][2]MAIN[7][1]MAIN[7][0]MAIN[6][0]MAIN[6][3]MAIN[7][4]MAIN[7][5]MAIN[6][6]MAIN[6][9]OMUX[0]
Source
0000000000off
0001000001IMUX_SR[0]
0001000010IMUX_SR[2]
0001000100IMUX_G0_DATA[0]
0001001000IMUX_G0_DATA[1]
0001010000IMUX_G0_DATA[2]
0001100000IMUX_G0_DATA[3]
0010000100OUT_SEC[2]
0010001000OUT_SEC[3]
0010010000OUT_SEC[4]
0010100000OUT_SEC[5]
0100000001OUT_SEC[6]
0100000010OUT_SEC[7]
0100000100OUT_SEC[8]
0100001000OUT_SEC[9]
0100010000OUT_SEC[10]
0100100000OUT_SEC[11]
1000000001OUT_SEC[12]
1000000010OUT_SEC[13]
1000000100OUT_HALF0[17]
1000001000OUT_HALF0[16]
1000010000OUT_HALF0[15]
1000100000OUT_HALF0[14]
virtex2 INT_DCM_V2P switchbox INT muxes OMUX[1]
BitsDestination
MAIN[6][8]MAIN[7][7]MAIN[7][8]MAIN[7][9]MAIN[6][2]MAIN[7][3]MAIN[6][4]MAIN[6][5]MAIN[7][6]MAIN[6][7]OMUX[1]
Source
0000000000off
0001000001IMUX_SR[0]
0001000010IMUX_SR[2]
0001000100IMUX_G0_DATA[0]
0001001000IMUX_G0_DATA[1]
0001010000IMUX_G0_DATA[2]
0001100000IMUX_G0_DATA[3]
0010000100OUT_SEC[2]
0010001000OUT_SEC[3]
0010010000OUT_SEC[4]
0010100000OUT_SEC[5]
0100000001OUT_SEC[6]
0100000010OUT_SEC[7]
0100000100OUT_SEC[8]
0100001000OUT_SEC[9]
0100010000OUT_SEC[10]
0100100000OUT_SEC[11]
1000000001OUT_SEC[12]
1000000010OUT_SEC[13]
1000000100OUT_HALF0[17]
1000001000OUT_HALF0[16]
1000010000OUT_HALF0[15]
1000100000OUT_HALF0[14]
virtex2 INT_DCM_V2P switchbox INT muxes OMUX[2]
BitsDestination
MAIN[6][11]MAIN[7][12]MAIN[7][11]MAIN[7][10]MAIN[6][10]MAIN[6][13]MAIN[7][14]MAIN[7][15]MAIN[6][16]MAIN[6][19]OMUX[2]
Source
0000000000off
0001000001IMUX_SR[1]
0001000010IMUX_SR[3]
0001000100IMUX_G0_DATA[4]
0001001000IMUX_G0_DATA[5]
0001010000IMUX_G0_DATA[6]
0001100000IMUX_G0_DATA[7]
0010000100OUT_SEC[2]
0010001000OUT_SEC[3]
0010010000OUT_SEC[4]
0010100000OUT_SEC[5]
0100000001OUT_SEC[6]
0100000010OUT_SEC[7]
0100000100OUT_SEC[8]
0100001000OUT_SEC[9]
0100010000OUT_SEC[10]
0100100000OUT_SEC[11]
1000000001OUT_SEC[12]
1000000010OUT_SEC[13]
1000000100OUT_HALF0[17]
1000001000OUT_HALF0[16]
1000010000OUT_HALF0[15]
1000100000OUT_HALF0[14]
virtex2 INT_DCM_V2P switchbox INT muxes OMUX[3]
BitsDestination
MAIN[6][18]MAIN[7][17]MAIN[7][18]MAIN[7][19]MAIN[6][12]MAIN[7][13]MAIN[6][14]MAIN[6][15]MAIN[7][16]MAIN[6][17]OMUX[3]
Source
0000000000off
0001000001IMUX_SR[1]
0001000010IMUX_SR[3]
0001000100IMUX_G0_DATA[4]
0001001000IMUX_G0_DATA[5]
0001010000IMUX_G0_DATA[6]
0001100000IMUX_G0_DATA[7]
0010000100OUT_SEC[2]
0010001000OUT_SEC[3]
0010010000OUT_SEC[4]
0010100000OUT_SEC[5]
0100000001OUT_SEC[6]
0100000010OUT_SEC[7]
0100000100OUT_SEC[8]
0100001000OUT_SEC[9]
0100010000OUT_SEC[10]
0100100000OUT_SEC[11]
1000000001OUT_SEC[12]
1000000010OUT_SEC[13]
1000000100OUT_HALF0[17]
1000001000OUT_HALF0[16]
1000010000OUT_HALF0[15]
1000100000OUT_HALF0[14]
virtex2 INT_DCM_V2P switchbox INT muxes OMUX[4]
BitsDestination
MAIN[6][21]MAIN[7][22]MAIN[7][21]MAIN[7][20]MAIN[6][20]MAIN[6][23]MAIN[7][24]MAIN[7][25]MAIN[6][26]MAIN[6][29]OMUX[4]
Source
0000000000off
0001000001IMUX_TI[0]
0001000010IMUX_TI[1]
0001000100IMUX_G1_DATA[4]
0001001000IMUX_G1_DATA[5]
0001010000IMUX_G1_DATA[6]
0001100000IMUX_G1_DATA[7]
0010000100OUT_SEC[2]
0010001000OUT_SEC[3]
0010010000OUT_SEC[4]
0010100000OUT_SEC[5]
0100000001OUT_SEC[6]
0100000010OUT_SEC[7]
0100000100OUT_SEC[8]
0100001000OUT_SEC[9]
0100010000OUT_SEC[10]
0100100000OUT_SEC[11]
1000000001OUT_SEC[12]
1000000010OUT_SEC[13]
1000000100OUT_HALF0[17]
1000001000OUT_HALF0[16]
1000010000OUT_HALF0[15]
1000100000OUT_HALF0[14]
virtex2 INT_DCM_V2P switchbox INT muxes OMUX[5]
BitsDestination
MAIN[6][28]MAIN[7][27]MAIN[7][28]MAIN[7][29]MAIN[6][22]MAIN[7][23]MAIN[6][24]MAIN[6][25]MAIN[7][26]MAIN[6][27]OMUX[5]
Source
0000000000off
0001000001IMUX_TI[0]
0001000010IMUX_TI[1]
0001000100IMUX_G1_DATA[4]
0001001000IMUX_G1_DATA[5]
0001010000IMUX_G1_DATA[6]
0001100000IMUX_G1_DATA[7]
0010000100OUT_SEC[2]
0010001000OUT_SEC[3]
0010010000OUT_SEC[4]
0010100000OUT_SEC[5]
0100000001OUT_SEC[6]
0100000010OUT_SEC[7]
0100000100OUT_SEC[8]
0100001000OUT_SEC[9]
0100010000OUT_SEC[10]
0100100000OUT_SEC[11]
1000000001OUT_SEC[12]
1000000010OUT_SEC[13]
1000000100OUT_HALF0[17]
1000001000OUT_HALF0[16]
1000010000OUT_HALF0[15]
1000100000OUT_HALF0[14]
virtex2 INT_DCM_V2P switchbox INT muxes OMUX[6]
BitsDestination
MAIN[6][31]MAIN[7][32]MAIN[7][31]MAIN[7][30]MAIN[6][36]MAIN[6][39]MAIN[6][30]MAIN[6][33]MAIN[7][34]MAIN[7][35]OMUX[6]
Source
0000000000off
0001000001IMUX_G1_DATA[0]
0001000010IMUX_G1_DATA[1]
0001000100IMUX_G1_DATA[2]
0001001000IMUX_G1_DATA[3]
0010000001OUT_SEC[2]
0010000010OUT_SEC[3]
0010000100OUT_SEC[4]
0010001000OUT_SEC[5]
0100000001OUT_SEC[8]
0100000010OUT_SEC[9]
0100000100OUT_SEC[10]
0100001000OUT_SEC[11]
0100010000OUT_SEC[6]
0100100000OUT_SEC[7]
1000000001OUT_HALF0[17]
1000000010OUT_HALF0[16]
1000000100OUT_HALF0[15]
1000001000OUT_HALF0[14]
1000010000OUT_SEC[12]
1000100000OUT_SEC[13]
virtex2 INT_DCM_V2P switchbox INT muxes OMUX[7]
BitsDestination
MAIN[6][38]MAIN[7][37]MAIN[7][38]MAIN[7][39]MAIN[7][36]MAIN[6][37]MAIN[6][32]MAIN[7][33]MAIN[6][34]MAIN[6][35]OMUX[7]
Source
0000000000off
0001000001IMUX_G1_DATA[0]
0001000010IMUX_G1_DATA[1]
0001000100IMUX_G1_DATA[2]
0001001000IMUX_G1_DATA[3]
0010000001OUT_SEC[2]
0010000010OUT_SEC[3]
0010000100OUT_SEC[4]
0010001000OUT_SEC[5]
0100000001OUT_SEC[8]
0100000010OUT_SEC[9]
0100000100OUT_SEC[10]
0100001000OUT_SEC[11]
0100010000OUT_SEC[6]
0100100000OUT_SEC[7]
1000000001OUT_HALF0[17]
1000000010OUT_HALF0[16]
1000000100OUT_HALF0[15]
1000001000OUT_HALF0[14]
1000010000OUT_SEC[12]
1000100000OUT_SEC[13]
virtex2 INT_DCM_V2P switchbox INT muxes OMUX[8]
BitsDestination
MAIN[6][41]MAIN[7][42]MAIN[7][41]MAIN[7][40]MAIN[6][40]MAIN[6][43]MAIN[7][44]MAIN[7][45]MAIN[6][46]MAIN[6][49]OMUX[8]
Source
0000000000off
0001000001IMUX_DCM_CLK[0]
0001000010IMUX_DCM_CLK[1]
0001000100IMUX_G2_DATA[0]
0001001000IMUX_G2_DATA[1]
0001010000IMUX_G2_DATA[2]
0001100000IMUX_G2_DATA[3]
0010000100OUT_SEC[2]
0010001000OUT_SEC[3]
0010010000OUT_SEC[4]
0010100000OUT_SEC[5]
0100000001OUT_SEC[6]
0100000010OUT_SEC[7]
0100000100OUT_SEC[8]
0100001000OUT_SEC[9]
0100010000OUT_SEC[10]
0100100000OUT_SEC[11]
1000000001OUT_SEC[12]
1000000010OUT_SEC[13]
1000000100OUT_HALF1[17]
1000001000OUT_HALF1[16]
1000010000OUT_HALF1[15]
1000100000OUT_HALF1[14]
virtex2 INT_DCM_V2P switchbox INT muxes OMUX[9]
BitsDestination
MAIN[6][48]MAIN[7][47]MAIN[7][48]MAIN[7][49]MAIN[6][42]MAIN[7][43]MAIN[6][44]MAIN[6][45]MAIN[7][46]MAIN[6][47]OMUX[9]
Source
0000000000off
0001000001IMUX_DCM_CLK[0]
0001000010IMUX_DCM_CLK[1]
0001000100IMUX_G2_DATA[0]
0001001000IMUX_G2_DATA[1]
0001010000IMUX_G2_DATA[2]
0001100000IMUX_G2_DATA[3]
0010000100OUT_SEC[2]
0010001000OUT_SEC[3]
0010010000OUT_SEC[4]
0010100000OUT_SEC[5]
0100000001OUT_SEC[6]
0100000010OUT_SEC[7]
0100000100OUT_SEC[8]
0100001000OUT_SEC[9]
0100010000OUT_SEC[10]
0100100000OUT_SEC[11]
1000000001OUT_SEC[12]
1000000010OUT_SEC[13]
1000000100OUT_HALF1[17]
1000001000OUT_HALF1[16]
1000010000OUT_HALF1[15]
1000100000OUT_HALF1[14]
virtex2 INT_DCM_V2P switchbox INT muxes OMUX[10]
BitsDestination
MAIN[6][51]MAIN[7][52]MAIN[7][51]MAIN[7][50]MAIN[6][56]MAIN[6][59]MAIN[6][50]MAIN[6][53]MAIN[7][54]MAIN[7][55]OMUX[10]
Source
0000000000off
0001000001IMUX_G2_DATA[4]
0001000010IMUX_G2_DATA[5]
0001000100IMUX_G2_DATA[6]
0001001000IMUX_G2_DATA[7]
0010000001OUT_SEC[2]
0010000010OUT_SEC[3]
0010000100OUT_SEC[4]
0010001000OUT_SEC[5]
0100000001OUT_SEC[8]
0100000010OUT_SEC[9]
0100000100OUT_SEC[10]
0100001000OUT_SEC[11]
0100010000OUT_SEC[6]
0100100000OUT_SEC[7]
1000000001OUT_HALF1[17]
1000000010OUT_HALF1[16]
1000000100OUT_HALF1[15]
1000001000OUT_HALF1[14]
1000010000OUT_SEC[12]
1000100000OUT_SEC[13]
virtex2 INT_DCM_V2P switchbox INT muxes OMUX[11]
BitsDestination
MAIN[6][58]MAIN[7][57]MAIN[7][58]MAIN[7][59]MAIN[7][56]MAIN[6][57]MAIN[6][52]MAIN[7][53]MAIN[6][54]MAIN[6][55]OMUX[11]
Source
0000000000off
0001000001IMUX_G2_DATA[4]
0001000010IMUX_G2_DATA[5]
0001000100IMUX_G2_DATA[6]
0001001000IMUX_G2_DATA[7]
0010000001OUT_SEC[2]
0010000010OUT_SEC[3]
0010000100OUT_SEC[4]
0010001000OUT_SEC[5]
0100000001OUT_SEC[8]
0100000010OUT_SEC[9]
0100000100OUT_SEC[10]
0100001000OUT_SEC[11]
0100010000OUT_SEC[6]
0100100000OUT_SEC[7]
1000000001OUT_HALF1[17]
1000000010OUT_HALF1[16]
1000000100OUT_HALF1[15]
1000001000OUT_HALF1[14]
1000010000OUT_SEC[12]
1000100000OUT_SEC[13]
virtex2 INT_DCM_V2P switchbox INT muxes OMUX[12]
BitsDestination
MAIN[6][61]MAIN[7][62]MAIN[7][61]MAIN[7][60]MAIN[6][66]MAIN[6][69]MAIN[6][60]MAIN[6][63]MAIN[7][64]MAIN[7][65]OMUX[12]
Source
0000000000off
0001000001IMUX_G3_DATA[4]
0001000010IMUX_G3_DATA[5]
0001000100IMUX_G3_DATA[6]
0001001000IMUX_G3_DATA[7]
0010000001OUT_SEC[2]
0010000010OUT_SEC[3]
0010000100OUT_SEC[4]
0010001000OUT_SEC[5]
0100000001OUT_SEC[8]
0100000010OUT_SEC[9]
0100000100OUT_SEC[10]
0100001000OUT_SEC[11]
0100010000OUT_SEC[6]
0100100000OUT_SEC[7]
1000000001OUT_HALF1[17]
1000000010OUT_HALF1[16]
1000000100OUT_HALF1[15]
1000001000OUT_HALF1[14]
1000010000OUT_SEC[12]
1000100000OUT_SEC[13]
virtex2 INT_DCM_V2P switchbox INT muxes OMUX[13]
BitsDestination
MAIN[6][68]MAIN[7][67]MAIN[7][68]MAIN[7][69]MAIN[7][66]MAIN[6][67]MAIN[6][62]MAIN[7][63]MAIN[6][64]MAIN[6][65]OMUX[13]
Source
0000000000off
0001000001IMUX_G3_DATA[4]
0001000010IMUX_G3_DATA[5]
0001000100IMUX_G3_DATA[6]
0001001000IMUX_G3_DATA[7]
0010000001OUT_SEC[2]
0010000010OUT_SEC[3]
0010000100OUT_SEC[4]
0010001000OUT_SEC[5]
0100000001OUT_SEC[8]
0100000010OUT_SEC[9]
0100000100OUT_SEC[10]
0100001000OUT_SEC[11]
0100010000OUT_SEC[6]
0100100000OUT_SEC[7]
1000000001OUT_HALF1[17]
1000000010OUT_HALF1[16]
1000000100OUT_HALF1[15]
1000001000OUT_HALF1[14]
1000010000OUT_SEC[12]
1000100000OUT_SEC[13]
virtex2 INT_DCM_V2P switchbox INT muxes OMUX[14]
BitsDestination
MAIN[6][71]MAIN[7][72]MAIN[7][71]MAIN[7][70]MAIN[6][70]MAIN[6][73]MAIN[7][74]MAIN[7][75]MAIN[6][76]MAIN[6][79]OMUX[14]
Source
0000000000off
0001000001IMUX_CE[2]
0001000010IMUX_CE[3]
0001000100IMUX_G3_DATA[0]
0001001000IMUX_G3_DATA[1]
0001010000IMUX_G3_DATA[2]
0001100000IMUX_G3_DATA[3]
0010000100OUT_SEC[2]
0010001000OUT_SEC[3]
0010010000OUT_SEC[4]
0010100000OUT_SEC[5]
0100000001OUT_SEC[6]
0100000010OUT_SEC[7]
0100000100OUT_SEC[8]
0100001000OUT_SEC[9]
0100010000OUT_SEC[10]
0100100000OUT_SEC[11]
1000000001OUT_SEC[12]
1000000010OUT_SEC[13]
1000000100OUT_HALF1[17]
1000001000OUT_HALF1[16]
1000010000OUT_HALF1[15]
1000100000OUT_HALF1[14]
virtex2 INT_DCM_V2P switchbox INT muxes OMUX[15]
BitsDestination
MAIN[6][78]MAIN[7][77]MAIN[7][78]MAIN[7][79]MAIN[6][72]MAIN[7][73]MAIN[6][74]MAIN[6][75]MAIN[7][76]MAIN[6][77]OMUX[15]
Source
0000000000off
0001000001IMUX_CE[2]
0001000010IMUX_CE[3]
0001000100IMUX_G3_DATA[0]
0001001000IMUX_G3_DATA[1]
0001010000IMUX_G3_DATA[2]
0001100000IMUX_G3_DATA[3]
0010000100OUT_SEC[2]
0010001000OUT_SEC[3]
0010010000OUT_SEC[4]
0010100000OUT_SEC[5]
0100000001OUT_SEC[6]
0100000010OUT_SEC[7]
0100000100OUT_SEC[8]
0100001000OUT_SEC[9]
0100010000OUT_SEC[10]
0100100000OUT_SEC[11]
1000000001OUT_SEC[12]
1000000010OUT_SEC[13]
1000000100OUT_HALF1[17]
1000001000OUT_HALF1[16]
1000010000OUT_HALF1[15]
1000100000OUT_HALF1[14]
virtex2 INT_DCM_V2P switchbox INT muxes DBL_W0[0]
BitsDestination
MAIN[16][5]MAIN[16][6]MAIN[17][6]MAIN[17][5]MAIN[15][7]MAIN[14][5]MAIN[14][4]MAIN[15][6]DBL_W0[0]
Source
00000000off
00010001OMUX_S0
00010010HEX_E6[0]
00011000HEX_N6[0]
00100001OMUX_NW10
00100010HEX_S6[1]
00101000HEX_W6[0]
01000001DBL_W2[0]
01000010HEX_N3[0]
01000100HEX_S3[0]
01001000DBL_N3[9]
10000001DBL_W2_N[8]
10000010DBL_S1[0]
10000100DBL_S2[2]
10001000DBL_N1[0]
virtex2 INT_DCM_V2P switchbox INT muxes DBL_W0[1]
BitsDestination
MAIN[16][13]MAIN[16][14]MAIN[17][14]MAIN[17][13]MAIN[15][15]MAIN[14][13]MAIN[14][12]MAIN[15][14]DBL_W0[1]
Source
00000000off
00010001OMUX[2]
00010010HEX_E6[1]
00011000HEX_N6[1]
00100001OMUX_W1
00100010HEX_S6[2]
00101000HEX_W6[1]
01000001DBL_W2[1]
01000010HEX_N3[1]
01000100HEX_S3[1]
01001000DBL_N2[0]
10000001DBL_W2_N[9]
10000010DBL_S1[1]
10000100DBL_S2[3]
10001000DBL_N1[1]
virtex2 INT_DCM_V2P switchbox INT muxes DBL_W0[2]
BitsDestination
MAIN[15][23]MAIN[14][20]MAIN[15][22]MAIN[14][21]MAIN[16][22]MAIN[16][21]MAIN[17][22]MAIN[17][21]DBL_W0[2]
Source
00000000off
00010001OMUX[4]
00010100DBL_S2[4]
00011000HEX_S3[2]
00100001OMUX[6]
00100010OMUX_WN14
00100100DBL_W2[0]
00101000DBL_W2[2]
01000001HEX_E6[2]
01000010HEX_S6[3]
01000100DBL_S1[2]
01001000HEX_N3[2]
10000001HEX_N6[2]
10000010HEX_W6[2]
10000100DBL_N1[2]
10001000DBL_N2[1]
virtex2 INT_DCM_V2P switchbox INT muxes DBL_W0[3]
BitsDestination
MAIN[16][30]MAIN[16][29]MAIN[17][30]MAIN[17][29]MAIN[15][31]MAIN[14][29]MAIN[14][28]MAIN[15][30]DBL_W0[3]
Source
00000000off
00010001OMUX_W6
00010010HEX_E6[3]
00011000HEX_N6[3]
00100001OMUX_NW10
00100010HEX_S6[4]
00101000HEX_W6[3]
01000001DBL_W2[1]
01000010DBL_S1[3]
01000100DBL_S2[5]
01001000DBL_N1[3]
10000001DBL_W2[3]
10000010HEX_N3[3]
10000100HEX_S3[3]
10001000DBL_N2[2]
virtex2 INT_DCM_V2P switchbox INT muxes DBL_W0[4]
BitsDestination
MAIN[16][38]MAIN[16][37]MAIN[17][38]MAIN[17][37]MAIN[15][39]MAIN[14][37]MAIN[14][36]MAIN[15][38]DBL_W0[4]
Source
00000000off
00010001OMUX_WS1
00010010HEX_E6[4]
00011000HEX_N6[4]
00100001OMUX_N12
00100010HEX_S6[5]
00101000HEX_W6[4]
01000001DBL_W2[2]
01000010DBL_S1[4]
01000100DBL_S2[6]
01001000DBL_N1[4]
10000001DBL_W2[4]
10000010HEX_N3[4]
10000100HEX_S3[4]
10001000DBL_N2[3]
virtex2 INT_DCM_V2P switchbox INT muxes DBL_W0[5]
BitsDestination
MAIN[16][46]MAIN[16][45]MAIN[17][46]MAIN[17][45]MAIN[15][47]MAIN[14][45]MAIN[14][44]MAIN[15][46]DBL_W0[5]
Source
00000000off
00010001OMUX_S3
00010010HEX_E6[5]
00011000HEX_N6[5]
00100001OMUX_WN14
00100010HEX_S6[6]
00101000HEX_W6[5]
01000001DBL_W2[3]
01000010DBL_S1[5]
01000100DBL_S2[7]
01001000DBL_N1[5]
10000001DBL_W2[5]
10000010HEX_N3[5]
10000100HEX_S3[5]
10001000DBL_N2[4]
virtex2 INT_DCM_V2P switchbox INT muxes DBL_W0[6]
BitsDestination
MAIN[15][55]MAIN[14][52]MAIN[15][54]MAIN[14][53]MAIN[16][54]MAIN[16][53]MAIN[17][53]MAIN[17][54]DBL_W0[6]
Source
00000000off
00010001OMUX[11]
00010100DBL_S2[8]
00011000HEX_S3[6]
00100001OMUX_W9
00100010OMUX_SW5
00100100DBL_W2[4]
00101000DBL_W2[6]
01000001HEX_S6[7]
01000010HEX_E6[6]
01000100DBL_S1[6]
01001000HEX_N3[6]
10000001HEX_W6[6]
10000010HEX_N6[6]
10000100DBL_N1[6]
10001000DBL_N2[5]
virtex2 INT_DCM_V2P switchbox INT muxes DBL_W0[7]
BitsDestination
MAIN[16][62]MAIN[16][61]MAIN[17][61]MAIN[17][62]MAIN[15][63]MAIN[14][61]MAIN[14][60]MAIN[15][62]DBL_W0[7]
Source
00000000off
00010001OMUX[9]
00010010HEX_S6[8]
00011000HEX_W6[7]
00100001OMUX_WS1
00100010HEX_E6[7]
00101000HEX_N6[7]
01000001DBL_W2[5]
01000010DBL_S1[7]
01000100DBL_S2[9]
01001000DBL_N1[7]
10000001DBL_W2[7]
10000010HEX_N3[7]
10000100HEX_S3[7]
10001000DBL_N2[6]
virtex2 INT_DCM_V2P switchbox INT muxes DBL_W0[8]
BitsDestination
MAIN[16][70]MAIN[16][69]MAIN[17][69]MAIN[17][70]MAIN[15][71]MAIN[14][69]MAIN[14][68]MAIN[15][70]DBL_W0[8]
Source
00000000off
00010001OMUX[13]
00010010HEX_S6[9]
00011000HEX_W6[8]
00100001OMUX_W14
00100010HEX_E6[8]
00101000HEX_N6[8]
01000001DBL_W2[6]
01000010DBL_S1[8]
01000100DBL_S3[0]
01001000DBL_N1[8]
10000001DBL_W2[8]
10000010HEX_N3[8]
10000100HEX_S3[8]
10001000DBL_N2[7]
virtex2 INT_DCM_V2P switchbox INT muxes DBL_W0[9]
BitsDestination
MAIN[15][79]MAIN[14][76]MAIN[14][77]MAIN[15][78]MAIN[16][78]MAIN[16][77]MAIN[17][77]MAIN[17][78]DBL_W0[9]
Source
00000000off
00010001OMUX[13]
00010010OMUX_SW5
00010100DBL_W2[7]
00011000DBL_W2[9]
00100001OMUX_S0
00100010OMUX[15]
00100100DBL_S3[1]
00101000HEX_S3[9]
01000001HEX_S7[0]
01000010HEX_E6[9]
01000100DBL_S1[9]
01001000HEX_N3[9]
10000001HEX_W6[9]
10000010HEX_N6[9]
10000100DBL_N1[9]
10001000DBL_N2[8]
virtex2 INT_DCM_V2P switchbox INT muxes DBL_E0[0]
BitsDestination
MAIN[17][7]MAIN[17][4]MAIN[16][4]MAIN[16][7]MAIN[15][5]MAIN[14][7]MAIN[15][4]MAIN[14][6]DBL_E0[0]
Source
00000000off
00010001OMUX_E2
00010010HEX_S6[1]
00011000HEX_W6[0]
00100001OMUX_EN8
00100010HEX_E6[0]
00101000HEX_N6[0]
01000001DBL_E2[0]
01000010DBL_S1[0]
01000100DBL_S2[2]
01001000DBL_N1[0]
10000001DBL_E2[2]
10000010HEX_N3[0]
10000100HEX_S3[0]
10001000DBL_N3[9]
virtex2 INT_DCM_V2P switchbox INT muxes DBL_E0[1]
BitsDestination
MAIN[17][15]MAIN[17][12]MAIN[16][12]MAIN[16][15]MAIN[15][13]MAIN[14][15]MAIN[15][12]MAIN[14][14]DBL_E0[1]
Source
00000000off
00010001OMUX_S4
00010010HEX_S6[2]
00011000HEX_W6[1]
00100001OMUX_N10
00100010HEX_E6[1]
00101000HEX_N6[1]
01000001DBL_E2[1]
01000010DBL_S1[1]
01000100DBL_S2[3]
01001000DBL_N1[1]
10000001DBL_E2[3]
10000010HEX_N3[1]
10000100HEX_S3[1]
10001000DBL_N2[0]
virtex2 INT_DCM_V2P switchbox INT muxes DBL_E0[2]
BitsDestination
MAIN[15][21]MAIN[15][20]MAIN[14][22]MAIN[14][23]MAIN[17][23]MAIN[17][20]MAIN[16][23]MAIN[16][20]DBL_E0[2]
Source
00000000off
00010001OMUX[4]
00010100DBL_S2[4]
00011000HEX_S3[2]
00100001OMUX_NE12
00100010OMUX[6]
00100100DBL_E2[2]
00101000DBL_E2[4]
01000001HEX_E6[2]
01000010HEX_S6[3]
01000100DBL_S1[2]
01001000HEX_N3[2]
10000001HEX_N6[2]
10000010HEX_W6[2]
10000100DBL_N1[2]
10001000DBL_N2[1]
virtex2 INT_DCM_V2P switchbox INT muxes DBL_E0[3]
BitsDestination
MAIN[17][31]MAIN[17][28]MAIN[16][28]MAIN[16][31]MAIN[15][29]MAIN[14][31]MAIN[15][28]MAIN[14][30]DBL_E0[3]
Source
00000000off
00010001OMUX_SE3
00010010HEX_S6[4]
00011000HEX_W6[3]
00100001OMUX_EN8
00100010HEX_E6[3]
00101000HEX_N6[3]
01000001DBL_E2[3]
01000010DBL_S1[3]
01000100DBL_S2[5]
01001000DBL_N1[3]
10000001DBL_E2[5]
10000010HEX_N3[3]
10000100HEX_S3[3]
10001000DBL_N2[2]
virtex2 INT_DCM_V2P switchbox INT muxes DBL_E0[4]
BitsDestination
MAIN[17][39]MAIN[17][36]MAIN[16][39]MAIN[16][36]MAIN[15][37]MAIN[14][39]MAIN[15][36]MAIN[14][38]DBL_E0[4]
Source
00000000off
00010001OMUX_E7
00010010HEX_E6[4]
00011000HEX_N6[4]
00100001OMUX_E8
00100010HEX_S6[5]
00101000HEX_W6[4]
01000001DBL_E2[4]
01000010DBL_S1[4]
01000100DBL_S2[6]
01001000DBL_N1[4]
10000001DBL_E2[6]
10000010HEX_N3[4]
10000100HEX_S3[4]
10001000DBL_N2[3]
virtex2 INT_DCM_V2P switchbox INT muxes DBL_E0[5]
BitsDestination
MAIN[17][47]MAIN[17][44]MAIN[16][44]MAIN[16][47]MAIN[15][45]MAIN[14][47]MAIN[15][44]MAIN[14][46]DBL_E0[5]
Source
00000000off
00010001OMUX_ES7
00010010HEX_S6[6]
00011000HEX_W6[5]
00100001OMUX_NE12
00100010HEX_E6[5]
00101000HEX_N6[5]
01000001DBL_E2[5]
01000010DBL_S1[5]
01000100DBL_S2[7]
01001000DBL_N1[5]
10000001DBL_E2[7]
10000010HEX_N3[5]
10000100HEX_S3[5]
10001000DBL_N2[4]
virtex2 INT_DCM_V2P switchbox INT muxes DBL_E0[6]
BitsDestination
MAIN[17][55]MAIN[17][52]MAIN[16][55]MAIN[16][52]MAIN[15][53]MAIN[15][52]MAIN[14][55]MAIN[14][54]DBL_E0[6]
Source
00000000off
00010001OMUX[9]
00010100HEX_E6[6]
00011000HEX_N6[6]
00100001OMUX_SE3
00100010OMUX[11]
00100100HEX_S6[7]
00101000HEX_W6[6]
01000001DBL_E2[6]
01000010DBL_S2[8]
01000100DBL_S1[6]
01001000DBL_N1[6]
10000001DBL_E2[8]
10000010HEX_S3[6]
10000100HEX_N3[6]
10001000DBL_N2[5]
virtex2 INT_DCM_V2P switchbox INT muxes DBL_E0[7]
BitsDestination
MAIN[17][63]MAIN[17][60]MAIN[16][60]MAIN[16][63]MAIN[15][61]MAIN[14][63]MAIN[15][60]MAIN[14][62]DBL_E0[7]
Source
00000000off
00010001OMUX_S5
00010010HEX_S6[8]
00011000HEX_W6[7]
00100001OMUX_N11
00100010HEX_E6[7]
00101000HEX_N6[7]
01000001DBL_E2[7]
01000010DBL_S1[7]
01000100DBL_S2[9]
01001000DBL_N1[7]
10000001DBL_E2[9]
10000010HEX_N3[7]
10000100HEX_S3[7]
10001000DBL_N2[6]
virtex2 INT_DCM_V2P switchbox INT muxes DBL_E0[8]
BitsDestination
MAIN[17][71]MAIN[17][68]MAIN[16][68]MAIN[16][71]MAIN[15][69]MAIN[14][71]MAIN[15][68]MAIN[14][70]DBL_E0[8]
Source
00000000off
00010001OMUX_ES7
00010010HEX_S6[9]
00011000HEX_W6[8]
00100001OMUX_E13
00100010HEX_E6[8]
00101000HEX_N6[8]
01000001DBL_E2[8]
01000010DBL_S1[8]
01000100DBL_S3[0]
01001000DBL_N1[8]
10000001DBL_E2_S[0]
10000010HEX_N3[8]
10000100HEX_S3[8]
10001000DBL_N2[7]
virtex2 INT_DCM_V2P switchbox INT muxes DBL_E0[9]
BitsDestination
MAIN[17][79]MAIN[17][76]MAIN[16][79]MAIN[16][76]MAIN[15][77]MAIN[15][76]MAIN[14][78]MAIN[14][79]DBL_E0[9]
Source
00000000off
00010001OMUX[15]
00010010OMUX_N15
00010100HEX_E6[9]
00011000HEX_N6[9]
00100001OMUX_S0
00100010OMUX_S2
00100100HEX_S7[0]
00101000HEX_W6[9]
01000001DBL_S3[1]
01000010DBL_E2[9]
01000100DBL_S1[9]
01001000DBL_N1[9]
10000001HEX_S3[9]
10000010DBL_E2_S[1]
10000100HEX_N3[9]
10001000DBL_N2[8]
virtex2 INT_DCM_V2P switchbox INT muxes DBL_S0[0]
BitsDestination
MAIN[15][0]MAIN[15][1]MAIN[14][2]MAIN[14][3]MAIN[17][3]MAIN[17][0]MAIN[16][3]MAIN[16][0]DBL_S0[0]
Source
00000000off
00010001OMUX[0]
00010100DBL_E2[1]
00011000HEX_E3[0]
00100001OMUX[2]
00100010OMUX_S0
00100100DBL_S2[0]
00101000DBL_S2[2]
01000001HEX_W6_N[9]
01000010HEX_N6[0]
01000100DBL_W1[0]
01001000DBL_W2_N[8]
10000001HEX_S6[0]
10000010HEX_E6[0]
10000100DBL_E1[0]
10001000HEX_W3[0]
virtex2 INT_DCM_V2P switchbox INT muxes DBL_S0[1]
BitsDestination
MAIN[17][11]MAIN[17][8]MAIN[16][8]MAIN[16][11]MAIN[14][11]MAIN[15][8]MAIN[15][9]MAIN[14][10]DBL_S0[1]
Source
00000000off
00010001OMUX[2]
00010010HEX_N6[1]
00010100HEX_E6[1]
00100001OMUX_E2
00100010HEX_W6[0]
00100100HEX_S6[1]
01000001DBL_S2[1]
01000010DBL_W1[1]
01000100DBL_E1[1]
01001000DBL_E2[2]
10000001DBL_S2[3]
10000010DBL_W2_N[9]
10000100HEX_W3[1]
10001000HEX_E3[1]
virtex2 INT_DCM_V2P switchbox INT muxes DBL_S0[2]
BitsDestination
MAIN[15][16]MAIN[15][17]MAIN[14][18]MAIN[14][19]MAIN[17][19]MAIN[17][16]MAIN[16][16]MAIN[16][19]DBL_S0[2]
Source
00000000off
00010001OMUX[4]
00010100DBL_E2[3]
00011000HEX_E3[2]
00100001OMUX[6]
00100010OMUX_S4
00100100DBL_S2[2]
00101000DBL_S2[4]
01000001HEX_N6[2]
01000010HEX_W6[1]
01000100DBL_W1[2]
01001000DBL_W2[0]
10000001HEX_E6[2]
10000010HEX_S6[2]
10000100DBL_E1[2]
10001000HEX_W3[2]
virtex2 INT_DCM_V2P switchbox INT muxes DBL_S0[3]
BitsDestination
MAIN[17][27]MAIN[17][24]MAIN[16][27]MAIN[16][24]MAIN[14][27]MAIN[15][24]MAIN[15][25]MAIN[14][26]DBL_S0[3]
Source
00000000off
00010001OMUX[6]
00010010HEX_W6[2]
00010100HEX_S6[3]
00100001OMUX_W6
00100010HEX_N6[3]
00100100HEX_E6[3]
01000001DBL_S2[3]
01000010DBL_W1[3]
01000100DBL_E1[3]
01001000DBL_E2[4]
10000001DBL_S2[5]
10000010DBL_W2[1]
10000100HEX_W3[3]
10001000HEX_E3[3]
virtex2 INT_DCM_V2P switchbox INT muxes DBL_S0[4]
BitsDestination
MAIN[17][35]MAIN[17][32]MAIN[16][32]MAIN[16][35]MAIN[14][35]MAIN[15][32]MAIN[15][33]MAIN[14][34]DBL_S0[4]
Source
00000000off
00010001OMUX_WS1
00010010HEX_N6[4]
00010100HEX_E6[4]
00100001OMUX_SE3
00100010HEX_W6[3]
00100100HEX_S6[4]
01000001DBL_S2[4]
01000010DBL_W1[4]
01000100DBL_E1[4]
01001000DBL_E2[5]
10000001DBL_S2[6]
10000010DBL_W2[2]
10000100HEX_W3[4]
10001000HEX_E3[4]
virtex2 INT_DCM_V2P switchbox INT muxes DBL_S0[5]
BitsDestination
MAIN[17][43]MAIN[17][40]MAIN[16][40]MAIN[16][43]MAIN[14][43]MAIN[15][40]MAIN[15][41]MAIN[14][42]DBL_S0[5]
Source
00000000off
00010001OMUX_S3
00010010HEX_N6[5]
00010100HEX_E6[5]
00100001OMUX_E8
00100010HEX_W6[4]
00100100HEX_S6[5]
01000001DBL_S2[5]
01000010DBL_W1[5]
01000100DBL_E1[5]
01001000DBL_E2[6]
10000001DBL_S2[7]
10000010DBL_W2[3]
10000100HEX_W3[5]
10001000HEX_E3[5]
virtex2 INT_DCM_V2P switchbox INT muxes DBL_S0[6]
BitsDestination
MAIN[17][51]MAIN[17][48]MAIN[16][48]MAIN[16][51]MAIN[14][51]MAIN[15][48]MAIN[15][49]MAIN[14][50]DBL_S0[6]
Source
00000000off
00010001OMUX_SW5
00010010HEX_N6[6]
00010100HEX_E6[6]
00100001OMUX_ES7
00100010HEX_W6[5]
00100100HEX_S6[6]
01000001DBL_S2[6]
01000010DBL_W1[6]
01000100DBL_E1[6]
01001000DBL_E2[7]
10000001DBL_S2[8]
10000010DBL_W2[4]
10000100HEX_W3[6]
10001000HEX_E3[6]
virtex2 INT_DCM_V2P switchbox INT muxes DBL_S0[7]
BitsDestination
MAIN[15][56]MAIN[15][57]MAIN[14][58]MAIN[14][59]MAIN[17][59]MAIN[17][56]MAIN[16][59]MAIN[16][56]DBL_S0[7]
Source
00000000off
00010001OMUX[11]
00010100DBL_E2[8]
00011000HEX_E3[7]
00100001OMUX_SE3
00100010OMUX_WS1
00100100DBL_S2[7]
00101000DBL_S2[9]
01000001HEX_W6[6]
01000010HEX_N6[7]
01000100DBL_W1[7]
01001000DBL_W2[5]
10000001HEX_S6[7]
10000010HEX_E6[7]
10000100DBL_E1[7]
10001000HEX_W3[7]
virtex2 INT_DCM_V2P switchbox INT muxes DBL_S0[8]
BitsDestination
MAIN[17][67]MAIN[17][64]MAIN[16][67]MAIN[16][64]MAIN[14][67]MAIN[15][64]MAIN[15][65]MAIN[14][66]DBL_S0[8]
Source
00000000off
00010001OMUX_S5
00010010HEX_W6[7]
00010100HEX_S6[8]
00100001OMUX_W14
00100010HEX_N6[8]
00100100HEX_E6[8]
01000001DBL_S2[8]
01000010DBL_W1[8]
01000100DBL_E1[8]
01001000DBL_E2[9]
10000001DBL_S3[0]
10000010DBL_W2[6]
10000100HEX_W3[8]
10001000HEX_E3[8]
virtex2 INT_DCM_V2P switchbox INT muxes DBL_S0[9]
BitsDestination
MAIN[15][72]MAIN[15][73]MAIN[14][74]MAIN[14][75]MAIN[17][75]MAIN[17][72]MAIN[16][72]MAIN[16][75]DBL_S0[9]
Source
00000000off
00010001OMUX[15]
00010100DBL_E2_S[0]
00011000HEX_E3[9]
00100001OMUX_SW5
00100010OMUX_ES7
00100100DBL_S2[9]
00101000DBL_S3[1]
01000001HEX_N6[9]
01000010HEX_W6[8]
01000100DBL_W1[9]
01001000DBL_W2[7]
10000001HEX_E6[9]
10000010HEX_S6[9]
10000100DBL_E1[9]
10001000HEX_W3[9]
virtex2 INT_DCM_V2P switchbox INT muxes DBL_N0[0]
BitsDestination
MAIN[14][0]MAIN[15][3]MAIN[15][2]MAIN[14][1]MAIN[16][2]MAIN[16][1]MAIN[17][2]MAIN[17][1]DBL_N0[0]
Source
00000000off
00010001OMUX[0]
00010100DBL_E2[1]
00011000HEX_E3[0]
00100001OMUX_N13
00100010OMUX_EN8
00100100DBL_N3[8]
00101000DBL_N2[0]
01000001HEX_W6_N[9]
01000010HEX_N6[0]
01000100DBL_W1[0]
01001000DBL_W2_N[8]
10000001HEX_S6[0]
10000010HEX_E6[0]
10000100DBL_E1[0]
10001000HEX_W3[0]
virtex2 INT_DCM_V2P switchbox INT muxes DBL_N0[1]
BitsDestination
MAIN[16][10]MAIN[16][9]MAIN[17][9]MAIN[17][10]MAIN[14][9]MAIN[14][8]MAIN[15][11]MAIN[15][10]DBL_N0[1]
Source
00000000off
00010001OMUX_N10
00010010HEX_N6[1]
00010100HEX_E6[1]
00100001OMUX_NW10
00100010HEX_W6[0]
00100100HEX_S6[1]
01000001DBL_N3[9]
01000010DBL_W1[1]
01000100DBL_E1[1]
01001000DBL_E2[2]
10000001DBL_N2[1]
10000010DBL_W2_N[9]
10000100HEX_W3[1]
10001000HEX_E3[1]
virtex2 INT_DCM_V2P switchbox INT muxes DBL_N0[2]
BitsDestination
MAIN[14][16]MAIN[15][19]MAIN[15][18]MAIN[14][17]MAIN[16][18]MAIN[16][17]MAIN[17][17]MAIN[17][18]DBL_N0[2]
Source
00000000off
00010001OMUX[4]
00010100DBL_E2[3]
00011000HEX_E3[2]
00100001OMUX_NE12
00100010OMUX_W1
00100100DBL_N2[0]
00101000DBL_N2[2]
01000001HEX_N6[2]
01000010HEX_W6[1]
01000100DBL_W1[2]
01001000DBL_W2[0]
10000001HEX_E6[2]
10000010HEX_S6[2]
10000100DBL_E1[2]
10001000HEX_W3[2]
virtex2 INT_DCM_V2P switchbox INT muxes DBL_N0[3]
BitsDestination
MAIN[16][26]MAIN[16][25]MAIN[17][25]MAIN[17][26]MAIN[14][25]MAIN[14][24]MAIN[15][27]MAIN[15][26]DBL_N0[3]
Source
00000000off
00010001OMUX_EN8
00010010HEX_N6[3]
00010100HEX_E6[3]
00100001OMUX_WN14
00100010HEX_W6[2]
00100100HEX_S6[3]
01000001DBL_N2[1]
01000010DBL_W1[3]
01000100DBL_E1[3]
01001000DBL_E2[4]
10000001DBL_N2[3]
10000010DBL_W2[1]
10000100HEX_W3[3]
10001000HEX_E3[3]
virtex2 INT_DCM_V2P switchbox INT muxes DBL_N0[4]
BitsDestination
MAIN[16][34]MAIN[16][33]MAIN[17][33]MAIN[17][34]MAIN[14][33]MAIN[14][32]MAIN[15][35]MAIN[15][34]DBL_N0[4]
Source
00000000off
00010001OMUX_E7
00010010HEX_N6[4]
00010100HEX_E6[4]
00100001OMUX_NW10
00100010HEX_W6[3]
00100100HEX_S6[4]
01000001DBL_N2[2]
01000010DBL_W1[4]
01000100DBL_E1[4]
01001000DBL_E2[5]
10000001DBL_N2[4]
10000010DBL_W2[2]
10000100HEX_W3[4]
10001000HEX_E3[4]
virtex2 INT_DCM_V2P switchbox INT muxes DBL_N0[5]
BitsDestination
MAIN[16][42]MAIN[16][41]MAIN[17][42]MAIN[17][41]MAIN[14][41]MAIN[14][40]MAIN[15][43]MAIN[15][42]DBL_N0[5]
Source
00000000off
00010001OMUX_N12
00010010HEX_W6[4]
00010100HEX_S6[5]
00100001OMUX_NE12
00100010HEX_N6[5]
00100100HEX_E6[5]
01000001DBL_N2[3]
01000010DBL_W1[5]
01000100DBL_E1[5]
01001000DBL_E2[6]
10000001DBL_N2[5]
10000010DBL_W2[3]
10000100HEX_W3[5]
10001000HEX_E3[5]
virtex2 INT_DCM_V2P switchbox INT muxes DBL_N0[6]
BitsDestination
MAIN[16][50]MAIN[16][49]MAIN[17][49]MAIN[17][50]MAIN[14][49]MAIN[14][48]MAIN[15][51]MAIN[15][50]DBL_N0[6]
Source
00000000off
00010001OMUX[9]
00010010HEX_N6[6]
00010100HEX_E6[6]
00100001OMUX_WN14
00100010HEX_W6[5]
00100100HEX_S6[6]
01000001DBL_N2[4]
01000010DBL_W1[6]
01000100DBL_E1[6]
01001000DBL_E2[7]
10000001DBL_N2[6]
10000010DBL_W2[4]
10000100HEX_W3[6]
10001000HEX_E3[6]
virtex2 INT_DCM_V2P switchbox INT muxes DBL_N0[7]
BitsDestination
MAIN[14][56]MAIN[15][59]MAIN[15][58]MAIN[14][57]MAIN[16][58]MAIN[16][57]MAIN[17][58]MAIN[17][57]DBL_N0[7]
Source
00000000off
00010001OMUX[11]
00010100DBL_E2[8]
00011000HEX_E3[7]
00100001OMUX_W9
00100010OMUX_N11
00100100DBL_N2[5]
00101000DBL_N2[7]
01000001HEX_W6[6]
01000010HEX_N6[7]
01000100DBL_W1[7]
01001000DBL_W2[5]
10000001HEX_S6[7]
10000010HEX_E6[7]
10000100DBL_E1[7]
10001000HEX_W3[7]
virtex2 INT_DCM_V2P switchbox INT muxes DBL_N0[8]
BitsDestination
MAIN[16][66]MAIN[16][65]MAIN[17][66]MAIN[17][65]MAIN[14][65]MAIN[14][64]MAIN[15][67]MAIN[15][66]DBL_N0[8]
Source
00000000off
00010001OMUX[9]
00010010HEX_W6[7]
00010100HEX_S6[8]
00100001OMUX_E13
00100010HEX_N6[8]
00100100HEX_E6[8]
01000001DBL_N2[6]
01000010DBL_W1[8]
01000100DBL_E1[8]
01001000DBL_E2[9]
10000001DBL_N2[8]
10000010DBL_W2[6]
10000100HEX_W3[8]
10001000HEX_E3[8]
virtex2 INT_DCM_V2P switchbox INT muxes DBL_N0[9]
BitsDestination
MAIN[16][74]MAIN[16][73]MAIN[17][74]MAIN[17][73]MAIN[14][72]MAIN[15][75]MAIN[14][73]MAIN[15][74]DBL_N0[9]
Source
00000000off
00010001OMUX[13]
00010100HEX_W6[8]
00011000HEX_S6[9]
00100001OMUX_N15
00100010OMUX[15]
00100100HEX_N6[9]
00101000HEX_E6[9]
01000001DBL_N2[7]
01000010DBL_E2_S[0]
01000100DBL_W1[9]
01001000DBL_E1[9]
10000001DBL_N2[9]
10000010HEX_E3[9]
10000100DBL_W2[7]
10001000HEX_W3[9]
virtex2 INT_DCM_V2P switchbox INT muxes HEX_W0[0]
BitsDestination
MAIN[20][4]MAIN[20][6]MAIN[20][5]MAIN[18][4]MAIN[19][6]MAIN[18][6]MAIN[19][4]HEX_W0[0]
Source
0000000off
0010001OMUX_S0
0010010HEX_S3[0]
0010100HEX_N3[0]
0011000LH[6]
0100010OMUX_NW10
0100100HEX_W6[0]
0101000HEX_W6_N[8]
1000010LH[18]
1000100HEX_N7[9]
1001000HEX_S6[2]
virtex2 INT_DCM_V2P switchbox INT muxes HEX_W0[1]
BitsDestination
MAIN[21][12]MAIN[20][15]MAIN[21][14]MAIN[18][13]MAIN[19][15]MAIN[18][15]MAIN[19][13]HEX_W0[1]
Source
0000000off
0010001OMUX[2]
0010100HEX_W6[1]
0011000HEX_W6_N[9]
0100001LH[0]
0100010OMUX_W1
0100100HEX_S3[1]
0101000HEX_N3[1]
1000010LH[12]
1000100HEX_N6[0]
1001000HEX_S6[3]
virtex2 INT_DCM_V2P switchbox INT muxes HEX_W0[2]
BitsDestination
MAIN[19][22]MAIN[18][20]MAIN[18][22]MAIN[19][20]MAIN[20][22]MAIN[20][21]MAIN[20][20]HEX_W0[2]
Source
0000000off
0001001OMUX[4]
0001010OMUX[6]
0010001LH[18]
0010010HEX_S3[2]
0010100OMUX_WN14
0100001HEX_S6[4]
0100010LH[6]
0100100HEX_W6[0]
1000001HEX_N6[1]
1000010HEX_N3[2]
1000100HEX_W6[2]
virtex2 INT_DCM_V2P switchbox INT muxes HEX_W0[3]
BitsDestination
MAIN[21][28]MAIN[20][31]MAIN[21][30]MAIN[19][31]MAIN[18][29]MAIN[18][31]MAIN[19][29]HEX_W0[3]
Source
0000000off
0010001OMUX_W6
0010100HEX_W6[1]
0011000HEX_W6[3]
0100001LH[0]
0100010OMUX_NW10
0100100HEX_N3[3]
0101000HEX_S3[3]
1000010LH[12]
1000100HEX_S6[5]
1001000HEX_N6[2]
virtex2 INT_DCM_V2P switchbox INT muxes HEX_W0[4]
BitsDestination
MAIN[20][36]MAIN[20][38]MAIN[20][37]MAIN[19][38]MAIN[18][36]MAIN[18][38]MAIN[19][36]HEX_W0[4]
Source
0000000off
0010001OMUX_WS1
0010010HEX_S3[4]
0010100LH[6]
0011000HEX_N3[4]
0100010OMUX_N12
0100100HEX_W6[2]
0101000HEX_W6[4]
1000010LH[18]
1000100HEX_S6[6]
1001000HEX_N6[3]
virtex2 INT_DCM_V2P switchbox INT muxes HEX_W0[5]
BitsDestination
MAIN[21][44]MAIN[20][47]MAIN[21][46]MAIN[19][47]MAIN[18][45]MAIN[18][47]MAIN[19][45]HEX_W0[5]
Source
0000000off
0010001OMUX_S3
0010100HEX_W6[3]
0011000HEX_W6[5]
0100001LH[0]
0100010OMUX_WN14
0100100HEX_N3[5]
0101000HEX_S3[5]
1000010LH[12]
1000100HEX_S6[7]
1001000HEX_N6[4]
virtex2 INT_DCM_V2P switchbox INT muxes HEX_W0[6]
BitsDestination
MAIN[20][52]MAIN[20][53]MAIN[20][54]MAIN[19][54]MAIN[18][52]MAIN[18][54]MAIN[19][52]HEX_W0[6]
Source
0000000off
0010001OMUX[11]
0010010OMUX_W9
0010100HEX_W6[4]
0011000HEX_W6[6]
0100001OMUX_SW5
0100010HEX_S3[6]
0100100LH[6]
0101000HEX_N3[6]
1000010LH[18]
1000100HEX_S6[8]
1001000HEX_N6[5]
virtex2 INT_DCM_V2P switchbox INT muxes HEX_W0[7]
BitsDestination
MAIN[21][60]MAIN[21][62]MAIN[20][63]MAIN[19][63]MAIN[18][61]MAIN[19][61]MAIN[18][63]HEX_W0[7]
Source
0000000off
0010001OMUX[9]
0010010LH[0]
0010100HEX_N3[7]
0011000HEX_S3[7]
0100010OMUX_WS1
0100100HEX_W6[5]
0101000HEX_W6[7]
1000001LH[12]
1000100HEX_S6[9]
1001000HEX_N6[6]
virtex2 INT_DCM_V2P switchbox INT muxes HEX_W0[8]
BitsDestination
MAIN[20][68]MAIN[20][69]MAIN[20][70]MAIN[19][70]MAIN[18][68]MAIN[19][68]MAIN[18][70]HEX_W0[8]
Source
0000000off
0010001OMUX[13]
0010100HEX_W6[6]
0011000HEX_W6[8]
0100001HEX_S3[8]
0100010OMUX_W14
0100100LH[6]
0101000HEX_N3[8]
1000001LH[18]
1000100HEX_S7[0]
1001000HEX_N6[7]
virtex2 INT_DCM_V2P switchbox INT muxes HEX_W0[9]
BitsDestination
MAIN[21][78]MAIN[21][76]MAIN[20][79]MAIN[19][79]MAIN[18][77]MAIN[19][77]MAIN[18][79]HEX_W0[9]
Source
0000000off
0010001OMUX[13]
0010010LH[0]
0010100HEX_N3[9]
0011000HEX_S3[9]
0100001LH[12]
0100010OMUX[15]
0100100HEX_S7[1]
0101000HEX_N6[8]
1000001OMUX_S0
1000010OMUX_SW5
1000100HEX_W6[7]
1001000HEX_W6[9]
virtex2 INT_DCM_V2P switchbox INT muxes HEX_E0[0]
BitsDestination
MAIN[21][4]MAIN[21][6]MAIN[20][7]MAIN[19][7]MAIN[18][5]MAIN[19][5]MAIN[18][7]HEX_E0[0]
Source
0000000off
0010001OMUX_E2
0010010LH[6]
0010100HEX_N3[0]
0011000HEX_S3[0]
0100010OMUX_EN8
0100100HEX_E6[0]
0101000HEX_E6[2]
1000001LH[18]
1000100HEX_S6[2]
1001000HEX_N7[9]
virtex2 INT_DCM_V2P switchbox INT muxes HEX_E0[1]
BitsDestination
MAIN[20][12]MAIN[20][13]MAIN[20][14]MAIN[19][14]MAIN[18][12]MAIN[19][12]MAIN[18][14]HEX_E0[1]
Source
0000000off
0010001OMUX_S4
0010100HEX_E6[1]
0011000HEX_E6[3]
0100001HEX_S3[1]
0100010OMUX_N10
0100100LH[0]
0101000HEX_N3[1]
1000001LH[12]
1000100HEX_S6[3]
1001000HEX_N6[0]
virtex2 INT_DCM_V2P switchbox INT muxes HEX_E0[2]
BitsDestination
MAIN[21][22]MAIN[20][23]MAIN[21][20]MAIN[19][23]MAIN[18][21]MAIN[18][23]MAIN[19][21]HEX_E0[2]
Source
0000000off
0010001OMUX[4]
0010010LH[18]
0010100HEX_S6[4]
0011000HEX_N6[1]
0100001LH[6]
0100010OMUX[6]
0100100HEX_N3[2]
0101000HEX_S3[2]
1000001OMUX_NE12
1000100HEX_E6[2]
1001000HEX_E6[4]
virtex2 INT_DCM_V2P switchbox INT muxes HEX_E0[3]
BitsDestination
MAIN[20][28]MAIN[20][29]MAIN[20][30]MAIN[19][30]MAIN[18][28]MAIN[19][28]MAIN[18][30]HEX_E0[3]
Source
0000000off
0010001OMUX_SE3
0010100HEX_E6[3]
0011000HEX_E6[5]
0100001HEX_S3[3]
0100010OMUX_EN8
0100100LH[0]
0101000HEX_N3[3]
1000001LH[12]
1000100HEX_S6[5]
1001000HEX_N6[2]
virtex2 INT_DCM_V2P switchbox INT muxes HEX_E0[4]
BitsDestination
MAIN[21][36]MAIN[20][39]MAIN[21][38]MAIN[19][39]MAIN[18][37]MAIN[18][39]MAIN[19][37]HEX_E0[4]
Source
0000000off
0010001OMUX_E7
0010100HEX_E6[4]
0011000HEX_E6[6]
0100001LH[6]
0100010OMUX_E8
0100100HEX_N3[4]
0101000HEX_S3[4]
1000010LH[18]
1000100HEX_S6[6]
1001000HEX_N6[3]
virtex2 INT_DCM_V2P switchbox INT muxes HEX_E0[5]
BitsDestination
MAIN[20][44]MAIN[20][45]MAIN[20][46]MAIN[19][46]MAIN[18][44]MAIN[19][44]MAIN[18][46]HEX_E0[5]
Source
0000000off
0010001OMUX_ES7
0010100HEX_E6[5]
0011000HEX_E6[7]
0100001HEX_S3[5]
0100010OMUX_NE12
0100100LH[0]
0101000HEX_N3[5]
1000001LH[12]
1000100HEX_S6[7]
1001000HEX_N6[4]
virtex2 INT_DCM_V2P switchbox INT muxes HEX_E0[6]
BitsDestination
MAIN[21][52]MAIN[20][55]MAIN[21][54]MAIN[19][55]MAIN[18][53]MAIN[18][55]MAIN[19][53]HEX_E0[6]
Source
0000000off
0010001OMUX[9]
0010010OMUX[11]
0010100HEX_E6[6]
0011000HEX_E6[8]
0100001LH[6]
0100010OMUX_SE3
0100100HEX_N3[6]
0101000HEX_S3[6]
1000010LH[18]
1000100HEX_S6[8]
1001000HEX_N6[5]
virtex2 INT_DCM_V2P switchbox INT muxes HEX_E0[7]
BitsDestination
MAIN[20][60]MAIN[20][61]MAIN[20][62]MAIN[19][62]MAIN[18][60]MAIN[19][60]MAIN[18][62]HEX_E0[7]
Source
0000000off
0010001OMUX_S5
0010100HEX_E6[7]
0011000HEX_E6[9]
0100001HEX_S3[7]
0100010OMUX_N11
0100100LH[0]
0101000HEX_N3[7]
1000001LH[12]
1000100HEX_S6[9]
1001000HEX_N6[6]
virtex2 INT_DCM_V2P switchbox INT muxes HEX_E0[8]
BitsDestination
MAIN[21][68]MAIN[21][70]MAIN[20][71]MAIN[19][71]MAIN[18][69]MAIN[19][69]MAIN[18][71]HEX_E0[8]
Source
0000000off
0010001OMUX_ES7
0010010LH[6]
0010100HEX_N3[8]
0011000HEX_S3[8]
0100010OMUX_E13
0100100HEX_E6[8]
0101000HEX_E6_S[0]
1000001LH[18]
1000100HEX_S7[0]
1001000HEX_N6[7]
virtex2 INT_DCM_V2P switchbox INT muxes HEX_E0[9]
BitsDestination
MAIN[20][77]MAIN[20][78]MAIN[20][76]MAIN[19][78]MAIN[18][76]MAIN[18][78]MAIN[19][76]HEX_E0[9]
Source
0000000off
0010001OMUX[15]
0010010LH[12]
0010100HEX_S7[1]
0011000HEX_N6[8]
0100001OMUX_S0
0100010OMUX_S2
0100100HEX_E6[9]
0101000HEX_E6_S[1]
1000001OMUX_N15
1000010HEX_S3[9]
1000100LH[0]
1001000HEX_N3[9]
virtex2 INT_DCM_V2P switchbox INT muxes HEX_S0[0]
BitsDestination
MAIN[20][3]MAIN[21][2]MAIN[21][0]MAIN[19][3]MAIN[18][1]MAIN[18][3]MAIN[19][1]HEX_S0[0]
Source
0000000off
0010001OMUX[0]
0010010LV[0]
0010100HEX_E6[1]
0011000HEX_W6_N[8]
0100001OMUX[2]
0100100HEX_S6[0]
0101000HEX_S6[2]
1000001LV[12]
1000010OMUX_S0
1000100HEX_W3[0]
1001000HEX_E3[0]
virtex2 INT_DCM_V2P switchbox INT muxes HEX_S0[1]
BitsDestination
MAIN[20][8]MAIN[20][9]MAIN[20][10]MAIN[18][8]MAIN[19][10]MAIN[19][8]MAIN[18][10]HEX_S0[1]
Source
0000000off
0010001OMUX[2]
0010100HEX_S6[3]
0011000HEX_S6[1]
0100001HEX_E3[1]
0100010OMUX_E2
0100100HEX_W3[1]
0101000LV[18]
1000001LV[6]
1000100HEX_W6_N[9]
1001000HEX_E6[2]
virtex2 INT_DCM_V2P switchbox INT muxes HEX_S0[2]
BitsDestination
MAIN[21][16]MAIN[20][19]MAIN[21][18]MAIN[19][19]MAIN[18][17]MAIN[19][17]MAIN[18][19]HEX_S0[2]
Source
0000000off
0010001OMUX[4]
0010010OMUX_S4
0010100HEX_S6[2]
0011000HEX_S6[4]
0100001OMUX[6]
0100010LV[12]
0100100HEX_W3[2]
0101000HEX_E3[2]
1000001LV[0]
1000100HEX_E6[3]
1001000HEX_W6[0]
virtex2 INT_DCM_V2P switchbox INT muxes HEX_S0[3]
BitsDestination
MAIN[20][24]MAIN[20][26]MAIN[20][25]MAIN[18][24]MAIN[19][26]MAIN[18][26]MAIN[19][24]HEX_S0[3]
Source
0000000off
0010001OMUX[6]
0010010HEX_E3[3]
0010100HEX_W3[3]
0011000LV[18]
0100010OMUX_W6
0100100HEX_S6[5]
0101000HEX_S6[3]
1000010LV[6]
1000100HEX_W6[1]
1001000HEX_E6[4]
virtex2 INT_DCM_V2P switchbox INT muxes HEX_S0[4]
BitsDestination
MAIN[21][32]MAIN[21][34]MAIN[20][35]MAIN[19][35]MAIN[18][33]MAIN[19][33]MAIN[18][35]HEX_S0[4]
Source
0000000off
0010001OMUX_WS1
0010010LV[12]
0010100HEX_W3[4]
0011000HEX_E3[4]
0100010OMUX_SE3
0100100HEX_S6[4]
0101000HEX_S6[6]
1000001LV[0]
1000100HEX_E6[5]
1001000HEX_W6[2]
virtex2 INT_DCM_V2P switchbox INT muxes HEX_S0[5]
BitsDestination
MAIN[20][40]MAIN[20][41]MAIN[20][42]MAIN[18][40]MAIN[19][42]MAIN[19][40]MAIN[18][42]HEX_S0[5]
Source
0000000off
0010001OMUX_S3
0010100HEX_S6[7]
0011000HEX_S6[5]
0100001HEX_E3[5]
0100010OMUX_E8
0100100HEX_W3[5]
0101000LV[18]
1000001LV[6]
1000100HEX_W6[3]
1001000HEX_E6[6]
virtex2 INT_DCM_V2P switchbox INT muxes HEX_S0[6]
BitsDestination
MAIN[21][48]MAIN[21][50]MAIN[20][51]MAIN[19][51]MAIN[18][49]MAIN[19][49]MAIN[18][51]HEX_S0[6]
Source
0000000off
0010001OMUX_SW5
0010010LV[12]
0010100HEX_W3[6]
0011000HEX_E3[6]
0100010OMUX_ES7
0100100HEX_S6[6]
0101000HEX_S6[8]
1000001LV[0]
1000100HEX_E6[7]
1001000HEX_W6[4]
virtex2 INT_DCM_V2P switchbox INT muxes HEX_S0[7]
BitsDestination
MAIN[20][57]MAIN[20][58]MAIN[20][56]MAIN[18][56]MAIN[19][58]MAIN[18][58]MAIN[19][56]HEX_S0[7]
Source
0000000off
0010001OMUX[11]
0010010LV[6]
0010100HEX_W6[5]
0011000HEX_E6[8]
0100010OMUX_WS1
0100100HEX_S6[9]
0101000HEX_S6[7]
1000001OMUX_SE3
1000010HEX_E3[7]
1000100HEX_W3[7]
1001000LV[18]
virtex2 INT_DCM_V2P switchbox INT muxes HEX_S0[8]
BitsDestination
MAIN[21][64]MAIN[20][67]MAIN[21][66]MAIN[19][67]MAIN[18][65]MAIN[18][67]MAIN[19][65]HEX_S0[8]
Source
0000000off
0010001OMUX_S5
0010100HEX_S6[8]
0011000HEX_S7[0]
0100001LV[12]
0100010OMUX_W14
0100100HEX_W3[8]
0101000HEX_E3[8]
1000010LV[0]
1000100HEX_E6[9]
1001000HEX_W6[6]
virtex2 INT_DCM_V2P switchbox INT muxes HEX_S0[9]
BitsDestination
MAIN[20][72]MAIN[20][73]MAIN[20][74]MAIN[18][72]MAIN[19][74]MAIN[18][74]MAIN[19][72]HEX_S0[9]
Source
0000000off
0010001OMUX[15]
0010010OMUX_SW5
0010100HEX_S7[1]
0011000HEX_S6[9]
0100001OMUX_ES7
0100010HEX_E3[9]
0100100HEX_W3[9]
0101000LV[18]
1000010LV[6]
1000100HEX_W6[7]
1001000HEX_E6_S[0]
virtex2 INT_DCM_V2P switchbox INT muxes HEX_N0[0]
BitsDestination
MAIN[20][1]MAIN[20][2]MAIN[20][0]MAIN[18][0]MAIN[19][2]MAIN[18][2]MAIN[19][0]HEX_N0[0]
Source
0000000off
0010001OMUX[0]
0010010LV[0]
0010100HEX_W6_N[8]
0011000HEX_E6[1]
0100010OMUX_EN8
0100100HEX_N6[0]
0101000HEX_N7[8]
1000001OMUX_N13
1000010HEX_E3[0]
1000100HEX_W3[0]
1001000LV[12]
virtex2 INT_DCM_V2P switchbox INT muxes HEX_N0[1]
BitsDestination
MAIN[21][8]MAIN[21][10]MAIN[20][11]MAIN[19][11]MAIN[18][9]MAIN[19][9]MAIN[18][11]HEX_N0[1]
Source
0000000off
0010001OMUX_N10
0010010LV[18]
0010100HEX_W3[1]
0011000HEX_E3[1]
0100010OMUX_NW10
0100100HEX_N7[9]
0101000HEX_N6[1]
1000001LV[6]
1000100HEX_E6[2]
1001000HEX_W6_N[9]
virtex2 INT_DCM_V2P switchbox INT muxes HEX_N0[2]
BitsDestination
MAIN[20][16]MAIN[20][17]MAIN[20][18]MAIN[18][16]MAIN[19][18]MAIN[18][18]MAIN[19][16]HEX_N0[2]
Source
0000000off
0010001OMUX[4]
0010010OMUX_NE12
0010100HEX_N6[2]
0011000HEX_N6[0]
0100001OMUX_W1
0100010HEX_E3[2]
0100100HEX_W3[2]
0101000LV[12]
1000010LV[0]
1000100HEX_W6[0]
1001000HEX_E6[3]
virtex2 INT_DCM_V2P switchbox INT muxes HEX_N0[3]
BitsDestination
MAIN[21][24]MAIN[21][26]MAIN[20][27]MAIN[19][27]MAIN[18][25]MAIN[19][25]MAIN[18][27]HEX_N0[3]
Source
0000000off
0010001OMUX_EN8
0010010LV[18]
0010100HEX_W3[3]
0011000HEX_E3[3]
0100010OMUX_WN14
0100100HEX_N6[1]
0101000HEX_N6[3]
1000001LV[6]
1000100HEX_E6[4]
1001000HEX_W6[1]
virtex2 INT_DCM_V2P switchbox INT muxes HEX_N0[4]
BitsDestination
MAIN[20][32]MAIN[20][33]MAIN[20][34]MAIN[18][32]MAIN[19][34]MAIN[19][32]MAIN[18][34]HEX_N0[4]
Source
0000000off
0010001OMUX_E7
0010100HEX_N6[4]
0011000HEX_N6[2]
0100001HEX_E3[4]
0100010OMUX_NW10
0100100HEX_W3[4]
0101000LV[12]
1000001LV[0]
1000100HEX_W6[2]
1001000HEX_E6[5]
virtex2 INT_DCM_V2P switchbox INT muxes HEX_N0[5]
BitsDestination
MAIN[21][40]MAIN[20][43]MAIN[21][42]MAIN[19][43]MAIN[18][41]MAIN[18][43]MAIN[19][41]HEX_N0[5]
Source
0000000off
0010001OMUX_N12
0010100HEX_N6[3]
0011000HEX_N6[5]
0100001LV[18]
0100010OMUX_NE12
0100100HEX_W3[5]
0101000HEX_E3[5]
1000010LV[6]
1000100HEX_E6[6]
1001000HEX_W6[3]
virtex2 INT_DCM_V2P switchbox INT muxes HEX_N0[6]
BitsDestination
MAIN[20][48]MAIN[20][49]MAIN[20][50]MAIN[18][48]MAIN[19][50]MAIN[19][48]MAIN[18][50]HEX_N0[6]
Source
0000000off
0010001OMUX[9]
0010100HEX_N6[6]
0011000HEX_N6[4]
0100001HEX_E3[6]
0100010OMUX_WN14
0100100HEX_W3[6]
0101000LV[12]
1000001LV[0]
1000100HEX_W6[4]
1001000HEX_E6[7]
virtex2 INT_DCM_V2P switchbox INT muxes HEX_N0[7]
BitsDestination
MAIN[20][59]MAIN[21][58]MAIN[21][56]MAIN[19][59]MAIN[18][57]MAIN[18][59]MAIN[19][57]HEX_N0[7]
Source
0000000off
0010001OMUX[11]
0010010LV[6]
0010100HEX_E6[8]
0011000HEX_W6[5]
0100001OMUX_W9
0100100HEX_N6[5]
0101000HEX_N6[7]
1000001LV[18]
1000010OMUX_N11
1000100HEX_W3[7]
1001000HEX_E3[7]
virtex2 INT_DCM_V2P switchbox INT muxes HEX_N0[8]
BitsDestination
MAIN[20][64]MAIN[20][66]MAIN[20][65]MAIN[18][64]MAIN[19][66]MAIN[18][66]MAIN[19][64]HEX_N0[8]
Source
0000000off
0010001OMUX[9]
0010010HEX_E3[8]
0010100HEX_W3[8]
0011000LV[12]
0100010OMUX_E13
0100100HEX_N6[8]
0101000HEX_N6[6]
1000010LV[0]
1000100HEX_W6[6]
1001000HEX_E6[9]
virtex2 INT_DCM_V2P switchbox INT muxes HEX_N0[9]
BitsDestination
MAIN[21][72]MAIN[20][75]MAIN[21][74]MAIN[19][75]MAIN[18][73]MAIN[18][75]MAIN[19][73]HEX_N0[9]
Source
0000000off
0010001OMUX[13]
0010010OMUX[15]
0010100HEX_N6[7]
0011000HEX_N6[9]
0100001LV[18]
0100010OMUX_N15
0100100HEX_W3[9]
0101000HEX_E3[9]
1000010LV[6]
1000100HEX_E6_S[0]
1001000HEX_W6[7]
virtex2 INT_DCM_V2P switchbox INT muxes LH[0]
BitsDestination
MAIN[21][47]MAIN[21][49]MAIN[21][51]LH[0]
Source
000off
001DBL_W1[5]
011OMUX_S4
101DBL_E1[6]
111OMUX[11]
virtex2 INT_DCM_V2P switchbox INT muxes LH[6]
BitsDestination
MAIN[21][31]MAIN[21][33]MAIN[21][29]LH[6]
Source
000off
001OMUX[4]
011OMUX_N15
101DBL_E1[4]
111DBL_W1[3]
virtex2 INT_DCM_V2P switchbox INT muxes LH[12]
BitsDestination
MAIN[21][41]MAIN[21][45]MAIN[21][43]LH[12]
Source
000off
001DBL_W1[5]
011OMUX_S4
101DBL_E1[6]
111OMUX[11]
virtex2 INT_DCM_V2P switchbox INT muxes LH[18]
BitsDestination
MAIN[21][39]MAIN[21][37]MAIN[21][35]LH[18]
Source
000off
001OMUX[4]
011OMUX_N15
101DBL_E1[4]
111DBL_W1[3]
virtex2 INT_DCM_V2P switchbox INT muxes LV[0]
BitsDestination
MAIN[21][7]MAIN[21][9]MAIN[21][19]MAIN[21][25]MAIN[21][21]MAIN[21][11]MAIN[21][5]LV[0]
Source
0000000off
0000011HEX_E1[1]
0000101OMUX_E2
0001001DBL_W1[1]
0010001HEX_E6[1]
0100001HEX_E4[1]
1000011OMUX[0]
1000101HEX_E2[1]
1001001HEX_E5[1]
1010001DBL_E1[2]
1100001HEX_E3[1]
virtex2 INT_DCM_V2P switchbox INT muxes LV[6]
BitsDestination
MAIN[21][73]MAIN[21][61]MAIN[21][55]MAIN[21][69]MAIN[21][71]MAIN[21][65]MAIN[21][75]LV[6]
Source
0000000off
0000011OMUX_W9
0000101DBL_W1[7]
0001001HEX_W5[7]
0010001HEX_W3[7]
0100001HEX_W4[7]
1000011OMUX[15]
1000101HEX_W2[7]
1001001DBL_E1[8]
1010001HEX_W0[7]
1100001HEX_W1[7]
virtex2 INT_DCM_V2P switchbox INT muxes LV[12]
BitsDestination
MAIN[21][13]MAIN[21][1]MAIN[21][27]MAIN[21][23]MAIN[21][17]MAIN[21][3]MAIN[21][15]LV[12]
Source
0000000off
0000011HEX_E1[1]
0000101OMUX_E2
0001001DBL_W1[1]
0010001HEX_E6[1]
0100001HEX_E4[1]
1000011OMUX[0]
1000101HEX_E2[1]
1001001HEX_E5[1]
1010001DBL_E1[2]
1100001HEX_E3[1]
virtex2 INT_DCM_V2P switchbox INT muxes LV[18]
BitsDestination
MAIN[21][67]MAIN[21][53]MAIN[21][57]MAIN[21][77]MAIN[21][59]MAIN[21][79]MAIN[21][63]LV[18]
Source
0000000off
0000011OMUX_W9
0000101DBL_W1[7]
0001001HEX_W5[7]
0010001HEX_W3[7]
0100001HEX_W4[7]
1000011OMUX[15]
1000101HEX_W2[7]
1001001DBL_E1[8]
1010001HEX_W0[7]
1100001HEX_W1[7]
virtex2 INT_DCM_V2P switchbox INT muxes IMUX_DCM_CLK[0]
BitsDestination
MAIN[5][38]MAIN[5][39]MAIN[5][37]MAIN[4][39]MAIN[5][40]MAIN[5][42]MAIN[4][42]MAIN[4][40]MAIN[4][46]MAIN[5][48]MAIN[4][44]MAIN[5][44]IMUX_DCM_CLK[0]
Source
000000000000PULLUP
000100000001GCLK[0]
000100000010GCLK[1]
000100000100DCM_CLKPAD[0]
000100001000DCM_CLKPAD[1]
000100010000HEX_N3[6]
000100100000HEX_N0[6]
000101000000HEX_S6[6]
000110000000HEX_S3[6]
001000000001GCLK[2]
001000000010GCLK[3]
001000000100DCM_CLKPAD[2]
001000001000DCM_CLKPAD[3]
001000010000HEX_S2[6]
001000100000HEX_N1[6]
001001000000HEX_N4[6]
001010000000HEX_S4[6]
010000000001GCLK[4]
010000000010GCLK[5]
010000000100DCM_CLKPAD[4]
010000001000DCM_CLKPAD[5]
010000010000HEX_S1[6]
010000100000HEX_S5[6]
010001000000HEX_N5[6]
010010000000HEX_N2[6]
100000000001GCLK[7]
100000000010GCLK[6]
100000000100DCM_CLKPAD[6]
100000001000DCM_CLKPAD[7]
100000010000DBL_W1[5]
100000100000DBL_W2[5]
100001000000DBL_E0[5]
100010000000DBL_E1[5]
virtex2 INT_DCM_V2P switchbox INT muxes IMUX_DCM_CLK[1]
BitsDestination
MAIN[5][46]MAIN[5][47]MAIN[5][49]MAIN[4][47]MAIN[4][37]MAIN[4][41]MAIN[5][43]MAIN[5][41]MAIN[4][45]MAIN[4][49]MAIN[5][45]MAIN[4][43]IMUX_DCM_CLK[1]
Source
000000000000PULLUP
000100000001GCLK[0]
000100000010GCLK[1]
000100000100DCM_CLKPAD[0]
000100001000DCM_CLKPAD[1]
000100010000HEX_N3[6]
000100100000HEX_N0[6]
000101000000HEX_S6[6]
000110000000HEX_S3[6]
001000000001GCLK[2]
001000000010GCLK[3]
001000000100DCM_CLKPAD[2]
001000001000DCM_CLKPAD[3]
001000010000HEX_S2[6]
001000100000HEX_N1[6]
001001000000HEX_N4[6]
001010000000HEX_S4[6]
010000000001GCLK[4]
010000000010GCLK[5]
010000000100DCM_CLKPAD[4]
010000001000DCM_CLKPAD[5]
010000010000HEX_S1[6]
010000100000HEX_S5[6]
010001000000HEX_N5[6]
010010000000HEX_N2[6]
100000000001GCLK[7]
100000000010GCLK[6]
100000000100DCM_CLKPAD[6]
100000001000DCM_CLKPAD[7]
100000010000DBL_W1[5]
100000100000DBL_W2[5]
100001000000DBL_E0[5]
100010000000DBL_E1[5]
virtex2 INT_DCM_V2P switchbox INT muxes IMUX_DCM_CLK[2]
BitsDestination
MAIN[5][53]MAIN[5][52]MAIN[5][50]MAIN[4][52]MAIN[4][62]MAIN[4][58]MAIN[5][56]MAIN[5][58]MAIN[4][54]MAIN[4][50]MAIN[5][54]MAIN[4][56]IMUX_DCM_CLK[2]
Source
000000000000PULLUP
000100000001GCLK[0]
000100000010GCLK[1]
000100000100DCM_CLKPAD[0]
000100001000DCM_CLKPAD[1]
000100010000HEX_S6[6]
000100100000HEX_N3[6]
000101000000HEX_N0[6]
000110000000HEX_S4[6]
001000000001GCLK[2]
001000000010GCLK[3]
001000000100DCM_CLKPAD[2]
001000001000DCM_CLKPAD[3]
001000010000HEX_N5[6]
001000100000HEX_S3[6]
001001000000HEX_S2[6]
001010000000HEX_N2[6]
010000000001GCLK[4]
010000000010GCLK[5]
010000000100DCM_CLKPAD[4]
010000001000DCM_CLKPAD[5]
010000010000HEX_S1[6]
010000100000HEX_S5[6]
010001000000HEX_N4[6]
010010000000HEX_N1[6]
100000000001GCLK[7]
100000000010GCLK[6]
100000000100DCM_CLKPAD[6]
100000001000DCM_CLKPAD[7]
100000010000DBL_W1[6]
100000100000DBL_W2[6]
100001000000DBL_E0[6]
100010000000DBL_E1[6]
virtex2 INT_DCM_V2P switchbox INT muxes IMUX_SR[0]
BitsDestination
MAIN[5][3]MAIN[4][3]MAIN[5][5]MAIN[4][5]MAIN[5][1]MAIN[5][2]MAIN[4][2]MAIN[5][0]IMUX_SR[0]
Source
00000000PULLUP
00010001DBL_W1[0]
00010010HEX_N1[0]
00010100HEX_N5[0]
00011000HEX_S4[0]
00100001DBL_W2[0]
00100010HEX_S5[0]
00100100HEX_S1[0]
00101000HEX_N3[0]
01000001HEX_N2[0]
01000010DBL_E0[0]
01000100HEX_S2[0]
01001000HEX_N0[0]
10000001HEX_S3[0]
10000010DBL_E1[0]
10000100HEX_N4[0]
10001000HEX_S6[0]
virtex2 INT_DCM_V2P switchbox INT muxes IMUX_SR[1]
BitsDestination
MAIN[4][12]MAIN[5][12]MAIN[5][14]MAIN[4][14]MAIN[5][16]MAIN[5][15]MAIN[5][17]MAIN[4][15]IMUX_SR[1]
Source
00000000PULLUP
00010001DBL_W1[1]
00010010HEX_N2[0]
00010100HEX_S2[0]
00011000HEX_N0[0]
00100001DBL_W2[1]
00100010HEX_S3[0]
00100100HEX_N4[0]
00101000HEX_S6[0]
01000001HEX_S5[0]
01000010DBL_E0[1]
01000100HEX_S1[0]
01001000HEX_N3[0]
10000001HEX_N1[0]
10000010DBL_E1[1]
10000100HEX_N5[0]
10001000HEX_S4[0]
virtex2 INT_DCM_V2P switchbox INT muxes IMUX_SR[2]
BitsDestination
MAIN[4][0]MAIN[4][4]MAIN[4][8]MAIN[5][4]MAIN[5][7]MAIN[5][8]MAIN[4][6]MAIN[5][6]IMUX_SR[2]
Source
00000000PULLUP
00010001DBL_W1[0]
00010010HEX_N1[0]
00010100HEX_N5[0]
00011000HEX_S4[0]
00100001DBL_W2[0]
00100010HEX_S5[0]
00100100HEX_S1[0]
00101000HEX_N3[0]
01000001HEX_N2[0]
01000010DBL_E0[0]
01000100HEX_S2[0]
01001000HEX_N0[0]
10000001HEX_S3[0]
10000010DBL_E1[0]
10000100HEX_N4[0]
10001000HEX_S6[0]
virtex2 INT_DCM_V2P switchbox INT muxes IMUX_SR[3]
BitsDestination
MAIN[5][13]MAIN[4][9]MAIN[4][17]MAIN[4][13]MAIN[5][10]MAIN[5][9]MAIN[5][11]MAIN[4][11]IMUX_SR[3]
Source
00000000PULLUP
00010001DBL_W1[1]
00010010HEX_N2[0]
00010100HEX_S2[0]
00011000HEX_N0[0]
00100001DBL_W2[1]
00100010HEX_S3[0]
00100100HEX_N4[0]
00101000HEX_S6[0]
01000001HEX_S5[0]
01000010DBL_E0[1]
01000100HEX_S1[0]
01001000HEX_N3[0]
10000001HEX_N1[0]
10000010DBL_E1[1]
10000100HEX_N5[0]
10001000HEX_S4[0]
virtex2 INT_DCM_V2P switchbox INT muxes IMUX_CE[2]
BitsDestination
MAIN[5][75]MAIN[4][71]MAIN[4][79]MAIN[4][75]MAIN[5][72]MAIN[5][71]MAIN[5][73]MAIN[4][73]IMUX_CE[2]
Source
00000000PULLUP
00010001DBL_W1[9]
00010010HEX_S1[9]
00010100HEX_S2[9]
00011000HEX_S5[9]
00100001DBL_W2[9]
00100010HEX_N5[9]
00100100HEX_N4[9]
00101000HEX_N1[9]
01000001HEX_S6[9]
01000010DBL_E0[9]
01000100HEX_S4[9]
01001000HEX_S3[9]
10000001HEX_N0[9]
10000010DBL_E1[9]
10000100HEX_N2[9]
10001000HEX_N3[9]
virtex2 INT_DCM_V2P switchbox INT muxes IMUX_CE[3]
BitsDestination
MAIN[4][74]MAIN[5][74]MAIN[5][76]MAIN[4][76]MAIN[5][78]MAIN[5][77]MAIN[5][79]MAIN[4][77]IMUX_CE[3]
Source
00000000PULLUP
00010001DBL_W1[9]
00010010HEX_S1[9]
00010100HEX_S2[9]
00011000HEX_S5[9]
00100001DBL_W2[9]
00100010HEX_N5[9]
00100100HEX_N4[9]
00101000HEX_N1[9]
01000001HEX_S6[9]
01000010DBL_E0[9]
01000100HEX_S4[9]
01001000HEX_S3[9]
10000001HEX_N0[9]
10000010DBL_E1[9]
10000100HEX_N2[9]
10001000HEX_N3[9]
virtex2 INT_DCM_V2P switchbox INT muxes IMUX_TI[0]
BitsDestination
MAIN[5][18]MAIN[5][19]MAIN[4][20]MAIN[5][20]MAIN[5][27]MAIN[4][25]MAIN[4][23]MAIN[5][23]MAIN[4][21]MAIN[5][21]IMUX_TI[0]
Source
0000000000PULLUP
0001000001OMUX[2]
0001000010OMUX[3]
0001000100HEX_N5[3]
0001001000HEX_N2[3]
0001010000HEX_S5[3]
0001100000HEX_S2[3]
0010000001OMUX[4]
0010000010HEX_N0[3]
0010000100DBL_W1[2]
0010001000DBL_W2[2]
0010010000HEX_N3[3]
0010100000HEX_S4[3]
0100000001OMUX[5]
0100000010DBL_W2[3]
0100000100DBL_W1[3]
0100001000DBL_E1[3]
0100010000DBL_E0[3]
0100100000HEX_S1[3]
1000000001DBL_E0[2]
1000000010HEX_S6[3]
1000000100DBL_E1[2]
1000001000HEX_S3[3]
1000010000HEX_N1[3]
1000100000HEX_N4[3]
virtex2 INT_DCM_V2P switchbox INT muxes IMUX_TI[1]
BitsDestination
MAIN[5][28]MAIN[5][25]MAIN[4][26]MAIN[5][26]MAIN[4][28]MAIN[4][24]MAIN[5][22]MAIN[5][24]MAIN[4][22]MAIN[4][18]IMUX_TI[1]
Source
0000000000PULLUP
0001000001OMUX[2]
0001000010OMUX[3]
0001000100HEX_N5[3]
0001001000HEX_N2[3]
0001010000HEX_S5[3]
0001100000HEX_S2[3]
0010000001OMUX[4]
0010000010HEX_N0[3]
0010000100DBL_W1[2]
0010001000DBL_W2[2]
0010010000HEX_N3[3]
0010100000HEX_S4[3]
0100000001OMUX[5]
0100000010DBL_W2[3]
0100000100DBL_W1[3]
0100001000DBL_E1[3]
0100010000DBL_E0[3]
0100100000HEX_S1[3]
1000000001DBL_E0[2]
1000000010HEX_S6[3]
1000000100DBL_E1[2]
1000001000HEX_S3[3]
1000010000HEX_N1[3]
1000100000HEX_N4[3]
virtex2 INT_DCM_V2P switchbox INT muxes IMUX_G0_FAN[0]
BitsDestination
MAIN[9][16]MAIN[9][19]MAIN[8][19]MAIN[8][16]MAIN[10][17]MAIN[10][19]MAIN[11][19]MAIN[11][17]MAIN[13][17]MAIN[12][19]MAIN[13][19]MAIN[12][17]IMUX_G0_FAN[0]
Source
000000000000PULLUP
000100000001OMUX_W1
000100000010OMUX_E2
000100000100OMUX_NW10
000100001000OMUX_N10
000100010000DBL_S1[0]
000100100000IMUX_G1_FAN[0]
000101000000DBL_N2[0]
000110000000IMUX_G2_FAN[0]
001000000001DBL_E0[1]
001000000010DBL_S0[0]
001000000100OMUX_EN8
001000001000DBL_W0[0]
001000010000DBL_N1[1]
001000100000DBL_S1[2]
001001000000DBL_W2[1]
001010000000DBL_S1[1]
010000000001DBL_E2[1]
010000000010DBL_S0[2]
010000000100DBL_E2[0]
010000001000DBL_E2[2]
010000010000DBL_W1[0]
010000100000DBL_E1[2]
010001000000DBL_E1[1]
010010000000DBL_N2[1]
100000000001DBL_S2[0]
100000000010DBL_S2[2]
100000000100DBL_N0[1]
100000001000DBL_S2[1]
100000010000DBL_E1[0]
100000100000DBL_W1[1]
100001000000DBL_W2[0]
100010000000DBL_N1[0]
virtex2 INT_DCM_V2P switchbox INT muxes IMUX_G0_FAN[1]
BitsDestination
MAIN[9][17]MAIN[9][18]MAIN[8][18]MAIN[8][17]MAIN[10][16]MAIN[10][18]MAIN[11][18]MAIN[11][16]MAIN[13][16]MAIN[12][18]MAIN[13][18]MAIN[12][16]IMUX_G0_FAN[1]
Source
000000000000PULLUP
000100000001OMUX_W1
000100000010OMUX_E2
000100000100OMUX_NW10
000100001000OMUX_N10
000100010000DBL_S1[0]
000100100000IMUX_G1_FAN[0]
000101000000DBL_N2[0]
000110000000IMUX_G2_FAN[0]
001000000001DBL_E0[1]
001000000010DBL_S0[0]
001000000100OMUX_EN8
001000001000DBL_W0[0]
001000010000DBL_N1[1]
001000100000DBL_S1[2]
001001000000DBL_W2[1]
001010000000DBL_S1[1]
010000000001DBL_E2[1]
010000000010DBL_S0[2]
010000000100DBL_E2[0]
010000001000DBL_E2[2]
010000010000DBL_W1[0]
010000100000DBL_E1[2]
010001000000DBL_E1[1]
010010000000DBL_N2[1]
100000000001DBL_S2[0]
100000000010DBL_S2[2]
100000000100DBL_N0[1]
100000001000DBL_S2[1]
100000010000DBL_E1[0]
100000100000DBL_W1[1]
100001000000DBL_W2[0]
100010000000DBL_N1[0]
virtex2 INT_DCM_V2P switchbox INT muxes IMUX_G0_DATA[0]
BitsDestination
MAIN[9][0]MAIN[9][3]MAIN[8][3]MAIN[8][0]MAIN[10][1]MAIN[10][3]MAIN[11][3]MAIN[11][1]MAIN[13][1]MAIN[12][3]MAIN[13][3]MAIN[12][1]IMUX_G0_DATA[0]
Source
000000000000PULLUP
000100000001OMUX_W1
000100000010OMUX_E2
000100000100OMUX_NW10
000100001000OMUX_N10
000100010000DBL_S1[0]
000100100000IMUX_G1_FAN[0]
000101000000DBL_N2[0]
000110000000IMUX_G2_FAN[0]
001000000001DBL_E0[1]
001000000010DBL_S0[0]
001000000100OMUX_EN8
001000001000DBL_W0[0]
001000010000DBL_N1[1]
001000100000DBL_S1[2]
001001000000DBL_W2[1]
001010000000DBL_S1[1]
010000000001DBL_E2[1]
010000000010DBL_S0[2]
010000000100DBL_E2[0]
010000001000DBL_E2[2]
010000010000DBL_W1[0]
010000100000DBL_E1[2]
010001000000DBL_E1[1]
010010000000DBL_N2[1]
100000000001DBL_S2[0]
100000000010DBL_S2[2]
100000000100DBL_N0[1]
100000001000DBL_S2[1]
100000010000DBL_E1[0]
100000100000DBL_W1[1]
100001000000DBL_W2[0]
100010000000DBL_N1[0]
virtex2 INT_DCM_V2P switchbox INT muxes IMUX_G0_DATA[1]
BitsDestination
MAIN[9][1]MAIN[9][2]MAIN[8][2]MAIN[8][1]MAIN[10][0]MAIN[10][2]MAIN[11][2]MAIN[11][0]MAIN[13][0]MAIN[12][2]MAIN[13][2]MAIN[12][0]IMUX_G0_DATA[1]
Source
000000000000PULLUP
000100000001OMUX_W1
000100000010OMUX_E2
000100000100OMUX_NW10
000100001000OMUX_N10
000100010000DBL_S1[0]
000100100000IMUX_G1_FAN[0]
000101000000DBL_N2[0]
000110000000IMUX_G2_FAN[0]
001000000001DBL_E0[1]
001000000010DBL_S0[0]
001000000100OMUX_EN8
001000001000DBL_W0[0]
001000010000DBL_N1[1]
001000100000DBL_S1[2]
001001000000DBL_W2[1]
001010000000DBL_S1[1]
010000000001DBL_E2[1]
010000000010DBL_S0[2]
010000000100DBL_E2[0]
010000001000DBL_E2[2]
010000010000DBL_W1[0]
010000100000DBL_E1[2]
010001000000DBL_E1[1]
010010000000DBL_N2[1]
100000000001DBL_S2[0]
100000000010DBL_S2[2]
100000000100DBL_N0[1]
100000001000DBL_S2[1]
100000010000DBL_E1[0]
100000100000DBL_W1[1]
100001000000DBL_W2[0]
100010000000DBL_N1[0]
virtex2 INT_DCM_V2P switchbox INT muxes IMUX_G0_DATA[2]
BitsDestination
MAIN[9][7]MAIN[9][4]MAIN[8][4]MAIN[8][7]MAIN[10][6]MAIN[10][4]MAIN[11][4]MAIN[11][6]MAIN[13][6]MAIN[12][4]MAIN[13][4]MAIN[12][6]IMUX_G0_DATA[2]
Source
000000000000PULLUP
000100000001OMUX_W1
000100000010OMUX_E2
000100000100OMUX_NW10
000100001000OMUX_N10
000100010000DBL_S1[0]
000100100000IMUX_G1_FAN[0]
000101000000DBL_N2[0]
000110000000IMUX_G2_FAN[0]
001000000001DBL_E0[1]
001000000010DBL_S0[0]
001000000100OMUX_EN8
001000001000DBL_W0[0]
001000010000DBL_N1[1]
001000100000DBL_S1[2]
001001000000DBL_W2[1]
001010000000DBL_S1[1]
010000000001DBL_E2[1]
010000000010DBL_S0[2]
010000000100DBL_E2[0]
010000001000DBL_E2[2]
010000010000DBL_W1[0]
010000100000DBL_E1[2]
010001000000DBL_E1[1]
010010000000DBL_N2[1]
100000000001DBL_S2[0]
100000000010DBL_S2[2]
100000000100DBL_N0[1]
100000001000DBL_S2[1]
100000010000DBL_E1[0]
100000100000DBL_W1[1]
100001000000DBL_W2[0]
100010000000DBL_N1[0]
virtex2 INT_DCM_V2P switchbox INT muxes IMUX_G0_DATA[3]
BitsDestination
MAIN[9][6]MAIN[9][5]MAIN[8][5]MAIN[8][6]MAIN[10][7]MAIN[10][5]MAIN[11][5]MAIN[11][7]MAIN[13][7]MAIN[12][5]MAIN[13][5]MAIN[12][7]IMUX_G0_DATA[3]
Source
000000000000PULLUP
000100000001OMUX_W1
000100000010OMUX_E2
000100000100OMUX_NW10
000100001000OMUX_N10
000100010000DBL_S1[0]
000100100000IMUX_G1_FAN[0]
000101000000DBL_N2[0]
000110000000IMUX_G2_FAN[0]
001000000001DBL_E0[1]
001000000010DBL_S0[0]
001000000100OMUX_EN8
001000001000DBL_W0[0]
001000010000DBL_N1[1]
001000100000DBL_S1[2]
001001000000DBL_W2[1]
001010000000DBL_S1[1]
010000000001DBL_E2[1]
010000000010DBL_S0[2]
010000000100DBL_E2[0]
010000001000DBL_E2[2]
010000010000DBL_W1[0]
010000100000DBL_E1[2]
010001000000DBL_E1[1]
010010000000DBL_N2[1]
100000000001DBL_S2[0]
100000000010DBL_S2[2]
100000000100DBL_N0[1]
100000001000DBL_S2[1]
100000010000DBL_E1[0]
100000100000DBL_W1[1]
100001000000DBL_W2[0]
100010000000DBL_N1[0]
virtex2 INT_DCM_V2P switchbox INT muxes IMUX_G0_DATA[4]
BitsDestination
MAIN[9][8]MAIN[9][11]MAIN[8][11]MAIN[8][8]MAIN[10][9]MAIN[10][11]MAIN[11][11]MAIN[11][9]MAIN[13][9]MAIN[12][11]MAIN[13][11]MAIN[12][9]IMUX_G0_DATA[4]
Source
000000000000PULLUP
000100000001OMUX_W1
000100000010OMUX_E2
000100000100OMUX_NW10
000100001000OMUX_N10
000100010000DBL_S1[0]
000100100000IMUX_G1_FAN[0]
000101000000DBL_N2[0]
000110000000IMUX_G2_FAN[0]
001000000001DBL_E0[1]
001000000010DBL_S0[0]
001000000100OMUX_EN8
001000001000DBL_W0[0]
001000010000DBL_N1[1]
001000100000DBL_S1[2]
001001000000DBL_W2[1]
001010000000DBL_S1[1]
010000000001DBL_E2[1]
010000000010DBL_S0[2]
010000000100DBL_E2[0]
010000001000DBL_E2[2]
010000010000DBL_W1[0]
010000100000DBL_E1[2]
010001000000DBL_E1[1]
010010000000DBL_N2[1]
100000000001DBL_S2[0]
100000000010DBL_S2[2]
100000000100DBL_N0[1]
100000001000DBL_S2[1]
100000010000DBL_E1[0]
100000100000DBL_W1[1]
100001000000DBL_W2[0]
100010000000DBL_N1[0]
virtex2 INT_DCM_V2P switchbox INT muxes IMUX_G0_DATA[5]
BitsDestination
MAIN[9][9]MAIN[9][10]MAIN[8][10]MAIN[8][9]MAIN[10][8]MAIN[10][10]MAIN[11][10]MAIN[11][8]MAIN[13][8]MAIN[12][10]MAIN[13][10]MAIN[12][8]IMUX_G0_DATA[5]
Source
000000000000PULLUP
000100000001OMUX_W1
000100000010OMUX_E2
000100000100OMUX_NW10
000100001000OMUX_N10
000100010000DBL_S1[0]
000100100000IMUX_G1_FAN[0]
000101000000DBL_N2[0]
000110000000IMUX_G2_FAN[0]
001000000001DBL_E0[1]
001000000010DBL_S0[0]
001000000100OMUX_EN8
001000001000DBL_W0[0]
001000010000DBL_N1[1]
001000100000DBL_S1[2]
001001000000DBL_W2[1]
001010000000DBL_S1[1]
010000000001DBL_E2[1]
010000000010DBL_S0[2]
010000000100DBL_E2[0]
010000001000DBL_E2[2]
010000010000DBL_W1[0]
010000100000DBL_E1[2]
010001000000DBL_E1[1]
010010000000DBL_N2[1]
100000000001DBL_S2[0]
100000000010DBL_S2[2]
100000000100DBL_N0[1]
100000001000DBL_S2[1]
100000010000DBL_E1[0]
100000100000DBL_W1[1]
100001000000DBL_W2[0]
100010000000DBL_N1[0]
virtex2 INT_DCM_V2P switchbox INT muxes IMUX_G0_DATA[6]
BitsDestination
MAIN[9][15]MAIN[9][12]MAIN[8][12]MAIN[8][15]MAIN[10][14]MAIN[10][12]MAIN[11][12]MAIN[11][14]MAIN[13][14]MAIN[12][12]MAIN[13][12]MAIN[12][14]IMUX_G0_DATA[6]
Source
000000000000PULLUP
000100000001OMUX_W1
000100000010OMUX_E2
000100000100OMUX_NW10
000100001000OMUX_N10
000100010000DBL_S1[0]
000100100000IMUX_G1_FAN[0]
000101000000DBL_N2[0]
000110000000IMUX_G2_FAN[0]
001000000001DBL_E0[1]
001000000010DBL_S0[0]
001000000100OMUX_EN8
001000001000DBL_W0[0]
001000010000DBL_N1[1]
001000100000DBL_S1[2]
001001000000DBL_W2[1]
001010000000DBL_S1[1]
010000000001DBL_E2[1]
010000000010DBL_S0[2]
010000000100DBL_E2[0]
010000001000DBL_E2[2]
010000010000DBL_W1[0]
010000100000DBL_E1[2]
010001000000DBL_E1[1]
010010000000DBL_N2[1]
100000000001DBL_S2[0]
100000000010DBL_S2[2]
100000000100DBL_N0[1]
100000001000DBL_S2[1]
100000010000DBL_E1[0]
100000100000DBL_W1[1]
100001000000DBL_W2[0]
100010000000DBL_N1[0]
virtex2 INT_DCM_V2P switchbox INT muxes IMUX_G0_DATA[7]
BitsDestination
MAIN[9][14]MAIN[9][13]MAIN[8][13]MAIN[8][14]MAIN[10][15]MAIN[10][13]MAIN[11][13]MAIN[11][15]MAIN[13][15]MAIN[12][13]MAIN[13][13]MAIN[12][15]IMUX_G0_DATA[7]
Source
000000000000PULLUP
000100000001OMUX_W1
000100000010OMUX_E2
000100000100OMUX_NW10
000100001000OMUX_N10
000100010000DBL_S1[0]
000100100000IMUX_G1_FAN[0]
000101000000DBL_N2[0]
000110000000IMUX_G2_FAN[0]
001000000001DBL_E0[1]
001000000010DBL_S0[0]
001000000100OMUX_EN8
001000001000DBL_W0[0]
001000010000DBL_N1[1]
001000100000DBL_S1[2]
001001000000DBL_W2[1]
001010000000DBL_S1[1]
010000000001DBL_E2[1]
010000000010DBL_S0[2]
010000000100DBL_E2[0]
010000001000DBL_E2[2]
010000010000DBL_W1[0]
010000100000DBL_E1[2]
010001000000DBL_E1[1]
010010000000DBL_N2[1]
100000000001DBL_S2[0]
100000000010DBL_S2[2]
100000000100DBL_N0[1]
100000001000DBL_S2[1]
100000010000DBL_E1[0]
100000100000DBL_W1[1]
100001000000DBL_W2[0]
100010000000DBL_N1[0]
virtex2 INT_DCM_V2P switchbox INT muxes IMUX_G1_FAN[0]
BitsDestination
MAIN[9][23]MAIN[9][20]MAIN[8][23]MAIN[8][20]MAIN[10][22]MAIN[10][20]MAIN[11][22]MAIN[11][20]MAIN[13][20]MAIN[13][22]MAIN[12][22]MAIN[12][20]IMUX_G1_FAN[0]
Source
000000000000PULLUP
000100000001OMUX_W6
000100000010DBL_S0[4]
000100000100DBL_W0[4]
000100001000DBL_E0[3]
000100010000DBL_W1[2]
000100100000DBL_N1[4]
000101000000DBL_W2[4]
000110000000DBL_N2[4]
001000000001OMUX_N12
001000000010OMUX_E7
001000000100OMUX_NE12
001000001000OMUX_WN14
001000010000IMUX_G3_FAN[1]
001000100000DBL_S1[3]
001001000000DBL_E1[4]
001010000000IMUX_G0_FAN[1]
010000000001DBL_E2[4]
010000000010DBL_E2[3]
010000000100DBL_W2[3]
010000001000DBL_W0[2]
010000010000DBL_N1[2]
010000100000DBL_W1[3]
010001000000DBL_W1[4]
010010000000DBL_N2[3]
100000000001DBL_N0[3]
100000000010DBL_S2[4]
100000000100DBL_S2[3]
100000001000DBL_W2[2]
100000010000DBL_S1[4]
100000100000DBL_E1[3]
100001000000DBL_N2[2]
100010000000DBL_N1[3]
virtex2 INT_DCM_V2P switchbox INT muxes IMUX_G1_FAN[1]
BitsDestination
MAIN[9][22]MAIN[9][21]MAIN[8][22]MAIN[8][21]MAIN[10][23]MAIN[10][21]MAIN[11][23]MAIN[11][21]MAIN[13][21]MAIN[13][23]MAIN[12][23]MAIN[12][21]IMUX_G1_FAN[1]
Source
000000000000PULLUP
000100000001OMUX_W6
000100000010DBL_S0[4]
000100000100DBL_W0[4]
000100001000DBL_E0[3]
000100010000DBL_W1[2]
000100100000DBL_N1[4]
000101000000DBL_W2[4]
000110000000DBL_N2[4]
001000000001OMUX_N12
001000000010OMUX_E7
001000000100OMUX_NE12
001000001000OMUX_WN14
001000010000IMUX_G3_FAN[1]
001000100000DBL_S1[3]
001001000000DBL_E1[4]
001010000000IMUX_G0_FAN[1]
010000000001DBL_E2[4]
010000000010DBL_E2[3]
010000000100DBL_W2[3]
010000001000DBL_W0[2]
010000010000DBL_N1[2]
010000100000DBL_W1[3]
010001000000DBL_W1[4]
010010000000DBL_N2[3]
100000000001DBL_N0[3]
100000000010DBL_S2[4]
100000000100DBL_S2[3]
100000001000DBL_W2[2]
100000010000DBL_S1[4]
100000100000DBL_E1[3]
100001000000DBL_N2[2]
100010000000DBL_N1[3]
virtex2 INT_DCM_V2P switchbox INT muxes IMUX_G1_DATA[0]
BitsDestination
MAIN[9][39]MAIN[9][36]MAIN[8][39]MAIN[8][36]MAIN[10][38]MAIN[10][36]MAIN[11][38]MAIN[11][36]MAIN[13][36]MAIN[13][38]MAIN[12][38]MAIN[12][36]IMUX_G1_DATA[0]
Source
000000000000PULLUP
000100000001OMUX_W6
000100000010DBL_S0[4]
000100000100DBL_W0[4]
000100001000DBL_E0[3]
000100010000DBL_W1[2]
000100100000DBL_N1[4]
000101000000DBL_W2[4]
000110000000DBL_N2[4]
001000000001OMUX_N12
001000000010OMUX_E7
001000000100OMUX_NE12
001000001000OMUX_WN14
001000010000IMUX_G3_FAN[1]
001000100000DBL_S1[3]
001001000000DBL_E1[4]
001010000000IMUX_G0_FAN[1]
010000000001DBL_E2[4]
010000000010DBL_E2[3]
010000000100DBL_W2[3]
010000001000DBL_W0[2]
010000010000DBL_N1[2]
010000100000DBL_W1[3]
010001000000DBL_W1[4]
010010000000DBL_N2[3]
100000000001DBL_N0[3]
100000000010DBL_S2[4]
100000000100DBL_S2[3]
100000001000DBL_W2[2]
100000010000DBL_S1[4]
100000100000DBL_E1[3]
100001000000DBL_N2[2]
100010000000DBL_N1[3]
virtex2 INT_DCM_V2P switchbox INT muxes IMUX_G1_DATA[1]
BitsDestination
MAIN[9][38]MAIN[9][37]MAIN[8][38]MAIN[8][37]MAIN[10][39]MAIN[10][37]MAIN[11][39]MAIN[11][37]MAIN[13][37]MAIN[13][39]MAIN[12][39]MAIN[12][37]IMUX_G1_DATA[1]
Source
000000000000PULLUP
000100000001OMUX_W6
000100000010DBL_S0[4]
000100000100DBL_W0[4]
000100001000DBL_E0[3]
000100010000DBL_W1[2]
000100100000DBL_N1[4]
000101000000DBL_W2[4]
000110000000DBL_N2[4]
001000000001OMUX_N12
001000000010OMUX_E7
001000000100OMUX_NE12
001000001000OMUX_WN14
001000010000IMUX_G3_FAN[1]
001000100000DBL_S1[3]
001001000000DBL_E1[4]
001010000000IMUX_G0_FAN[1]
010000000001DBL_E2[4]
010000000010DBL_E2[3]
010000000100DBL_W2[3]
010000001000DBL_W0[2]
010000010000DBL_N1[2]
010000100000DBL_W1[3]
010001000000DBL_W1[4]
010010000000DBL_N2[3]
100000000001DBL_N0[3]
100000000010DBL_S2[4]
100000000100DBL_S2[3]
100000001000DBL_W2[2]
100000010000DBL_S1[4]
100000100000DBL_E1[3]
100001000000DBL_N2[2]
100010000000DBL_N1[3]
virtex2 INT_DCM_V2P switchbox INT muxes IMUX_G1_DATA[2]
BitsDestination
MAIN[9][32]MAIN[9][35]MAIN[8][32]MAIN[8][35]MAIN[10][33]MAIN[10][35]MAIN[11][33]MAIN[11][35]MAIN[13][35]MAIN[13][33]MAIN[12][33]MAIN[12][35]IMUX_G1_DATA[2]
Source
000000000000PULLUP
000100000001OMUX_W6
000100000010DBL_S0[4]
000100000100DBL_W0[4]
000100001000DBL_E0[3]
000100010000DBL_W1[2]
000100100000DBL_N1[4]
000101000000DBL_W2[4]
000110000000DBL_N2[4]
001000000001OMUX_N12
001000000010OMUX_E7
001000000100OMUX_NE12
001000001000OMUX_WN14
001000010000IMUX_G3_FAN[1]
001000100000DBL_S1[3]
001001000000DBL_E1[4]
001010000000IMUX_G0_FAN[1]
010000000001DBL_E2[4]
010000000010DBL_E2[3]
010000000100DBL_W2[3]
010000001000DBL_W0[2]
010000010000DBL_N1[2]
010000100000DBL_W1[3]
010001000000DBL_W1[4]
010010000000DBL_N2[3]
100000000001DBL_N0[3]
100000000010DBL_S2[4]
100000000100DBL_S2[3]
100000001000DBL_W2[2]
100000010000DBL_S1[4]
100000100000DBL_E1[3]
100001000000DBL_N2[2]
100010000000DBL_N1[3]
virtex2 INT_DCM_V2P switchbox INT muxes IMUX_G1_DATA[3]
BitsDestination
MAIN[9][33]MAIN[9][34]MAIN[8][33]MAIN[8][34]MAIN[10][32]MAIN[10][34]MAIN[11][32]MAIN[11][34]MAIN[13][34]MAIN[13][32]MAIN[12][32]MAIN[12][34]IMUX_G1_DATA[3]
Source
000000000000PULLUP
000100000001OMUX_W6
000100000010DBL_S0[4]
000100000100DBL_W0[4]
000100001000DBL_E0[3]
000100010000DBL_W1[2]
000100100000DBL_N1[4]
000101000000DBL_W2[4]
000110000000DBL_N2[4]
001000000001OMUX_N12
001000000010OMUX_E7
001000000100OMUX_NE12
001000001000OMUX_WN14
001000010000IMUX_G3_FAN[1]
001000100000DBL_S1[3]
001001000000DBL_E1[4]
001010000000IMUX_G0_FAN[1]
010000000001DBL_E2[4]
010000000010DBL_E2[3]
010000000100DBL_W2[3]
010000001000DBL_W0[2]
010000010000DBL_N1[2]
010000100000DBL_W1[3]
010001000000DBL_W1[4]
010010000000DBL_N2[3]
100000000001DBL_N0[3]
100000000010DBL_S2[4]
100000000100DBL_S2[3]
100000001000DBL_W2[2]
100000010000DBL_S1[4]
100000100000DBL_E1[3]
100001000000DBL_N2[2]
100010000000DBL_N1[3]
virtex2 INT_DCM_V2P switchbox INT muxes IMUX_G1_DATA[4]
BitsDestination
MAIN[9][31]MAIN[9][28]MAIN[8][31]MAIN[8][28]MAIN[10][30]MAIN[10][28]MAIN[11][30]MAIN[11][28]MAIN[13][28]MAIN[13][30]MAIN[12][30]MAIN[12][28]IMUX_G1_DATA[4]
Source
000000000000PULLUP
000100000001OMUX_W6
000100000010DBL_S0[4]
000100000100DBL_W0[4]
000100001000DBL_E0[3]
000100010000DBL_W1[2]
000100100000DBL_N1[4]
000101000000DBL_W2[4]
000110000000DBL_N2[4]
001000000001OMUX_N12
001000000010OMUX_E7
001000000100OMUX_NE12
001000001000OMUX_WN14
001000010000IMUX_G3_FAN[1]
001000100000DBL_S1[3]
001001000000DBL_E1[4]
001010000000IMUX_G0_FAN[1]
010000000001DBL_E2[4]
010000000010DBL_E2[3]
010000000100DBL_W2[3]
010000001000DBL_W0[2]
010000010000DBL_N1[2]
010000100000DBL_W1[3]
010001000000DBL_W1[4]
010010000000DBL_N2[3]
100000000001DBL_N0[3]
100000000010DBL_S2[4]
100000000100DBL_S2[3]
100000001000DBL_W2[2]
100000010000DBL_S1[4]
100000100000DBL_E1[3]
100001000000DBL_N2[2]
100010000000DBL_N1[3]
virtex2 INT_DCM_V2P switchbox INT muxes IMUX_G1_DATA[5]
BitsDestination
MAIN[9][30]MAIN[9][29]MAIN[8][30]MAIN[8][29]MAIN[10][31]MAIN[10][29]MAIN[11][31]MAIN[11][29]MAIN[13][29]MAIN[13][31]MAIN[12][31]MAIN[12][29]IMUX_G1_DATA[5]
Source
000000000000PULLUP
000100000001OMUX_W6
000100000010DBL_S0[4]
000100000100DBL_W0[4]
000100001000DBL_E0[3]
000100010000DBL_W1[2]
000100100000DBL_N1[4]
000101000000DBL_W2[4]
000110000000DBL_N2[4]
001000000001OMUX_N12
001000000010OMUX_E7
001000000100OMUX_NE12
001000001000OMUX_WN14
001000010000IMUX_G3_FAN[1]
001000100000DBL_S1[3]
001001000000DBL_E1[4]
001010000000IMUX_G0_FAN[1]
010000000001DBL_E2[4]
010000000010DBL_E2[3]
010000000100DBL_W2[3]
010000001000DBL_W0[2]
010000010000DBL_N1[2]
010000100000DBL_W1[3]
010001000000DBL_W1[4]
010010000000DBL_N2[3]
100000000001DBL_N0[3]
100000000010DBL_S2[4]
100000000100DBL_S2[3]
100000001000DBL_W2[2]
100000010000DBL_S1[4]
100000100000DBL_E1[3]
100001000000DBL_N2[2]
100010000000DBL_N1[3]
virtex2 INT_DCM_V2P switchbox INT muxes IMUX_G1_DATA[6]
BitsDestination
MAIN[9][24]MAIN[9][27]MAIN[8][24]MAIN[8][27]MAIN[10][25]MAIN[10][27]MAIN[11][25]MAIN[11][27]MAIN[13][27]MAIN[13][25]MAIN[12][25]MAIN[12][27]IMUX_G1_DATA[6]
Source
000000000000PULLUP
000100000001OMUX_W6
000100000010DBL_S0[4]
000100000100DBL_W0[4]
000100001000DBL_E0[3]
000100010000DBL_W1[2]
000100100000DBL_N1[4]
000101000000DBL_W2[4]
000110000000DBL_N2[4]
001000000001OMUX_N12
001000000010OMUX_E7
001000000100OMUX_NE12
001000001000OMUX_WN14
001000010000IMUX_G3_FAN[1]
001000100000DBL_S1[3]
001001000000DBL_E1[4]
001010000000IMUX_G0_FAN[1]
010000000001DBL_E2[4]
010000000010DBL_E2[3]
010000000100DBL_W2[3]
010000001000DBL_W0[2]
010000010000DBL_N1[2]
010000100000DBL_W1[3]
010001000000DBL_W1[4]
010010000000DBL_N2[3]
100000000001DBL_N0[3]
100000000010DBL_S2[4]
100000000100DBL_S2[3]
100000001000DBL_W2[2]
100000010000DBL_S1[4]
100000100000DBL_E1[3]
100001000000DBL_N2[2]
100010000000DBL_N1[3]
virtex2 INT_DCM_V2P switchbox INT muxes IMUX_G1_DATA[7]
BitsDestination
MAIN[9][25]MAIN[9][26]MAIN[8][25]MAIN[8][26]MAIN[10][24]MAIN[10][26]MAIN[11][24]MAIN[11][26]MAIN[13][26]MAIN[13][24]MAIN[12][24]MAIN[12][26]IMUX_G1_DATA[7]
Source
000000000000PULLUP
000100000001OMUX_W6
000100000010DBL_S0[4]
000100000100DBL_W0[4]
000100001000DBL_E0[3]
000100010000DBL_W1[2]
000100100000DBL_N1[4]
000101000000DBL_W2[4]
000110000000DBL_N2[4]
001000000001OMUX_N12
001000000010OMUX_E7
001000000100OMUX_NE12
001000001000OMUX_WN14
001000010000IMUX_G3_FAN[1]
001000100000DBL_S1[3]
001001000000DBL_E1[4]
001010000000IMUX_G0_FAN[1]
010000000001DBL_E2[4]
010000000010DBL_E2[3]
010000000100DBL_W2[3]
010000001000DBL_W0[2]
010000010000DBL_N1[2]
010000100000DBL_W1[3]
010001000000DBL_W1[4]
010010000000DBL_N2[3]
100000000001DBL_N0[3]
100000000010DBL_S2[4]
100000000100DBL_S2[3]
100000001000DBL_W2[2]
100000010000DBL_S1[4]
100000100000DBL_E1[3]
100001000000DBL_N2[2]
100010000000DBL_N1[3]
virtex2 INT_DCM_V2P switchbox INT muxes IMUX_G2_FAN[0]
BitsDestination
MAIN[9][56]MAIN[9][59]MAIN[8][59]MAIN[8][56]MAIN[10][57]MAIN[10][59]MAIN[11][59]MAIN[11][57]MAIN[13][59]MAIN[13][57]MAIN[12][59]MAIN[12][57]IMUX_G2_FAN[0]
Source
000000000000PULLUP
000100000001OMUX_WS1
000100000010OMUX_E8
000100000100OMUX_SE3
000100001000OMUX_W9
000100010000DBL_S1[5]
000100100000IMUX_G3_FAN[0]
000101000000DBL_N2[5]
000110000000IMUX_G0_FAN[0]
001000000001DBL_E0[5]
001000000010OMUX_S3
001000000100DBL_W0[6]
001000001000DBL_S0[6]
001000010000DBL_N1[6]
001000100000DBL_S1[7]
001001000000DBL_W2[6]
001010000000DBL_S1[6]
010000000001DBL_E2[6]
010000000010DBL_E2[5]
010000000100DBL_E2[7]
010000001000DBL_E0[7]
010000010000DBL_W1[5]
010000100000DBL_E1[7]
010001000000DBL_E1[6]
010010000000DBL_N2[6]
100000000001DBL_S2[5]
100000000010DBL_N0[5]
100000000100DBL_S2[6]
100000001000DBL_S2[7]
100000010000DBL_E1[5]
100000100000DBL_W1[6]
100001000000DBL_W2[5]
100010000000DBL_N1[5]
virtex2 INT_DCM_V2P switchbox INT muxes IMUX_G2_FAN[1]
BitsDestination
MAIN[9][57]MAIN[9][58]MAIN[8][58]MAIN[8][57]MAIN[10][56]MAIN[10][58]MAIN[11][58]MAIN[11][56]MAIN[13][58]MAIN[13][56]MAIN[12][58]MAIN[12][56]IMUX_G2_FAN[1]
Source
000000000000PULLUP
000100000001OMUX_WS1
000100000010OMUX_E8
000100000100OMUX_SE3
000100001000OMUX_W9
000100010000DBL_S1[5]
000100100000IMUX_G3_FAN[0]
000101000000DBL_N2[5]
000110000000IMUX_G0_FAN[0]
001000000001DBL_E0[5]
001000000010OMUX_S3
001000000100DBL_W0[6]
001000001000DBL_S0[6]
001000010000DBL_N1[6]
001000100000DBL_S1[7]
001001000000DBL_W2[6]
001010000000DBL_S1[6]
010000000001DBL_E2[6]
010000000010DBL_E2[5]
010000000100DBL_E2[7]
010000001000DBL_E0[7]
010000010000DBL_W1[5]
010000100000DBL_E1[7]
010001000000DBL_E1[6]
010010000000DBL_N2[6]
100000000001DBL_S2[5]
100000000010DBL_N0[5]
100000000100DBL_S2[6]
100000001000DBL_S2[7]
100000010000DBL_E1[5]
100000100000DBL_W1[6]
100001000000DBL_W2[5]
100010000000DBL_N1[5]
virtex2 INT_DCM_V2P switchbox INT muxes IMUX_G2_DATA[0]
BitsDestination
MAIN[9][40]MAIN[9][43]MAIN[8][43]MAIN[8][40]MAIN[10][41]MAIN[10][43]MAIN[11][43]MAIN[11][41]MAIN[13][43]MAIN[13][41]MAIN[12][43]MAIN[12][41]IMUX_G2_DATA[0]
Source
000000000000PULLUP
000100000001OMUX_WS1
000100000010OMUX_E8
000100000100OMUX_SE3
000100001000OMUX_W9
000100010000DBL_S1[5]
000100100000IMUX_G3_FAN[0]
000101000000DBL_N2[5]
000110000000IMUX_G0_FAN[0]
001000000001DBL_E0[5]
001000000010OMUX_S3
001000000100DBL_W0[6]
001000001000DBL_S0[6]
001000010000DBL_N1[6]
001000100000DBL_S1[7]
001001000000DBL_W2[6]
001010000000DBL_S1[6]
010000000001DBL_E2[6]
010000000010DBL_E2[5]
010000000100DBL_E2[7]
010000001000DBL_E0[7]
010000010000DBL_W1[5]
010000100000DBL_E1[7]
010001000000DBL_E1[6]
010010000000DBL_N2[6]
100000000001DBL_S2[5]
100000000010DBL_N0[5]
100000000100DBL_S2[6]
100000001000DBL_S2[7]
100000010000DBL_E1[5]
100000100000DBL_W1[6]
100001000000DBL_W2[5]
100010000000DBL_N1[5]
virtex2 INT_DCM_V2P switchbox INT muxes IMUX_G2_DATA[1]
BitsDestination
MAIN[9][41]MAIN[9][42]MAIN[8][42]MAIN[8][41]MAIN[10][40]MAIN[10][42]MAIN[11][42]MAIN[11][40]MAIN[13][42]MAIN[13][40]MAIN[12][42]MAIN[12][40]IMUX_G2_DATA[1]
Source
000000000000PULLUP
000100000001OMUX_WS1
000100000010OMUX_E8
000100000100OMUX_SE3
000100001000OMUX_W9
000100010000DBL_S1[5]
000100100000IMUX_G3_FAN[0]
000101000000DBL_N2[5]
000110000000IMUX_G0_FAN[0]
001000000001DBL_E0[5]
001000000010OMUX_S3
001000000100DBL_W0[6]
001000001000DBL_S0[6]
001000010000DBL_N1[6]
001000100000DBL_S1[7]
001001000000DBL_W2[6]
001010000000DBL_S1[6]
010000000001DBL_E2[6]
010000000010DBL_E2[5]
010000000100DBL_E2[7]
010000001000DBL_E0[7]
010000010000DBL_W1[5]
010000100000DBL_E1[7]
010001000000DBL_E1[6]
010010000000DBL_N2[6]
100000000001DBL_S2[5]
100000000010DBL_N0[5]
100000000100DBL_S2[6]
100000001000DBL_S2[7]
100000010000DBL_E1[5]
100000100000DBL_W1[6]
100001000000DBL_W2[5]
100010000000DBL_N1[5]
virtex2 INT_DCM_V2P switchbox INT muxes IMUX_G2_DATA[2]
BitsDestination
MAIN[9][47]MAIN[9][44]MAIN[8][44]MAIN[8][47]MAIN[10][46]MAIN[10][44]MAIN[11][44]MAIN[11][46]MAIN[13][44]MAIN[13][46]MAIN[12][44]MAIN[12][46]IMUX_G2_DATA[2]
Source
000000000000PULLUP
000100000001OMUX_WS1
000100000010OMUX_E8
000100000100OMUX_SE3
000100001000OMUX_W9
000100010000DBL_S1[5]
000100100000IMUX_G3_FAN[0]
000101000000DBL_N2[5]
000110000000IMUX_G0_FAN[0]
001000000001DBL_E0[5]
001000000010OMUX_S3
001000000100DBL_W0[6]
001000001000DBL_S0[6]
001000010000DBL_N1[6]
001000100000DBL_S1[7]
001001000000DBL_W2[6]
001010000000DBL_S1[6]
010000000001DBL_E2[6]
010000000010DBL_E2[5]
010000000100DBL_E2[7]
010000001000DBL_E0[7]
010000010000DBL_W1[5]
010000100000DBL_E1[7]
010001000000DBL_E1[6]
010010000000DBL_N2[6]
100000000001DBL_S2[5]
100000000010DBL_N0[5]
100000000100DBL_S2[6]
100000001000DBL_S2[7]
100000010000DBL_E1[5]
100000100000DBL_W1[6]
100001000000DBL_W2[5]
100010000000DBL_N1[5]
virtex2 INT_DCM_V2P switchbox INT muxes IMUX_G2_DATA[3]
BitsDestination
MAIN[9][46]MAIN[9][45]MAIN[8][45]MAIN[8][46]MAIN[10][47]MAIN[10][45]MAIN[11][45]MAIN[11][47]MAIN[13][45]MAIN[13][47]MAIN[12][45]MAIN[12][47]IMUX_G2_DATA[3]
Source
000000000000PULLUP
000100000001OMUX_WS1
000100000010OMUX_E8
000100000100OMUX_SE3
000100001000OMUX_W9
000100010000DBL_S1[5]
000100100000IMUX_G3_FAN[0]
000101000000DBL_N2[5]
000110000000IMUX_G0_FAN[0]
001000000001DBL_E0[5]
001000000010OMUX_S3
001000000100DBL_W0[6]
001000001000DBL_S0[6]
001000010000DBL_N1[6]
001000100000DBL_S1[7]
001001000000DBL_W2[6]
001010000000DBL_S1[6]
010000000001DBL_E2[6]
010000000010DBL_E2[5]
010000000100DBL_E2[7]
010000001000DBL_E0[7]
010000010000DBL_W1[5]
010000100000DBL_E1[7]
010001000000DBL_E1[6]
010010000000DBL_N2[6]
100000000001DBL_S2[5]
100000000010DBL_N0[5]
100000000100DBL_S2[6]
100000001000DBL_S2[7]
100000010000DBL_E1[5]
100000100000DBL_W1[6]
100001000000DBL_W2[5]
100010000000DBL_N1[5]
virtex2 INT_DCM_V2P switchbox INT muxes IMUX_G2_DATA[4]
BitsDestination
MAIN[9][48]MAIN[9][51]MAIN[8][51]MAIN[8][48]MAIN[10][49]MAIN[10][51]MAIN[11][51]MAIN[11][49]MAIN[13][51]MAIN[13][49]MAIN[12][51]MAIN[12][49]IMUX_G2_DATA[4]
Source
000000000000PULLUP
000100000001OMUX_WS1
000100000010OMUX_E8
000100000100OMUX_SE3
000100001000OMUX_W9
000100010000DBL_S1[5]
000100100000IMUX_G3_FAN[0]
000101000000DBL_N2[5]
000110000000IMUX_G0_FAN[0]
001000000001DBL_E0[5]
001000000010OMUX_S3
001000000100DBL_W0[6]
001000001000DBL_S0[6]
001000010000DBL_N1[6]
001000100000DBL_S1[7]
001001000000DBL_W2[6]
001010000000DBL_S1[6]
010000000001DBL_E2[6]
010000000010DBL_E2[5]
010000000100DBL_E2[7]
010000001000DBL_E0[7]
010000010000DBL_W1[5]
010000100000DBL_E1[7]
010001000000DBL_E1[6]
010010000000DBL_N2[6]
100000000001DBL_S2[5]
100000000010DBL_N0[5]
100000000100DBL_S2[6]
100000001000DBL_S2[7]
100000010000DBL_E1[5]
100000100000DBL_W1[6]
100001000000DBL_W2[5]
100010000000DBL_N1[5]
virtex2 INT_DCM_V2P switchbox INT muxes IMUX_G2_DATA[5]
BitsDestination
MAIN[9][49]MAIN[9][50]MAIN[8][50]MAIN[8][49]MAIN[10][48]MAIN[10][50]MAIN[11][50]MAIN[11][48]MAIN[13][50]MAIN[13][48]MAIN[12][50]MAIN[12][48]IMUX_G2_DATA[5]
Source
000000000000PULLUP
000100000001OMUX_WS1
000100000010OMUX_E8
000100000100OMUX_SE3
000100001000OMUX_W9
000100010000DBL_S1[5]
000100100000IMUX_G3_FAN[0]
000101000000DBL_N2[5]
000110000000IMUX_G0_FAN[0]
001000000001DBL_E0[5]
001000000010OMUX_S3
001000000100DBL_W0[6]
001000001000DBL_S0[6]
001000010000DBL_N1[6]
001000100000DBL_S1[7]
001001000000DBL_W2[6]
001010000000DBL_S1[6]
010000000001DBL_E2[6]
010000000010DBL_E2[5]
010000000100DBL_E2[7]
010000001000DBL_E0[7]
010000010000DBL_W1[5]
010000100000DBL_E1[7]
010001000000DBL_E1[6]
010010000000DBL_N2[6]
100000000001DBL_S2[5]
100000000010DBL_N0[5]
100000000100DBL_S2[6]
100000001000DBL_S2[7]
100000010000DBL_E1[5]
100000100000DBL_W1[6]
100001000000DBL_W2[5]
100010000000DBL_N1[5]
virtex2 INT_DCM_V2P switchbox INT muxes IMUX_G2_DATA[6]
BitsDestination
MAIN[9][55]MAIN[9][52]MAIN[8][52]MAIN[8][55]MAIN[10][54]MAIN[10][52]MAIN[11][52]MAIN[11][54]MAIN[13][52]MAIN[13][54]MAIN[12][52]MAIN[12][54]IMUX_G2_DATA[6]
Source
000000000000PULLUP
000100000001OMUX_WS1
000100000010OMUX_E8
000100000100OMUX_SE3
000100001000OMUX_W9
000100010000DBL_S1[5]
000100100000IMUX_G3_FAN[0]
000101000000DBL_N2[5]
000110000000IMUX_G0_FAN[0]
001000000001DBL_E0[5]
001000000010OMUX_S3
001000000100DBL_W0[6]
001000001000DBL_S0[6]
001000010000DBL_N1[6]
001000100000DBL_S1[7]
001001000000DBL_W2[6]
001010000000DBL_S1[6]
010000000001DBL_E2[6]
010000000010DBL_E2[5]
010000000100DBL_E2[7]
010000001000DBL_E0[7]
010000010000DBL_W1[5]
010000100000DBL_E1[7]
010001000000DBL_E1[6]
010010000000DBL_N2[6]
100000000001DBL_S2[5]
100000000010DBL_N0[5]
100000000100DBL_S2[6]
100000001000DBL_S2[7]
100000010000DBL_E1[5]
100000100000DBL_W1[6]
100001000000DBL_W2[5]
100010000000DBL_N1[5]
virtex2 INT_DCM_V2P switchbox INT muxes IMUX_G2_DATA[7]
BitsDestination
MAIN[9][54]MAIN[9][53]MAIN[8][53]MAIN[8][54]MAIN[10][55]MAIN[10][53]MAIN[11][53]MAIN[11][55]MAIN[13][53]MAIN[13][55]MAIN[12][53]MAIN[12][55]IMUX_G2_DATA[7]
Source
000000000000PULLUP
000100000001OMUX_WS1
000100000010OMUX_E8
000100000100OMUX_SE3
000100001000OMUX_W9
000100010000DBL_S1[5]
000100100000IMUX_G3_FAN[0]
000101000000DBL_N2[5]
000110000000IMUX_G0_FAN[0]
001000000001DBL_E0[5]
001000000010OMUX_S3
001000000100DBL_W0[6]
001000001000DBL_S0[6]
001000010000DBL_N1[6]
001000100000DBL_S1[7]
001001000000DBL_W2[6]
001010000000DBL_S1[6]
010000000001DBL_E2[6]
010000000010DBL_E2[5]
010000000100DBL_E2[7]
010000001000DBL_E0[7]
010000010000DBL_W1[5]
010000100000DBL_E1[7]
010001000000DBL_E1[6]
010010000000DBL_N2[6]
100000000001DBL_S2[5]
100000000010DBL_N0[5]
100000000100DBL_S2[6]
100000001000DBL_S2[7]
100000010000DBL_E1[5]
100000100000DBL_W1[6]
100001000000DBL_W2[5]
100010000000DBL_N1[5]
virtex2 INT_DCM_V2P switchbox INT muxes IMUX_G3_FAN[0]
BitsDestination
MAIN[9][63]MAIN[9][60]MAIN[8][60]MAIN[8][63]MAIN[10][62]MAIN[10][60]MAIN[11][62]MAIN[11][60]MAIN[13][62]MAIN[12][62]MAIN[12][60]MAIN[13][60]IMUX_G3_FAN[0]
Source
000000000000PULLUP
000100000001OMUX_S5
000100000010OMUX_W14
000100000100OMUX_ES7
000100001000OMUX_E13
000100010000IMUX_G1_FAN[1]
000100100000DBL_S1[8]
000101000000DBL_E1[9]
000110000000IMUX_G2_FAN[1]
001000000001DBL_W0[8]
001000000010OMUX_SW5
001000000100DBL_S0[8]
001000001000DBL_E0[9]
001000010000DBL_W1[7]
001000100000DBL_N1[9]
001001000000DBL_W2[9]
001010000000DBL_N2[9]
010000000001DBL_N0[7]
010000000010DBL_E2[9]
010000000100DBL_E2[8]
010000001000DBL_W2[8]
010000010000DBL_N1[7]
010000100000DBL_W1[8]
010001000000DBL_W1[9]
010010000000DBL_N2[8]
100000000001DBL_W2[7]
100000000010DBL_N0[9]
100000000100DBL_S2[9]
100000001000DBL_S2[8]
100000010000DBL_S1[9]
100000100000DBL_E1[8]
100001000000DBL_N2[7]
100010000000DBL_N1[8]
virtex2 INT_DCM_V2P switchbox INT muxes IMUX_G3_FAN[1]
BitsDestination
MAIN[9][62]MAIN[9][61]MAIN[8][61]MAIN[8][62]MAIN[10][63]MAIN[10][61]MAIN[11][63]MAIN[11][61]MAIN[13][63]MAIN[12][63]MAIN[12][61]MAIN[13][61]IMUX_G3_FAN[1]
Source
000000000000PULLUP
000100000001OMUX_S5
000100000010OMUX_W14
000100000100OMUX_ES7
000100001000OMUX_E13
000100010000IMUX_G1_FAN[1]
000100100000DBL_S1[8]
000101000000DBL_E1[9]
000110000000IMUX_G2_FAN[1]
001000000001DBL_W0[8]
001000000010OMUX_SW5
001000000100DBL_S0[8]
001000001000DBL_E0[9]
001000010000DBL_W1[7]
001000100000DBL_N1[9]
001001000000DBL_W2[9]
001010000000DBL_N2[9]
010000000001DBL_N0[7]
010000000010DBL_E2[9]
010000000100DBL_E2[8]
010000001000DBL_W2[8]
010000010000DBL_N1[7]
010000100000DBL_W1[8]
010001000000DBL_W1[9]
010010000000DBL_N2[8]
100000000001DBL_W2[7]
100000000010DBL_N0[9]
100000000100DBL_S2[9]
100000001000DBL_S2[8]
100000010000DBL_S1[9]
100000100000DBL_E1[8]
100001000000DBL_N2[7]
100010000000DBL_N1[8]
virtex2 INT_DCM_V2P switchbox INT muxes IMUX_G3_DATA[0]
BitsDestination
MAIN[9][79]MAIN[9][76]MAIN[8][76]MAIN[8][79]MAIN[10][78]MAIN[10][76]MAIN[11][78]MAIN[11][76]MAIN[13][78]MAIN[12][78]MAIN[12][76]MAIN[13][76]IMUX_G3_DATA[0]
Source
000000000000PULLUP
000100000001OMUX_S5
000100000010OMUX_W14
000100000100OMUX_ES7
000100001000OMUX_E13
000100010000IMUX_G1_FAN[1]
000100100000DBL_S1[8]
000101000000DBL_E1[9]
000110000000IMUX_G2_FAN[1]
001000000001DBL_W0[8]
001000000010OMUX_SW5
001000000100DBL_S0[8]
001000001000DBL_E0[9]
001000010000DBL_W1[7]
001000100000DBL_N1[9]
001001000000DBL_W2[9]
001010000000DBL_N2[9]
010000000001DBL_N0[7]
010000000010DBL_E2[9]
010000000100DBL_E2[8]
010000001000DBL_W2[8]
010000010000DBL_N1[7]
010000100000DBL_W1[8]
010001000000DBL_W1[9]
010010000000DBL_N2[8]
100000000001DBL_W2[7]
100000000010DBL_N0[9]
100000000100DBL_S2[9]
100000001000DBL_S2[8]
100000010000DBL_S1[9]
100000100000DBL_E1[8]
100001000000DBL_N2[7]
100010000000DBL_N1[8]
virtex2 INT_DCM_V2P switchbox INT muxes IMUX_G3_DATA[1]
BitsDestination
MAIN[9][78]MAIN[9][77]MAIN[8][77]MAIN[8][78]MAIN[10][79]MAIN[10][77]MAIN[11][79]MAIN[11][77]MAIN[13][79]MAIN[12][79]MAIN[12][77]MAIN[13][77]IMUX_G3_DATA[1]
Source
000000000000PULLUP
000100000001OMUX_S5
000100000010OMUX_W14
000100000100OMUX_ES7
000100001000OMUX_E13
000100010000IMUX_G1_FAN[1]
000100100000DBL_S1[8]
000101000000DBL_E1[9]
000110000000IMUX_G2_FAN[1]
001000000001DBL_W0[8]
001000000010OMUX_SW5
001000000100DBL_S0[8]
001000001000DBL_E0[9]
001000010000DBL_W1[7]
001000100000DBL_N1[9]
001001000000DBL_W2[9]
001010000000DBL_N2[9]
010000000001DBL_N0[7]
010000000010DBL_E2[9]
010000000100DBL_E2[8]
010000001000DBL_W2[8]
010000010000DBL_N1[7]
010000100000DBL_W1[8]
010001000000DBL_W1[9]
010010000000DBL_N2[8]
100000000001DBL_W2[7]
100000000010DBL_N0[9]
100000000100DBL_S2[9]
100000001000DBL_S2[8]
100000010000DBL_S1[9]
100000100000DBL_E1[8]
100001000000DBL_N2[7]
100010000000DBL_N1[8]
virtex2 INT_DCM_V2P switchbox INT muxes IMUX_G3_DATA[2]
BitsDestination
MAIN[9][72]MAIN[9][75]MAIN[8][75]MAIN[8][72]MAIN[10][73]MAIN[10][75]MAIN[11][73]MAIN[11][75]MAIN[13][73]MAIN[12][73]MAIN[12][75]MAIN[13][75]IMUX_G3_DATA[2]
Source
000000000000PULLUP
000100000001OMUX_S5
000100000010OMUX_W14
000100000100OMUX_ES7
000100001000OMUX_E13
000100010000IMUX_G1_FAN[1]
000100100000DBL_S1[8]
000101000000DBL_E1[9]
000110000000IMUX_G2_FAN[1]
001000000001DBL_W0[8]
001000000010OMUX_SW5
001000000100DBL_S0[8]
001000001000DBL_E0[9]
001000010000DBL_W1[7]
001000100000DBL_N1[9]
001001000000DBL_W2[9]
001010000000DBL_N2[9]
010000000001DBL_N0[7]
010000000010DBL_E2[9]
010000000100DBL_E2[8]
010000001000DBL_W2[8]
010000010000DBL_N1[7]
010000100000DBL_W1[8]
010001000000DBL_W1[9]
010010000000DBL_N2[8]
100000000001DBL_W2[7]
100000000010DBL_N0[9]
100000000100DBL_S2[9]
100000001000DBL_S2[8]
100000010000DBL_S1[9]
100000100000DBL_E1[8]
100001000000DBL_N2[7]
100010000000DBL_N1[8]
virtex2 INT_DCM_V2P switchbox INT muxes IMUX_G3_DATA[3]
BitsDestination
MAIN[9][73]MAIN[9][74]MAIN[8][74]MAIN[8][73]MAIN[10][72]MAIN[10][74]MAIN[11][72]MAIN[11][74]MAIN[13][72]MAIN[12][72]MAIN[12][74]MAIN[13][74]IMUX_G3_DATA[3]
Source
000000000000PULLUP
000100000001OMUX_S5
000100000010OMUX_W14
000100000100OMUX_ES7
000100001000OMUX_E13
000100010000IMUX_G1_FAN[1]
000100100000DBL_S1[8]
000101000000DBL_E1[9]
000110000000IMUX_G2_FAN[1]
001000000001DBL_W0[8]
001000000010OMUX_SW5
001000000100DBL_S0[8]
001000001000DBL_E0[9]
001000010000DBL_W1[7]
001000100000DBL_N1[9]
001001000000DBL_W2[9]
001010000000DBL_N2[9]
010000000001DBL_N0[7]
010000000010DBL_E2[9]
010000000100DBL_E2[8]
010000001000DBL_W2[8]
010000010000DBL_N1[7]
010000100000DBL_W1[8]
010001000000DBL_W1[9]
010010000000DBL_N2[8]
100000000001DBL_W2[7]
100000000010DBL_N0[9]
100000000100DBL_S2[9]
100000001000DBL_S2[8]
100000010000DBL_S1[9]
100000100000DBL_E1[8]
100001000000DBL_N2[7]
100010000000DBL_N1[8]
virtex2 INT_DCM_V2P switchbox INT muxes IMUX_G3_DATA[4]
BitsDestination
MAIN[9][71]MAIN[9][68]MAIN[8][68]MAIN[8][71]MAIN[10][70]MAIN[10][68]MAIN[11][70]MAIN[11][68]MAIN[13][70]MAIN[12][70]MAIN[12][68]MAIN[13][68]IMUX_G3_DATA[4]
Source
000000000000PULLUP
000100000001OMUX_S5
000100000010OMUX_W14
000100000100OMUX_ES7
000100001000OMUX_E13
000100010000IMUX_G1_FAN[1]
000100100000DBL_S1[8]
000101000000DBL_E1[9]
000110000000IMUX_G2_FAN[1]
001000000001DBL_W0[8]
001000000010OMUX_SW5
001000000100DBL_S0[8]
001000001000DBL_E0[9]
001000010000DBL_W1[7]
001000100000DBL_N1[9]
001001000000DBL_W2[9]
001010000000DBL_N2[9]
010000000001DBL_N0[7]
010000000010DBL_E2[9]
010000000100DBL_E2[8]
010000001000DBL_W2[8]
010000010000DBL_N1[7]
010000100000DBL_W1[8]
010001000000DBL_W1[9]
010010000000DBL_N2[8]
100000000001DBL_W2[7]
100000000010DBL_N0[9]
100000000100DBL_S2[9]
100000001000DBL_S2[8]
100000010000DBL_S1[9]
100000100000DBL_E1[8]
100001000000DBL_N2[7]
100010000000DBL_N1[8]
virtex2 INT_DCM_V2P switchbox INT muxes IMUX_G3_DATA[5]
BitsDestination
MAIN[9][70]MAIN[9][69]MAIN[8][69]MAIN[8][70]MAIN[10][71]MAIN[10][69]MAIN[11][71]MAIN[11][69]MAIN[13][71]MAIN[12][71]MAIN[12][69]MAIN[13][69]IMUX_G3_DATA[5]
Source
000000000000PULLUP
000100000001OMUX_S5
000100000010OMUX_W14
000100000100OMUX_ES7
000100001000OMUX_E13
000100010000IMUX_G1_FAN[1]
000100100000DBL_S1[8]
000101000000DBL_E1[9]
000110000000IMUX_G2_FAN[1]
001000000001DBL_W0[8]
001000000010OMUX_SW5
001000000100DBL_S0[8]
001000001000DBL_E0[9]
001000010000DBL_W1[7]
001000100000DBL_N1[9]
001001000000DBL_W2[9]
001010000000DBL_N2[9]
010000000001DBL_N0[7]
010000000010DBL_E2[9]
010000000100DBL_E2[8]
010000001000DBL_W2[8]
010000010000DBL_N1[7]
010000100000DBL_W1[8]
010001000000DBL_W1[9]
010010000000DBL_N2[8]
100000000001DBL_W2[7]
100000000010DBL_N0[9]
100000000100DBL_S2[9]
100000001000DBL_S2[8]
100000010000DBL_S1[9]
100000100000DBL_E1[8]
100001000000DBL_N2[7]
100010000000DBL_N1[8]
virtex2 INT_DCM_V2P switchbox INT muxes IMUX_G3_DATA[6]
BitsDestination
MAIN[9][64]MAIN[9][67]MAIN[8][67]MAIN[8][64]MAIN[10][65]MAIN[10][67]MAIN[11][65]MAIN[11][67]MAIN[13][65]MAIN[12][65]MAIN[12][67]MAIN[13][67]IMUX_G3_DATA[6]
Source
000000000000PULLUP
000100000001OMUX_S5
000100000010OMUX_W14
000100000100OMUX_ES7
000100001000OMUX_E13
000100010000IMUX_G1_FAN[1]
000100100000DBL_S1[8]
000101000000DBL_E1[9]
000110000000IMUX_G2_FAN[1]
001000000001DBL_W0[8]
001000000010OMUX_SW5
001000000100DBL_S0[8]
001000001000DBL_E0[9]
001000010000DBL_W1[7]
001000100000DBL_N1[9]
001001000000DBL_W2[9]
001010000000DBL_N2[9]
010000000001DBL_N0[7]
010000000010DBL_E2[9]
010000000100DBL_E2[8]
010000001000DBL_W2[8]
010000010000DBL_N1[7]
010000100000DBL_W1[8]
010001000000DBL_W1[9]
010010000000DBL_N2[8]
100000000001DBL_W2[7]
100000000010DBL_N0[9]
100000000100DBL_S2[9]
100000001000DBL_S2[8]
100000010000DBL_S1[9]
100000100000DBL_E1[8]
100001000000DBL_N2[7]
100010000000DBL_N1[8]
virtex2 INT_DCM_V2P switchbox INT muxes IMUX_G3_DATA[7]
BitsDestination
MAIN[9][65]MAIN[9][66]MAIN[8][66]MAIN[8][65]MAIN[10][64]MAIN[10][66]MAIN[11][64]MAIN[11][66]MAIN[13][64]MAIN[12][64]MAIN[12][66]MAIN[13][66]IMUX_G3_DATA[7]
Source
000000000000PULLUP
000100000001OMUX_S5
000100000010OMUX_W14
000100000100OMUX_ES7
000100001000OMUX_E13
000100010000IMUX_G1_FAN[1]
000100100000DBL_S1[8]
000101000000DBL_E1[9]
000110000000IMUX_G2_FAN[1]
001000000001DBL_W0[8]
001000000010OMUX_SW5
001000000100DBL_S0[8]
001000001000DBL_E0[9]
001000010000DBL_W1[7]
001000100000DBL_N1[9]
001001000000DBL_W2[9]
001010000000DBL_N2[9]
010000000001DBL_N0[7]
010000000010DBL_E2[9]
010000000100DBL_E2[8]
010000001000DBL_W2[8]
010000010000DBL_N1[7]
010000100000DBL_W1[8]
010001000000DBL_W1[9]
010010000000DBL_N2[8]
100000000001DBL_W2[7]
100000000010DBL_N0[9]
100000000100DBL_S2[9]
100000001000DBL_S2[8]
100000010000DBL_S1[9]
100000100000DBL_E1[8]
100001000000DBL_N2[7]
100010000000DBL_N1[8]

Bitstream

virtex2 INT_DCM_V2P rect MAIN
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21
B79 - - - - INT: mux IMUX_CE[2] bit 5 INT: mux IMUX_CE[3] bit 1 INT: mux OMUX[14] bit 0 INT: mux OMUX[15] bit 6 INT: mux IMUX_G3_DATA[0] bit 8 INT: mux IMUX_G3_DATA[0] bit 11 INT: mux IMUX_G3_DATA[1] bit 7 INT: mux IMUX_G3_DATA[1] bit 5 INT: mux IMUX_G3_DATA[1] bit 2 INT: mux IMUX_G3_DATA[1] bit 3 INT: mux DBL_E0[9] bit 0 INT: mux DBL_W0[9] bit 7 INT: mux DBL_E0[9] bit 5 INT: mux DBL_E0[9] bit 7 INT: mux HEX_W0[9] bit 0 INT: mux HEX_W0[9] bit 3 INT: mux HEX_W0[9] bit 4 INT: mux LV[18] bit 1
B78 - - - - INT: !invert IMUX_CE_OPTINV[3] ← IMUX_CE[3] INT: mux IMUX_CE[3] bit 3 INT: mux OMUX[15] bit 9 INT: mux OMUX[15] bit 7 INT: mux IMUX_G3_DATA[1] bit 8 INT: mux IMUX_G3_DATA[1] bit 11 INT: mux IMUX_G3_DATA[0] bit 7 INT: mux IMUX_G3_DATA[0] bit 5 INT: mux IMUX_G3_DATA[0] bit 2 INT: mux IMUX_G3_DATA[0] bit 3 INT: mux DBL_E0[9] bit 1 INT: mux DBL_W0[9] bit 4 INT: mux DBL_W0[9] bit 3 INT: mux DBL_W0[9] bit 0 INT: mux HEX_E0[9] bit 1 INT: mux HEX_E0[9] bit 3 INT: mux HEX_E0[9] bit 5 INT: mux HEX_W0[9] bit 6
B77 - - - - INT: mux IMUX_CE[3] bit 0 INT: mux IMUX_CE[3] bit 2 INT: mux OMUX[15] bit 0 INT: mux OMUX[15] bit 8 INT: mux IMUX_G3_DATA[1] bit 9 INT: mux IMUX_G3_DATA[1] bit 10 INT: mux IMUX_G3_DATA[1] bit 6 INT: mux IMUX_G3_DATA[1] bit 4 INT: mux IMUX_G3_DATA[1] bit 1 INT: mux IMUX_G3_DATA[1] bit 0 INT: mux DBL_W0[9] bit 5 INT: mux DBL_E0[9] bit 3 INT: mux DBL_W0[9] bit 2 INT: mux DBL_W0[9] bit 1 INT: mux HEX_W0[9] bit 2 INT: mux HEX_W0[9] bit 1 INT: mux HEX_E0[9] bit 6 INT: mux LV[18] bit 3
B76 - - - - INT: mux IMUX_CE[3] bit 4 INT: mux IMUX_CE[3] bit 5 INT: mux OMUX[14] bit 1 INT: mux OMUX[15] bit 1 INT: mux IMUX_G3_DATA[0] bit 9 INT: mux IMUX_G3_DATA[0] bit 10 INT: mux IMUX_G3_DATA[0] bit 6 INT: mux IMUX_G3_DATA[0] bit 4 INT: mux IMUX_G3_DATA[0] bit 1 INT: mux IMUX_G3_DATA[0] bit 0 INT: mux DBL_W0[9] bit 6 INT: mux DBL_E0[9] bit 2 INT: mux DBL_E0[9] bit 4 INT: mux DBL_E0[9] bit 6 INT: mux HEX_E0[9] bit 2 INT: mux HEX_E0[9] bit 0 INT: mux HEX_E0[9] bit 4 INT: mux HEX_W0[9] bit 5
B75 - - - - INT: mux IMUX_CE[2] bit 4 INT: mux IMUX_CE[2] bit 7 INT: mux OMUX[15] bit 2 INT: mux OMUX[14] bit 2 INT: mux IMUX_G3_DATA[2] bit 9 INT: mux IMUX_G3_DATA[2] bit 10 INT: mux IMUX_G3_DATA[2] bit 6 INT: mux IMUX_G3_DATA[2] bit 4 INT: mux IMUX_G3_DATA[2] bit 1 INT: mux IMUX_G3_DATA[2] bit 0 INT: mux DBL_S0[9] bit 4 INT: mux DBL_N0[9] bit 2 INT: mux DBL_S0[9] bit 0 INT: mux DBL_S0[9] bit 3 INT: mux HEX_N0[9] bit 1 INT: mux HEX_N0[9] bit 3 INT: mux HEX_N0[9] bit 5 INT: mux LV[6] bit 0
B74 - - - - INT: mux IMUX_CE[3] bit 7 INT: mux IMUX_CE[3] bit 6 INT: mux OMUX[15] bit 3 INT: mux OMUX[14] bit 3 INT: mux IMUX_G3_DATA[3] bit 9 INT: mux IMUX_G3_DATA[3] bit 10 INT: mux IMUX_G3_DATA[3] bit 6 INT: mux IMUX_G3_DATA[3] bit 4 INT: mux IMUX_G3_DATA[3] bit 1 INT: mux IMUX_G3_DATA[3] bit 0 INT: mux DBL_S0[9] bit 5 INT: mux DBL_N0[9] bit 0 INT: mux DBL_N0[9] bit 7 INT: mux DBL_N0[9] bit 5 INT: mux HEX_S0[9] bit 1 INT: mux HEX_S0[9] bit 2 INT: mux HEX_S0[9] bit 4 INT: mux HEX_N0[9] bit 4
B73 - - - - INT: mux IMUX_CE[2] bit 0 INT: mux IMUX_CE[2] bit 1 INT: mux OMUX[14] bit 4 INT: mux OMUX[15] bit 4 INT: mux IMUX_G3_DATA[3] bit 8 INT: mux IMUX_G3_DATA[3] bit 11 INT: mux IMUX_G3_DATA[2] bit 7 INT: mux IMUX_G3_DATA[2] bit 5 INT: mux IMUX_G3_DATA[2] bit 2 INT: mux IMUX_G3_DATA[2] bit 3 INT: mux DBL_N0[9] bit 1 INT: mux DBL_S0[9] bit 6 INT: mux DBL_N0[9] bit 6 INT: mux DBL_N0[9] bit 4 INT: mux HEX_N0[9] bit 2 INT: mux HEX_N0[9] bit 0 INT: mux HEX_S0[9] bit 5 INT: mux LV[6] bit 6
B72 - - - - INT: !invert IMUX_CE_OPTINV[2] ← IMUX_CE[2] INT: mux IMUX_CE[2] bit 3 INT: mux OMUX[15] bit 5 INT: mux OMUX[14] bit 8 INT: mux IMUX_G3_DATA[2] bit 8 INT: mux IMUX_G3_DATA[2] bit 11 INT: mux IMUX_G3_DATA[3] bit 7 INT: mux IMUX_G3_DATA[3] bit 5 INT: mux IMUX_G3_DATA[3] bit 2 INT: mux IMUX_G3_DATA[3] bit 3 INT: mux DBL_N0[9] bit 3 INT: mux DBL_S0[9] bit 7 INT: mux DBL_S0[9] bit 1 INT: mux DBL_S0[9] bit 2 INT: mux HEX_S0[9] bit 3 INT: mux HEX_S0[9] bit 0 INT: mux HEX_S0[9] bit 6 INT: mux HEX_N0[9] bit 6
B71 - - - - INT: mux IMUX_CE[2] bit 6 INT: mux IMUX_CE[2] bit 2 INT: mux OMUX[14] bit 9 INT: mux OMUX[14] bit 7 INT: mux IMUX_G3_DATA[4] bit 8 INT: mux IMUX_G3_DATA[4] bit 11 INT: mux IMUX_G3_DATA[5] bit 7 INT: mux IMUX_G3_DATA[5] bit 5 INT: mux IMUX_G3_DATA[5] bit 2 INT: mux IMUX_G3_DATA[5] bit 3 INT: mux DBL_E0[8] bit 2 INT: mux DBL_W0[8] bit 3 INT: mux DBL_E0[8] bit 4 INT: mux DBL_E0[8] bit 7 INT: mux HEX_E0[8] bit 0 INT: mux HEX_E0[8] bit 3 INT: mux HEX_E0[8] bit 4 INT: mux LV[6] bit 2
B70 - - - - - - INT: mux OMUX[14] bit 5 INT: mux OMUX[14] bit 6 INT: mux IMUX_G3_DATA[5] bit 8 INT: mux IMUX_G3_DATA[5] bit 11 INT: mux IMUX_G3_DATA[4] bit 7 INT: mux IMUX_G3_DATA[4] bit 5 INT: mux IMUX_G3_DATA[4] bit 2 INT: mux IMUX_G3_DATA[4] bit 3 INT: mux DBL_E0[8] bit 0 INT: mux DBL_W0[8] bit 0 INT: mux DBL_W0[8] bit 7 INT: mux DBL_W0[8] bit 4 INT: mux HEX_W0[8] bit 0 INT: mux HEX_W0[8] bit 3 INT: mux HEX_W0[8] bit 4 INT: mux HEX_E0[8] bit 5
B69 - - - - - - INT: mux OMUX[12] bit 4 INT: mux OMUX[13] bit 6 INT: mux IMUX_G3_DATA[5] bit 9 INT: mux IMUX_G3_DATA[5] bit 10 INT: mux IMUX_G3_DATA[5] bit 6 INT: mux IMUX_G3_DATA[5] bit 4 INT: mux IMUX_G3_DATA[5] bit 1 INT: mux IMUX_G3_DATA[5] bit 0 INT: mux DBL_W0[8] bit 2 INT: mux DBL_E0[8] bit 3 INT: mux DBL_W0[8] bit 6 INT: mux DBL_W0[8] bit 5 INT: mux HEX_E0[8] bit 2 INT: mux HEX_E0[8] bit 1 INT: mux HEX_W0[8] bit 5 INT: mux LV[6] bit 3
B68 - - - - - - INT: mux OMUX[13] bit 9 INT: mux OMUX[13] bit 7 INT: mux IMUX_G3_DATA[4] bit 9 INT: mux IMUX_G3_DATA[4] bit 10 INT: mux IMUX_G3_DATA[4] bit 6 INT: mux IMUX_G3_DATA[4] bit 4 INT: mux IMUX_G3_DATA[4] bit 1 INT: mux IMUX_G3_DATA[4] bit 0 INT: mux DBL_W0[8] bit 1 INT: mux DBL_E0[8] bit 1 INT: mux DBL_E0[8] bit 5 INT: mux DBL_E0[8] bit 6 INT: mux HEX_W0[8] bit 2 INT: mux HEX_W0[8] bit 1 INT: mux HEX_W0[8] bit 6 INT: mux HEX_E0[8] bit 6
B67 - - - - - - INT: mux OMUX[13] bit 4 INT: mux OMUX[13] bit 8 INT: mux IMUX_G3_DATA[6] bit 9 INT: mux IMUX_G3_DATA[6] bit 10 INT: mux IMUX_G3_DATA[6] bit 6 INT: mux IMUX_G3_DATA[6] bit 4 INT: mux IMUX_G3_DATA[6] bit 1 INT: mux IMUX_G3_DATA[6] bit 0 INT: mux DBL_S0[8] bit 3 INT: mux DBL_N0[8] bit 1 INT: mux DBL_S0[8] bit 5 INT: mux DBL_S0[8] bit 7 INT: mux HEX_S0[8] bit 1 INT: mux HEX_S0[8] bit 3 INT: mux HEX_S0[8] bit 5 INT: mux LV[18] bit 6
B66 - - - - - - INT: mux OMUX[12] bit 5 INT: mux OMUX[13] bit 5 INT: mux IMUX_G3_DATA[7] bit 9 INT: mux IMUX_G3_DATA[7] bit 10 INT: mux IMUX_G3_DATA[7] bit 6 INT: mux IMUX_G3_DATA[7] bit 4 INT: mux IMUX_G3_DATA[7] bit 1 INT: mux IMUX_G3_DATA[7] bit 0 INT: mux DBL_S0[8] bit 0 INT: mux DBL_N0[8] bit 0 INT: mux DBL_N0[8] bit 7 INT: mux DBL_N0[8] bit 5 INT: mux HEX_N0[8] bit 1 INT: mux HEX_N0[8] bit 2 INT: mux HEX_N0[8] bit 5 INT: mux HEX_S0[8] bit 4
B65 - - - - - - INT: mux OMUX[13] bit 0 INT: mux OMUX[12] bit 0 INT: mux IMUX_G3_DATA[7] bit 8 INT: mux IMUX_G3_DATA[7] bit 11 INT: mux IMUX_G3_DATA[6] bit 7 INT: mux IMUX_G3_DATA[6] bit 5 INT: mux IMUX_G3_DATA[6] bit 2 INT: mux IMUX_G3_DATA[6] bit 3 INT: mux DBL_N0[8] bit 3 INT: mux DBL_S0[8] bit 1 INT: mux DBL_N0[8] bit 6 INT: mux DBL_N0[8] bit 4 INT: mux HEX_S0[8] bit 2 INT: mux HEX_S0[8] bit 0 INT: mux HEX_N0[8] bit 4 INT: mux LV[6] bit 1
B64 - - - - - - INT: mux OMUX[13] bit 1 INT: mux OMUX[12] bit 1 INT: mux IMUX_G3_DATA[6] bit 8 INT: mux IMUX_G3_DATA[6] bit 11 INT: mux IMUX_G3_DATA[7] bit 7 INT: mux IMUX_G3_DATA[7] bit 5 INT: mux IMUX_G3_DATA[7] bit 2 INT: mux IMUX_G3_DATA[7] bit 3 INT: mux DBL_N0[8] bit 2 INT: mux DBL_S0[8] bit 2 INT: mux DBL_S0[8] bit 4 INT: mux DBL_S0[8] bit 6 INT: mux HEX_N0[8] bit 3 INT: mux HEX_N0[8] bit 0 INT: mux HEX_N0[8] bit 6 INT: mux HEX_S0[8] bit 6
B63 - - - - - - INT: mux OMUX[12] bit 2 INT: mux OMUX[13] bit 2 INT: mux IMUX_G3_FAN[0] bit 8 INT: mux IMUX_G3_FAN[0] bit 11 INT: mux IMUX_G3_FAN[1] bit 7 INT: mux IMUX_G3_FAN[1] bit 5 INT: mux IMUX_G3_FAN[1] bit 2 INT: mux IMUX_G3_FAN[1] bit 3 INT: mux DBL_E0[7] bit 2 INT: mux DBL_W0[7] bit 3 INT: mux DBL_E0[7] bit 4 INT: mux DBL_E0[7] bit 7 INT: mux HEX_W0[7] bit 0 INT: mux HEX_W0[7] bit 3 INT: mux HEX_W0[7] bit 4 INT: mux LV[18] bit 0
B62 - - - - INT: mux IMUX_DCM_CLK[2] bit 7 - INT: mux OMUX[13] bit 3 INT: mux OMUX[12] bit 8 INT: mux IMUX_G3_FAN[1] bit 8 INT: mux IMUX_G3_FAN[1] bit 11 INT: mux IMUX_G3_FAN[0] bit 7 INT: mux IMUX_G3_FAN[0] bit 5 INT: mux IMUX_G3_FAN[0] bit 2 INT: mux IMUX_G3_FAN[0] bit 3 INT: mux DBL_E0[7] bit 0 INT: mux DBL_W0[7] bit 0 INT: mux DBL_W0[7] bit 7 INT: mux DBL_W0[7] bit 4 INT: mux HEX_E0[7] bit 0 INT: mux HEX_E0[7] bit 3 INT: mux HEX_E0[7] bit 4 INT: mux HEX_W0[7] bit 5
B61 - - - - - - INT: mux OMUX[12] bit 9 INT: mux OMUX[12] bit 7 INT: mux IMUX_G3_FAN[1] bit 9 INT: mux IMUX_G3_FAN[1] bit 10 INT: mux IMUX_G3_FAN[1] bit 6 INT: mux IMUX_G3_FAN[1] bit 4 INT: mux IMUX_G3_FAN[1] bit 1 INT: mux IMUX_G3_FAN[1] bit 0 INT: mux DBL_W0[7] bit 2 INT: mux DBL_E0[7] bit 3 INT: mux DBL_W0[7] bit 6 INT: mux DBL_W0[7] bit 5 INT: mux HEX_W0[7] bit 2 INT: mux HEX_W0[7] bit 1 INT: mux HEX_E0[7] bit 5 INT: mux LV[6] bit 5
B60 - - - - - - INT: mux OMUX[12] bit 3 INT: mux OMUX[12] bit 6 INT: mux IMUX_G3_FAN[0] bit 9 INT: mux IMUX_G3_FAN[0] bit 10 INT: mux IMUX_G3_FAN[0] bit 6 INT: mux IMUX_G3_FAN[0] bit 4 INT: mux IMUX_G3_FAN[0] bit 1 INT: mux IMUX_G3_FAN[0] bit 0 INT: mux DBL_W0[7] bit 1 INT: mux DBL_E0[7] bit 1 INT: mux DBL_E0[7] bit 5 INT: mux DBL_E0[7] bit 6 INT: mux HEX_E0[7] bit 2 INT: mux HEX_E0[7] bit 1 INT: mux HEX_E0[7] bit 6 INT: mux HEX_W0[7] bit 6
B59 - - - - - - INT: mux OMUX[10] bit 4 INT: mux OMUX[11] bit 6 INT: mux IMUX_G2_FAN[0] bit 9 INT: mux IMUX_G2_FAN[0] bit 10 INT: mux IMUX_G2_FAN[0] bit 6 INT: mux IMUX_G2_FAN[0] bit 5 INT: mux IMUX_G2_FAN[0] bit 1 INT: mux IMUX_G2_FAN[0] bit 3 INT: mux DBL_S0[7] bit 4 INT: mux DBL_N0[7] bit 6 INT: mux DBL_S0[7] bit 1 INT: mux DBL_S0[7] bit 3 INT: mux HEX_N0[7] bit 1 INT: mux HEX_N0[7] bit 3 INT: mux HEX_N0[7] bit 6 INT: mux LV[18] bit 2
B58 - - - - INT: mux IMUX_DCM_CLK[2] bit 6 INT: mux IMUX_DCM_CLK[2] bit 4 INT: mux OMUX[11] bit 9 INT: mux OMUX[11] bit 7 INT: mux IMUX_G2_FAN[1] bit 9 INT: mux IMUX_G2_FAN[1] bit 10 INT: mux IMUX_G2_FAN[1] bit 6 INT: mux IMUX_G2_FAN[1] bit 5 INT: mux IMUX_G2_FAN[1] bit 1 INT: mux IMUX_G2_FAN[1] bit 3 INT: mux DBL_S0[7] bit 5 INT: mux DBL_N0[7] bit 5 INT: mux DBL_N0[7] bit 3 INT: mux DBL_N0[7] bit 1 INT: mux HEX_S0[7] bit 1 INT: mux HEX_S0[7] bit 2 INT: mux HEX_S0[7] bit 5 INT: mux HEX_N0[7] bit 5
B57 - - - - - - INT: mux OMUX[11] bit 4 INT: mux OMUX[11] bit 8 INT: mux IMUX_G2_FAN[1] bit 8 INT: mux IMUX_G2_FAN[1] bit 11 INT: mux IMUX_G2_FAN[0] bit 7 INT: mux IMUX_G2_FAN[0] bit 4 INT: mux IMUX_G2_FAN[0] bit 0 INT: mux IMUX_G2_FAN[0] bit 2 INT: mux DBL_N0[7] bit 4 INT: mux DBL_S0[7] bit 6 INT: mux DBL_N0[7] bit 2 INT: mux DBL_N0[7] bit 0 INT: mux HEX_N0[7] bit 2 INT: mux HEX_N0[7] bit 0 INT: mux HEX_S0[7] bit 6 INT: mux LV[18] bit 4
B56 - - - - INT: mux IMUX_DCM_CLK[2] bit 0 INT: mux IMUX_DCM_CLK[2] bit 5 INT: mux OMUX[10] bit 5 INT: mux OMUX[11] bit 5 INT: mux IMUX_G2_FAN[0] bit 8 INT: mux IMUX_G2_FAN[0] bit 11 INT: mux IMUX_G2_FAN[1] bit 7 INT: mux IMUX_G2_FAN[1] bit 4 INT: mux IMUX_G2_FAN[1] bit 0 INT: mux IMUX_G2_FAN[1] bit 2 INT: mux DBL_N0[7] bit 7 INT: mux DBL_S0[7] bit 7 INT: mux DBL_S0[7] bit 0 INT: mux DBL_S0[7] bit 2 INT: mux HEX_S0[7] bit 3 INT: mux HEX_S0[7] bit 0 INT: mux HEX_S0[7] bit 4 INT: mux HEX_N0[7] bit 4
B55 - - - - - - INT: mux OMUX[11] bit 0 INT: mux OMUX[10] bit 0 INT: mux IMUX_G2_DATA[6] bit 8 INT: mux IMUX_G2_DATA[6] bit 11 INT: mux IMUX_G2_DATA[7] bit 7 INT: mux IMUX_G2_DATA[7] bit 4 INT: mux IMUX_G2_DATA[7] bit 0 INT: mux IMUX_G2_DATA[7] bit 2 INT: mux DBL_E0[6] bit 1 INT: mux DBL_W0[6] bit 7 INT: mux DBL_E0[6] bit 5 INT: mux DBL_E0[6] bit 7 INT: mux HEX_E0[6] bit 1 INT: mux HEX_E0[6] bit 3 INT: mux HEX_E0[6] bit 5 INT: mux LV[6] bit 4
B54 - - - - INT: mux IMUX_DCM_CLK[2] bit 3 INT: mux IMUX_DCM_CLK[2] bit 1 INT: mux OMUX[11] bit 1 INT: mux OMUX[10] bit 1 INT: mux IMUX_G2_DATA[7] bit 8 INT: mux IMUX_G2_DATA[7] bit 11 INT: mux IMUX_G2_DATA[6] bit 7 INT: mux IMUX_G2_DATA[6] bit 4 INT: mux IMUX_G2_DATA[6] bit 0 INT: mux IMUX_G2_DATA[6] bit 2 INT: mux DBL_E0[6] bit 0 INT: mux DBL_W0[6] bit 5 INT: mux DBL_W0[6] bit 3 INT: mux DBL_W0[6] bit 0 INT: mux HEX_W0[6] bit 1 INT: mux HEX_W0[6] bit 3 INT: mux HEX_W0[6] bit 4 INT: mux HEX_E0[6] bit 4
B53 - - - - - INT: mux IMUX_DCM_CLK[2] bit 11 INT: mux OMUX[10] bit 2 INT: mux OMUX[11] bit 2 INT: mux IMUX_G2_DATA[7] bit 9 INT: mux IMUX_G2_DATA[7] bit 10 INT: mux IMUX_G2_DATA[7] bit 6 INT: mux IMUX_G2_DATA[7] bit 5 INT: mux IMUX_G2_DATA[7] bit 1 INT: mux IMUX_G2_DATA[7] bit 3 INT: mux DBL_W0[6] bit 4 INT: mux DBL_E0[6] bit 3 INT: mux DBL_W0[6] bit 2 INT: mux DBL_W0[6] bit 1 INT: mux HEX_E0[6] bit 2 INT: mux HEX_E0[6] bit 0 INT: mux HEX_W0[6] bit 5 INT: mux LV[18] bit 5
B52 - - - - INT: mux IMUX_DCM_CLK[2] bit 8 INT: mux IMUX_DCM_CLK[2] bit 10 INT: mux OMUX[11] bit 3 INT: mux OMUX[10] bit 8 INT: mux IMUX_G2_DATA[6] bit 9 INT: mux IMUX_G2_DATA[6] bit 10 INT: mux IMUX_G2_DATA[6] bit 6 INT: mux IMUX_G2_DATA[6] bit 5 INT: mux IMUX_G2_DATA[6] bit 1 INT: mux IMUX_G2_DATA[6] bit 3 INT: mux DBL_W0[6] bit 6 INT: mux DBL_E0[6] bit 2 INT: mux DBL_E0[6] bit 4 INT: mux DBL_E0[6] bit 6 INT: mux HEX_W0[6] bit 2 INT: mux HEX_W0[6] bit 0 INT: mux HEX_W0[6] bit 6 INT: mux HEX_E0[6] bit 6
B51 - - - - INT: invert IMUX_DCM_CLK_OPTINV[2] ← IMUX_DCM_CLK[2] - INT: mux OMUX[10] bit 9 INT: mux OMUX[10] bit 7 INT: mux IMUX_G2_DATA[4] bit 9 INT: mux IMUX_G2_DATA[4] bit 10 INT: mux IMUX_G2_DATA[4] bit 6 INT: mux IMUX_G2_DATA[4] bit 5 INT: mux IMUX_G2_DATA[4] bit 1 INT: mux IMUX_G2_DATA[4] bit 3 INT: mux DBL_S0[6] bit 3 INT: mux DBL_N0[6] bit 1 INT: mux DBL_S0[6] bit 4 INT: mux DBL_S0[6] bit 7 INT: mux HEX_S0[6] bit 0 INT: mux HEX_S0[6] bit 3 INT: mux HEX_S0[6] bit 4 INT: mux LH[0] bit 0
B50 - - - - INT: mux IMUX_DCM_CLK[2] bit 2 INT: mux IMUX_DCM_CLK[2] bit 9 INT: mux OMUX[10] bit 3 INT: mux OMUX[10] bit 6 INT: mux IMUX_G2_DATA[5] bit 9 INT: mux IMUX_G2_DATA[5] bit 10 INT: mux IMUX_G2_DATA[5] bit 6 INT: mux IMUX_G2_DATA[5] bit 5 INT: mux IMUX_G2_DATA[5] bit 1 INT: mux IMUX_G2_DATA[5] bit 3 INT: mux DBL_S0[6] bit 0 INT: mux DBL_N0[6] bit 0 INT: mux DBL_N0[6] bit 7 INT: mux DBL_N0[6] bit 4 INT: mux HEX_N0[6] bit 0 INT: mux HEX_N0[6] bit 2 INT: mux HEX_N0[6] bit 4 INT: mux HEX_S0[6] bit 5
B49 - - - - INT: mux IMUX_DCM_CLK[1] bit 2 INT: mux IMUX_DCM_CLK[1] bit 9 INT: mux OMUX[8] bit 0 INT: mux OMUX[9] bit 6 INT: mux IMUX_G2_DATA[5] bit 8 INT: mux IMUX_G2_DATA[5] bit 11 INT: mux IMUX_G2_DATA[4] bit 7 INT: mux IMUX_G2_DATA[4] bit 4 INT: mux IMUX_G2_DATA[4] bit 0 INT: mux IMUX_G2_DATA[4] bit 2 INT: mux DBL_N0[6] bit 3 INT: mux DBL_S0[6] bit 1 INT: mux DBL_N0[6] bit 6 INT: mux DBL_N0[6] bit 5 INT: mux HEX_S0[6] bit 2 INT: mux HEX_S0[6] bit 1 INT: mux HEX_N0[6] bit 5 INT: mux LH[0] bit 1
B48 - - - - INT: invert IMUX_DCM_CLK_OPTINV[1] ← IMUX_DCM_CLK[1] INT: mux IMUX_DCM_CLK[0] bit 2 INT: mux OMUX[9] bit 9 INT: mux OMUX[9] bit 7 INT: mux IMUX_G2_DATA[4] bit 8 INT: mux IMUX_G2_DATA[4] bit 11 INT: mux IMUX_G2_DATA[5] bit 7 INT: mux IMUX_G2_DATA[5] bit 4 INT: mux IMUX_G2_DATA[5] bit 0 INT: mux IMUX_G2_DATA[5] bit 2 INT: mux DBL_N0[6] bit 2 INT: mux DBL_S0[6] bit 2 INT: mux DBL_S0[6] bit 5 INT: mux DBL_S0[6] bit 6 INT: mux HEX_N0[6] bit 3 INT: mux HEX_N0[6] bit 1 INT: mux HEX_N0[6] bit 6 INT: mux HEX_S0[6] bit 6
B47 - - - - INT: mux IMUX_DCM_CLK[1] bit 8 INT: mux IMUX_DCM_CLK[1] bit 10 INT: mux OMUX[9] bit 0 INT: mux OMUX[9] bit 8 INT: mux IMUX_G2_DATA[2] bit 8 INT: mux IMUX_G2_DATA[2] bit 11 INT: mux IMUX_G2_DATA[3] bit 7 INT: mux IMUX_G2_DATA[3] bit 4 INT: mux IMUX_G2_DATA[3] bit 0 INT: mux IMUX_G2_DATA[3] bit 2 INT: mux DBL_E0[5] bit 2 INT: mux DBL_W0[5] bit 3 INT: mux DBL_E0[5] bit 4 INT: mux DBL_E0[5] bit 7 INT: mux HEX_W0[5] bit 1 INT: mux HEX_W0[5] bit 3 INT: mux HEX_W0[5] bit 5 INT: mux LH[0] bit 2
B46 - - - - INT: mux IMUX_DCM_CLK[0] bit 3 INT: mux IMUX_DCM_CLK[1] bit 11 INT: mux OMUX[8] bit 1 INT: mux OMUX[9] bit 1 INT: mux IMUX_G2_DATA[3] bit 8 INT: mux IMUX_G2_DATA[3] bit 11 INT: mux IMUX_G2_DATA[2] bit 7 INT: mux IMUX_G2_DATA[2] bit 4 INT: mux IMUX_G2_DATA[2] bit 0 INT: mux IMUX_G2_DATA[2] bit 2 INT: mux DBL_E0[5] bit 0 INT: mux DBL_W0[5] bit 0 INT: mux DBL_W0[5] bit 7 INT: mux DBL_W0[5] bit 5 INT: mux HEX_E0[5] bit 0 INT: mux HEX_E0[5] bit 3 INT: mux HEX_E0[5] bit 4 INT: mux HEX_W0[5] bit 4
B45 - - - - INT: mux IMUX_DCM_CLK[1] bit 3 INT: mux IMUX_DCM_CLK[1] bit 1 INT: mux OMUX[9] bit 2 INT: mux OMUX[8] bit 2 INT: mux IMUX_G2_DATA[3] bit 9 INT: mux IMUX_G2_DATA[3] bit 10 INT: mux IMUX_G2_DATA[3] bit 6 INT: mux IMUX_G2_DATA[3] bit 5 INT: mux IMUX_G2_DATA[3] bit 1 INT: mux IMUX_G2_DATA[3] bit 3 INT: mux DBL_W0[5] bit 2 INT: mux DBL_E0[5] bit 3 INT: mux DBL_W0[5] bit 6 INT: mux DBL_W0[5] bit 4 INT: mux HEX_W0[5] bit 2 INT: mux HEX_W0[5] bit 0 INT: mux HEX_E0[5] bit 5 INT: mux LH[12] bit 1
B44 - - - - INT: mux IMUX_DCM_CLK[0] bit 1 INT: mux IMUX_DCM_CLK[0] bit 0 INT: mux OMUX[9] bit 3 INT: mux OMUX[8] bit 3 INT: mux IMUX_G2_DATA[2] bit 9 INT: mux IMUX_G2_DATA[2] bit 10 INT: mux IMUX_G2_DATA[2] bit 6 INT: mux IMUX_G2_DATA[2] bit 5 INT: mux IMUX_G2_DATA[2] bit 1 INT: mux IMUX_G2_DATA[2] bit 3 INT: mux DBL_W0[5] bit 1 INT: mux DBL_E0[5] bit 1 INT: mux DBL_E0[5] bit 5 INT: mux DBL_E0[5] bit 6 INT: mux HEX_E0[5] bit 2 INT: mux HEX_E0[5] bit 1 INT: mux HEX_E0[5] bit 6 INT: mux HEX_W0[5] bit 6
B43 - - - - INT: mux IMUX_DCM_CLK[1] bit 0 INT: mux IMUX_DCM_CLK[1] bit 5 INT: mux OMUX[8] bit 4 INT: mux OMUX[9] bit 4 INT: mux IMUX_G2_DATA[0] bit 9 INT: mux IMUX_G2_DATA[0] bit 10 INT: mux IMUX_G2_DATA[0] bit 6 INT: mux IMUX_G2_DATA[0] bit 5 INT: mux IMUX_G2_DATA[0] bit 1 INT: mux IMUX_G2_DATA[0] bit 3 INT: mux DBL_S0[5] bit 3 INT: mux DBL_N0[5] bit 1 INT: mux DBL_S0[5] bit 4 INT: mux DBL_S0[5] bit 7 INT: mux HEX_N0[5] bit 1 INT: mux HEX_N0[5] bit 3 INT: mux HEX_N0[5] bit 5 INT: mux LH[12] bit 0
B42 - - - - INT: mux IMUX_DCM_CLK[0] bit 5 INT: mux IMUX_DCM_CLK[0] bit 6 INT: mux OMUX[9] bit 5 INT: mux OMUX[8] bit 8 INT: mux IMUX_G2_DATA[1] bit 9 INT: mux IMUX_G2_DATA[1] bit 10 INT: mux IMUX_G2_DATA[1] bit 6 INT: mux IMUX_G2_DATA[1] bit 5 INT: mux IMUX_G2_DATA[1] bit 1 INT: mux IMUX_G2_DATA[1] bit 3 INT: mux DBL_S0[5] bit 0 INT: mux DBL_N0[5] bit 0 INT: mux DBL_N0[5] bit 7 INT: mux DBL_N0[5] bit 5 INT: mux HEX_S0[5] bit 0 INT: mux HEX_S0[5] bit 2 INT: mux HEX_S0[5] bit 4 INT: mux HEX_N0[5] bit 4
B41 - - - - INT: mux IMUX_DCM_CLK[1] bit 6 INT: mux IMUX_DCM_CLK[1] bit 4 INT: mux OMUX[8] bit 9 INT: mux OMUX[8] bit 7 INT: mux IMUX_G2_DATA[1] bit 8 INT: mux IMUX_G2_DATA[1] bit 11 INT: mux IMUX_G2_DATA[0] bit 7 INT: mux IMUX_G2_DATA[0] bit 4 INT: mux IMUX_G2_DATA[0] bit 0 INT: mux IMUX_G2_DATA[0] bit 2 INT: mux DBL_N0[5] bit 3 INT: mux DBL_S0[5] bit 1 INT: mux DBL_N0[5] bit 6 INT: mux DBL_N0[5] bit 4 INT: mux HEX_N0[5] bit 2 INT: mux HEX_N0[5] bit 0 INT: mux HEX_S0[5] bit 5 INT: mux LH[12] bit 2
B40 - - - - INT: mux IMUX_DCM_CLK[0] bit 4 INT: mux IMUX_DCM_CLK[0] bit 7 INT: mux OMUX[8] bit 5 INT: mux OMUX[8] bit 6 INT: mux IMUX_G2_DATA[0] bit 8 INT: mux IMUX_G2_DATA[0] bit 11 INT: mux IMUX_G2_DATA[1] bit 7 INT: mux IMUX_G2_DATA[1] bit 4 INT: mux IMUX_G2_DATA[1] bit 0 INT: mux IMUX_G2_DATA[1] bit 2 INT: mux DBL_N0[5] bit 2 INT: mux DBL_S0[5] bit 2 INT: mux DBL_S0[5] bit 5 INT: mux DBL_S0[5] bit 6 INT: mux HEX_S0[5] bit 3 INT: mux HEX_S0[5] bit 1 INT: mux HEX_S0[5] bit 6 INT: mux HEX_N0[5] bit 6
B39 - - - - INT: mux IMUX_DCM_CLK[0] bit 8 INT: mux IMUX_DCM_CLK[0] bit 10 INT: mux OMUX[6] bit 4 INT: mux OMUX[7] bit 6 INT: mux IMUX_G1_DATA[0] bit 9 INT: mux IMUX_G1_DATA[0] bit 11 INT: mux IMUX_G1_DATA[1] bit 7 INT: mux IMUX_G1_DATA[1] bit 5 INT: mux IMUX_G1_DATA[1] bit 1 INT: mux IMUX_G1_DATA[1] bit 2 INT: mux DBL_E0[4] bit 2 INT: mux DBL_W0[4] bit 3 INT: mux DBL_E0[4] bit 5 INT: mux DBL_E0[4] bit 7 INT: mux HEX_E0[4] bit 1 INT: mux HEX_E0[4] bit 3 INT: mux HEX_E0[4] bit 5 INT: mux LH[18] bit 2
B38 - - - - INT: invert IMUX_DCM_CLK_OPTINV[0] ← IMUX_DCM_CLK[0] INT: mux IMUX_DCM_CLK[0] bit 11 INT: mux OMUX[7] bit 9 INT: mux OMUX[7] bit 7 INT: mux IMUX_G1_DATA[1] bit 9 INT: mux IMUX_G1_DATA[1] bit 11 INT: mux IMUX_G1_DATA[0] bit 7 INT: mux IMUX_G1_DATA[0] bit 5 INT: mux IMUX_G1_DATA[0] bit 1 INT: mux IMUX_G1_DATA[0] bit 2 INT: mux DBL_E0[4] bit 0 INT: mux DBL_W0[4] bit 0 INT: mux DBL_W0[4] bit 7 INT: mux DBL_W0[4] bit 5 INT: mux HEX_W0[4] bit 1 INT: mux HEX_W0[4] bit 3 INT: mux HEX_W0[4] bit 5 INT: mux HEX_E0[4] bit 4
B37 - - - - INT: mux IMUX_DCM_CLK[1] bit 7 INT: mux IMUX_DCM_CLK[0] bit 9 INT: mux OMUX[7] bit 4 INT: mux OMUX[7] bit 8 INT: mux IMUX_G1_DATA[1] bit 8 INT: mux IMUX_G1_DATA[1] bit 10 INT: mux IMUX_G1_DATA[1] bit 6 INT: mux IMUX_G1_DATA[1] bit 4 INT: mux IMUX_G1_DATA[1] bit 0 INT: mux IMUX_G1_DATA[1] bit 3 INT: mux DBL_W0[4] bit 2 INT: mux DBL_E0[4] bit 3 INT: mux DBL_W0[4] bit 6 INT: mux DBL_W0[4] bit 4 INT: mux HEX_E0[4] bit 2 INT: mux HEX_E0[4] bit 0 INT: mux HEX_W0[4] bit 4 INT: mux LH[18] bit 1
B36 - - - - - - INT: mux OMUX[6] bit 5 INT: mux OMUX[7] bit 5 INT: mux IMUX_G1_DATA[0] bit 8 INT: mux IMUX_G1_DATA[0] bit 10 INT: mux IMUX_G1_DATA[0] bit 6 INT: mux IMUX_G1_DATA[0] bit 4 INT: mux IMUX_G1_DATA[0] bit 0 INT: mux IMUX_G1_DATA[0] bit 3 INT: mux DBL_W0[4] bit 1 INT: mux DBL_E0[4] bit 1 INT: mux DBL_E0[4] bit 4 INT: mux DBL_E0[4] bit 6 INT: mux HEX_W0[4] bit 2 INT: mux HEX_W0[4] bit 0 INT: mux HEX_W0[4] bit 6 INT: mux HEX_E0[4] bit 6
B35 - - - - - - INT: mux OMUX[7] bit 0 INT: mux OMUX[6] bit 0 INT: mux IMUX_G1_DATA[2] bit 8 INT: mux IMUX_G1_DATA[2] bit 10 INT: mux IMUX_G1_DATA[2] bit 6 INT: mux IMUX_G1_DATA[2] bit 4 INT: mux IMUX_G1_DATA[2] bit 0 INT: mux IMUX_G1_DATA[2] bit 3 INT: mux DBL_S0[4] bit 3 INT: mux DBL_N0[4] bit 1 INT: mux DBL_S0[4] bit 4 INT: mux DBL_S0[4] bit 7 INT: mux HEX_S0[4] bit 0 INT: mux HEX_S0[4] bit 3 INT: mux HEX_S0[4] bit 4 INT: mux LH[18] bit 0
B34 - - - - - - INT: mux OMUX[7] bit 1 INT: mux OMUX[6] bit 1 INT: mux IMUX_G1_DATA[3] bit 8 INT: mux IMUX_G1_DATA[3] bit 10 INT: mux IMUX_G1_DATA[3] bit 6 INT: mux IMUX_G1_DATA[3] bit 4 INT: mux IMUX_G1_DATA[3] bit 0 INT: mux IMUX_G1_DATA[3] bit 3 INT: mux DBL_S0[4] bit 0 INT: mux DBL_N0[4] bit 0 INT: mux DBL_N0[4] bit 7 INT: mux DBL_N0[4] bit 4 INT: mux HEX_N0[4] bit 0 INT: mux HEX_N0[4] bit 2 INT: mux HEX_N0[4] bit 4 INT: mux HEX_S0[4] bit 5
B33 - - - - - - INT: mux OMUX[6] bit 2 INT: mux OMUX[7] bit 2 INT: mux IMUX_G1_DATA[3] bit 9 INT: mux IMUX_G1_DATA[3] bit 11 INT: mux IMUX_G1_DATA[2] bit 7 INT: mux IMUX_G1_DATA[2] bit 5 INT: mux IMUX_G1_DATA[2] bit 1 INT: mux IMUX_G1_DATA[2] bit 2 INT: mux DBL_N0[4] bit 3 INT: mux DBL_S0[4] bit 1 INT: mux DBL_N0[4] bit 6 INT: mux DBL_N0[4] bit 5 INT: mux HEX_S0[4] bit 2 INT: mux HEX_S0[4] bit 1 INT: mux HEX_N0[4] bit 5 INT: mux LH[6] bit 1
B32 - - - - - - INT: mux OMUX[7] bit 3 INT: mux OMUX[6] bit 8 INT: mux IMUX_G1_DATA[2] bit 9 INT: mux IMUX_G1_DATA[2] bit 11 INT: mux IMUX_G1_DATA[3] bit 7 INT: mux IMUX_G1_DATA[3] bit 5 INT: mux IMUX_G1_DATA[3] bit 1 INT: mux IMUX_G1_DATA[3] bit 2 INT: mux DBL_N0[4] bit 2 INT: mux DBL_S0[4] bit 2 INT: mux DBL_S0[4] bit 5 INT: mux DBL_S0[4] bit 6 INT: mux HEX_N0[4] bit 3 INT: mux HEX_N0[4] bit 1 INT: mux HEX_N0[4] bit 6 INT: mux HEX_S0[4] bit 6
B31 - - - - - - INT: mux OMUX[6] bit 9 INT: mux OMUX[6] bit 7 INT: mux IMUX_G1_DATA[4] bit 9 INT: mux IMUX_G1_DATA[4] bit 11 INT: mux IMUX_G1_DATA[5] bit 7 INT: mux IMUX_G1_DATA[5] bit 5 INT: mux IMUX_G1_DATA[5] bit 1 INT: mux IMUX_G1_DATA[5] bit 2 INT: mux DBL_E0[3] bit 2 INT: mux DBL_W0[3] bit 3 INT: mux DBL_E0[3] bit 4 INT: mux DBL_E0[3] bit 7 INT: mux HEX_W0[3] bit 1 INT: mux HEX_W0[3] bit 3 INT: mux HEX_W0[3] bit 5 INT: mux LH[6] bit 2
B30 - - - - - - INT: mux OMUX[6] bit 3 INT: mux OMUX[6] bit 6 INT: mux IMUX_G1_DATA[5] bit 9 INT: mux IMUX_G1_DATA[5] bit 11 INT: mux IMUX_G1_DATA[4] bit 7 INT: mux IMUX_G1_DATA[4] bit 5 INT: mux IMUX_G1_DATA[4] bit 1 INT: mux IMUX_G1_DATA[4] bit 2 INT: mux DBL_E0[3] bit 0 INT: mux DBL_W0[3] bit 0 INT: mux DBL_W0[3] bit 7 INT: mux DBL_W0[3] bit 5 INT: mux HEX_E0[3] bit 0 INT: mux HEX_E0[3] bit 3 INT: mux HEX_E0[3] bit 4 INT: mux HEX_W0[3] bit 4
B29 - - - - - - INT: mux OMUX[4] bit 0 INT: mux OMUX[5] bit 6 INT: mux IMUX_G1_DATA[5] bit 8 INT: mux IMUX_G1_DATA[5] bit 10 INT: mux IMUX_G1_DATA[5] bit 6 INT: mux IMUX_G1_DATA[5] bit 4 INT: mux IMUX_G1_DATA[5] bit 0 INT: mux IMUX_G1_DATA[5] bit 3 INT: mux DBL_W0[3] bit 2 INT: mux DBL_E0[3] bit 3 INT: mux DBL_W0[3] bit 6 INT: mux DBL_W0[3] bit 4 INT: mux HEX_W0[3] bit 2 INT: mux HEX_W0[3] bit 0 INT: mux HEX_E0[3] bit 5 INT: mux LH[6] bit 0
B28 - - - - INT: mux IMUX_TI[1] bit 5 INT: mux IMUX_TI[1] bit 9 INT: mux OMUX[5] bit 9 INT: mux OMUX[5] bit 7 INT: mux IMUX_G1_DATA[4] bit 8 INT: mux IMUX_G1_DATA[4] bit 10 INT: mux IMUX_G1_DATA[4] bit 6 INT: mux IMUX_G1_DATA[4] bit 4 INT: mux IMUX_G1_DATA[4] bit 0 INT: mux IMUX_G1_DATA[4] bit 3 INT: mux DBL_W0[3] bit 1 INT: mux DBL_E0[3] bit 1 INT: mux DBL_E0[3] bit 5 INT: mux DBL_E0[3] bit 6 INT: mux HEX_E0[3] bit 2 INT: mux HEX_E0[3] bit 1 INT: mux HEX_E0[3] bit 6 INT: mux HEX_W0[3] bit 6
B27 - - - - INT: !invert IMUX_TI_OPTINV[1] ← IMUX_TI[1] INT: mux IMUX_TI[0] bit 5 INT: mux OMUX[5] bit 0 INT: mux OMUX[5] bit 8 INT: mux IMUX_G1_DATA[6] bit 8 INT: mux IMUX_G1_DATA[6] bit 10 INT: mux IMUX_G1_DATA[6] bit 6 INT: mux IMUX_G1_DATA[6] bit 4 INT: mux IMUX_G1_DATA[6] bit 0 INT: mux IMUX_G1_DATA[6] bit 3 INT: mux DBL_S0[3] bit 3 INT: mux DBL_N0[3] bit 1 INT: mux DBL_S0[3] bit 5 INT: mux DBL_S0[3] bit 7 INT: mux HEX_N0[3] bit 0 INT: mux HEX_N0[3] bit 3 INT: mux HEX_N0[3] bit 4 INT: mux LV[12] bit 4
B26 - - - - INT: mux IMUX_TI[1] bit 7 INT: mux IMUX_TI[1] bit 6 INT: mux OMUX[4] bit 1 INT: mux OMUX[5] bit 1 INT: mux IMUX_G1_DATA[7] bit 8 INT: mux IMUX_G1_DATA[7] bit 10 INT: mux IMUX_G1_DATA[7] bit 6 INT: mux IMUX_G1_DATA[7] bit 4 INT: mux IMUX_G1_DATA[7] bit 0 INT: mux IMUX_G1_DATA[7] bit 3 INT: mux DBL_S0[3] bit 0 INT: mux DBL_N0[3] bit 0 INT: mux DBL_N0[3] bit 7 INT: mux DBL_N0[3] bit 4 INT: mux HEX_S0[3] bit 1 INT: mux HEX_S0[3] bit 2 INT: mux HEX_S0[3] bit 5 INT: mux HEX_N0[3] bit 5
B25 - - - - INT: mux IMUX_TI[0] bit 4 INT: mux IMUX_TI[1] bit 8 INT: mux OMUX[5] bit 2 INT: mux OMUX[4] bit 2 INT: mux IMUX_G1_DATA[7] bit 9 INT: mux IMUX_G1_DATA[7] bit 11 INT: mux IMUX_G1_DATA[6] bit 7 INT: mux IMUX_G1_DATA[6] bit 5 INT: mux IMUX_G1_DATA[6] bit 1 INT: mux IMUX_G1_DATA[6] bit 2 INT: mux DBL_N0[3] bit 3 INT: mux DBL_S0[3] bit 1 INT: mux DBL_N0[3] bit 6 INT: mux DBL_N0[3] bit 5 INT: mux HEX_N0[3] bit 2 INT: mux HEX_N0[3] bit 1 INT: mux HEX_S0[3] bit 4 INT: mux LV[0] bit 3
B24 - - - - INT: mux IMUX_TI[1] bit 4 INT: mux IMUX_TI[1] bit 2 INT: mux OMUX[5] bit 3 INT: mux OMUX[4] bit 3 INT: mux IMUX_G1_DATA[6] bit 9 INT: mux IMUX_G1_DATA[6] bit 11 INT: mux IMUX_G1_DATA[7] bit 7 INT: mux IMUX_G1_DATA[7] bit 5 INT: mux IMUX_G1_DATA[7] bit 1 INT: mux IMUX_G1_DATA[7] bit 2 INT: mux DBL_N0[3] bit 2 INT: mux DBL_S0[3] bit 2 INT: mux DBL_S0[3] bit 4 INT: mux DBL_S0[3] bit 6 INT: mux HEX_S0[3] bit 3 INT: mux HEX_S0[3] bit 0 INT: mux HEX_S0[3] bit 6 INT: mux HEX_N0[3] bit 6
B23 - - - - INT: mux IMUX_TI[0] bit 3 INT: mux IMUX_TI[0] bit 2 INT: mux OMUX[4] bit 4 INT: mux OMUX[5] bit 4 INT: mux IMUX_G1_FAN[0] bit 9 INT: mux IMUX_G1_FAN[0] bit 11 INT: mux IMUX_G1_FAN[1] bit 7 INT: mux IMUX_G1_FAN[1] bit 5 INT: mux IMUX_G1_FAN[1] bit 1 INT: mux IMUX_G1_FAN[1] bit 2 INT: mux DBL_E0[2] bit 4 INT: mux DBL_W0[2] bit 7 INT: mux DBL_E0[2] bit 1 INT: mux DBL_E0[2] bit 3 INT: mux HEX_E0[2] bit 1 INT: mux HEX_E0[2] bit 3 INT: mux HEX_E0[2] bit 5 INT: mux LV[12] bit 3
B22 - - - - INT: mux IMUX_TI[1] bit 1 INT: mux IMUX_TI[1] bit 3 INT: mux OMUX[5] bit 5 INT: mux OMUX[4] bit 8 INT: mux IMUX_G1_FAN[1] bit 9 INT: mux IMUX_G1_FAN[1] bit 11 INT: mux IMUX_G1_FAN[0] bit 7 INT: mux IMUX_G1_FAN[0] bit 5 INT: mux IMUX_G1_FAN[0] bit 1 INT: mux IMUX_G1_FAN[0] bit 2 INT: mux DBL_E0[2] bit 5 INT: mux DBL_W0[2] bit 5 INT: mux DBL_W0[2] bit 3 INT: mux DBL_W0[2] bit 1 INT: mux HEX_W0[2] bit 4 INT: mux HEX_W0[2] bit 6 INT: mux HEX_W0[2] bit 2 INT: mux HEX_E0[2] bit 6
B21 - - - - INT: mux IMUX_TI[0] bit 1 INT: mux IMUX_TI[0] bit 0 INT: mux OMUX[4] bit 9 INT: mux OMUX[4] bit 7 INT: mux IMUX_G1_FAN[1] bit 8 INT: mux IMUX_G1_FAN[1] bit 10 INT: mux IMUX_G1_FAN[1] bit 6 INT: mux IMUX_G1_FAN[1] bit 4 INT: mux IMUX_G1_FAN[1] bit 0 INT: mux IMUX_G1_FAN[1] bit 3 INT: mux DBL_W0[2] bit 4 INT: mux DBL_E0[2] bit 7 INT: mux DBL_W0[2] bit 2 INT: mux DBL_W0[2] bit 0 INT: mux HEX_E0[2] bit 2 INT: mux HEX_E0[2] bit 0 INT: mux HEX_W0[2] bit 1 INT: mux LV[0] bit 2
B20 - - - - INT: mux IMUX_TI[0] bit 7 INT: mux IMUX_TI[0] bit 6 INT: mux OMUX[4] bit 5 INT: mux OMUX[4] bit 6 INT: mux IMUX_G1_FAN[0] bit 8 INT: mux IMUX_G1_FAN[0] bit 10 INT: mux IMUX_G1_FAN[0] bit 6 INT: mux IMUX_G1_FAN[0] bit 4 INT: mux IMUX_G1_FAN[0] bit 0 INT: mux IMUX_G1_FAN[0] bit 3 INT: mux DBL_W0[2] bit 6 INT: mux DBL_E0[2] bit 6 INT: mux DBL_E0[2] bit 0 INT: mux DBL_E0[2] bit 2 INT: mux HEX_W0[2] bit 5 INT: mux HEX_W0[2] bit 3 INT: mux HEX_W0[2] bit 0 INT: mux HEX_E0[2] bit 4
B19 - - - - INT: !invert IMUX_TI_OPTINV[0] ← IMUX_TI[0] INT: mux IMUX_TI[0] bit 8 INT: mux OMUX[2] bit 0 INT: mux OMUX[3] bit 6 INT: mux IMUX_G0_FAN[0] bit 9 INT: mux IMUX_G0_FAN[0] bit 10 INT: mux IMUX_G0_FAN[0] bit 6 INT: mux IMUX_G0_FAN[0] bit 5 INT: mux IMUX_G0_FAN[0] bit 2 INT: mux IMUX_G0_FAN[0] bit 1 INT: mux DBL_S0[2] bit 4 INT: mux DBL_N0[2] bit 6 INT: mux DBL_S0[2] bit 0 INT: mux DBL_S0[2] bit 3 INT: mux HEX_S0[2] bit 0 INT: mux HEX_S0[2] bit 3 INT: mux HEX_S0[2] bit 5 INT: mux LV[0] bit 4
B18 - - - - INT: mux IMUX_TI[1] bit 0 INT: mux IMUX_TI[0] bit 9 INT: mux OMUX[3] bit 9 INT: mux OMUX[3] bit 7 INT: mux IMUX_G0_FAN[1] bit 9 INT: mux IMUX_G0_FAN[1] bit 10 INT: mux IMUX_G0_FAN[1] bit 6 INT: mux IMUX_G0_FAN[1] bit 5 INT: mux IMUX_G0_FAN[1] bit 2 INT: mux IMUX_G0_FAN[1] bit 1 INT: mux DBL_S0[2] bit 5 INT: mux DBL_N0[2] bit 5 INT: mux DBL_N0[2] bit 3 INT: mux DBL_N0[2] bit 0 INT: mux HEX_N0[2] bit 1 INT: mux HEX_N0[2] bit 2 INT: mux HEX_N0[2] bit 4 INT: mux HEX_S0[2] bit 4
B17 - - - - INT: mux IMUX_SR[3] bit 5 INT: mux IMUX_SR[1] bit 1 INT: mux OMUX[3] bit 0 INT: mux OMUX[3] bit 8 INT: mux IMUX_G0_FAN[1] bit 8 INT: mux IMUX_G0_FAN[1] bit 11 INT: mux IMUX_G0_FAN[0] bit 7 INT: mux IMUX_G0_FAN[0] bit 4 INT: mux IMUX_G0_FAN[0] bit 0 INT: mux IMUX_G0_FAN[0] bit 3 INT: mux DBL_N0[2] bit 4 INT: mux DBL_S0[2] bit 6 INT: mux DBL_N0[2] bit 2 INT: mux DBL_N0[2] bit 1 INT: mux HEX_S0[2] bit 2 INT: mux HEX_S0[2] bit 1 INT: mux HEX_N0[2] bit 5 INT: mux LV[12] bit 2
B16 - - - - INT: !invert IMUX_SR_OPTINV[1] ← IMUX_SR[1] INT: mux IMUX_SR[1] bit 3 INT: mux OMUX[2] bit 1 INT: mux OMUX[3] bit 1 INT: mux IMUX_G0_FAN[0] bit 8 INT: mux IMUX_G0_FAN[0] bit 11 INT: mux IMUX_G0_FAN[1] bit 7 INT: mux IMUX_G0_FAN[1] bit 4 INT: mux IMUX_G0_FAN[1] bit 0 INT: mux IMUX_G0_FAN[1] bit 3 INT: mux DBL_N0[2] bit 7 INT: mux DBL_S0[2] bit 7 INT: mux DBL_S0[2] bit 1 INT: mux DBL_S0[2] bit 2 INT: mux HEX_N0[2] bit 3 INT: mux HEX_N0[2] bit 0 INT: mux HEX_N0[2] bit 6 INT: mux HEX_S0[2] bit 6
B15 - - - - INT: mux IMUX_SR[1] bit 0 INT: mux IMUX_SR[1] bit 2 INT: mux OMUX[3] bit 2 INT: mux OMUX[2] bit 2 INT: mux IMUX_G0_DATA[6] bit 8 INT: mux IMUX_G0_DATA[6] bit 11 INT: mux IMUX_G0_DATA[7] bit 7 INT: mux IMUX_G0_DATA[7] bit 4 INT: mux IMUX_G0_DATA[7] bit 0 INT: mux IMUX_G0_DATA[7] bit 3 INT: mux DBL_E0[1] bit 2 INT: mux DBL_W0[1] bit 3 INT: mux DBL_E0[1] bit 4 INT: mux DBL_E0[1] bit 7 INT: mux HEX_W0[1] bit 1 INT: mux HEX_W0[1] bit 2 INT: mux HEX_W0[1] bit 5 INT: mux LV[12] bit 0
B14 - - - - INT: mux IMUX_SR[1] bit 4 INT: mux IMUX_SR[1] bit 5 INT: mux OMUX[3] bit 3 INT: mux OMUX[2] bit 3 INT: mux IMUX_G0_DATA[7] bit 8 INT: mux IMUX_G0_DATA[7] bit 11 INT: mux IMUX_G0_DATA[6] bit 7 INT: mux IMUX_G0_DATA[6] bit 4 INT: mux IMUX_G0_DATA[6] bit 0 INT: mux IMUX_G0_DATA[6] bit 3 INT: mux DBL_E0[1] bit 0 INT: mux DBL_W0[1] bit 0 INT: mux DBL_W0[1] bit 6 INT: mux DBL_W0[1] bit 5 INT: mux HEX_E0[1] bit 0 INT: mux HEX_E0[1] bit 3 INT: mux HEX_E0[1] bit 4 INT: mux HEX_W0[1] bit 4
B13 - - - - INT: mux IMUX_SR[3] bit 4 INT: mux IMUX_SR[3] bit 7 INT: mux OMUX[2] bit 4 INT: mux OMUX[3] bit 4 INT: mux IMUX_G0_DATA[7] bit 9 INT: mux IMUX_G0_DATA[7] bit 10 INT: mux IMUX_G0_DATA[7] bit 6 INT: mux IMUX_G0_DATA[7] bit 5 INT: mux IMUX_G0_DATA[7] bit 2 INT: mux IMUX_G0_DATA[7] bit 1 INT: mux DBL_W0[1] bit 2 INT: mux DBL_E0[1] bit 3 INT: mux DBL_W0[1] bit 7 INT: mux DBL_W0[1] bit 4 INT: mux HEX_W0[1] bit 3 INT: mux HEX_W0[1] bit 0 INT: mux HEX_E0[1] bit 5 INT: mux LV[12] bit 6
B12 - - - - INT: mux IMUX_SR[1] bit 7 INT: mux IMUX_SR[1] bit 6 INT: mux OMUX[3] bit 5 INT: mux OMUX[2] bit 8 INT: mux IMUX_G0_DATA[6] bit 9 INT: mux IMUX_G0_DATA[6] bit 10 INT: mux IMUX_G0_DATA[6] bit 6 INT: mux IMUX_G0_DATA[6] bit 5 INT: mux IMUX_G0_DATA[6] bit 2 INT: mux IMUX_G0_DATA[6] bit 1 INT: mux DBL_W0[1] bit 1 INT: mux DBL_E0[1] bit 1 INT: mux DBL_E0[1] bit 5 INT: mux DBL_E0[1] bit 6 INT: mux HEX_E0[1] bit 2 INT: mux HEX_E0[1] bit 1 INT: mux HEX_E0[1] bit 6 INT: mux HEX_W0[1] bit 6
B11 - - - - INT: mux IMUX_SR[3] bit 0 INT: mux IMUX_SR[3] bit 1 INT: mux OMUX[2] bit 9 INT: mux OMUX[2] bit 7 INT: mux IMUX_G0_DATA[4] bit 9 INT: mux IMUX_G0_DATA[4] bit 10 INT: mux IMUX_G0_DATA[4] bit 6 INT: mux IMUX_G0_DATA[4] bit 5 INT: mux IMUX_G0_DATA[4] bit 2 INT: mux IMUX_G0_DATA[4] bit 1 INT: mux DBL_S0[1] bit 3 INT: mux DBL_N0[1] bit 1 INT: mux DBL_S0[1] bit 4 INT: mux DBL_S0[1] bit 7 INT: mux HEX_N0[1] bit 0 INT: mux HEX_N0[1] bit 3 INT: mux HEX_N0[1] bit 4 INT: mux LV[0] bit 1
B10 - - - - INT: !invert IMUX_SR_OPTINV[3] ← IMUX_SR[3] INT: mux IMUX_SR[3] bit 3 INT: mux OMUX[2] bit 5 INT: mux OMUX[2] bit 6 INT: mux IMUX_G0_DATA[5] bit 9 INT: mux IMUX_G0_DATA[5] bit 10 INT: mux IMUX_G0_DATA[5] bit 6 INT: mux IMUX_G0_DATA[5] bit 5 INT: mux IMUX_G0_DATA[5] bit 2 INT: mux IMUX_G0_DATA[5] bit 1 INT: mux DBL_S0[1] bit 0 INT: mux DBL_N0[1] bit 0 INT: mux DBL_N0[1] bit 7 INT: mux DBL_N0[1] bit 4 INT: mux HEX_S0[1] bit 0 INT: mux HEX_S0[1] bit 2 INT: mux HEX_S0[1] bit 4 INT: mux HEX_N0[1] bit 5
B9 - - - - INT: mux IMUX_SR[3] bit 6 INT: mux IMUX_SR[3] bit 2 INT: mux OMUX[0] bit 0 INT: mux OMUX[1] bit 6 INT: mux IMUX_G0_DATA[5] bit 8 INT: mux IMUX_G0_DATA[5] bit 11 INT: mux IMUX_G0_DATA[4] bit 7 INT: mux IMUX_G0_DATA[4] bit 4 INT: mux IMUX_G0_DATA[4] bit 0 INT: mux IMUX_G0_DATA[4] bit 3 INT: mux DBL_N0[1] bit 3 INT: mux DBL_S0[1] bit 1 INT: mux DBL_N0[1] bit 6 INT: mux DBL_N0[1] bit 5 INT: mux HEX_N0[1] bit 2 INT: mux HEX_N0[1] bit 1 INT: mux HEX_S0[1] bit 5 INT: mux LV[0] bit 5
B8 - - - - INT: mux IMUX_SR[2] bit 5 INT: mux IMUX_SR[2] bit 2 INT: mux OMUX[1] bit 9 INT: mux OMUX[1] bit 7 INT: mux IMUX_G0_DATA[4] bit 8 INT: mux IMUX_G0_DATA[4] bit 11 INT: mux IMUX_G0_DATA[5] bit 7 INT: mux IMUX_G0_DATA[5] bit 4 INT: mux IMUX_G0_DATA[5] bit 0 INT: mux IMUX_G0_DATA[5] bit 3 INT: mux DBL_N0[1] bit 2 INT: mux DBL_S0[1] bit 2 INT: mux DBL_S0[1] bit 5 INT: mux DBL_S0[1] bit 6 INT: mux HEX_S0[1] bit 3 INT: mux HEX_S0[1] bit 1 INT: mux HEX_S0[1] bit 6 INT: mux HEX_N0[1] bit 6
B7 - - - - INT: !invert IMUX_SR_OPTINV[2] ← IMUX_SR[2] INT: mux IMUX_SR[2] bit 3 INT: mux OMUX[1] bit 0 INT: mux OMUX[1] bit 8 INT: mux IMUX_G0_DATA[2] bit 8 INT: mux IMUX_G0_DATA[2] bit 11 INT: mux IMUX_G0_DATA[3] bit 7 INT: mux IMUX_G0_DATA[3] bit 4 INT: mux IMUX_G0_DATA[3] bit 0 INT: mux IMUX_G0_DATA[3] bit 3 INT: mux DBL_E0[0] bit 2 INT: mux DBL_W0[0] bit 3 INT: mux DBL_E0[0] bit 4 INT: mux DBL_E0[0] bit 7 INT: mux HEX_E0[0] bit 0 INT: mux HEX_E0[0] bit 3 INT: mux HEX_E0[0] bit 4 INT: mux LV[0] bit 6
B6 - - - - INT: mux IMUX_SR[2] bit 1 INT: mux IMUX_SR[2] bit 0 INT: mux OMUX[0] bit 1 INT: mux OMUX[1] bit 1 INT: mux IMUX_G0_DATA[3] bit 8 INT: mux IMUX_G0_DATA[3] bit 11 INT: mux IMUX_G0_DATA[2] bit 7 INT: mux IMUX_G0_DATA[2] bit 4 INT: mux IMUX_G0_DATA[2] bit 0 INT: mux IMUX_G0_DATA[2] bit 3 INT: mux DBL_E0[0] bit 0 INT: mux DBL_W0[0] bit 0 INT: mux DBL_W0[0] bit 6 INT: mux DBL_W0[0] bit 5 INT: mux HEX_W0[0] bit 1 INT: mux HEX_W0[0] bit 2 INT: mux HEX_W0[0] bit 5 INT: mux HEX_E0[0] bit 5
B5 - - - - INT: mux IMUX_SR[0] bit 4 INT: mux IMUX_SR[0] bit 5 INT: mux OMUX[1] bit 2 INT: mux OMUX[0] bit 2 INT: mux IMUX_G0_DATA[3] bit 9 INT: mux IMUX_G0_DATA[3] bit 10 INT: mux IMUX_G0_DATA[3] bit 6 INT: mux IMUX_G0_DATA[3] bit 5 INT: mux IMUX_G0_DATA[3] bit 2 INT: mux IMUX_G0_DATA[3] bit 1 INT: mux DBL_W0[0] bit 2 INT: mux DBL_E0[0] bit 3 INT: mux DBL_W0[0] bit 7 INT: mux DBL_W0[0] bit 4 INT: mux HEX_E0[0] bit 2 INT: mux HEX_E0[0] bit 1 INT: mux HEX_W0[0] bit 4 INT: mux LV[0] bit 0
B4 - - - - INT: mux IMUX_SR[2] bit 6 INT: mux IMUX_SR[2] bit 4 INT: mux OMUX[1] bit 3 INT: mux OMUX[0] bit 3 INT: mux IMUX_G0_DATA[2] bit 9 INT: mux IMUX_G0_DATA[2] bit 10 INT: mux IMUX_G0_DATA[2] bit 6 INT: mux IMUX_G0_DATA[2] bit 5 INT: mux IMUX_G0_DATA[2] bit 2 INT: mux IMUX_G0_DATA[2] bit 1 INT: mux DBL_W0[0] bit 1 INT: mux DBL_E0[0] bit 1 INT: mux DBL_E0[0] bit 5 INT: mux DBL_E0[0] bit 6 INT: mux HEX_W0[0] bit 3 INT: mux HEX_W0[0] bit 0 INT: mux HEX_W0[0] bit 6 INT: mux HEX_E0[0] bit 6
B3 - - - - INT: mux IMUX_SR[0] bit 6 INT: mux IMUX_SR[0] bit 7 INT: mux OMUX[0] bit 4 INT: mux OMUX[1] bit 4 INT: mux IMUX_G0_DATA[0] bit 9 INT: mux IMUX_G0_DATA[0] bit 10 INT: mux IMUX_G0_DATA[0] bit 6 INT: mux IMUX_G0_DATA[0] bit 5 INT: mux IMUX_G0_DATA[0] bit 2 INT: mux IMUX_G0_DATA[0] bit 1 INT: mux DBL_S0[0] bit 4 INT: mux DBL_N0[0] bit 6 INT: mux DBL_S0[0] bit 1 INT: mux DBL_S0[0] bit 3 INT: mux HEX_S0[0] bit 1 INT: mux HEX_S0[0] bit 3 INT: mux HEX_S0[0] bit 6 INT: mux LV[12] bit 1
B2 - - - - INT: mux IMUX_SR[0] bit 1 INT: mux IMUX_SR[0] bit 2 INT: mux OMUX[1] bit 5 INT: mux OMUX[0] bit 8 INT: mux IMUX_G0_DATA[1] bit 9 INT: mux IMUX_G0_DATA[1] bit 10 INT: mux IMUX_G0_DATA[1] bit 6 INT: mux IMUX_G0_DATA[1] bit 5 INT: mux IMUX_G0_DATA[1] bit 2 INT: mux IMUX_G0_DATA[1] bit 1 INT: mux DBL_S0[0] bit 5 INT: mux DBL_N0[0] bit 5 INT: mux DBL_N0[0] bit 3 INT: mux DBL_N0[0] bit 1 INT: mux HEX_N0[0] bit 1 INT: mux HEX_N0[0] bit 2 INT: mux HEX_N0[0] bit 5 INT: mux HEX_S0[0] bit 5
B1 - - - - INT: !invert IMUX_SR_OPTINV[0] ← IMUX_SR[0] INT: mux IMUX_SR[0] bit 3 INT: mux OMUX[0] bit 9 INT: mux OMUX[0] bit 7 INT: mux IMUX_G0_DATA[1] bit 8 INT: mux IMUX_G0_DATA[1] bit 11 INT: mux IMUX_G0_DATA[0] bit 7 INT: mux IMUX_G0_DATA[0] bit 4 INT: mux IMUX_G0_DATA[0] bit 0 INT: mux IMUX_G0_DATA[0] bit 3 INT: mux DBL_N0[0] bit 4 INT: mux DBL_S0[0] bit 6 INT: mux DBL_N0[0] bit 2 INT: mux DBL_N0[0] bit 0 INT: mux HEX_S0[0] bit 2 INT: mux HEX_S0[0] bit 0 INT: mux HEX_N0[0] bit 6 INT: mux LV[12] bit 5
B0 - - - - INT: mux IMUX_SR[2] bit 7 INT: mux IMUX_SR[0] bit 0 INT: mux OMUX[0] bit 5 INT: mux OMUX[0] bit 6 INT: mux IMUX_G0_DATA[0] bit 8 INT: mux IMUX_G0_DATA[0] bit 11 INT: mux IMUX_G0_DATA[1] bit 7 INT: mux IMUX_G0_DATA[1] bit 4 INT: mux IMUX_G0_DATA[1] bit 0 INT: mux IMUX_G0_DATA[1] bit 3 INT: mux DBL_N0[0] bit 7 INT: mux DBL_S0[0] bit 7 INT: mux DBL_S0[0] bit 0 INT: mux DBL_S0[0] bit 2 INT: mux HEX_N0[0] bit 3 INT: mux HEX_N0[0] bit 0 INT: mux HEX_N0[0] bit 4 INT: mux HEX_S0[0] bit 4

INT_CNR

Used with the corner tiles.

Tile INT_CNR

Cells: 1

Switchbox INT

virtex2 INT_CNR switchbox INT programmable inverters
DestinationSourceBit
IMUX_CLK_OPTINV[0]IMUX_CLK[0]MAIN[4][41]
IMUX_CLK_OPTINV[1]IMUX_CLK[1]MAIN[4][49]
IMUX_CLK_OPTINV[2]IMUX_CLK[2]MAIN[4][52]
IMUX_CLK_OPTINV[3]IMUX_CLK[3]MAIN[4][60]
IMUX_SR_OPTINV[0]IMUX_SR[0]!MAIN[4][1]
IMUX_SR_OPTINV[1]IMUX_SR[1]!MAIN[4][16]
IMUX_SR_OPTINV[2]IMUX_SR[2]!MAIN[4][7]
IMUX_SR_OPTINV[3]IMUX_SR[3]!MAIN[4][10]
IMUX_CE_OPTINV[0]IMUX_CE[0]!MAIN[4][63]
IMUX_CE_OPTINV[1]IMUX_CE[1]!MAIN[4][69]
IMUX_CE_OPTINV[2]IMUX_CE[2]!MAIN[4][72]
IMUX_CE_OPTINV[3]IMUX_CE[3]!MAIN[4][78]
IMUX_TI_OPTINV[0]IMUX_TI[0]!MAIN[4][19]
IMUX_TI_OPTINV[1]IMUX_TI[1]!MAIN[4][27]
IMUX_TS_OPTINV[0]IMUX_TS[0]MAIN[4][38]
IMUX_TS_OPTINV[1]IMUX_TS[1]MAIN[4][30]
virtex2 INT_CNR switchbox INT muxes OMUX[0]
BitsDestination
MAIN[6][1]MAIN[7][2]MAIN[7][1]MAIN[7][0]MAIN[6][0]MAIN[6][3]MAIN[7][4]MAIN[7][5]MAIN[6][6]MAIN[6][9]OMUX[0]
Source
0000000000off
0001000001IMUX_SR[0]
0001000010IMUX_SR[2]
0001000100IMUX_G0_DATA[0]
0001001000IMUX_G0_DATA[1]
0001010000IMUX_G0_DATA[2]
0001100000IMUX_G0_DATA[3]
0010000001OUT_FAN[0]
0010000010OUT_FAN[1]
0010000100OUT_FAN[3]
0010001000OUT_FAN[2]
0010010000OUT_FAN[4]
0010100000OUT_FAN[5]
0100000001OUT_FAN[6]
0100000010OUT_FAN[7]
0100000100OUT_HALF0[8]
0100001000OUT_HALF0[9]
0100010000OUT_HALF0[10]
0100100000OUT_HALF0[11]
1000000001OUT_HALF0[12]
1000000010OUT_HALF0[13]
1000000100OUT_HALF0[14]
1000001000OUT_HALF0[15]
1000010000OUT_HALF0[16]
1000100000OUT_HALF0[17]
virtex2 INT_CNR switchbox INT muxes OMUX[1]
BitsDestination
MAIN[6][8]MAIN[7][7]MAIN[7][8]MAIN[7][9]MAIN[6][2]MAIN[7][3]MAIN[6][4]MAIN[6][5]MAIN[7][6]MAIN[6][7]OMUX[1]
Source
0000000000off
0001000001IMUX_SR[0]
0001000010IMUX_SR[2]
0001000100IMUX_G0_DATA[0]
0001001000IMUX_G0_DATA[1]
0001010000IMUX_G0_DATA[2]
0001100000IMUX_G0_DATA[3]
0010000001OUT_FAN[0]
0010000010OUT_FAN[1]
0010000100OUT_FAN[3]
0010001000OUT_FAN[2]
0010010000OUT_FAN[4]
0010100000OUT_FAN[5]
0100000001OUT_FAN[6]
0100000010OUT_FAN[7]
0100000100OUT_HALF0[8]
0100001000OUT_HALF0[9]
0100010000OUT_HALF0[10]
0100100000OUT_HALF0[11]
1000000001OUT_HALF0[12]
1000000010OUT_HALF0[13]
1000000100OUT_HALF0[14]
1000001000OUT_HALF0[15]
1000010000OUT_HALF0[16]
1000100000OUT_HALF0[17]
virtex2 INT_CNR switchbox INT muxes OMUX[2]
BitsDestination
MAIN[6][11]MAIN[7][12]MAIN[7][11]MAIN[7][10]MAIN[6][10]MAIN[6][13]MAIN[7][14]MAIN[7][15]MAIN[6][16]MAIN[6][19]OMUX[2]
Source
0000000000off
0001000001IMUX_SR[1]
0001000010IMUX_SR[3]
0001000100IMUX_G0_DATA[4]
0001001000IMUX_G0_DATA[5]
0001010000IMUX_G0_DATA[6]
0001100000IMUX_G0_DATA[7]
0010000001OUT_FAN[0]
0010000010OUT_FAN[1]
0010000100OUT_FAN[3]
0010001000OUT_FAN[2]
0010010000OUT_FAN[4]
0010100000OUT_FAN[5]
0100000001OUT_FAN[6]
0100000010OUT_FAN[7]
0100000100OUT_HALF0[8]
0100001000OUT_HALF0[9]
0100010000OUT_HALF0[10]
0100100000OUT_HALF0[11]
1000000001OUT_HALF0[12]
1000000010OUT_HALF0[13]
1000000100OUT_HALF0[14]
1000001000OUT_HALF0[15]
1000010000OUT_HALF0[16]
1000100000OUT_HALF0[17]
virtex2 INT_CNR switchbox INT muxes OMUX[3]
BitsDestination
MAIN[6][18]MAIN[7][17]MAIN[7][18]MAIN[7][19]MAIN[6][12]MAIN[7][13]MAIN[6][14]MAIN[6][15]MAIN[7][16]MAIN[6][17]OMUX[3]
Source
0000000000off
0001000001IMUX_SR[1]
0001000010IMUX_SR[3]
0001000100IMUX_G0_DATA[4]
0001001000IMUX_G0_DATA[5]
0001010000IMUX_G0_DATA[6]
0001100000IMUX_G0_DATA[7]
0010000001OUT_FAN[0]
0010000010OUT_FAN[1]
0010000100OUT_FAN[3]
0010001000OUT_FAN[2]
0010010000OUT_FAN[4]
0010100000OUT_FAN[5]
0100000001OUT_FAN[6]
0100000010OUT_FAN[7]
0100000100OUT_HALF0[8]
0100001000OUT_HALF0[9]
0100010000OUT_HALF0[10]
0100100000OUT_HALF0[11]
1000000001OUT_HALF0[12]
1000000010OUT_HALF0[13]
1000000100OUT_HALF0[14]
1000001000OUT_HALF0[15]
1000010000OUT_HALF0[16]
1000100000OUT_HALF0[17]
virtex2 INT_CNR switchbox INT muxes OMUX[4]
BitsDestination
MAIN[6][21]MAIN[7][22]MAIN[7][21]MAIN[7][20]MAIN[6][20]MAIN[6][23]MAIN[7][24]MAIN[7][25]MAIN[6][26]MAIN[6][29]OMUX[4]
Source
0000000000off
0001000001IMUX_TI[0]
0001000010IMUX_TI[1]
0001000100IMUX_G1_DATA[4]
0001001000IMUX_G1_DATA[5]
0001010000IMUX_G1_DATA[6]
0001100000IMUX_G1_DATA[7]
0010000001OUT_FAN[0]
0010000010OUT_FAN[1]
0010000100OUT_FAN[3]
0010001000OUT_FAN[2]
0010010000OUT_FAN[4]
0010100000OUT_FAN[5]
0100000001OUT_FAN[6]
0100000010OUT_FAN[7]
0100000100OUT_HALF0[8]
0100001000OUT_HALF0[9]
0100010000OUT_HALF0[10]
0100100000OUT_HALF0[11]
1000000001OUT_HALF0[12]
1000000010OUT_HALF0[13]
1000000100OUT_HALF0[14]
1000001000OUT_HALF0[15]
1000010000OUT_HALF0[16]
1000100000OUT_HALF0[17]
virtex2 INT_CNR switchbox INT muxes OMUX[5]
BitsDestination
MAIN[6][28]MAIN[7][27]MAIN[7][28]MAIN[7][29]MAIN[6][22]MAIN[7][23]MAIN[6][24]MAIN[6][25]MAIN[7][26]MAIN[6][27]OMUX[5]
Source
0000000000off
0001000001IMUX_TI[0]
0001000010IMUX_TI[1]
0001000100IMUX_G1_DATA[4]
0001001000IMUX_G1_DATA[5]
0001010000IMUX_G1_DATA[6]
0001100000IMUX_G1_DATA[7]
0010000001OUT_FAN[0]
0010000010OUT_FAN[1]
0010000100OUT_FAN[3]
0010001000OUT_FAN[2]
0010010000OUT_FAN[4]
0010100000OUT_FAN[5]
0100000001OUT_FAN[6]
0100000010OUT_FAN[7]
0100000100OUT_HALF0[8]
0100001000OUT_HALF0[9]
0100010000OUT_HALF0[10]
0100100000OUT_HALF0[11]
1000000001OUT_HALF0[12]
1000000010OUT_HALF0[13]
1000000100OUT_HALF0[14]
1000001000OUT_HALF0[15]
1000010000OUT_HALF0[16]
1000100000OUT_HALF0[17]
virtex2 INT_CNR switchbox INT muxes OMUX[6]
BitsDestination
MAIN[6][31]MAIN[7][32]MAIN[7][31]MAIN[7][30]MAIN[6][30]MAIN[6][33]MAIN[7][34]MAIN[7][35]MAIN[6][36]MAIN[6][39]OMUX[6]
Source
0000000000off
0001000001IMUX_TS[0]
0001000010IMUX_TS[1]
0001000100IMUX_G1_DATA[0]
0001001000IMUX_G1_DATA[1]
0001010000IMUX_G1_DATA[2]
0001100000IMUX_G1_DATA[3]
0010000001OUT_FAN[0]
0010000010OUT_FAN[1]
0010000100OUT_FAN[3]
0010001000OUT_FAN[2]
0010010000OUT_FAN[4]
0010100000OUT_FAN[5]
0100000001OUT_FAN[6]
0100000010OUT_FAN[7]
0100000100OUT_HALF0[8]
0100001000OUT_HALF0[9]
0100010000OUT_HALF0[10]
0100100000OUT_HALF0[11]
1000000001OUT_HALF0[12]
1000000010OUT_HALF0[13]
1000000100OUT_HALF0[14]
1000001000OUT_HALF0[15]
1000010000OUT_HALF0[16]
1000100000OUT_HALF0[17]
virtex2 INT_CNR switchbox INT muxes OMUX[7]
BitsDestination
MAIN[6][38]MAIN[7][37]MAIN[7][38]MAIN[7][39]MAIN[6][32]MAIN[7][33]MAIN[6][34]MAIN[6][35]MAIN[7][36]MAIN[6][37]OMUX[7]
Source
0000000000off
0001000001IMUX_TS[0]
0001000010IMUX_TS[1]
0001000100IMUX_G1_DATA[0]
0001001000IMUX_G1_DATA[1]
0001010000IMUX_G1_DATA[2]
0001100000IMUX_G1_DATA[3]
0010000001OUT_FAN[0]
0010000010OUT_FAN[1]
0010000100OUT_FAN[3]
0010001000OUT_FAN[2]
0010010000OUT_FAN[4]
0010100000OUT_FAN[5]
0100000001OUT_FAN[6]
0100000010OUT_FAN[7]
0100000100OUT_HALF0[8]
0100001000OUT_HALF0[9]
0100010000OUT_HALF0[10]
0100100000OUT_HALF0[11]
1000000001OUT_HALF0[12]
1000000010OUT_HALF0[13]
1000000100OUT_HALF0[14]
1000001000OUT_HALF0[15]
1000010000OUT_HALF0[16]
1000100000OUT_HALF0[17]
virtex2 INT_CNR switchbox INT muxes OMUX[8]
BitsDestination
MAIN[6][41]MAIN[7][42]MAIN[7][41]MAIN[7][40]MAIN[6][40]MAIN[6][43]MAIN[7][44]MAIN[7][45]MAIN[6][46]MAIN[6][49]OMUX[8]
Source
0000000000off
0001000001IMUX_CLK[0]
0001000010IMUX_CLK[1]
0001000100IMUX_G2_DATA[0]
0001001000IMUX_G2_DATA[1]
0001010000IMUX_G2_DATA[2]
0001100000IMUX_G2_DATA[3]
0010000001OUT_FAN[0]
0010000010OUT_FAN[1]
0010000100OUT_FAN[3]
0010001000OUT_FAN[2]
0010010000OUT_FAN[4]
0010100000OUT_FAN[5]
0100000001OUT_FAN[6]
0100000010OUT_FAN[7]
0100000100OUT_HALF1[8]
0100001000OUT_HALF1[9]
0100010000OUT_HALF1[10]
0100100000OUT_HALF1[11]
1000000001OUT_HALF1[12]
1000000010OUT_HALF1[13]
1000000100OUT_HALF1[14]
1000001000OUT_HALF1[15]
1000010000OUT_HALF1[16]
1000100000OUT_HALF1[17]
virtex2 INT_CNR switchbox INT muxes OMUX[9]
BitsDestination
MAIN[6][48]MAIN[7][47]MAIN[7][48]MAIN[7][49]MAIN[6][42]MAIN[7][43]MAIN[6][44]MAIN[6][45]MAIN[7][46]MAIN[6][47]OMUX[9]
Source
0000000000off
0001000001IMUX_CLK[0]
0001000010IMUX_CLK[1]
0001000100IMUX_G2_DATA[0]
0001001000IMUX_G2_DATA[1]
0001010000IMUX_G2_DATA[2]
0001100000IMUX_G2_DATA[3]
0010000001OUT_FAN[0]
0010000010OUT_FAN[1]
0010000100OUT_FAN[3]
0010001000OUT_FAN[2]
0010010000OUT_FAN[4]
0010100000OUT_FAN[5]
0100000001OUT_FAN[6]
0100000010OUT_FAN[7]
0100000100OUT_HALF1[8]
0100001000OUT_HALF1[9]
0100010000OUT_HALF1[10]
0100100000OUT_HALF1[11]
1000000001OUT_HALF1[12]
1000000010OUT_HALF1[13]
1000000100OUT_HALF1[14]
1000001000OUT_HALF1[15]
1000010000OUT_HALF1[16]
1000100000OUT_HALF1[17]
virtex2 INT_CNR switchbox INT muxes OMUX[10]
BitsDestination
MAIN[6][51]MAIN[7][52]MAIN[7][51]MAIN[7][50]MAIN[6][50]MAIN[6][53]MAIN[7][54]MAIN[7][55]MAIN[6][59]MAIN[6][56]OMUX[10]
Source
0000000000off
0001000001IMUX_CLK[2]
0001000010IMUX_CLK[3]
0001000100IMUX_G2_DATA[4]
0001001000IMUX_G2_DATA[5]
0001010000IMUX_G2_DATA[6]
0001100000IMUX_G2_DATA[7]
0010000001OUT_FAN[1]
0010000010OUT_FAN[0]
0010000100OUT_FAN[3]
0010001000OUT_FAN[2]
0010010000OUT_FAN[4]
0010100000OUT_FAN[5]
0100000001OUT_FAN[7]
0100000010OUT_FAN[6]
0100000100OUT_HALF1[8]
0100001000OUT_HALF1[9]
0100010000OUT_HALF1[10]
0100100000OUT_HALF1[11]
1000000001OUT_HALF1[13]
1000000010OUT_HALF1[12]
1000000100OUT_HALF1[14]
1000001000OUT_HALF1[15]
1000010000OUT_HALF1[16]
1000100000OUT_HALF1[17]
virtex2 INT_CNR switchbox INT muxes OMUX[11]
BitsDestination
MAIN[6][58]MAIN[7][57]MAIN[7][58]MAIN[7][59]MAIN[6][52]MAIN[7][53]MAIN[6][54]MAIN[6][55]MAIN[6][57]MAIN[7][56]OMUX[11]
Source
0000000000off
0001000001IMUX_CLK[2]
0001000010IMUX_CLK[3]
0001000100IMUX_G2_DATA[4]
0001001000IMUX_G2_DATA[5]
0001010000IMUX_G2_DATA[6]
0001100000IMUX_G2_DATA[7]
0010000001OUT_FAN[1]
0010000010OUT_FAN[0]
0010000100OUT_FAN[3]
0010001000OUT_FAN[2]
0010010000OUT_FAN[4]
0010100000OUT_FAN[5]
0100000001OUT_FAN[7]
0100000010OUT_FAN[6]
0100000100OUT_HALF1[8]
0100001000OUT_HALF1[9]
0100010000OUT_HALF1[10]
0100100000OUT_HALF1[11]
1000000001OUT_HALF1[13]
1000000010OUT_HALF1[12]
1000000100OUT_HALF1[14]
1000001000OUT_HALF1[15]
1000010000OUT_HALF1[16]
1000100000OUT_HALF1[17]
virtex2 INT_CNR switchbox INT muxes OMUX[12]
BitsDestination
MAIN[6][61]MAIN[7][62]MAIN[7][61]MAIN[7][60]MAIN[6][60]MAIN[6][63]MAIN[7][64]MAIN[7][65]MAIN[6][69]MAIN[6][66]OMUX[12]
Source
0000000000off
0001000001IMUX_CE[0]
0001000010IMUX_CE[1]
0001000100IMUX_G3_DATA[4]
0001001000IMUX_G3_DATA[5]
0001010000IMUX_G3_DATA[6]
0001100000IMUX_G3_DATA[7]
0010000001OUT_FAN[1]
0010000010OUT_FAN[0]
0010000100OUT_FAN[3]
0010001000OUT_FAN[2]
0010010000OUT_FAN[4]
0010100000OUT_FAN[5]
0100000001OUT_FAN[7]
0100000010OUT_FAN[6]
0100000100OUT_HALF1[8]
0100001000OUT_HALF1[9]
0100010000OUT_HALF1[10]
0100100000OUT_HALF1[11]
1000000001OUT_HALF1[13]
1000000010OUT_HALF1[12]
1000000100OUT_HALF1[14]
1000001000OUT_HALF1[15]
1000010000OUT_HALF1[16]
1000100000OUT_HALF1[17]
virtex2 INT_CNR switchbox INT muxes OMUX[13]
BitsDestination
MAIN[6][68]MAIN[7][67]MAIN[7][68]MAIN[7][69]MAIN[6][62]MAIN[7][63]MAIN[6][64]MAIN[6][65]MAIN[6][67]MAIN[7][66]OMUX[13]
Source
0000000000off
0001000001IMUX_CE[0]
0001000010IMUX_CE[1]
0001000100IMUX_G3_DATA[4]
0001001000IMUX_G3_DATA[5]
0001010000IMUX_G3_DATA[6]
0001100000IMUX_G3_DATA[7]
0010000001OUT_FAN[1]
0010000010OUT_FAN[0]
0010000100OUT_FAN[3]
0010001000OUT_FAN[2]
0010010000OUT_FAN[4]
0010100000OUT_FAN[5]
0100000001OUT_FAN[7]
0100000010OUT_FAN[6]
0100000100OUT_HALF1[8]
0100001000OUT_HALF1[9]
0100010000OUT_HALF1[10]
0100100000OUT_HALF1[11]
1000000001OUT_HALF1[13]
1000000010OUT_HALF1[12]
1000000100OUT_HALF1[14]
1000001000OUT_HALF1[15]
1000010000OUT_HALF1[16]
1000100000OUT_HALF1[17]
virtex2 INT_CNR switchbox INT muxes OMUX[14]
BitsDestination
MAIN[6][71]MAIN[7][72]MAIN[7][71]MAIN[7][70]MAIN[6][70]MAIN[6][73]MAIN[7][74]MAIN[7][75]MAIN[6][76]MAIN[6][79]OMUX[14]
Source
0000000000off
0001000001IMUX_CE[2]
0001000010IMUX_CE[3]
0001000100IMUX_G3_DATA[0]
0001001000IMUX_G3_DATA[1]
0001010000IMUX_G3_DATA[2]
0001100000IMUX_G3_DATA[3]
0010000001OUT_FAN[0]
0010000010OUT_FAN[1]
0010000100OUT_FAN[3]
0010001000OUT_FAN[2]
0010010000OUT_FAN[4]
0010100000OUT_FAN[5]
0100000001OUT_FAN[6]
0100000010OUT_FAN[7]
0100000100OUT_HALF1[8]
0100001000OUT_HALF1[9]
0100010000OUT_HALF1[10]
0100100000OUT_HALF1[11]
1000000001OUT_HALF1[12]
1000000010OUT_HALF1[13]
1000000100OUT_HALF1[14]
1000001000OUT_HALF1[15]
1000010000OUT_HALF1[16]
1000100000OUT_HALF1[17]
virtex2 INT_CNR switchbox INT muxes OMUX[15]
BitsDestination
MAIN[6][78]MAIN[7][77]MAIN[7][78]MAIN[7][79]MAIN[6][72]MAIN[7][73]MAIN[6][74]MAIN[6][75]MAIN[7][76]MAIN[6][77]OMUX[15]
Source
0000000000off
0001000001IMUX_CE[2]
0001000010IMUX_CE[3]
0001000100IMUX_G3_DATA[0]
0001001000IMUX_G3_DATA[1]
0001010000IMUX_G3_DATA[2]
0001100000IMUX_G3_DATA[3]
0010000001OUT_FAN[0]
0010000010OUT_FAN[1]
0010000100OUT_FAN[3]
0010001000OUT_FAN[2]
0010010000OUT_FAN[4]
0010100000OUT_FAN[5]
0100000001OUT_FAN[6]
0100000010OUT_FAN[7]
0100000100OUT_HALF1[8]
0100001000OUT_HALF1[9]
0100010000OUT_HALF1[10]
0100100000OUT_HALF1[11]
1000000001OUT_HALF1[12]
1000000010OUT_HALF1[13]
1000000100OUT_HALF1[14]
1000001000OUT_HALF1[15]
1000010000OUT_HALF1[16]
1000100000OUT_HALF1[17]
virtex2 INT_CNR switchbox INT muxes DBL_W0[0]
BitsDestination
MAIN[16][5]MAIN[16][6]MAIN[17][6]MAIN[17][5]MAIN[15][7]MAIN[14][5]MAIN[14][4]MAIN[15][6]DBL_W0[0]
Source
00000000off
00010001OMUX_S0
00010010HEX_E6[0]
00010100OUT_FAN[3]
00011000HEX_N6[0]
00100001OMUX_NW10
00100010HEX_S6[1]
00100100OUT_FAN[4]
00101000HEX_W6[0]
01000001DBL_W2[0]
01000010HEX_N3[0]
01000100HEX_S3[0]
01001000DBL_N3[9]
10000001DBL_W2_N[8]
10000010DBL_S1[0]
10000100DBL_S2[2]
10001000DBL_N1[0]
virtex2 INT_CNR switchbox INT muxes DBL_W0[1]
BitsDestination
MAIN[16][13]MAIN[16][14]MAIN[17][14]MAIN[17][13]MAIN[15][15]MAIN[14][13]MAIN[14][12]MAIN[15][14]DBL_W0[1]
Source
00000000off
00010001OMUX[2]
00010010HEX_E6[1]
00010100OUT_FAN[2]
00011000HEX_N6[1]
00100001OMUX_W1
00100010HEX_S6[2]
00100100OUT_FAN[5]
00101000HEX_W6[1]
01000001DBL_W2[1]
01000010HEX_N3[1]
01000100HEX_S3[1]
01001000DBL_N2[0]
10000001DBL_W2_N[9]
10000010DBL_S1[1]
10000100DBL_S2[3]
10001000DBL_N1[1]
virtex2 INT_CNR switchbox INT muxes DBL_W0[2]
BitsDestination
MAIN[15][23]MAIN[14][20]MAIN[15][22]MAIN[14][21]MAIN[16][22]MAIN[16][21]MAIN[17][22]MAIN[17][21]DBL_W0[2]
Source
00000000off
00010001OMUX[4]
00010010OUT_FAN[3]
00010100DBL_S2[4]
00011000HEX_S3[2]
00100001OMUX[6]
00100010OMUX_WN14
00100100DBL_W2[0]
00101000DBL_W2[2]
01000001HEX_E6[2]
01000010HEX_S6[3]
01000100DBL_S1[2]
01001000HEX_N3[2]
10000001HEX_N6[2]
10000010HEX_W6[2]
10000100DBL_N1[2]
10001000DBL_N2[1]
virtex2 INT_CNR switchbox INT muxes DBL_W0[3]
BitsDestination
MAIN[16][30]MAIN[16][29]MAIN[17][30]MAIN[17][29]MAIN[15][31]MAIN[14][29]MAIN[14][28]MAIN[15][30]DBL_W0[3]
Source
00000000off
00010001OMUX_W6
00010010HEX_E6[3]
00010100OUT_FAN[4]
00011000HEX_N6[3]
00100001OMUX_NW10
00100010HEX_S6[4]
00100100OUT_FAN[2]
00101000HEX_W6[3]
01000001DBL_W2[1]
01000010DBL_S1[3]
01000100DBL_S2[5]
01001000DBL_N1[3]
10000001DBL_W2[3]
10000010HEX_N3[3]
10000100HEX_S3[3]
10001000DBL_N2[2]
virtex2 INT_CNR switchbox INT muxes DBL_W0[4]
BitsDestination
MAIN[16][38]MAIN[16][37]MAIN[17][38]MAIN[17][37]MAIN[15][39]MAIN[14][37]MAIN[14][36]MAIN[15][38]DBL_W0[4]
Source
00000000off
00010001OMUX_WS1
00010010HEX_E6[4]
00010100OUT_FAN[5]
00011000HEX_N6[4]
00100001OMUX_N12
00100010HEX_S6[5]
00100100OUT_FAN[6]
00101000HEX_W6[4]
01000001DBL_W2[2]
01000010DBL_S1[4]
01000100DBL_S2[6]
01001000DBL_N1[4]
10000001DBL_W2[4]
10000010HEX_N3[4]
10000100HEX_S3[4]
10001000DBL_N2[3]
virtex2 INT_CNR switchbox INT muxes DBL_W0[5]
BitsDestination
MAIN[16][46]MAIN[16][45]MAIN[17][46]MAIN[17][45]MAIN[15][47]MAIN[14][45]MAIN[14][44]MAIN[15][46]DBL_W0[5]
Source
00000000off
00010001OMUX_S3
00010010HEX_E6[5]
00010100OUT_FAN[1]
00011000HEX_N6[5]
00100001OMUX_WN14
00100010HEX_S6[6]
00100100OUT_FAN[7]
00101000HEX_W6[5]
01000001DBL_W2[3]
01000010DBL_S1[5]
01000100DBL_S2[7]
01001000DBL_N1[5]
10000001DBL_W2[5]
10000010HEX_N3[5]
10000100HEX_S3[5]
10001000DBL_N2[4]
virtex2 INT_CNR switchbox INT muxes DBL_W0[6]
BitsDestination
MAIN[15][55]MAIN[14][52]MAIN[15][54]MAIN[14][53]MAIN[16][54]MAIN[16][53]MAIN[17][53]MAIN[17][54]DBL_W0[6]
Source
00000000off
00010001OMUX[11]
00010010OUT_FAN[0]
00010100DBL_S2[8]
00011000HEX_S3[6]
00100001OMUX_W9
00100010OMUX_SW5
00100100DBL_W2[4]
00101000DBL_W2[6]
01000001HEX_S6[7]
01000010HEX_E6[6]
01000100DBL_S1[6]
01001000HEX_N3[6]
10000001HEX_W6[6]
10000010HEX_N6[6]
10000100DBL_N1[6]
10001000DBL_N2[5]
virtex2 INT_CNR switchbox INT muxes DBL_W0[7]
BitsDestination
MAIN[16][62]MAIN[16][61]MAIN[17][61]MAIN[17][62]MAIN[15][63]MAIN[14][61]MAIN[14][60]MAIN[15][62]DBL_W0[7]
Source
00000000off
00010001OMUX[9]
00010010HEX_S6[8]
00010100OUT_FAN[1]
00011000HEX_W6[7]
00100001OMUX_WS1
00100010HEX_E6[7]
00100100OUT_FAN[6]
00101000HEX_N6[7]
01000001DBL_W2[5]
01000010DBL_S1[7]
01000100DBL_S2[9]
01001000DBL_N1[7]
10000001DBL_W2[7]
10000010HEX_N3[7]
10000100HEX_S3[7]
10001000DBL_N2[6]
virtex2 INT_CNR switchbox INT muxes DBL_W0[8]
BitsDestination
MAIN[16][70]MAIN[16][69]MAIN[17][69]MAIN[17][70]MAIN[15][71]MAIN[14][69]MAIN[14][68]MAIN[15][70]DBL_W0[8]
Source
00000000off
00010001OMUX[13]
00010010HEX_S6[9]
00010100OUT_FAN[0]
00011000HEX_W6[8]
00100001OMUX_W14
00100010HEX_E6[8]
00100100OUT_FAN[7]
00101000HEX_N6[8]
01000001DBL_W2[6]
01000010DBL_S1[8]
01000100DBL_S3[0]
01001000DBL_N1[8]
10000001DBL_W2[8]
10000010HEX_N3[8]
10000100HEX_S3[8]
10001000DBL_N2[7]
virtex2 INT_CNR switchbox INT muxes DBL_W0[9]
BitsDestination
MAIN[15][79]MAIN[14][76]MAIN[14][77]MAIN[15][78]MAIN[16][78]MAIN[16][77]MAIN[17][77]MAIN[17][78]DBL_W0[9]
Source
00000000off
00010001OMUX[13]
00010010OMUX_SW5
00010100DBL_W2[7]
00011000DBL_W2[9]
00100001OMUX_S0
00100010OMUX[15]
00100100DBL_S3[1]
00101000HEX_S3[9]
01000001HEX_S7[0]
01000010HEX_E6[9]
01000100DBL_S1[9]
01001000HEX_N3[9]
10000001HEX_W6[9]
10000010HEX_N6[9]
10000100DBL_N1[9]
10001000DBL_N2[8]
virtex2 INT_CNR switchbox INT muxes DBL_E0[0]
BitsDestination
MAIN[17][7]MAIN[17][4]MAIN[16][4]MAIN[16][7]MAIN[15][5]MAIN[14][7]MAIN[15][4]MAIN[14][6]DBL_E0[0]
Source
00000000off
00010001OMUX_E2
00010010HEX_S6[1]
00010100OUT_FAN[4]
00011000HEX_W6[0]
00100001OMUX_EN8
00100010HEX_E6[0]
00100100OUT_FAN[3]
00101000HEX_N6[0]
01000001DBL_E2[0]
01000010DBL_S1[0]
01000100DBL_S2[2]
01001000DBL_N1[0]
10000001DBL_E2[2]
10000010HEX_N3[0]
10000100HEX_S3[0]
10001000DBL_N3[9]
virtex2 INT_CNR switchbox INT muxes DBL_E0[1]
BitsDestination
MAIN[17][15]MAIN[17][12]MAIN[16][12]MAIN[16][15]MAIN[15][13]MAIN[14][15]MAIN[15][12]MAIN[14][14]DBL_E0[1]
Source
00000000off
00010001OMUX_S4
00010010HEX_S6[2]
00010100OUT_FAN[5]
00011000HEX_W6[1]
00100001OMUX_N10
00100010HEX_E6[1]
00100100OUT_FAN[2]
00101000HEX_N6[1]
01000001DBL_E2[1]
01000010DBL_S1[1]
01000100DBL_S2[3]
01001000DBL_N1[1]
10000001DBL_E2[3]
10000010HEX_N3[1]
10000100HEX_S3[1]
10001000DBL_N2[0]
virtex2 INT_CNR switchbox INT muxes DBL_E0[2]
BitsDestination
MAIN[15][21]MAIN[15][20]MAIN[14][22]MAIN[14][23]MAIN[17][23]MAIN[17][20]MAIN[16][23]MAIN[16][20]DBL_E0[2]
Source
00000000off
00010001OMUX[4]
00010010OUT_FAN[3]
00010100DBL_S2[4]
00011000HEX_S3[2]
00100001OMUX_NE12
00100010OMUX[6]
00100100DBL_E2[2]
00101000DBL_E2[4]
01000001HEX_E6[2]
01000010HEX_S6[3]
01000100DBL_S1[2]
01001000HEX_N3[2]
10000001HEX_N6[2]
10000010HEX_W6[2]
10000100DBL_N1[2]
10001000DBL_N2[1]
virtex2 INT_CNR switchbox INT muxes DBL_E0[3]
BitsDestination
MAIN[17][31]MAIN[17][28]MAIN[16][28]MAIN[16][31]MAIN[15][29]MAIN[14][31]MAIN[15][28]MAIN[14][30]DBL_E0[3]
Source
00000000off
00010001OMUX_SE3
00010010HEX_S6[4]
00010100OUT_FAN[2]
00011000HEX_W6[3]
00100001OMUX_EN8
00100010HEX_E6[3]
00100100OUT_FAN[4]
00101000HEX_N6[3]
01000001DBL_E2[3]
01000010DBL_S1[3]
01000100DBL_S2[5]
01001000DBL_N1[3]
10000001DBL_E2[5]
10000010HEX_N3[3]
10000100HEX_S3[3]
10001000DBL_N2[2]
virtex2 INT_CNR switchbox INT muxes DBL_E0[4]
BitsDestination
MAIN[17][39]MAIN[17][36]MAIN[16][39]MAIN[16][36]MAIN[15][37]MAIN[14][39]MAIN[15][36]MAIN[14][38]DBL_E0[4]
Source
00000000off
00010001OMUX_E7
00010010HEX_E6[4]
00010100OUT_FAN[5]
00011000HEX_N6[4]
00100001OMUX_E8
00100010HEX_S6[5]
00100100OUT_FAN[6]
00101000HEX_W6[4]
01000001DBL_E2[4]
01000010DBL_S1[4]
01000100DBL_S2[6]
01001000DBL_N1[4]
10000001DBL_E2[6]
10000010HEX_N3[4]
10000100HEX_S3[4]
10001000DBL_N2[3]
virtex2 INT_CNR switchbox INT muxes DBL_E0[5]
BitsDestination
MAIN[17][47]MAIN[17][44]MAIN[16][44]MAIN[16][47]MAIN[15][45]MAIN[14][47]MAIN[15][44]MAIN[14][46]DBL_E0[5]
Source
00000000off
00010001OMUX_ES7
00010010HEX_S6[6]
00010100OUT_FAN[7]
00011000HEX_W6[5]
00100001OMUX_NE12
00100010HEX_E6[5]
00100100OUT_FAN[1]
00101000HEX_N6[5]
01000001DBL_E2[5]
01000010DBL_S1[5]
01000100DBL_S2[7]
01001000DBL_N1[5]
10000001DBL_E2[7]
10000010HEX_N3[5]
10000100HEX_S3[5]
10001000DBL_N2[4]
virtex2 INT_CNR switchbox INT muxes DBL_E0[6]
BitsDestination
MAIN[17][55]MAIN[17][52]MAIN[16][55]MAIN[16][52]MAIN[15][53]MAIN[15][52]MAIN[14][55]MAIN[14][54]DBL_E0[6]
Source
00000000off
00010001OMUX[9]
00010010OUT_FAN[0]
00010100HEX_E6[6]
00011000HEX_N6[6]
00100001OMUX_SE3
00100010OMUX[11]
00100100HEX_S6[7]
00101000HEX_W6[6]
01000001DBL_E2[6]
01000010DBL_S2[8]
01000100DBL_S1[6]
01001000DBL_N1[6]
10000001DBL_E2[8]
10000010HEX_S3[6]
10000100HEX_N3[6]
10001000DBL_N2[5]
virtex2 INT_CNR switchbox INT muxes DBL_E0[7]
BitsDestination
MAIN[17][63]MAIN[17][60]MAIN[16][60]MAIN[16][63]MAIN[15][61]MAIN[14][63]MAIN[15][60]MAIN[14][62]DBL_E0[7]
Source
00000000off
00010001OMUX_S5
00010010HEX_S6[8]
00010100OUT_FAN[1]
00011000HEX_W6[7]
00100001OMUX_N11
00100010HEX_E6[7]
00100100OUT_FAN[6]
00101000HEX_N6[7]
01000001DBL_E2[7]
01000010DBL_S1[7]
01000100DBL_S2[9]
01001000DBL_N1[7]
10000001DBL_E2[9]
10000010HEX_N3[7]
10000100HEX_S3[7]
10001000DBL_N2[6]
virtex2 INT_CNR switchbox INT muxes DBL_E0[8]
BitsDestination
MAIN[17][71]MAIN[17][68]MAIN[16][68]MAIN[16][71]MAIN[15][69]MAIN[14][71]MAIN[15][68]MAIN[14][70]DBL_E0[8]
Source
00000000off
00010001OMUX_ES7
00010010HEX_S6[9]
00010100OUT_FAN[0]
00011000HEX_W6[8]
00100001OMUX_E13
00100010HEX_E6[8]
00100100OUT_FAN[7]
00101000HEX_N6[8]
01000001DBL_E2[8]
01000010DBL_S1[8]
01000100DBL_S3[0]
01001000DBL_N1[8]
10000001DBL_E2_S[0]
10000010HEX_N3[8]
10000100HEX_S3[8]
10001000DBL_N2[7]
virtex2 INT_CNR switchbox INT muxes DBL_E0[9]
BitsDestination
MAIN[17][79]MAIN[17][76]MAIN[16][79]MAIN[16][76]MAIN[15][77]MAIN[15][76]MAIN[14][78]MAIN[14][79]DBL_E0[9]
Source
00000000off
00010001OMUX[15]
00010010OMUX_N15
00010100HEX_E6[9]
00011000HEX_N6[9]
00100001OMUX_S0
00100010OMUX_S2
00100100HEX_S7[0]
00101000HEX_W6[9]
01000001DBL_S3[1]
01000010DBL_E2[9]
01000100DBL_S1[9]
01001000DBL_N1[9]
10000001HEX_S3[9]
10000010DBL_E2_S[1]
10000100HEX_N3[9]
10001000DBL_N2[8]
virtex2 INT_CNR switchbox INT muxes DBL_S0[0]
BitsDestination
MAIN[15][0]MAIN[15][1]MAIN[14][2]MAIN[14][3]MAIN[17][3]MAIN[17][0]MAIN[16][3]MAIN[16][0]DBL_S0[0]
Source
00000000off
00010001OMUX[0]
00010010OUT_FAN[3]
00010100DBL_E2[1]
00011000HEX_E3[0]
00100001OMUX[2]
00100010OMUX_S0
00100100DBL_S2[0]
00101000DBL_S2[2]
01000001HEX_W6_N[9]
01000010HEX_N6[0]
01000100DBL_W1[0]
01001000DBL_W2_N[8]
10000001HEX_S6[0]
10000010HEX_E6[0]
10000100DBL_E1[0]
10001000HEX_W3[0]
virtex2 INT_CNR switchbox INT muxes DBL_S0[1]
BitsDestination
MAIN[17][11]MAIN[17][8]MAIN[16][8]MAIN[16][11]MAIN[14][11]MAIN[15][8]MAIN[15][9]MAIN[14][10]DBL_S0[1]
Source
00000000off
00010001OMUX[2]
00010010HEX_N6[1]
00010100HEX_E6[1]
00011000OUT_FAN[2]
00100001OMUX_E2
00100010HEX_W6[0]
00100100HEX_S6[1]
00101000OUT_FAN[4]
01000001DBL_S2[1]
01000010DBL_W1[1]
01000100DBL_E1[1]
01001000DBL_E2[2]
10000001DBL_S2[3]
10000010DBL_W2_N[9]
10000100HEX_W3[1]
10001000HEX_E3[1]
virtex2 INT_CNR switchbox INT muxes DBL_S0[2]
BitsDestination
MAIN[15][16]MAIN[15][17]MAIN[14][18]MAIN[14][19]MAIN[17][19]MAIN[17][16]MAIN[16][16]MAIN[16][19]DBL_S0[2]
Source
00000000off
00010001OMUX[4]
00010010OUT_FAN[5]
00010100DBL_E2[3]
00011000HEX_E3[2]
00100001OMUX[6]
00100010OMUX_S4
00100100DBL_S2[2]
00101000DBL_S2[4]
01000001HEX_N6[2]
01000010HEX_W6[1]
01000100DBL_W1[2]
01001000DBL_W2[0]
10000001HEX_E6[2]
10000010HEX_S6[2]
10000100DBL_E1[2]
10001000HEX_W3[2]
virtex2 INT_CNR switchbox INT muxes DBL_S0[3]
BitsDestination
MAIN[17][27]MAIN[17][24]MAIN[16][27]MAIN[16][24]MAIN[14][27]MAIN[15][24]MAIN[15][25]MAIN[14][26]DBL_S0[3]
Source
00000000off
00010001OMUX[6]
00010010HEX_W6[2]
00010100HEX_S6[3]
00011000OUT_FAN[3]
00100001OMUX_W6
00100010HEX_N6[3]
00100100HEX_E6[3]
00101000OUT_FAN[4]
01000001DBL_S2[3]
01000010DBL_W1[3]
01000100DBL_E1[3]
01001000DBL_E2[4]
10000001DBL_S2[5]
10000010DBL_W2[1]
10000100HEX_W3[3]
10001000HEX_E3[3]
virtex2 INT_CNR switchbox INT muxes DBL_S0[4]
BitsDestination
MAIN[17][35]MAIN[17][32]MAIN[16][32]MAIN[16][35]MAIN[14][35]MAIN[15][32]MAIN[15][33]MAIN[14][34]DBL_S0[4]
Source
00000000off
00010001OMUX_WS1
00010010HEX_N6[4]
00010100HEX_E6[4]
00011000OUT_FAN[5]
00100001OMUX_SE3
00100010HEX_W6[3]
00100100HEX_S6[4]
00101000OUT_FAN[2]
01000001DBL_S2[4]
01000010DBL_W1[4]
01000100DBL_E1[4]
01001000DBL_E2[5]
10000001DBL_S2[6]
10000010DBL_W2[2]
10000100HEX_W3[4]
10001000HEX_E3[4]
virtex2 INT_CNR switchbox INT muxes DBL_S0[5]
BitsDestination
MAIN[17][43]MAIN[17][40]MAIN[16][40]MAIN[16][43]MAIN[14][43]MAIN[15][40]MAIN[15][41]MAIN[14][42]DBL_S0[5]
Source
00000000off
00010001OMUX_S3
00010010HEX_N6[5]
00010100HEX_E6[5]
00011000OUT_FAN[1]
00100001OMUX_E8
00100010HEX_W6[4]
00100100HEX_S6[5]
00101000OUT_FAN[6]
01000001DBL_S2[5]
01000010DBL_W1[5]
01000100DBL_E1[5]
01001000DBL_E2[6]
10000001DBL_S2[7]
10000010DBL_W2[3]
10000100HEX_W3[5]
10001000HEX_E3[5]
virtex2 INT_CNR switchbox INT muxes DBL_S0[6]
BitsDestination
MAIN[17][51]MAIN[17][48]MAIN[16][48]MAIN[16][51]MAIN[14][51]MAIN[15][48]MAIN[15][49]MAIN[14][50]DBL_S0[6]
Source
00000000off
00010001OMUX_SW5
00010010HEX_N6[6]
00010100HEX_E6[6]
00011000OUT_FAN[0]
00100001OMUX_ES7
00100010HEX_W6[5]
00100100HEX_S6[6]
00101000OUT_FAN[7]
01000001DBL_S2[6]
01000010DBL_W1[6]
01000100DBL_E1[6]
01001000DBL_E2[7]
10000001DBL_S2[8]
10000010DBL_W2[4]
10000100HEX_W3[6]
10001000HEX_E3[6]
virtex2 INT_CNR switchbox INT muxes DBL_S0[7]
BitsDestination
MAIN[15][56]MAIN[15][57]MAIN[14][58]MAIN[14][59]MAIN[17][59]MAIN[17][56]MAIN[16][59]MAIN[16][56]DBL_S0[7]
Source
00000000off
00010001OMUX[11]
00010010OUT_FAN[6]
00010100DBL_E2[8]
00011000HEX_E3[7]
00100001OMUX_SE3
00100010OMUX_WS1
00100100DBL_S2[7]
00101000DBL_S2[9]
01000001HEX_W6[6]
01000010HEX_N6[7]
01000100DBL_W1[7]
01001000DBL_W2[5]
10000001HEX_S6[7]
10000010HEX_E6[7]
10000100DBL_E1[7]
10001000HEX_W3[7]
virtex2 INT_CNR switchbox INT muxes DBL_S0[8]
BitsDestination
MAIN[17][67]MAIN[17][64]MAIN[16][67]MAIN[16][64]MAIN[14][67]MAIN[15][64]MAIN[15][65]MAIN[14][66]DBL_S0[8]
Source
00000000off
00010001OMUX_S5
00010010HEX_W6[7]
00010100HEX_S6[8]
00011000OUT_FAN[1]
00100001OMUX_W14
00100010HEX_N6[8]
00100100HEX_E6[8]
00101000OUT_FAN[7]
01000001DBL_S2[8]
01000010DBL_W1[8]
01000100DBL_E1[8]
01001000DBL_E2[9]
10000001DBL_S3[0]
10000010DBL_W2[6]
10000100HEX_W3[8]
10001000HEX_E3[8]
virtex2 INT_CNR switchbox INT muxes DBL_S0[9]
BitsDestination
MAIN[15][72]MAIN[15][73]MAIN[14][74]MAIN[14][75]MAIN[17][75]MAIN[17][72]MAIN[16][72]MAIN[16][75]DBL_S0[9]
Source
00000000off
00010001OMUX[15]
00010010OUT_FAN[0]
00010100DBL_E2_S[0]
00011000HEX_E3[9]
00100001OMUX_SW5
00100010OMUX_ES7
00100100DBL_S2[9]
00101000DBL_S3[1]
01000001HEX_N6[9]
01000010HEX_W6[8]
01000100DBL_W1[9]
01001000DBL_W2[7]
10000001HEX_E6[9]
10000010HEX_S6[9]
10000100DBL_E1[9]
10001000HEX_W3[9]
virtex2 INT_CNR switchbox INT muxes DBL_N0[0]
BitsDestination
MAIN[14][0]MAIN[15][3]MAIN[15][2]MAIN[14][1]MAIN[16][2]MAIN[16][1]MAIN[17][2]MAIN[17][1]DBL_N0[0]
Source
00000000off
00010001OMUX[0]
00010010OUT_FAN[3]
00010100DBL_E2[1]
00011000HEX_E3[0]
00100001OMUX_N13
00100010OMUX_EN8
00100100DBL_N3[8]
00101000DBL_N2[0]
01000001HEX_W6_N[9]
01000010HEX_N6[0]
01000100DBL_W1[0]
01001000DBL_W2_N[8]
10000001HEX_S6[0]
10000010HEX_E6[0]
10000100DBL_E1[0]
10001000HEX_W3[0]
virtex2 INT_CNR switchbox INT muxes DBL_N0[1]
BitsDestination
MAIN[16][10]MAIN[16][9]MAIN[17][9]MAIN[17][10]MAIN[14][9]MAIN[14][8]MAIN[15][11]MAIN[15][10]DBL_N0[1]
Source
00000000off
00010001OMUX_N10
00010010HEX_N6[1]
00010100HEX_E6[1]
00011000OUT_FAN[2]
00100001OMUX_NW10
00100010HEX_W6[0]
00100100HEX_S6[1]
00101000OUT_FAN[4]
01000001DBL_N3[9]
01000010DBL_W1[1]
01000100DBL_E1[1]
01001000DBL_E2[2]
10000001DBL_N2[1]
10000010DBL_W2_N[9]
10000100HEX_W3[1]
10001000HEX_E3[1]
virtex2 INT_CNR switchbox INT muxes DBL_N0[2]
BitsDestination
MAIN[14][16]MAIN[15][19]MAIN[15][18]MAIN[14][17]MAIN[16][18]MAIN[16][17]MAIN[17][17]MAIN[17][18]DBL_N0[2]
Source
00000000off
00010001OMUX[4]
00010010OUT_FAN[5]
00010100DBL_E2[3]
00011000HEX_E3[2]
00100001OMUX_NE12
00100010OMUX_W1
00100100DBL_N2[0]
00101000DBL_N2[2]
01000001HEX_N6[2]
01000010HEX_W6[1]
01000100DBL_W1[2]
01001000DBL_W2[0]
10000001HEX_E6[2]
10000010HEX_S6[2]
10000100DBL_E1[2]
10001000HEX_W3[2]
virtex2 INT_CNR switchbox INT muxes DBL_N0[3]
BitsDestination
MAIN[16][26]MAIN[16][25]MAIN[17][25]MAIN[17][26]MAIN[14][25]MAIN[14][24]MAIN[15][27]MAIN[15][26]DBL_N0[3]
Source
00000000off
00010001OMUX_EN8
00010010HEX_N6[3]
00010100HEX_E6[3]
00011000OUT_FAN[4]
00100001OMUX_WN14
00100010HEX_W6[2]
00100100HEX_S6[3]
00101000OUT_FAN[3]
01000001DBL_N2[1]
01000010DBL_W1[3]
01000100DBL_E1[3]
01001000DBL_E2[4]
10000001DBL_N2[3]
10000010DBL_W2[1]
10000100HEX_W3[3]
10001000HEX_E3[3]
virtex2 INT_CNR switchbox INT muxes DBL_N0[4]
BitsDestination
MAIN[16][34]MAIN[16][33]MAIN[17][33]MAIN[17][34]MAIN[14][33]MAIN[14][32]MAIN[15][35]MAIN[15][34]DBL_N0[4]
Source
00000000off
00010001OMUX_E7
00010010HEX_N6[4]
00010100HEX_E6[4]
00011000OUT_FAN[5]
00100001OMUX_NW10
00100010HEX_W6[3]
00100100HEX_S6[4]
00101000OUT_FAN[2]
01000001DBL_N2[2]
01000010DBL_W1[4]
01000100DBL_E1[4]
01001000DBL_E2[5]
10000001DBL_N2[4]
10000010DBL_W2[2]
10000100HEX_W3[4]
10001000HEX_E3[4]
virtex2 INT_CNR switchbox INT muxes DBL_N0[5]
BitsDestination
MAIN[16][42]MAIN[16][41]MAIN[17][42]MAIN[17][41]MAIN[14][41]MAIN[14][40]MAIN[15][43]MAIN[15][42]DBL_N0[5]
Source
00000000off
00010001OMUX_N12
00010010HEX_W6[4]
00010100HEX_S6[5]
00011000OUT_FAN[6]
00100001OMUX_NE12
00100010HEX_N6[5]
00100100HEX_E6[5]
00101000OUT_FAN[1]
01000001DBL_N2[3]
01000010DBL_W1[5]
01000100DBL_E1[5]
01001000DBL_E2[6]
10000001DBL_N2[5]
10000010DBL_W2[3]
10000100HEX_W3[5]
10001000HEX_E3[5]
virtex2 INT_CNR switchbox INT muxes DBL_N0[6]
BitsDestination
MAIN[16][50]MAIN[16][49]MAIN[17][49]MAIN[17][50]MAIN[14][49]MAIN[14][48]MAIN[15][51]MAIN[15][50]DBL_N0[6]
Source
00000000off
00010001OMUX[9]
00010010HEX_N6[6]
00010100HEX_E6[6]
00011000OUT_FAN[0]
00100001OMUX_WN14
00100010HEX_W6[5]
00100100HEX_S6[6]
00101000OUT_FAN[7]
01000001DBL_N2[4]
01000010DBL_W1[6]
01000100DBL_E1[6]
01001000DBL_E2[7]
10000001DBL_N2[6]
10000010DBL_W2[4]
10000100HEX_W3[6]
10001000HEX_E3[6]
virtex2 INT_CNR switchbox INT muxes DBL_N0[7]
BitsDestination
MAIN[14][56]MAIN[15][59]MAIN[15][58]MAIN[14][57]MAIN[16][58]MAIN[16][57]MAIN[17][58]MAIN[17][57]DBL_N0[7]
Source
00000000off
00010001OMUX[11]
00010010OUT_FAN[6]
00010100DBL_E2[8]
00011000HEX_E3[7]
00100001OMUX_W9
00100010OMUX_N11
00100100DBL_N2[5]
00101000DBL_N2[7]
01000001HEX_W6[6]
01000010HEX_N6[7]
01000100DBL_W1[7]
01001000DBL_W2[5]
10000001HEX_S6[7]
10000010HEX_E6[7]
10000100DBL_E1[7]
10001000HEX_W3[7]
virtex2 INT_CNR switchbox INT muxes DBL_N0[8]
BitsDestination
MAIN[16][66]MAIN[16][65]MAIN[17][66]MAIN[17][65]MAIN[14][65]MAIN[14][64]MAIN[15][67]MAIN[15][66]DBL_N0[8]
Source
00000000off
00010001OMUX[9]
00010010HEX_W6[7]
00010100HEX_S6[8]
00011000OUT_FAN[1]
00100001OMUX_E13
00100010HEX_N6[8]
00100100HEX_E6[8]
00101000OUT_FAN[7]
01000001DBL_N2[6]
01000010DBL_W1[8]
01000100DBL_E1[8]
01001000DBL_E2[9]
10000001DBL_N2[8]
10000010DBL_W2[6]
10000100HEX_W3[8]
10001000HEX_E3[8]
virtex2 INT_CNR switchbox INT muxes DBL_N0[9]
BitsDestination
MAIN[16][74]MAIN[16][73]MAIN[17][74]MAIN[17][73]MAIN[14][72]MAIN[15][75]MAIN[14][73]MAIN[15][74]DBL_N0[9]
Source
00000000off
00010001OMUX[13]
00010010OUT_FAN[0]
00010100HEX_W6[8]
00011000HEX_S6[9]
00100001OMUX_N15
00100010OMUX[15]
00100100HEX_N6[9]
00101000HEX_E6[9]
01000001DBL_N2[7]
01000010DBL_E2_S[0]
01000100DBL_W1[9]
01001000DBL_E1[9]
10000001DBL_N2[9]
10000010HEX_E3[9]
10000100DBL_W2[7]
10001000HEX_W3[9]
virtex2 INT_CNR switchbox INT muxes HEX_W0[0]
BitsDestination
MAIN[20][4]MAIN[20][6]MAIN[20][5]MAIN[18][4]MAIN[19][6]MAIN[18][6]MAIN[19][4]HEX_W0[0]
Source
0000000off
0010001OMUX_S0
0010010HEX_S3[0]
0010100HEX_N3[0]
0011000LH[6]
0100001OUT_FAN[4]
0100010OMUX_NW10
0100100HEX_W6[0]
0101000HEX_W6_N[8]
1000001OUT_FAN[3]
1000010LH[18]
1000100HEX_N7[9]
1001000HEX_S6[2]
virtex2 INT_CNR switchbox INT muxes HEX_W0[1]
BitsDestination
MAIN[21][12]MAIN[20][15]MAIN[21][14]MAIN[18][13]MAIN[19][15]MAIN[18][15]MAIN[19][13]HEX_W0[1]
Source
0000000off
0010001OMUX[2]
0010010OUT_FAN[5]
0010100HEX_W6[1]
0011000HEX_W6_N[9]
0100001LH[0]
0100010OMUX_W1
0100100HEX_S3[1]
0101000HEX_N3[1]
1000001OUT_FAN[2]
1000010LH[12]
1000100HEX_N6[0]
1001000HEX_S6[3]
virtex2 INT_CNR switchbox INT muxes HEX_W0[2]
BitsDestination
MAIN[20][22]MAIN[20][21]MAIN[20][20]MAIN[19][22]MAIN[18][20]MAIN[18][22]MAIN[19][20]HEX_W0[2]
Source
0000000off
0010001OMUX[4]
0010010LH[18]
0010100HEX_S6[4]
0011000HEX_N6[1]
0100001OMUX[6]
0100010HEX_S3[2]
0100100LH[6]
0101000HEX_N3[2]
1000001OUT_FAN[3]
1000010OMUX_WN14
1000100HEX_W6[0]
1001000HEX_W6[2]
virtex2 INT_CNR switchbox INT muxes HEX_W0[3]
BitsDestination
MAIN[21][28]MAIN[20][31]MAIN[21][30]MAIN[19][31]MAIN[18][29]MAIN[18][31]MAIN[19][29]HEX_W0[3]
Source
0000000off
0010001OMUX_W6
0010010OUT_FAN[2]
0010100HEX_W6[1]
0011000HEX_W6[3]
0100001LH[0]
0100010OMUX_NW10
0100100HEX_N3[3]
0101000HEX_S3[3]
1000001OUT_FAN[4]
1000010LH[12]
1000100HEX_S6[5]
1001000HEX_N6[2]
virtex2 INT_CNR switchbox INT muxes HEX_W0[4]
BitsDestination
MAIN[20][36]MAIN[20][38]MAIN[20][37]MAIN[19][38]MAIN[18][36]MAIN[18][38]MAIN[19][36]HEX_W0[4]
Source
0000000off
0010001OMUX_WS1
0010010HEX_S3[4]
0010100LH[6]
0011000HEX_N3[4]
0100001OUT_FAN[6]
0100010OMUX_N12
0100100HEX_W6[2]
0101000HEX_W6[4]
1000001OUT_FAN[5]
1000010LH[18]
1000100HEX_S6[6]
1001000HEX_N6[3]
virtex2 INT_CNR switchbox INT muxes HEX_W0[5]
BitsDestination
MAIN[21][44]MAIN[20][47]MAIN[21][46]MAIN[19][47]MAIN[18][45]MAIN[18][47]MAIN[19][45]HEX_W0[5]
Source
0000000off
0010001OMUX_S3
0010010OUT_FAN[7]
0010100HEX_W6[3]
0011000HEX_W6[5]
0100001LH[0]
0100010OMUX_WN14
0100100HEX_N3[5]
0101000HEX_S3[5]
1000001OUT_FAN[1]
1000010LH[12]
1000100HEX_S6[7]
1001000HEX_N6[4]
virtex2 INT_CNR switchbox INT muxes HEX_W0[6]
BitsDestination
MAIN[20][52]MAIN[20][53]MAIN[20][54]MAIN[19][54]MAIN[18][52]MAIN[18][54]MAIN[19][52]HEX_W0[6]
Source
0000000off
0010001OMUX[11]
0010010OMUX_W9
0010100HEX_W6[4]
0011000HEX_W6[6]
0100001OMUX_SW5
0100010HEX_S3[6]
0100100LH[6]
0101000HEX_N3[6]
1000001OUT_FAN[0]
1000010LH[18]
1000100HEX_S6[8]
1001000HEX_N6[5]
virtex2 INT_CNR switchbox INT muxes HEX_W0[7]
BitsDestination
MAIN[21][60]MAIN[21][62]MAIN[20][63]MAIN[19][63]MAIN[18][61]MAIN[19][61]MAIN[18][63]HEX_W0[7]
Source
0000000off
0010001OMUX[9]
0010010LH[0]
0010100HEX_N3[7]
0011000HEX_S3[7]
0100001OUT_FAN[1]
0100010OMUX_WS1
0100100HEX_W6[5]
0101000HEX_W6[7]
1000001LH[12]
1000010OUT_FAN[6]
1000100HEX_S6[9]
1001000HEX_N6[6]
virtex2 INT_CNR switchbox INT muxes HEX_W0[8]
BitsDestination
MAIN[20][68]MAIN[20][69]MAIN[20][70]MAIN[19][70]MAIN[18][68]MAIN[19][68]MAIN[18][70]HEX_W0[8]
Source
0000000off
0010001OMUX[13]
0010010OUT_FAN[0]
0010100HEX_W6[6]
0011000HEX_W6[8]
0100001HEX_S3[8]
0100010OMUX_W14
0100100LH[6]
0101000HEX_N3[8]
1000001LH[18]
1000010OUT_FAN[7]
1000100HEX_S7[0]
1001000HEX_N6[7]
virtex2 INT_CNR switchbox INT muxes HEX_W0[9]
BitsDestination
MAIN[21][78]MAIN[21][76]MAIN[20][79]MAIN[19][79]MAIN[18][77]MAIN[19][77]MAIN[18][79]HEX_W0[9]
Source
0000000off
0010001OMUX[13]
0010010LH[0]
0010100HEX_N3[9]
0011000HEX_S3[9]
0100001LH[12]
0100010OMUX[15]
0100100HEX_S7[1]
0101000HEX_N6[8]
1000001OMUX_S0
1000010OMUX_SW5
1000100HEX_W6[7]
1001000HEX_W6[9]
virtex2 INT_CNR switchbox INT muxes HEX_E0[0]
BitsDestination
MAIN[21][4]MAIN[21][6]MAIN[20][7]MAIN[19][7]MAIN[18][5]MAIN[19][5]MAIN[18][7]HEX_E0[0]
Source
0000000off
0010001OMUX_E2
0010010LH[6]
0010100HEX_N3[0]
0011000HEX_S3[0]
0100001OUT_FAN[4]
0100010OMUX_EN8
0100100HEX_E6[0]
0101000HEX_E6[2]
1000001LH[18]
1000010OUT_FAN[3]
1000100HEX_S6[2]
1001000HEX_N7[9]
virtex2 INT_CNR switchbox INT muxes HEX_E0[1]
BitsDestination
MAIN[20][12]MAIN[20][13]MAIN[20][14]MAIN[19][14]MAIN[18][12]MAIN[19][12]MAIN[18][14]HEX_E0[1]
Source
0000000off
0010001OMUX_S4
0010010OUT_FAN[5]
0010100HEX_E6[1]
0011000HEX_E6[3]
0100001HEX_S3[1]
0100010OMUX_N10
0100100LH[0]
0101000HEX_N3[1]
1000001LH[12]
1000010OUT_FAN[2]
1000100HEX_S6[3]
1001000HEX_N6[0]
virtex2 INT_CNR switchbox INT muxes HEX_E0[2]
BitsDestination
MAIN[21][22]MAIN[20][23]MAIN[21][20]MAIN[19][23]MAIN[18][21]MAIN[18][23]MAIN[19][21]HEX_E0[2]
Source
0000000off
0010001OMUX[4]
0010010LH[18]
0010100HEX_S6[4]
0011000HEX_N6[1]
0100001LH[6]
0100010OMUX[6]
0100100HEX_N3[2]
0101000HEX_S3[2]
1000001OMUX_NE12
1000010OUT_FAN[3]
1000100HEX_E6[2]
1001000HEX_E6[4]
virtex2 INT_CNR switchbox INT muxes HEX_E0[3]
BitsDestination
MAIN[20][28]MAIN[20][29]MAIN[20][30]MAIN[19][30]MAIN[18][28]MAIN[19][28]MAIN[18][30]HEX_E0[3]
Source
0000000off
0010001OMUX_SE3
0010010OUT_FAN[2]
0010100HEX_E6[3]
0011000HEX_E6[5]
0100001HEX_S3[3]
0100010OMUX_EN8
0100100LH[0]
0101000HEX_N3[3]
1000001LH[12]
1000010OUT_FAN[4]
1000100HEX_S6[5]
1001000HEX_N6[2]
virtex2 INT_CNR switchbox INT muxes HEX_E0[4]
BitsDestination
MAIN[21][36]MAIN[20][39]MAIN[21][38]MAIN[19][39]MAIN[18][37]MAIN[18][39]MAIN[19][37]HEX_E0[4]
Source
0000000off
0010001OMUX_E7
0010010OUT_FAN[6]
0010100HEX_E6[4]
0011000HEX_E6[6]
0100001LH[6]
0100010OMUX_E8
0100100HEX_N3[4]
0101000HEX_S3[4]
1000001OUT_FAN[5]
1000010LH[18]
1000100HEX_S6[6]
1001000HEX_N6[3]
virtex2 INT_CNR switchbox INT muxes HEX_E0[5]
BitsDestination
MAIN[20][44]MAIN[20][45]MAIN[20][46]MAIN[19][46]MAIN[18][44]MAIN[19][44]MAIN[18][46]HEX_E0[5]
Source
0000000off
0010001OMUX_ES7
0010010OUT_FAN[7]
0010100HEX_E6[5]
0011000HEX_E6[7]
0100001HEX_S3[5]
0100010OMUX_NE12
0100100LH[0]
0101000HEX_N3[5]
1000001LH[12]
1000010OUT_FAN[1]
1000100HEX_S6[7]
1001000HEX_N6[4]
virtex2 INT_CNR switchbox INT muxes HEX_E0[6]
BitsDestination
MAIN[21][52]MAIN[20][55]MAIN[21][54]MAIN[19][55]MAIN[18][53]MAIN[18][55]MAIN[19][53]HEX_E0[6]
Source
0000000off
0010001OMUX[9]
0010010OMUX[11]
0010100HEX_E6[6]
0011000HEX_E6[8]
0100001LH[6]
0100010OMUX_SE3
0100100HEX_N3[6]
0101000HEX_S3[6]
1000001OUT_FAN[0]
1000010LH[18]
1000100HEX_S6[8]
1001000HEX_N6[5]
virtex2 INT_CNR switchbox INT muxes HEX_E0[7]
BitsDestination
MAIN[20][60]MAIN[20][61]MAIN[20][62]MAIN[19][62]MAIN[18][60]MAIN[19][60]MAIN[18][62]HEX_E0[7]
Source
0000000off
0010001OMUX_S5
0010010OUT_FAN[1]
0010100HEX_E6[7]
0011000HEX_E6[9]
0100001HEX_S3[7]
0100010OMUX_N11
0100100LH[0]
0101000HEX_N3[7]
1000001LH[12]
1000010OUT_FAN[6]
1000100HEX_S6[9]
1001000HEX_N6[6]
virtex2 INT_CNR switchbox INT muxes HEX_E0[8]
BitsDestination
MAIN[21][68]MAIN[21][70]MAIN[20][71]MAIN[19][71]MAIN[18][69]MAIN[19][69]MAIN[18][71]HEX_E0[8]
Source
0000000off
0010001OMUX_ES7
0010010LH[6]
0010100HEX_N3[8]
0011000HEX_S3[8]
0100001OUT_FAN[0]
0100010OMUX_E13
0100100HEX_E6[8]
0101000HEX_E6_S[0]
1000001LH[18]
1000010OUT_FAN[7]
1000100HEX_S7[0]
1001000HEX_N6[7]
virtex2 INT_CNR switchbox INT muxes HEX_E0[9]
BitsDestination
MAIN[20][77]MAIN[20][78]MAIN[20][76]MAIN[19][78]MAIN[18][76]MAIN[18][78]MAIN[19][76]HEX_E0[9]
Source
0000000off
0010001OMUX[15]
0010010LH[12]
0010100HEX_S7[1]
0011000HEX_N6[8]
0100001OMUX_S0
0100010OMUX_S2
0100100HEX_E6[9]
0101000HEX_E6_S[1]
1000001OMUX_N15
1000010HEX_S3[9]
1000100LH[0]
1001000HEX_N3[9]
virtex2 INT_CNR switchbox INT muxes HEX_S0[0]
BitsDestination
MAIN[20][3]MAIN[21][2]MAIN[21][0]MAIN[19][3]MAIN[18][1]MAIN[18][3]MAIN[19][1]HEX_S0[0]
Source
0000000off
0010001OMUX[0]
0010010LV[0]
0010100HEX_E6[1]
0011000HEX_W6_N[8]
0100001OMUX[2]
0100010OUT_FAN[3]
0100100HEX_S6[0]
0101000HEX_S6[2]
1000001LV[12]
1000010OMUX_S0
1000100HEX_W3[0]
1001000HEX_E3[0]
virtex2 INT_CNR switchbox INT muxes HEX_S0[1]
BitsDestination
MAIN[20][8]MAIN[20][9]MAIN[20][10]MAIN[18][8]MAIN[19][10]MAIN[19][8]MAIN[18][10]HEX_S0[1]
Source
0000000off
0010001OMUX[2]
0010010OUT_FAN[2]
0010100HEX_S6[3]
0011000HEX_S6[1]
0100001HEX_E3[1]
0100010OMUX_E2
0100100HEX_W3[1]
0101000LV[18]
1000001LV[6]
1000010OUT_FAN[4]
1000100HEX_W6_N[9]
1001000HEX_E6[2]
virtex2 INT_CNR switchbox INT muxes HEX_S0[2]
BitsDestination
MAIN[21][16]MAIN[20][19]MAIN[21][18]MAIN[19][19]MAIN[18][17]MAIN[19][17]MAIN[18][19]HEX_S0[2]
Source
0000000off
0010001OMUX[4]
0010010OMUX_S4
0010100HEX_S6[2]
0011000HEX_S6[4]
0100001OMUX[6]
0100010LV[12]
0100100HEX_W3[2]
0101000HEX_E3[2]
1000001LV[0]
1000010OUT_FAN[5]
1000100HEX_E6[3]
1001000HEX_W6[0]
virtex2 INT_CNR switchbox INT muxes HEX_S0[3]
BitsDestination
MAIN[20][24]MAIN[20][26]MAIN[20][25]MAIN[18][24]MAIN[19][26]MAIN[18][26]MAIN[19][24]HEX_S0[3]
Source
0000000off
0010001OMUX[6]
0010010HEX_E3[3]
0010100HEX_W3[3]
0011000LV[18]
0100001OUT_FAN[4]
0100010OMUX_W6
0100100HEX_S6[5]
0101000HEX_S6[3]
1000001OUT_FAN[3]
1000010LV[6]
1000100HEX_W6[1]
1001000HEX_E6[4]
virtex2 INT_CNR switchbox INT muxes HEX_S0[4]
BitsDestination
MAIN[21][32]MAIN[21][34]MAIN[20][35]MAIN[19][35]MAIN[18][33]MAIN[19][33]MAIN[18][35]HEX_S0[4]
Source
0000000off
0010001OMUX_WS1
0010010LV[12]
0010100HEX_W3[4]
0011000HEX_E3[4]
0100001OUT_FAN[5]
0100010OMUX_SE3
0100100HEX_S6[4]
0101000HEX_S6[6]
1000001LV[0]
1000010OUT_FAN[2]
1000100HEX_E6[5]
1001000HEX_W6[2]
virtex2 INT_CNR switchbox INT muxes HEX_S0[5]
BitsDestination
MAIN[20][40]MAIN[20][41]MAIN[20][42]MAIN[18][40]MAIN[19][42]MAIN[19][40]MAIN[18][42]HEX_S0[5]
Source
0000000off
0010001OMUX_S3
0010010OUT_FAN[1]
0010100HEX_S6[7]
0011000HEX_S6[5]
0100001HEX_E3[5]
0100010OMUX_E8
0100100HEX_W3[5]
0101000LV[18]
1000001LV[6]
1000010OUT_FAN[6]
1000100HEX_W6[3]
1001000HEX_E6[6]
virtex2 INT_CNR switchbox INT muxes HEX_S0[6]
BitsDestination
MAIN[21][48]MAIN[21][50]MAIN[20][51]MAIN[19][51]MAIN[18][49]MAIN[19][49]MAIN[18][51]HEX_S0[6]
Source
0000000off
0010001OMUX_SW5
0010010LV[12]
0010100HEX_W3[6]
0011000HEX_E3[6]
0100001OUT_FAN[0]
0100010OMUX_ES7
0100100HEX_S6[6]
0101000HEX_S6[8]
1000001LV[0]
1000010OUT_FAN[7]
1000100HEX_E6[7]
1001000HEX_W6[4]
virtex2 INT_CNR switchbox INT muxes HEX_S0[7]
BitsDestination
MAIN[20][57]MAIN[20][58]MAIN[20][56]MAIN[18][56]MAIN[19][58]MAIN[18][58]MAIN[19][56]HEX_S0[7]
Source
0000000off
0010001OMUX[11]
0010010LV[6]
0010100HEX_W6[5]
0011000HEX_E6[8]
0100001OUT_FAN[6]
0100010OMUX_WS1
0100100HEX_S6[9]
0101000HEX_S6[7]
1000001OMUX_SE3
1000010HEX_E3[7]
1000100HEX_W3[7]
1001000LV[18]
virtex2 INT_CNR switchbox INT muxes HEX_S0[8]
BitsDestination
MAIN[21][64]MAIN[20][67]MAIN[21][66]MAIN[19][67]MAIN[18][65]MAIN[18][67]MAIN[19][65]HEX_S0[8]
Source
0000000off
0010001OMUX_S5
0010010OUT_FAN[7]
0010100HEX_S6[8]
0011000HEX_S7[0]
0100001LV[12]
0100010OMUX_W14
0100100HEX_W3[8]
0101000HEX_E3[8]
1000001OUT_FAN[1]
1000010LV[0]
1000100HEX_E6[9]
1001000HEX_W6[6]
virtex2 INT_CNR switchbox INT muxes HEX_S0[9]
BitsDestination
MAIN[20][72]MAIN[20][73]MAIN[20][74]MAIN[18][72]MAIN[19][74]MAIN[18][74]MAIN[19][72]HEX_S0[9]
Source
0000000off
0010001OMUX[15]
0010010OMUX_SW5
0010100HEX_S7[1]
0011000HEX_S6[9]
0100001OMUX_ES7
0100010HEX_E3[9]
0100100HEX_W3[9]
0101000LV[18]
1000001OUT_FAN[0]
1000010LV[6]
1000100HEX_W6[7]
1001000HEX_E6_S[0]
virtex2 INT_CNR switchbox INT muxes HEX_N0[0]
BitsDestination
MAIN[20][1]MAIN[20][2]MAIN[20][0]MAIN[18][0]MAIN[19][2]MAIN[18][2]MAIN[19][0]HEX_N0[0]
Source
0000000off
0010001OMUX[0]
0010010LV[0]
0010100HEX_W6_N[8]
0011000HEX_E6[1]
0100001OUT_FAN[3]
0100010OMUX_EN8
0100100HEX_N6[0]
0101000HEX_N7[8]
1000001OMUX_N13
1000010HEX_E3[0]
1000100HEX_W3[0]
1001000LV[12]
virtex2 INT_CNR switchbox INT muxes HEX_N0[1]
BitsDestination
MAIN[21][8]MAIN[21][10]MAIN[20][11]MAIN[19][11]MAIN[18][9]MAIN[19][9]MAIN[18][11]HEX_N0[1]
Source
0000000off
0010001OMUX_N10
0010010LV[18]
0010100HEX_W3[1]
0011000HEX_E3[1]
0100001OUT_FAN[2]
0100010OMUX_NW10
0100100HEX_N7[9]
0101000HEX_N6[1]
1000001LV[6]
1000010OUT_FAN[4]
1000100HEX_E6[2]
1001000HEX_W6_N[9]
virtex2 INT_CNR switchbox INT muxes HEX_N0[2]
BitsDestination
MAIN[20][16]MAIN[20][17]MAIN[20][18]MAIN[18][16]MAIN[19][18]MAIN[18][18]MAIN[19][16]HEX_N0[2]
Source
0000000off
0010001OMUX[4]
0010010OMUX_NE12
0010100HEX_N6[2]
0011000HEX_N6[0]
0100001OMUX_W1
0100010HEX_E3[2]
0100100HEX_W3[2]
0101000LV[12]
1000001OUT_FAN[5]
1000010LV[0]
1000100HEX_W6[0]
1001000HEX_E6[3]
virtex2 INT_CNR switchbox INT muxes HEX_N0[3]
BitsDestination
MAIN[21][24]MAIN[21][26]MAIN[20][27]MAIN[19][27]MAIN[18][25]MAIN[19][25]MAIN[18][27]HEX_N0[3]
Source
0000000off
0010001OMUX_EN8
0010010LV[18]
0010100HEX_W3[3]
0011000HEX_E3[3]
0100001OUT_FAN[4]
0100010OMUX_WN14
0100100HEX_N6[1]
0101000HEX_N6[3]
1000001LV[6]
1000010OUT_FAN[3]
1000100HEX_E6[4]
1001000HEX_W6[1]
virtex2 INT_CNR switchbox INT muxes HEX_N0[4]
BitsDestination
MAIN[20][32]MAIN[20][33]MAIN[20][34]MAIN[18][32]MAIN[19][34]MAIN[19][32]MAIN[18][34]HEX_N0[4]
Source
0000000off
0010001OMUX_E7
0010010OUT_FAN[5]
0010100HEX_N6[4]
0011000HEX_N6[2]
0100001HEX_E3[4]
0100010OMUX_NW10
0100100HEX_W3[4]
0101000LV[12]
1000001LV[0]
1000010OUT_FAN[2]
1000100HEX_W6[2]
1001000HEX_E6[5]
virtex2 INT_CNR switchbox INT muxes HEX_N0[5]
BitsDestination
MAIN[21][40]MAIN[20][43]MAIN[21][42]MAIN[19][43]MAIN[18][41]MAIN[18][43]MAIN[19][41]HEX_N0[5]
Source
0000000off
0010001OMUX_N12
0010010OUT_FAN[1]
0010100HEX_N6[3]
0011000HEX_N6[5]
0100001LV[18]
0100010OMUX_NE12
0100100HEX_W3[5]
0101000HEX_E3[5]
1000001OUT_FAN[6]
1000010LV[6]
1000100HEX_E6[6]
1001000HEX_W6[3]
virtex2 INT_CNR switchbox INT muxes HEX_N0[6]
BitsDestination
MAIN[20][48]MAIN[20][49]MAIN[20][50]MAIN[18][48]MAIN[19][50]MAIN[19][48]MAIN[18][50]HEX_N0[6]
Source
0000000off
0010001OMUX[9]
0010010OUT_FAN[0]
0010100HEX_N6[6]
0011000HEX_N6[4]
0100001HEX_E3[6]
0100010OMUX_WN14
0100100HEX_W3[6]
0101000LV[12]
1000001LV[0]
1000010OUT_FAN[7]
1000100HEX_W6[4]
1001000HEX_E6[7]
virtex2 INT_CNR switchbox INT muxes HEX_N0[7]
BitsDestination
MAIN[20][59]MAIN[21][58]MAIN[21][56]MAIN[19][59]MAIN[18][57]MAIN[18][59]MAIN[19][57]HEX_N0[7]
Source
0000000off
0010001OMUX[11]
0010010LV[6]
0010100HEX_E6[8]
0011000HEX_W6[5]
0100001OMUX_W9
0100010OUT_FAN[6]
0100100HEX_N6[5]
0101000HEX_N6[7]
1000001LV[18]
1000010OMUX_N11
1000100HEX_W3[7]
1001000HEX_E3[7]
virtex2 INT_CNR switchbox INT muxes HEX_N0[8]
BitsDestination
MAIN[20][64]MAIN[20][66]MAIN[20][65]MAIN[18][64]MAIN[19][66]MAIN[18][66]MAIN[19][64]HEX_N0[8]
Source
0000000off
0010001OMUX[9]
0010010HEX_E3[8]
0010100HEX_W3[8]
0011000LV[12]
0100001OUT_FAN[7]
0100010OMUX_E13
0100100HEX_N6[8]
0101000HEX_N6[6]
1000001OUT_FAN[1]
1000010LV[0]
1000100HEX_W6[6]
1001000HEX_E6[9]
virtex2 INT_CNR switchbox INT muxes HEX_N0[9]
BitsDestination
MAIN[21][72]MAIN[20][75]MAIN[21][74]MAIN[19][75]MAIN[18][73]MAIN[18][75]MAIN[19][73]HEX_N0[9]
Source
0000000off
0010001OMUX[13]
0010010OMUX[15]
0010100HEX_N6[7]
0011000HEX_N6[9]
0100001LV[18]
0100010OMUX_N15
0100100HEX_W3[9]
0101000HEX_E3[9]
1000001OUT_FAN[0]
1000010LV[6]
1000100HEX_E6_S[0]
1001000HEX_W6[7]
virtex2 INT_CNR switchbox INT muxes LH[0]
BitsDestination
MAIN[21][47]MAIN[21][49]MAIN[21][51]LH[0]
Source
000off
001DBL_W1[5]
011OMUX_S4
101DBL_E1[6]
111OMUX[11]
virtex2 INT_CNR switchbox INT muxes LH[6]
BitsDestination
MAIN[21][31]MAIN[21][33]MAIN[21][29]LH[6]
Source
000off
001OMUX[4]
011OMUX_N15
101DBL_E1[4]
111DBL_W1[3]
virtex2 INT_CNR switchbox INT muxes LH[12]
BitsDestination
MAIN[21][41]MAIN[21][45]MAIN[21][43]LH[12]
Source
000off
001DBL_W1[5]
011OMUX_S4
101DBL_E1[6]
111OMUX[11]
virtex2 INT_CNR switchbox INT muxes LH[18]
BitsDestination
MAIN[21][39]MAIN[21][37]MAIN[21][35]LH[18]
Source
000off
001OMUX[4]
011OMUX_N15
101DBL_E1[4]
111DBL_W1[3]
virtex2 INT_CNR switchbox INT muxes LV[0]
BitsDestination
MAIN[21][7]MAIN[21][9]MAIN[21][19]MAIN[21][25]MAIN[21][21]MAIN[21][11]MAIN[21][5]LV[0]
Source
0000000off
0000011HEX_E1[1]
0000101OMUX_E2
0001001DBL_W1[1]
0010001HEX_E6[1]
0100001HEX_E4[1]
1000011OMUX[0]
1000101HEX_E2[1]
1001001HEX_E5[1]
1010001DBL_E1[2]
1100001HEX_E3[1]
virtex2 INT_CNR switchbox INT muxes LV[6]
BitsDestination
MAIN[21][73]MAIN[21][61]MAIN[21][55]MAIN[21][69]MAIN[21][71]MAIN[21][65]MAIN[21][75]LV[6]
Source
0000000off
0000011OMUX_W9
0000101DBL_W1[7]
0001001HEX_W5[7]
0010001HEX_W3[7]
0100001HEX_W4[7]
1000011OMUX[15]
1000101HEX_W2[7]
1001001DBL_E1[8]
1010001HEX_W0[7]
1100001HEX_W1[7]
virtex2 INT_CNR switchbox INT muxes LV[12]
BitsDestination
MAIN[21][13]MAIN[21][1]MAIN[21][27]MAIN[21][23]MAIN[21][17]MAIN[21][3]MAIN[21][15]LV[12]
Source
0000000off
0000011HEX_E1[1]
0000101OMUX_E2
0001001DBL_W1[1]
0010001HEX_E6[1]
0100001HEX_E4[1]
1000011OMUX[0]
1000101HEX_E2[1]
1001001HEX_E5[1]
1010001DBL_E1[2]
1100001HEX_E3[1]
virtex2 INT_CNR switchbox INT muxes LV[18]
BitsDestination
MAIN[21][67]MAIN[21][53]MAIN[21][57]MAIN[21][77]MAIN[21][59]MAIN[21][79]MAIN[21][63]LV[18]
Source
0000000off
0000011OMUX_W9
0000101DBL_W1[7]
0001001HEX_W5[7]
0010001HEX_W3[7]
0100001HEX_W4[7]
1000011OMUX[15]
1000101HEX_W2[7]
1001001DBL_E1[8]
1010001HEX_W0[7]
1100001HEX_W1[7]
virtex2 INT_CNR switchbox INT muxes IMUX_CLK[0]
BitsDestination
MAIN[5][41]MAIN[5][42]MAIN[5][40]MAIN[4][42]MAIN[5][49]MAIN[4][47]MAIN[4][43]MAIN[5][45]MAIN[4][45]MAIN[5][43]IMUX_CLK[0]
Source
0000000000PULLUP
0001000001GCLK[0]
0001000010GCLK[1]
0001000100GCLK[2]
0001001000HEX_N0[6]
0001010000HEX_N3[6]
0001100000HEX_S4[6]
0010000001GCLK[3]
0010000010HEX_S3[6]
0010000100GCLK[4]
0010001000HEX_S6[6]
0010010000HEX_N1[6]
0010100000HEX_N4[6]
0100000001GCLK[5]
0100000010HEX_N2[6]
0100000100HEX_N5[6]
0100001000GCLK[6]
0100010000HEX_S5[6]
0100100000HEX_S2[6]
1000000001GCLK[7]
1000000010DBL_W1[5]
1000000100DBL_E0[5]
1000001000DBL_E1[5]
1000010000DBL_W2[5]
1000100000HEX_S1[6]
virtex2 INT_CNR switchbox INT muxes IMUX_CLK[1]
BitsDestination
MAIN[5][47]MAIN[5][48]MAIN[5][50]MAIN[4][48]MAIN[4][50]MAIN[4][46]MAIN[4][44]MAIN[5][46]MAIN[5][44]MAIN[4][40]IMUX_CLK[1]
Source
0000000000PULLUP
0001000001GCLK[0]
0001000010GCLK[1]
0001000100GCLK[2]
0001001000HEX_N0[6]
0001010000HEX_N3[6]
0001100000HEX_S4[6]
0010000001GCLK[3]
0010000010HEX_S3[6]
0010000100GCLK[4]
0010001000HEX_S6[6]
0010010000HEX_N1[6]
0010100000HEX_N4[6]
0100000001GCLK[5]
0100000010HEX_N2[6]
0100000100HEX_N5[6]
0100001000GCLK[6]
0100010000HEX_S5[6]
0100100000HEX_S2[6]
1000000001GCLK[7]
1000000010DBL_W1[5]
1000000100DBL_E0[5]
1000001000DBL_E1[5]
1000010000DBL_W2[5]
1000100000HEX_S1[6]
virtex2 INT_CNR switchbox INT muxes IMUX_CLK[2]
BitsDestination
MAIN[5][54]MAIN[5][53]MAIN[5][51]MAIN[4][53]MAIN[4][51]MAIN[4][55]MAIN[4][57]MAIN[5][55]MAIN[5][57]MAIN[4][61]IMUX_CLK[2]
Source
0000000000PULLUP
0001000001GCLK[0]
0001000010GCLK[1]
0001000100GCLK[2]
0001001000HEX_N0[6]
0001010000HEX_N3[6]
0001100000HEX_S4[6]
0010000001GCLK[3]
0010000010HEX_S3[6]
0010000100GCLK[4]
0010001000HEX_S6[6]
0010010000HEX_N1[6]
0010100000HEX_N4[6]
0100000001GCLK[5]
0100000010HEX_N2[6]
0100000100HEX_N5[6]
0100001000GCLK[6]
0100010000HEX_S5[6]
0100100000HEX_S2[6]
1000000001GCLK[7]
1000000010DBL_W2[6]
1000000100DBL_E0[6]
1000001000DBL_E1[6]
1000010000DBL_W1[6]
1000100000HEX_S1[6]
virtex2 INT_CNR switchbox INT muxes IMUX_CLK[3]
BitsDestination
MAIN[5][60]MAIN[5][59]MAIN[5][61]MAIN[4][59]MAIN[5][52]MAIN[4][54]MAIN[4][58]MAIN[5][56]MAIN[4][56]MAIN[5][58]IMUX_CLK[3]
Source
0000000000PULLUP
0001000001GCLK[0]
0001000010GCLK[1]
0001000100GCLK[2]
0001001000HEX_N0[6]
0001010000HEX_N3[6]
0001100000HEX_S4[6]
0010000001GCLK[3]
0010000010HEX_S3[6]
0010000100GCLK[4]
0010001000HEX_S6[6]
0010010000HEX_N1[6]
0010100000HEX_N4[6]
0100000001GCLK[5]
0100000010HEX_N2[6]
0100000100HEX_N5[6]
0100001000GCLK[6]
0100010000HEX_S5[6]
0100100000HEX_S2[6]
1000000001GCLK[7]
1000000010DBL_W2[6]
1000000100DBL_E0[6]
1000001000DBL_E1[6]
1000010000DBL_W1[6]
1000100000HEX_S1[6]
virtex2 INT_CNR switchbox INT muxes IMUX_SR[0]
BitsDestination
MAIN[5][3]MAIN[4][3]MAIN[5][5]MAIN[4][5]MAIN[5][1]MAIN[5][2]MAIN[4][2]MAIN[5][0]IMUX_SR[0]
Source
00000000PULLUP
00010001DBL_W1[0]
00010010HEX_N1[0]
00010100HEX_N5[0]
00011000HEX_S4[0]
00100001DBL_W2[0]
00100010HEX_S5[0]
00100100HEX_S1[0]
00101000HEX_N3[0]
01000001HEX_N2[0]
01000010DBL_E0[0]
01000100HEX_S2[0]
01001000HEX_N0[0]
10000001HEX_S3[0]
10000010DBL_E1[0]
10000100HEX_N4[0]
10001000HEX_S6[0]
virtex2 INT_CNR switchbox INT muxes IMUX_SR[1]
BitsDestination
MAIN[4][12]MAIN[5][12]MAIN[5][14]MAIN[4][14]MAIN[5][16]MAIN[5][15]MAIN[5][17]MAIN[4][15]IMUX_SR[1]
Source
00000000PULLUP
00010001DBL_W1[1]
00010010HEX_N2[0]
00010100HEX_S2[0]
00011000HEX_N0[0]
00100001DBL_W2[1]
00100010HEX_S3[0]
00100100HEX_N4[0]
00101000HEX_S6[0]
01000001HEX_S5[0]
01000010DBL_E0[1]
01000100HEX_S1[0]
01001000HEX_N3[0]
10000001HEX_N1[0]
10000010DBL_E1[1]
10000100HEX_N5[0]
10001000HEX_S4[0]
virtex2 INT_CNR switchbox INT muxes IMUX_SR[2]
BitsDestination
MAIN[4][0]MAIN[4][4]MAIN[4][8]MAIN[5][4]MAIN[5][7]MAIN[5][8]MAIN[4][6]MAIN[5][6]IMUX_SR[2]
Source
00000000PULLUP
00010001DBL_W1[0]
00010010HEX_N1[0]
00010100HEX_N5[0]
00011000HEX_S4[0]
00100001DBL_W2[0]
00100010HEX_S5[0]
00100100HEX_S1[0]
00101000HEX_N3[0]
01000001HEX_N2[0]
01000010DBL_E0[0]
01000100HEX_S2[0]
01001000HEX_N0[0]
10000001HEX_S3[0]
10000010DBL_E1[0]
10000100HEX_N4[0]
10001000HEX_S6[0]
virtex2 INT_CNR switchbox INT muxes IMUX_SR[3]
BitsDestination
MAIN[5][13]MAIN[4][9]MAIN[4][17]MAIN[4][13]MAIN[5][10]MAIN[5][9]MAIN[5][11]MAIN[4][11]IMUX_SR[3]
Source
00000000PULLUP
00010001DBL_W1[1]
00010010HEX_N2[0]
00010100HEX_S2[0]
00011000HEX_N0[0]
00100001DBL_W2[1]
00100010HEX_S3[0]
00100100HEX_N4[0]
00101000HEX_S6[0]
01000001HEX_S5[0]
01000010DBL_E0[1]
01000100HEX_S1[0]
01001000HEX_N3[0]
10000001HEX_N1[0]
10000010DBL_E1[1]
10000100HEX_N5[0]
10001000HEX_S4[0]
virtex2 INT_CNR switchbox INT muxes IMUX_CE[0]
BitsDestination
MAIN[5][65]MAIN[4][65]MAIN[5][67]MAIN[4][67]MAIN[5][63]MAIN[5][64]MAIN[4][64]MAIN[5][62]IMUX_CE[0]
Source
00000000PULLUP
00010001DBL_W1[8]
00010010HEX_N0[9]
00010100HEX_N2[9]
00011000HEX_N3[9]
00100001DBL_W2[8]
00100010HEX_S6[9]
00100100HEX_S4[9]
00101000HEX_S3[9]
01000001HEX_S1[9]
01000010DBL_E0[8]
01000100HEX_S2[9]
01001000HEX_S5[9]
10000001HEX_N5[9]
10000010DBL_E1[8]
10000100HEX_N4[9]
10001000HEX_N1[9]
virtex2 INT_CNR switchbox INT muxes IMUX_CE[1]
BitsDestination
MAIN[4][62]MAIN[4][66]MAIN[4][70]MAIN[5][66]MAIN[5][69]MAIN[5][70]MAIN[4][68]MAIN[5][68]IMUX_CE[1]
Source
00000000PULLUP
00010001DBL_W1[8]
00010010HEX_N0[9]
00010100HEX_N2[9]
00011000HEX_N3[9]
00100001DBL_W2[8]
00100010HEX_S6[9]
00100100HEX_S4[9]
00101000HEX_S3[9]
01000001HEX_S1[9]
01000010DBL_E0[8]
01000100HEX_S2[9]
01001000HEX_S5[9]
10000001HEX_N5[9]
10000010DBL_E1[8]
10000100HEX_N4[9]
10001000HEX_N1[9]
virtex2 INT_CNR switchbox INT muxes IMUX_CE[2]
BitsDestination
MAIN[5][75]MAIN[4][71]MAIN[4][79]MAIN[4][75]MAIN[5][72]MAIN[5][71]MAIN[5][73]MAIN[4][73]IMUX_CE[2]
Source
00000000PULLUP
00010001DBL_W1[9]
00010010HEX_S1[9]
00010100HEX_S2[9]
00011000HEX_S5[9]
00100001DBL_W2[9]
00100010HEX_N5[9]
00100100HEX_N4[9]
00101000HEX_N1[9]
01000001HEX_S6[9]
01000010DBL_E0[9]
01000100HEX_S4[9]
01001000HEX_S3[9]
10000001HEX_N0[9]
10000010DBL_E1[9]
10000100HEX_N2[9]
10001000HEX_N3[9]
virtex2 INT_CNR switchbox INT muxes IMUX_CE[3]
BitsDestination
MAIN[4][74]MAIN[5][74]MAIN[5][76]MAIN[4][76]MAIN[5][78]MAIN[5][77]MAIN[5][79]MAIN[4][77]IMUX_CE[3]
Source
00000000PULLUP
00010001DBL_W1[9]
00010010HEX_S1[9]
00010100HEX_S2[9]
00011000HEX_S5[9]
00100001DBL_W2[9]
00100010HEX_N5[9]
00100100HEX_N4[9]
00101000HEX_N1[9]
01000001HEX_S6[9]
01000010DBL_E0[9]
01000100HEX_S4[9]
01001000HEX_S3[9]
10000001HEX_N0[9]
10000010DBL_E1[9]
10000100HEX_N2[9]
10001000HEX_N3[9]
virtex2 INT_CNR switchbox INT muxes IMUX_TI[0]
BitsDestination
MAIN[5][18]MAIN[5][19]MAIN[4][20]MAIN[5][20]MAIN[5][27]MAIN[4][25]MAIN[4][23]MAIN[5][23]MAIN[4][21]MAIN[5][21]IMUX_TI[0]
Source
0000000000PULLUP
0001000001OMUX[2]
0001000010OMUX[3]
0001000100HEX_N5[3]
0001001000HEX_N2[3]
0001010000HEX_S5[3]
0001100000HEX_S2[3]
0010000001OMUX[4]
0010000010HEX_N0[3]
0010000100DBL_W1[2]
0010001000DBL_W2[2]
0010010000HEX_N3[3]
0010100000HEX_S4[3]
0100000001OMUX[5]
0100000010DBL_W2[3]
0100000100DBL_W1[3]
0100001000DBL_E1[3]
0100010000DBL_E0[3]
0100100000HEX_S1[3]
1000000001DBL_E0[2]
1000000010HEX_S6[3]
1000000100DBL_E1[2]
1000001000HEX_S3[3]
1000010000HEX_N1[3]
1000100000HEX_N4[3]
virtex2 INT_CNR switchbox INT muxes IMUX_TI[1]
BitsDestination
MAIN[5][28]MAIN[5][25]MAIN[4][26]MAIN[5][26]MAIN[4][28]MAIN[4][24]MAIN[5][22]MAIN[5][24]MAIN[4][22]MAIN[4][18]IMUX_TI[1]
Source
0000000000PULLUP
0001000001OMUX[2]
0001000010OMUX[3]
0001000100HEX_N5[3]
0001001000HEX_N2[3]
0001010000HEX_S5[3]
0001100000HEX_S2[3]
0010000001OMUX[4]
0010000010HEX_N0[3]
0010000100DBL_W1[2]
0010001000DBL_W2[2]
0010010000HEX_N3[3]
0010100000HEX_S4[3]
0100000001OMUX[5]
0100000010DBL_W2[3]
0100000100DBL_W1[3]
0100001000DBL_E1[3]
0100010000DBL_E0[3]
0100100000HEX_S1[3]
1000000001DBL_E0[2]
1000000010HEX_S6[3]
1000000100DBL_E1[2]
1000001000HEX_S3[3]
1000010000HEX_N1[3]
1000100000HEX_N4[3]
virtex2 INT_CNR switchbox INT muxes IMUX_TS[0]
BitsDestination
MAIN[4][37]MAIN[5][39]MAIN[5][37]MAIN[5][38]MAIN[5][30]MAIN[4][32]MAIN[5][34]MAIN[4][34]MAIN[4][36]IMUX_TS[0]
Source
000000000PULLUP
000100001DBL_W1[4]
000100010HEX_N2[3]
000100100DBL_E0[4]
000101000DBL_E1[4]
000110000HEX_S1[3]
001000010DBL_W2[4]
001000100HEX_N5[3]
001001000HEX_S5[3]
001010000HEX_S2[3]
010000001HEX_S6[3]
010000010HEX_S3[3]
010001000HEX_N1[3]
010010000HEX_N4[3]
100000001HEX_N0[3]
100001000HEX_N3[3]
100010000HEX_S4[3]
virtex2 INT_CNR switchbox INT muxes IMUX_TS[1]
BitsDestination
MAIN[4][31]MAIN[5][29]MAIN[5][31]MAIN[5][32]MAIN[4][29]MAIN[4][33]MAIN[5][33]MAIN[5][35]MAIN[4][35]IMUX_TS[1]
Source
000000000PULLUP
000100001DBL_W1[4]
000100010HEX_N2[3]
000100100DBL_E0[4]
000101000DBL_E1[4]
000110000HEX_S1[3]
001000010DBL_W2[4]
001000100HEX_N5[3]
001001000HEX_S5[3]
001010000HEX_S2[3]
010000001HEX_S6[3]
010000010HEX_S3[3]
010001000HEX_N1[3]
010010000HEX_N4[3]
100000001HEX_N0[3]
100001000HEX_N3[3]
100010000HEX_S4[3]
virtex2 INT_CNR switchbox INT muxes IMUX_G0_FAN[0]
BitsDestination
MAIN[9][16]MAIN[9][19]MAIN[8][19]MAIN[8][16]MAIN[10][17]MAIN[10][19]MAIN[11][19]MAIN[11][17]MAIN[13][17]MAIN[12][19]MAIN[13][19]MAIN[12][17]IMUX_G0_FAN[0]
Source
000000000000off
000100000001OMUX_W1
000100000010OMUX_E2
000100000100OMUX_NW10
000100001000OMUX_N10
000100010000DBL_S1[0]
000100100000IMUX_G1_FAN[0]
000101000000DBL_N2[0]
000110000000IMUX_G2_FAN[0]
001000000001DBL_E0[1]
001000000010DBL_S0[0]
001000000100OMUX_EN8
001000001000DBL_W0[0]
001000010000DBL_N1[1]
001000100000DBL_S1[2]
001001000000DBL_W2[1]
001010000000DBL_S1[1]
010000000001DBL_E2[1]
010000000010DBL_S0[2]
010000000100DBL_E2[0]
010000001000DBL_E2[2]
010000010000DBL_W1[0]
010000100000DBL_E1[2]
010001000000DBL_E1[1]
010010000000DBL_N2[1]
100000000001DBL_S2[0]
100000000010DBL_S2[2]
100000000100DBL_N0[1]
100000001000DBL_S2[1]
100000010000DBL_E1[0]
100000100000DBL_W1[1]
100001000000DBL_W2[0]
100010000000DBL_N1[0]
virtex2 INT_CNR switchbox INT muxes IMUX_G0_FAN[1]
BitsDestination
MAIN[9][17]MAIN[9][18]MAIN[8][18]MAIN[8][17]MAIN[10][16]MAIN[10][18]MAIN[11][18]MAIN[11][16]MAIN[13][16]MAIN[12][18]MAIN[13][18]MAIN[12][16]IMUX_G0_FAN[1]
Source
000000000000off
000100000001OMUX_W1
000100000010OMUX_E2
000100000100OMUX_NW10
000100001000OMUX_N10
000100010000DBL_S1[0]
000100100000IMUX_G1_FAN[0]
000101000000DBL_N2[0]
000110000000IMUX_G2_FAN[0]
001000000001DBL_E0[1]
001000000010DBL_S0[0]
001000000100OMUX_EN8
001000001000DBL_W0[0]
001000010000DBL_N1[1]
001000100000DBL_S1[2]
001001000000DBL_W2[1]
001010000000DBL_S1[1]
010000000001DBL_E2[1]
010000000010DBL_S0[2]
010000000100DBL_E2[0]
010000001000DBL_E2[2]
010000010000DBL_W1[0]
010000100000DBL_E1[2]
010001000000DBL_E1[1]
010010000000DBL_N2[1]
100000000001DBL_S2[0]
100000000010DBL_S2[2]
100000000100DBL_N0[1]
100000001000DBL_S2[1]
100000010000DBL_E1[0]
100000100000DBL_W1[1]
100001000000DBL_W2[0]
100010000000DBL_N1[0]
virtex2 INT_CNR switchbox INT muxes IMUX_G0_DATA[0]
BitsDestination
MAIN[9][0]MAIN[9][3]MAIN[8][3]MAIN[8][0]MAIN[10][1]MAIN[10][3]MAIN[11][3]MAIN[11][1]MAIN[13][1]MAIN[12][3]MAIN[13][3]MAIN[12][1]IMUX_G0_DATA[0]
Source
000000000000PULLUP
000100000001OMUX_W1
000100000010OMUX_E2
000100000100OMUX_NW10
000100001000OMUX_N10
000100010000DBL_S1[0]
000100100000IMUX_G1_FAN[0]
000101000000DBL_N2[0]
000110000000IMUX_G2_FAN[0]
001000000001DBL_E0[1]
001000000010DBL_S0[0]
001000000100OMUX_EN8
001000001000DBL_W0[0]
001000010000DBL_N1[1]
001000100000DBL_S1[2]
001001000000DBL_W2[1]
001010000000DBL_S1[1]
010000000001DBL_E2[1]
010000000010DBL_S0[2]
010000000100DBL_E2[0]
010000001000DBL_E2[2]
010000010000DBL_W1[0]
010000100000DBL_E1[2]
010001000000DBL_E1[1]
010010000000DBL_N2[1]
100000000001DBL_S2[0]
100000000010DBL_S2[2]
100000000100DBL_N0[1]
100000001000DBL_S2[1]
100000010000DBL_E1[0]
100000100000DBL_W1[1]
100001000000DBL_W2[0]
100010000000DBL_N1[0]
virtex2 INT_CNR switchbox INT muxes IMUX_G0_DATA[1]
BitsDestination
MAIN[9][1]MAIN[9][2]MAIN[8][2]MAIN[8][1]MAIN[10][0]MAIN[10][2]MAIN[11][2]MAIN[11][0]MAIN[13][0]MAIN[12][2]MAIN[13][2]MAIN[12][0]IMUX_G0_DATA[1]
Source
000000000000PULLUP
000100000001OMUX_W1
000100000010OMUX_E2
000100000100OMUX_NW10
000100001000OMUX_N10
000100010000DBL_S1[0]
000100100000IMUX_G1_FAN[0]
000101000000DBL_N2[0]
000110000000IMUX_G2_FAN[0]
001000000001DBL_E0[1]
001000000010DBL_S0[0]
001000000100OMUX_EN8
001000001000DBL_W0[0]
001000010000DBL_N1[1]
001000100000DBL_S1[2]
001001000000DBL_W2[1]
001010000000DBL_S1[1]
010000000001DBL_E2[1]
010000000010DBL_S0[2]
010000000100DBL_E2[0]
010000001000DBL_E2[2]
010000010000DBL_W1[0]
010000100000DBL_E1[2]
010001000000DBL_E1[1]
010010000000DBL_N2[1]
100000000001DBL_S2[0]
100000000010DBL_S2[2]
100000000100DBL_N0[1]
100000001000DBL_S2[1]
100000010000DBL_E1[0]
100000100000DBL_W1[1]
100001000000DBL_W2[0]
100010000000DBL_N1[0]
virtex2 INT_CNR switchbox INT muxes IMUX_G0_DATA[2]
BitsDestination
MAIN[9][7]MAIN[9][4]MAIN[8][4]MAIN[8][7]MAIN[10][6]MAIN[10][4]MAIN[11][4]MAIN[11][6]MAIN[13][6]MAIN[12][4]MAIN[13][4]MAIN[12][6]IMUX_G0_DATA[2]
Source
000000000000PULLUP
000100000001OMUX_W1
000100000010OMUX_E2
000100000100OMUX_NW10
000100001000OMUX_N10
000100010000DBL_S1[0]
000100100000IMUX_G1_FAN[0]
000101000000DBL_N2[0]
000110000000IMUX_G2_FAN[0]
001000000001DBL_E0[1]
001000000010DBL_S0[0]
001000000100OMUX_EN8
001000001000DBL_W0[0]
001000010000DBL_N1[1]
001000100000DBL_S1[2]
001001000000DBL_W2[1]
001010000000DBL_S1[1]
010000000001DBL_E2[1]
010000000010DBL_S0[2]
010000000100DBL_E2[0]
010000001000DBL_E2[2]
010000010000DBL_W1[0]
010000100000DBL_E1[2]
010001000000DBL_E1[1]
010010000000DBL_N2[1]
100000000001DBL_S2[0]
100000000010DBL_S2[2]
100000000100DBL_N0[1]
100000001000DBL_S2[1]
100000010000DBL_E1[0]
100000100000DBL_W1[1]
100001000000DBL_W2[0]
100010000000DBL_N1[0]
virtex2 INT_CNR switchbox INT muxes IMUX_G0_DATA[3]
BitsDestination
MAIN[9][6]MAIN[9][5]MAIN[8][5]MAIN[8][6]MAIN[10][7]MAIN[10][5]MAIN[11][5]MAIN[11][7]MAIN[13][7]MAIN[12][5]MAIN[13][5]MAIN[12][7]IMUX_G0_DATA[3]
Source
000000000000PULLUP
000100000001OMUX_W1
000100000010OMUX_E2
000100000100OMUX_NW10
000100001000OMUX_N10
000100010000DBL_S1[0]
000100100000IMUX_G1_FAN[0]
000101000000DBL_N2[0]
000110000000IMUX_G2_FAN[0]
001000000001DBL_E0[1]
001000000010DBL_S0[0]
001000000100OMUX_EN8
001000001000DBL_W0[0]
001000010000DBL_N1[1]
001000100000DBL_S1[2]
001001000000DBL_W2[1]
001010000000DBL_S1[1]
010000000001DBL_E2[1]
010000000010DBL_S0[2]
010000000100DBL_E2[0]
010000001000DBL_E2[2]
010000010000DBL_W1[0]
010000100000DBL_E1[2]
010001000000DBL_E1[1]
010010000000DBL_N2[1]
100000000001DBL_S2[0]
100000000010DBL_S2[2]
100000000100DBL_N0[1]
100000001000DBL_S2[1]
100000010000DBL_E1[0]
100000100000DBL_W1[1]
100001000000DBL_W2[0]
100010000000DBL_N1[0]
virtex2 INT_CNR switchbox INT muxes IMUX_G0_DATA[4]
BitsDestination
MAIN[9][8]MAIN[9][11]MAIN[8][11]MAIN[8][8]MAIN[10][9]MAIN[10][11]MAIN[11][11]MAIN[11][9]MAIN[13][9]MAIN[12][11]MAIN[13][11]MAIN[12][9]IMUX_G0_DATA[4]
Source
000000000000PULLUP
000100000001OMUX_W1
000100000010OMUX_E2
000100000100OMUX_NW10
000100001000OMUX_N10
000100010000DBL_S1[0]
000100100000IMUX_G1_FAN[0]
000101000000DBL_N2[0]
000110000000IMUX_G2_FAN[0]
001000000001DBL_E0[1]
001000000010DBL_S0[0]
001000000100OMUX_EN8
001000001000DBL_W0[0]
001000010000DBL_N1[1]
001000100000DBL_S1[2]
001001000000DBL_W2[1]
001010000000DBL_S1[1]
010000000001DBL_E2[1]
010000000010DBL_S0[2]
010000000100DBL_E2[0]
010000001000DBL_E2[2]
010000010000DBL_W1[0]
010000100000DBL_E1[2]
010001000000DBL_E1[1]
010010000000DBL_N2[1]
100000000001DBL_S2[0]
100000000010DBL_S2[2]
100000000100DBL_N0[1]
100000001000DBL_S2[1]
100000010000DBL_E1[0]
100000100000DBL_W1[1]
100001000000DBL_W2[0]
100010000000DBL_N1[0]
virtex2 INT_CNR switchbox INT muxes IMUX_G0_DATA[5]
BitsDestination
MAIN[9][9]MAIN[9][10]MAIN[8][10]MAIN[8][9]MAIN[10][8]MAIN[10][10]MAIN[11][10]MAIN[11][8]MAIN[13][8]MAIN[12][10]MAIN[13][10]MAIN[12][8]IMUX_G0_DATA[5]
Source
000000000000PULLUP
000100000001OMUX_W1
000100000010OMUX_E2
000100000100OMUX_NW10
000100001000OMUX_N10
000100010000DBL_S1[0]
000100100000IMUX_G1_FAN[0]
000101000000DBL_N2[0]
000110000000IMUX_G2_FAN[0]
001000000001DBL_E0[1]
001000000010DBL_S0[0]
001000000100OMUX_EN8
001000001000DBL_W0[0]
001000010000DBL_N1[1]
001000100000DBL_S1[2]
001001000000DBL_W2[1]
001010000000DBL_S1[1]
010000000001DBL_E2[1]
010000000010DBL_S0[2]
010000000100DBL_E2[0]
010000001000DBL_E2[2]
010000010000DBL_W1[0]
010000100000DBL_E1[2]
010001000000DBL_E1[1]
010010000000DBL_N2[1]
100000000001DBL_S2[0]
100000000010DBL_S2[2]
100000000100DBL_N0[1]
100000001000DBL_S2[1]
100000010000DBL_E1[0]
100000100000DBL_W1[1]
100001000000DBL_W2[0]
100010000000DBL_N1[0]
virtex2 INT_CNR switchbox INT muxes IMUX_G0_DATA[6]
BitsDestination
MAIN[9][15]MAIN[9][12]MAIN[8][12]MAIN[8][15]MAIN[10][14]MAIN[10][12]MAIN[11][12]MAIN[11][14]MAIN[13][14]MAIN[12][12]MAIN[13][12]MAIN[12][14]IMUX_G0_DATA[6]
Source
000000000000PULLUP
000100000001OMUX_W1
000100000010OMUX_E2
000100000100OMUX_NW10
000100001000OMUX_N10
000100010000DBL_S1[0]
000100100000IMUX_G1_FAN[0]
000101000000DBL_N2[0]
000110000000IMUX_G2_FAN[0]
001000000001DBL_E0[1]
001000000010DBL_S0[0]
001000000100OMUX_EN8
001000001000DBL_W0[0]
001000010000DBL_N1[1]
001000100000DBL_S1[2]
001001000000DBL_W2[1]
001010000000DBL_S1[1]
010000000001DBL_E2[1]
010000000010DBL_S0[2]
010000000100DBL_E2[0]
010000001000DBL_E2[2]
010000010000DBL_W1[0]
010000100000DBL_E1[2]
010001000000DBL_E1[1]
010010000000DBL_N2[1]
100000000001DBL_S2[0]
100000000010DBL_S2[2]
100000000100DBL_N0[1]
100000001000DBL_S2[1]
100000010000DBL_E1[0]
100000100000DBL_W1[1]
100001000000DBL_W2[0]
100010000000DBL_N1[0]
virtex2 INT_CNR switchbox INT muxes IMUX_G0_DATA[7]
BitsDestination
MAIN[9][14]MAIN[9][13]MAIN[8][13]MAIN[8][14]MAIN[10][15]MAIN[10][13]MAIN[11][13]MAIN[11][15]MAIN[13][15]MAIN[12][13]MAIN[13][13]MAIN[12][15]IMUX_G0_DATA[7]
Source
000000000000PULLUP
000100000001OMUX_W1
000100000010OMUX_E2
000100000100OMUX_NW10
000100001000OMUX_N10
000100010000DBL_S1[0]
000100100000IMUX_G1_FAN[0]
000101000000DBL_N2[0]
000110000000IMUX_G2_FAN[0]
001000000001DBL_E0[1]
001000000010DBL_S0[0]
001000000100OMUX_EN8
001000001000DBL_W0[0]
001000010000DBL_N1[1]
001000100000DBL_S1[2]
001001000000DBL_W2[1]
001010000000DBL_S1[1]
010000000001DBL_E2[1]
010000000010DBL_S0[2]
010000000100DBL_E2[0]
010000001000DBL_E2[2]
010000010000DBL_W1[0]
010000100000DBL_E1[2]
010001000000DBL_E1[1]
010010000000DBL_N2[1]
100000000001DBL_S2[0]
100000000010DBL_S2[2]
100000000100DBL_N0[1]
100000001000DBL_S2[1]
100000010000DBL_E1[0]
100000100000DBL_W1[1]
100001000000DBL_W2[0]
100010000000DBL_N1[0]
virtex2 INT_CNR switchbox INT muxes IMUX_G1_FAN[0]
BitsDestination
MAIN[9][23]MAIN[9][20]MAIN[8][23]MAIN[8][20]MAIN[10][22]MAIN[10][20]MAIN[11][22]MAIN[11][20]MAIN[13][20]MAIN[13][22]MAIN[12][22]MAIN[12][20]IMUX_G1_FAN[0]
Source
000000000000off
000100000001OMUX_W6
000100000010DBL_S0[4]
000100000100DBL_W0[4]
000100001000DBL_E0[3]
000100010000DBL_W1[2]
000100100000DBL_N1[4]
000101000000DBL_W2[4]
000110000000DBL_N2[4]
001000000001OMUX_N12
001000000010OMUX_E7
001000000100OMUX_NE12
001000001000OMUX_WN14
001000010000IMUX_G3_FAN[1]
001000100000DBL_S1[3]
001001000000DBL_E1[4]
001010000000IMUX_G0_FAN[1]
010000000001DBL_E2[4]
010000000010DBL_E2[3]
010000000100DBL_W2[3]
010000001000DBL_W0[2]
010000010000DBL_N1[2]
010000100000DBL_W1[3]
010001000000DBL_W1[4]
010010000000DBL_N2[3]
100000000001DBL_N0[3]
100000000010DBL_S2[4]
100000000100DBL_S2[3]
100000001000DBL_W2[2]
100000010000DBL_S1[4]
100000100000DBL_E1[3]
100001000000DBL_N2[2]
100010000000DBL_N1[3]
virtex2 INT_CNR switchbox INT muxes IMUX_G1_FAN[1]
BitsDestination
MAIN[9][22]MAIN[9][21]MAIN[8][22]MAIN[8][21]MAIN[10][23]MAIN[10][21]MAIN[11][23]MAIN[11][21]MAIN[13][21]MAIN[13][23]MAIN[12][23]MAIN[12][21]IMUX_G1_FAN[1]
Source
000000000000off
000100000001OMUX_W6
000100000010DBL_S0[4]
000100000100DBL_W0[4]
000100001000DBL_E0[3]
000100010000DBL_W1[2]
000100100000DBL_N1[4]
000101000000DBL_W2[4]
000110000000DBL_N2[4]
001000000001OMUX_N12
001000000010OMUX_E7
001000000100OMUX_NE12
001000001000OMUX_WN14
001000010000IMUX_G3_FAN[1]
001000100000DBL_S1[3]
001001000000DBL_E1[4]
001010000000IMUX_G0_FAN[1]
010000000001DBL_E2[4]
010000000010DBL_E2[3]
010000000100DBL_W2[3]
010000001000DBL_W0[2]
010000010000DBL_N1[2]
010000100000DBL_W1[3]
010001000000DBL_W1[4]
010010000000DBL_N2[3]
100000000001DBL_N0[3]
100000000010DBL_S2[4]
100000000100DBL_S2[3]
100000001000DBL_W2[2]
100000010000DBL_S1[4]
100000100000DBL_E1[3]
100001000000DBL_N2[2]
100010000000DBL_N1[3]
virtex2 INT_CNR switchbox INT muxes IMUX_G1_DATA[0]
BitsDestination
MAIN[9][39]MAIN[9][36]MAIN[8][39]MAIN[8][36]MAIN[10][38]MAIN[10][36]MAIN[11][38]MAIN[11][36]MAIN[13][36]MAIN[13][38]MAIN[12][38]MAIN[12][36]IMUX_G1_DATA[0]
Source
000000000000PULLUP
000100000001OMUX_W6
000100000010DBL_S0[4]
000100000100DBL_W0[4]
000100001000DBL_E0[3]
000100010000DBL_W1[2]
000100100000DBL_N1[4]
000101000000DBL_W2[4]
000110000000DBL_N2[4]
001000000001OMUX_N12
001000000010OMUX_E7
001000000100OMUX_NE12
001000001000OMUX_WN14
001000010000IMUX_G3_FAN[1]
001000100000DBL_S1[3]
001001000000DBL_E1[4]
001010000000IMUX_G0_FAN[1]
010000000001DBL_E2[4]
010000000010DBL_E2[3]
010000000100DBL_W2[3]
010000001000DBL_W0[2]
010000010000DBL_N1[2]
010000100000DBL_W1[3]
010001000000DBL_W1[4]
010010000000DBL_N2[3]
100000000001DBL_N0[3]
100000000010DBL_S2[4]
100000000100DBL_S2[3]
100000001000DBL_W2[2]
100000010000DBL_S1[4]
100000100000DBL_E1[3]
100001000000DBL_N2[2]
100010000000DBL_N1[3]
virtex2 INT_CNR switchbox INT muxes IMUX_G1_DATA[1]
BitsDestination
MAIN[9][38]MAIN[9][37]MAIN[8][38]MAIN[8][37]MAIN[10][39]MAIN[10][37]MAIN[11][39]MAIN[11][37]MAIN[13][37]MAIN[13][39]MAIN[12][39]MAIN[12][37]IMUX_G1_DATA[1]
Source
000000000000PULLUP
000100000001OMUX_W6
000100000010DBL_S0[4]
000100000100DBL_W0[4]
000100001000DBL_E0[3]
000100010000DBL_W1[2]
000100100000DBL_N1[4]
000101000000DBL_W2[4]
000110000000DBL_N2[4]
001000000001OMUX_N12
001000000010OMUX_E7
001000000100OMUX_NE12
001000001000OMUX_WN14
001000010000IMUX_G3_FAN[1]
001000100000DBL_S1[3]
001001000000DBL_E1[4]
001010000000IMUX_G0_FAN[1]
010000000001DBL_E2[4]
010000000010DBL_E2[3]
010000000100DBL_W2[3]
010000001000DBL_W0[2]
010000010000DBL_N1[2]
010000100000DBL_W1[3]
010001000000DBL_W1[4]
010010000000DBL_N2[3]
100000000001DBL_N0[3]
100000000010DBL_S2[4]
100000000100DBL_S2[3]
100000001000DBL_W2[2]
100000010000DBL_S1[4]
100000100000DBL_E1[3]
100001000000DBL_N2[2]
100010000000DBL_N1[3]
virtex2 INT_CNR switchbox INT muxes IMUX_G1_DATA[2]
BitsDestination
MAIN[9][32]MAIN[9][35]MAIN[8][32]MAIN[8][35]MAIN[10][33]MAIN[10][35]MAIN[11][33]MAIN[11][35]MAIN[13][35]MAIN[13][33]MAIN[12][33]MAIN[12][35]IMUX_G1_DATA[2]
Source
000000000000PULLUP
000100000001OMUX_W6
000100000010DBL_S0[4]
000100000100DBL_W0[4]
000100001000DBL_E0[3]
000100010000DBL_W1[2]
000100100000DBL_N1[4]
000101000000DBL_W2[4]
000110000000DBL_N2[4]
001000000001OMUX_N12
001000000010OMUX_E7
001000000100OMUX_NE12
001000001000OMUX_WN14
001000010000IMUX_G3_FAN[1]
001000100000DBL_S1[3]
001001000000DBL_E1[4]
001010000000IMUX_G0_FAN[1]
010000000001DBL_E2[4]
010000000010DBL_E2[3]
010000000100DBL_W2[3]
010000001000DBL_W0[2]
010000010000DBL_N1[2]
010000100000DBL_W1[3]
010001000000DBL_W1[4]
010010000000DBL_N2[3]
100000000001DBL_N0[3]
100000000010DBL_S2[4]
100000000100DBL_S2[3]
100000001000DBL_W2[2]
100000010000DBL_S1[4]
100000100000DBL_E1[3]
100001000000DBL_N2[2]
100010000000DBL_N1[3]
virtex2 INT_CNR switchbox INT muxes IMUX_G1_DATA[3]
BitsDestination
MAIN[9][33]MAIN[9][34]MAIN[8][33]MAIN[8][34]MAIN[10][32]MAIN[10][34]MAIN[11][32]MAIN[11][34]MAIN[13][34]MAIN[13][32]MAIN[12][32]MAIN[12][34]IMUX_G1_DATA[3]
Source
000000000000PULLUP
000100000001OMUX_W6
000100000010DBL_S0[4]
000100000100DBL_W0[4]
000100001000DBL_E0[3]
000100010000DBL_W1[2]
000100100000DBL_N1[4]
000101000000DBL_W2[4]
000110000000DBL_N2[4]
001000000001OMUX_N12
001000000010OMUX_E7
001000000100OMUX_NE12
001000001000OMUX_WN14
001000010000IMUX_G3_FAN[1]
001000100000DBL_S1[3]
001001000000DBL_E1[4]
001010000000IMUX_G0_FAN[1]
010000000001DBL_E2[4]
010000000010DBL_E2[3]
010000000100DBL_W2[3]
010000001000DBL_W0[2]
010000010000DBL_N1[2]
010000100000DBL_W1[3]
010001000000DBL_W1[4]
010010000000DBL_N2[3]
100000000001DBL_N0[3]
100000000010DBL_S2[4]
100000000100DBL_S2[3]
100000001000DBL_W2[2]
100000010000DBL_S1[4]
100000100000DBL_E1[3]
100001000000DBL_N2[2]
100010000000DBL_N1[3]
virtex2 INT_CNR switchbox INT muxes IMUX_G1_DATA[4]
BitsDestination
MAIN[9][31]MAIN[9][28]MAIN[8][31]MAIN[8][28]MAIN[10][30]MAIN[10][28]MAIN[11][30]MAIN[11][28]MAIN[13][28]MAIN[13][30]MAIN[12][30]MAIN[12][28]IMUX_G1_DATA[4]
Source
000000000000PULLUP
000100000001OMUX_W6
000100000010DBL_S0[4]
000100000100DBL_W0[4]
000100001000DBL_E0[3]
000100010000DBL_W1[2]
000100100000DBL_N1[4]
000101000000DBL_W2[4]
000110000000DBL_N2[4]
001000000001OMUX_N12
001000000010OMUX_E7
001000000100OMUX_NE12
001000001000OMUX_WN14
001000010000IMUX_G3_FAN[1]
001000100000DBL_S1[3]
001001000000DBL_E1[4]
001010000000IMUX_G0_FAN[1]
010000000001DBL_E2[4]
010000000010DBL_E2[3]
010000000100DBL_W2[3]
010000001000DBL_W0[2]
010000010000DBL_N1[2]
010000100000DBL_W1[3]
010001000000DBL_W1[4]
010010000000DBL_N2[3]
100000000001DBL_N0[3]
100000000010DBL_S2[4]
100000000100DBL_S2[3]
100000001000DBL_W2[2]
100000010000DBL_S1[4]
100000100000DBL_E1[3]
100001000000DBL_N2[2]
100010000000DBL_N1[3]
virtex2 INT_CNR switchbox INT muxes IMUX_G1_DATA[5]
BitsDestination
MAIN[9][30]MAIN[9][29]MAIN[8][30]MAIN[8][29]MAIN[10][31]MAIN[10][29]MAIN[11][31]MAIN[11][29]MAIN[13][29]MAIN[13][31]MAIN[12][31]MAIN[12][29]IMUX_G1_DATA[5]
Source
000000000000PULLUP
000100000001OMUX_W6
000100000010DBL_S0[4]
000100000100DBL_W0[4]
000100001000DBL_E0[3]
000100010000DBL_W1[2]
000100100000DBL_N1[4]
000101000000DBL_W2[4]
000110000000DBL_N2[4]
001000000001OMUX_N12
001000000010OMUX_E7
001000000100OMUX_NE12
001000001000OMUX_WN14
001000010000IMUX_G3_FAN[1]
001000100000DBL_S1[3]
001001000000DBL_E1[4]
001010000000IMUX_G0_FAN[1]
010000000001DBL_E2[4]
010000000010DBL_E2[3]
010000000100DBL_W2[3]
010000001000DBL_W0[2]
010000010000DBL_N1[2]
010000100000DBL_W1[3]
010001000000DBL_W1[4]
010010000000DBL_N2[3]
100000000001DBL_N0[3]
100000000010DBL_S2[4]
100000000100DBL_S2[3]
100000001000DBL_W2[2]
100000010000DBL_S1[4]
100000100000DBL_E1[3]
100001000000DBL_N2[2]
100010000000DBL_N1[3]
virtex2 INT_CNR switchbox INT muxes IMUX_G1_DATA[6]
BitsDestination
MAIN[9][24]MAIN[9][27]MAIN[8][24]MAIN[8][27]MAIN[10][25]MAIN[10][27]MAIN[11][25]MAIN[11][27]MAIN[13][27]MAIN[13][25]MAIN[12][25]MAIN[12][27]IMUX_G1_DATA[6]
Source
000000000000PULLUP
000100000001OMUX_W6
000100000010DBL_S0[4]
000100000100DBL_W0[4]
000100001000DBL_E0[3]
000100010000DBL_W1[2]
000100100000DBL_N1[4]
000101000000DBL_W2[4]
000110000000DBL_N2[4]
001000000001OMUX_N12
001000000010OMUX_E7
001000000100OMUX_NE12
001000001000OMUX_WN14
001000010000IMUX_G3_FAN[1]
001000100000DBL_S1[3]
001001000000DBL_E1[4]
001010000000IMUX_G0_FAN[1]
010000000001DBL_E2[4]
010000000010DBL_E2[3]
010000000100DBL_W2[3]
010000001000DBL_W0[2]
010000010000DBL_N1[2]
010000100000DBL_W1[3]
010001000000DBL_W1[4]
010010000000DBL_N2[3]
100000000001DBL_N0[3]
100000000010DBL_S2[4]
100000000100DBL_S2[3]
100000001000DBL_W2[2]
100000010000DBL_S1[4]
100000100000DBL_E1[3]
100001000000DBL_N2[2]
100010000000DBL_N1[3]
virtex2 INT_CNR switchbox INT muxes IMUX_G1_DATA[7]
BitsDestination
MAIN[9][25]MAIN[9][26]MAIN[8][25]MAIN[8][26]MAIN[10][24]MAIN[10][26]MAIN[11][24]MAIN[11][26]MAIN[13][26]MAIN[13][24]MAIN[12][24]MAIN[12][26]IMUX_G1_DATA[7]
Source
000000000000PULLUP
000100000001OMUX_W6
000100000010DBL_S0[4]
000100000100DBL_W0[4]
000100001000DBL_E0[3]
000100010000DBL_W1[2]
000100100000DBL_N1[4]
000101000000DBL_W2[4]
000110000000DBL_N2[4]
001000000001OMUX_N12
001000000010OMUX_E7
001000000100OMUX_NE12
001000001000OMUX_WN14
001000010000IMUX_G3_FAN[1]
001000100000DBL_S1[3]
001001000000DBL_E1[4]
001010000000IMUX_G0_FAN[1]
010000000001DBL_E2[4]
010000000010DBL_E2[3]
010000000100DBL_W2[3]
010000001000DBL_W0[2]
010000010000DBL_N1[2]
010000100000DBL_W1[3]
010001000000DBL_W1[4]
010010000000DBL_N2[3]
100000000001DBL_N0[3]
100000000010DBL_S2[4]
100000000100DBL_S2[3]
100000001000DBL_W2[2]
100000010000DBL_S1[4]
100000100000DBL_E1[3]
100001000000DBL_N2[2]
100010000000DBL_N1[3]
virtex2 INT_CNR switchbox INT muxes IMUX_G2_FAN[0]
BitsDestination
MAIN[9][56]MAIN[9][59]MAIN[8][59]MAIN[8][56]MAIN[10][57]MAIN[10][59]MAIN[11][59]MAIN[11][57]MAIN[13][59]MAIN[13][57]MAIN[12][59]MAIN[12][57]IMUX_G2_FAN[0]
Source
000000000000off
000100000001OMUX_WS1
000100000010OMUX_E8
000100000100OMUX_SE3
000100001000OMUX_W9
000100010000DBL_S1[5]
000100100000IMUX_G3_FAN[0]
000101000000DBL_N2[5]
000110000000IMUX_G0_FAN[0]
001000000001DBL_E0[5]
001000000010OMUX_S3
001000000100DBL_W0[6]
001000001000DBL_S0[6]
001000010000DBL_N1[6]
001000100000DBL_S1[7]
001001000000DBL_W2[6]
001010000000DBL_S1[6]
010000000001DBL_E2[6]
010000000010DBL_E2[5]
010000000100DBL_E2[7]
010000001000DBL_E0[7]
010000010000DBL_W1[5]
010000100000DBL_E1[7]
010001000000DBL_E1[6]
010010000000DBL_N2[6]
100000000001DBL_S2[5]
100000000010DBL_N0[5]
100000000100DBL_S2[6]
100000001000DBL_S2[7]
100000010000DBL_E1[5]
100000100000DBL_W1[6]
100001000000DBL_W2[5]
100010000000DBL_N1[5]
virtex2 INT_CNR switchbox INT muxes IMUX_G2_FAN[1]
BitsDestination
MAIN[9][57]MAIN[9][58]MAIN[8][58]MAIN[8][57]MAIN[10][56]MAIN[10][58]MAIN[11][58]MAIN[11][56]MAIN[13][58]MAIN[13][56]MAIN[12][58]MAIN[12][56]IMUX_G2_FAN[1]
Source
000000000000off
000100000001OMUX_WS1
000100000010OMUX_E8
000100000100OMUX_SE3
000100001000OMUX_W9
000100010000DBL_S1[5]
000100100000IMUX_G3_FAN[0]
000101000000DBL_N2[5]
000110000000IMUX_G0_FAN[0]
001000000001DBL_E0[5]
001000000010OMUX_S3
001000000100DBL_W0[6]
001000001000DBL_S0[6]
001000010000DBL_N1[6]
001000100000DBL_S1[7]
001001000000DBL_W2[6]
001010000000DBL_S1[6]
010000000001DBL_E2[6]
010000000010DBL_E2[5]
010000000100DBL_E2[7]
010000001000DBL_E0[7]
010000010000DBL_W1[5]
010000100000DBL_E1[7]
010001000000DBL_E1[6]
010010000000DBL_N2[6]
100000000001DBL_S2[5]
100000000010DBL_N0[5]
100000000100DBL_S2[6]
100000001000DBL_S2[7]
100000010000DBL_E1[5]
100000100000DBL_W1[6]
100001000000DBL_W2[5]
100010000000DBL_N1[5]
virtex2 INT_CNR switchbox INT muxes IMUX_G2_DATA[0]
BitsDestination
MAIN[9][40]MAIN[9][43]MAIN[8][43]MAIN[8][40]MAIN[10][41]MAIN[10][43]MAIN[11][43]MAIN[11][41]MAIN[13][43]MAIN[13][41]MAIN[12][43]MAIN[12][41]IMUX_G2_DATA[0]
Source
000000000000PULLUP
000100000001OMUX_WS1
000100000010OMUX_E8
000100000100OMUX_SE3
000100001000OMUX_W9
000100010000DBL_S1[5]
000100100000IMUX_G3_FAN[0]
000101000000DBL_N2[5]
000110000000IMUX_G0_FAN[0]
001000000001DBL_E0[5]
001000000010OMUX_S3
001000000100DBL_W0[6]
001000001000DBL_S0[6]
001000010000DBL_N1[6]
001000100000DBL_S1[7]
001001000000DBL_W2[6]
001010000000DBL_S1[6]
010000000001DBL_E2[6]
010000000010DBL_E2[5]
010000000100DBL_E2[7]
010000001000DBL_E0[7]
010000010000DBL_W1[5]
010000100000DBL_E1[7]
010001000000DBL_E1[6]
010010000000DBL_N2[6]
100000000001DBL_S2[5]
100000000010DBL_N0[5]
100000000100DBL_S2[6]
100000001000DBL_S2[7]
100000010000DBL_E1[5]
100000100000DBL_W1[6]
100001000000DBL_W2[5]
100010000000DBL_N1[5]
virtex2 INT_CNR switchbox INT muxes IMUX_G2_DATA[1]
BitsDestination
MAIN[9][41]MAIN[9][42]MAIN[8][42]MAIN[8][41]MAIN[10][40]MAIN[10][42]MAIN[11][42]MAIN[11][40]MAIN[13][42]MAIN[13][40]MAIN[12][42]MAIN[12][40]IMUX_G2_DATA[1]
Source
000000000000PULLUP
000100000001OMUX_WS1
000100000010OMUX_E8
000100000100OMUX_SE3
000100001000OMUX_W9
000100010000DBL_S1[5]
000100100000IMUX_G3_FAN[0]
000101000000DBL_N2[5]
000110000000IMUX_G0_FAN[0]
001000000001DBL_E0[5]
001000000010OMUX_S3
001000000100DBL_W0[6]
001000001000DBL_S0[6]
001000010000DBL_N1[6]
001000100000DBL_S1[7]
001001000000DBL_W2[6]
001010000000DBL_S1[6]
010000000001DBL_E2[6]
010000000010DBL_E2[5]
010000000100DBL_E2[7]
010000001000DBL_E0[7]
010000010000DBL_W1[5]
010000100000DBL_E1[7]
010001000000DBL_E1[6]
010010000000DBL_N2[6]
100000000001DBL_S2[5]
100000000010DBL_N0[5]
100000000100DBL_S2[6]
100000001000DBL_S2[7]
100000010000DBL_E1[5]
100000100000DBL_W1[6]
100001000000DBL_W2[5]
100010000000DBL_N1[5]
virtex2 INT_CNR switchbox INT muxes IMUX_G2_DATA[2]
BitsDestination
MAIN[9][47]MAIN[9][44]MAIN[8][44]MAIN[8][47]MAIN[10][46]MAIN[10][44]MAIN[11][44]MAIN[11][46]MAIN[13][44]MAIN[13][46]MAIN[12][44]MAIN[12][46]IMUX_G2_DATA[2]
Source
000000000000PULLUP
000100000001OMUX_WS1
000100000010OMUX_E8
000100000100OMUX_SE3
000100001000OMUX_W9
000100010000DBL_S1[5]
000100100000IMUX_G3_FAN[0]
000101000000DBL_N2[5]
000110000000IMUX_G0_FAN[0]
001000000001DBL_E0[5]
001000000010OMUX_S3
001000000100DBL_W0[6]
001000001000DBL_S0[6]
001000010000DBL_N1[6]
001000100000DBL_S1[7]
001001000000DBL_W2[6]
001010000000DBL_S1[6]
010000000001DBL_E2[6]
010000000010DBL_E2[5]
010000000100DBL_E2[7]
010000001000DBL_E0[7]
010000010000DBL_W1[5]
010000100000DBL_E1[7]
010001000000DBL_E1[6]
010010000000DBL_N2[6]
100000000001DBL_S2[5]
100000000010DBL_N0[5]
100000000100DBL_S2[6]
100000001000DBL_S2[7]
100000010000DBL_E1[5]
100000100000DBL_W1[6]
100001000000DBL_W2[5]
100010000000DBL_N1[5]
virtex2 INT_CNR switchbox INT muxes IMUX_G2_DATA[3]
BitsDestination
MAIN[9][46]MAIN[9][45]MAIN[8][45]MAIN[8][46]MAIN[10][47]MAIN[10][45]MAIN[11][45]MAIN[11][47]MAIN[13][45]MAIN[13][47]MAIN[12][45]MAIN[12][47]IMUX_G2_DATA[3]
Source
000000000000PULLUP
000100000001OMUX_WS1
000100000010OMUX_E8
000100000100OMUX_SE3
000100001000OMUX_W9
000100010000DBL_S1[5]
000100100000IMUX_G3_FAN[0]
000101000000DBL_N2[5]
000110000000IMUX_G0_FAN[0]
001000000001DBL_E0[5]
001000000010OMUX_S3
001000000100DBL_W0[6]
001000001000DBL_S0[6]
001000010000DBL_N1[6]
001000100000DBL_S1[7]
001001000000DBL_W2[6]
001010000000DBL_S1[6]
010000000001DBL_E2[6]
010000000010DBL_E2[5]
010000000100DBL_E2[7]
010000001000DBL_E0[7]
010000010000DBL_W1[5]
010000100000DBL_E1[7]
010001000000DBL_E1[6]
010010000000DBL_N2[6]
100000000001DBL_S2[5]
100000000010DBL_N0[5]
100000000100DBL_S2[6]
100000001000DBL_S2[7]
100000010000DBL_E1[5]
100000100000DBL_W1[6]
100001000000DBL_W2[5]
100010000000DBL_N1[5]
virtex2 INT_CNR switchbox INT muxes IMUX_G2_DATA[4]
BitsDestination
MAIN[9][48]MAIN[9][51]MAIN[8][51]MAIN[8][48]MAIN[10][49]MAIN[10][51]MAIN[11][51]MAIN[11][49]MAIN[13][51]MAIN[13][49]MAIN[12][51]MAIN[12][49]IMUX_G2_DATA[4]
Source
000000000000PULLUP
000100000001OMUX_WS1
000100000010OMUX_E8
000100000100OMUX_SE3
000100001000OMUX_W9
000100010000DBL_S1[5]
000100100000IMUX_G3_FAN[0]
000101000000DBL_N2[5]
000110000000IMUX_G0_FAN[0]
001000000001DBL_E0[5]
001000000010OMUX_S3
001000000100DBL_W0[6]
001000001000DBL_S0[6]
001000010000DBL_N1[6]
001000100000DBL_S1[7]
001001000000DBL_W2[6]
001010000000DBL_S1[6]
010000000001DBL_E2[6]
010000000010DBL_E2[5]
010000000100DBL_E2[7]
010000001000DBL_E0[7]
010000010000DBL_W1[5]
010000100000DBL_E1[7]
010001000000DBL_E1[6]
010010000000DBL_N2[6]
100000000001DBL_S2[5]
100000000010DBL_N0[5]
100000000100DBL_S2[6]
100000001000DBL_S2[7]
100000010000DBL_E1[5]
100000100000DBL_W1[6]
100001000000DBL_W2[5]
100010000000DBL_N1[5]
virtex2 INT_CNR switchbox INT muxes IMUX_G2_DATA[5]
BitsDestination
MAIN[9][49]MAIN[9][50]MAIN[8][50]MAIN[8][49]MAIN[10][48]MAIN[10][50]MAIN[11][50]MAIN[11][48]MAIN[13][50]MAIN[13][48]MAIN[12][50]MAIN[12][48]IMUX_G2_DATA[5]
Source
000000000000PULLUP
000100000001OMUX_WS1
000100000010OMUX_E8
000100000100OMUX_SE3
000100001000OMUX_W9
000100010000DBL_S1[5]
000100100000IMUX_G3_FAN[0]
000101000000DBL_N2[5]
000110000000IMUX_G0_FAN[0]
001000000001DBL_E0[5]
001000000010OMUX_S3
001000000100DBL_W0[6]
001000001000DBL_S0[6]
001000010000DBL_N1[6]
001000100000DBL_S1[7]
001001000000DBL_W2[6]
001010000000DBL_S1[6]
010000000001DBL_E2[6]
010000000010DBL_E2[5]
010000000100DBL_E2[7]
010000001000DBL_E0[7]
010000010000DBL_W1[5]
010000100000DBL_E1[7]
010001000000DBL_E1[6]
010010000000DBL_N2[6]
100000000001DBL_S2[5]
100000000010DBL_N0[5]
100000000100DBL_S2[6]
100000001000DBL_S2[7]
100000010000DBL_E1[5]
100000100000DBL_W1[6]
100001000000DBL_W2[5]
100010000000DBL_N1[5]
virtex2 INT_CNR switchbox INT muxes IMUX_G2_DATA[6]
BitsDestination
MAIN[9][55]MAIN[9][52]MAIN[8][52]MAIN[8][55]MAIN[10][54]MAIN[10][52]MAIN[11][52]MAIN[11][54]MAIN[13][52]MAIN[13][54]MAIN[12][52]MAIN[12][54]IMUX_G2_DATA[6]
Source
000000000000PULLUP
000100000001OMUX_WS1
000100000010OMUX_E8
000100000100OMUX_SE3
000100001000OMUX_W9
000100010000DBL_S1[5]
000100100000IMUX_G3_FAN[0]
000101000000DBL_N2[5]
000110000000IMUX_G0_FAN[0]
001000000001DBL_E0[5]
001000000010OMUX_S3
001000000100DBL_W0[6]
001000001000DBL_S0[6]
001000010000DBL_N1[6]
001000100000DBL_S1[7]
001001000000DBL_W2[6]
001010000000DBL_S1[6]
010000000001DBL_E2[6]
010000000010DBL_E2[5]
010000000100DBL_E2[7]
010000001000DBL_E0[7]
010000010000DBL_W1[5]
010000100000DBL_E1[7]
010001000000DBL_E1[6]
010010000000DBL_N2[6]
100000000001DBL_S2[5]
100000000010DBL_N0[5]
100000000100DBL_S2[6]
100000001000DBL_S2[7]
100000010000DBL_E1[5]
100000100000DBL_W1[6]
100001000000DBL_W2[5]
100010000000DBL_N1[5]
virtex2 INT_CNR switchbox INT muxes IMUX_G2_DATA[7]
BitsDestination
MAIN[9][54]MAIN[9][53]MAIN[8][53]MAIN[8][54]MAIN[10][55]MAIN[10][53]MAIN[11][53]MAIN[11][55]MAIN[13][53]MAIN[13][55]MAIN[12][53]MAIN[12][55]IMUX_G2_DATA[7]
Source
000000000000PULLUP
000100000001OMUX_WS1
000100000010OMUX_E8
000100000100OMUX_SE3
000100001000OMUX_W9
000100010000DBL_S1[5]
000100100000IMUX_G3_FAN[0]
000101000000DBL_N2[5]
000110000000IMUX_G0_FAN[0]
001000000001DBL_E0[5]
001000000010OMUX_S3
001000000100DBL_W0[6]
001000001000DBL_S0[6]
001000010000DBL_N1[6]
001000100000DBL_S1[7]
001001000000DBL_W2[6]
001010000000DBL_S1[6]
010000000001DBL_E2[6]
010000000010DBL_E2[5]
010000000100DBL_E2[7]
010000001000DBL_E0[7]
010000010000DBL_W1[5]
010000100000DBL_E1[7]
010001000000DBL_E1[6]
010010000000DBL_N2[6]
100000000001DBL_S2[5]
100000000010DBL_N0[5]
100000000100DBL_S2[6]
100000001000DBL_S2[7]
100000010000DBL_E1[5]
100000100000DBL_W1[6]
100001000000DBL_W2[5]
100010000000DBL_N1[5]
virtex2 INT_CNR switchbox INT muxes IMUX_G3_FAN[0]
BitsDestination
MAIN[9][63]MAIN[9][60]MAIN[8][60]MAIN[8][63]MAIN[10][62]MAIN[10][60]MAIN[11][62]MAIN[11][60]MAIN[13][62]MAIN[12][62]MAIN[12][60]MAIN[13][60]IMUX_G3_FAN[0]
Source
000000000000off
000100000001OMUX_S5
000100000010OMUX_W14
000100000100OMUX_ES7
000100001000OMUX_E13
000100010000IMUX_G1_FAN[1]
000100100000DBL_S1[8]
000101000000DBL_E1[9]
000110000000IMUX_G2_FAN[1]
001000000001DBL_W0[8]
001000000010OMUX_SW5
001000000100DBL_S0[8]
001000001000DBL_E0[9]
001000010000DBL_W1[7]
001000100000DBL_N1[9]
001001000000DBL_W2[9]
001010000000DBL_N2[9]
010000000001DBL_N0[7]
010000000010DBL_E2[9]
010000000100DBL_E2[8]
010000001000DBL_W2[8]
010000010000DBL_N1[7]
010000100000DBL_W1[8]
010001000000DBL_W1[9]
010010000000DBL_N2[8]
100000000001DBL_W2[7]
100000000010DBL_N0[9]
100000000100DBL_S2[9]
100000001000DBL_S2[8]
100000010000DBL_S1[9]
100000100000DBL_E1[8]
100001000000DBL_N2[7]
100010000000DBL_N1[8]
virtex2 INT_CNR switchbox INT muxes IMUX_G3_FAN[1]
BitsDestination
MAIN[9][62]MAIN[9][61]MAIN[8][61]MAIN[8][62]MAIN[10][63]MAIN[10][61]MAIN[11][63]MAIN[11][61]MAIN[13][63]MAIN[12][63]MAIN[12][61]MAIN[13][61]IMUX_G3_FAN[1]
Source
000000000000off
000100000001OMUX_S5
000100000010OMUX_W14
000100000100OMUX_ES7
000100001000OMUX_E13
000100010000IMUX_G1_FAN[1]
000100100000DBL_S1[8]
000101000000DBL_E1[9]
000110000000IMUX_G2_FAN[1]
001000000001DBL_W0[8]
001000000010OMUX_SW5
001000000100DBL_S0[8]
001000001000DBL_E0[9]
001000010000DBL_W1[7]
001000100000DBL_N1[9]
001001000000DBL_W2[9]
001010000000DBL_N2[9]
010000000001DBL_N0[7]
010000000010DBL_E2[9]
010000000100DBL_E2[8]
010000001000DBL_W2[8]
010000010000DBL_N1[7]
010000100000DBL_W1[8]
010001000000DBL_W1[9]
010010000000DBL_N2[8]
100000000001DBL_W2[7]
100000000010DBL_N0[9]
100000000100DBL_S2[9]
100000001000DBL_S2[8]
100000010000DBL_S1[9]
100000100000DBL_E1[8]
100001000000DBL_N2[7]
100010000000DBL_N1[8]
virtex2 INT_CNR switchbox INT muxes IMUX_G3_DATA[0]
BitsDestination
MAIN[9][79]MAIN[9][76]MAIN[8][76]MAIN[8][79]MAIN[10][78]MAIN[10][76]MAIN[11][78]MAIN[11][76]MAIN[13][78]MAIN[12][78]MAIN[12][76]MAIN[13][76]IMUX_G3_DATA[0]
Source
000000000000PULLUP
000100000001OMUX_S5
000100000010OMUX_W14
000100000100OMUX_ES7
000100001000OMUX_E13
000100010000IMUX_G1_FAN[1]
000100100000DBL_S1[8]
000101000000DBL_E1[9]
000110000000IMUX_G2_FAN[1]
001000000001DBL_W0[8]
001000000010OMUX_SW5
001000000100DBL_S0[8]
001000001000DBL_E0[9]
001000010000DBL_W1[7]
001000100000DBL_N1[9]
001001000000DBL_W2[9]
001010000000DBL_N2[9]
010000000001DBL_N0[7]
010000000010DBL_E2[9]
010000000100DBL_E2[8]
010000001000DBL_W2[8]
010000010000DBL_N1[7]
010000100000DBL_W1[8]
010001000000DBL_W1[9]
010010000000DBL_N2[8]
100000000001DBL_W2[7]
100000000010DBL_N0[9]
100000000100DBL_S2[9]
100000001000DBL_S2[8]
100000010000DBL_S1[9]
100000100000DBL_E1[8]
100001000000DBL_N2[7]
100010000000DBL_N1[8]
virtex2 INT_CNR switchbox INT muxes IMUX_G3_DATA[1]
BitsDestination
MAIN[9][78]MAIN[9][77]MAIN[8][77]MAIN[8][78]MAIN[10][79]MAIN[10][77]MAIN[11][79]MAIN[11][77]MAIN[13][79]MAIN[12][79]MAIN[12][77]MAIN[13][77]IMUX_G3_DATA[1]
Source
000000000000PULLUP
000100000001OMUX_S5
000100000010OMUX_W14
000100000100OMUX_ES7
000100001000OMUX_E13
000100010000IMUX_G1_FAN[1]
000100100000DBL_S1[8]
000101000000DBL_E1[9]
000110000000IMUX_G2_FAN[1]
001000000001DBL_W0[8]
001000000010OMUX_SW5
001000000100DBL_S0[8]
001000001000DBL_E0[9]
001000010000DBL_W1[7]
001000100000DBL_N1[9]
001001000000DBL_W2[9]
001010000000DBL_N2[9]
010000000001DBL_N0[7]
010000000010DBL_E2[9]
010000000100DBL_E2[8]
010000001000DBL_W2[8]
010000010000DBL_N1[7]
010000100000DBL_W1[8]
010001000000DBL_W1[9]
010010000000DBL_N2[8]
100000000001DBL_W2[7]
100000000010DBL_N0[9]
100000000100DBL_S2[9]
100000001000DBL_S2[8]
100000010000DBL_S1[9]
100000100000DBL_E1[8]
100001000000DBL_N2[7]
100010000000DBL_N1[8]
virtex2 INT_CNR switchbox INT muxes IMUX_G3_DATA[2]
BitsDestination
MAIN[9][72]MAIN[9][75]MAIN[8][75]MAIN[8][72]MAIN[10][73]MAIN[10][75]MAIN[11][73]MAIN[11][75]MAIN[13][73]MAIN[12][73]MAIN[12][75]MAIN[13][75]IMUX_G3_DATA[2]
Source
000000000000PULLUP
000100000001OMUX_S5
000100000010OMUX_W14
000100000100OMUX_ES7
000100001000OMUX_E13
000100010000IMUX_G1_FAN[1]
000100100000DBL_S1[8]
000101000000DBL_E1[9]
000110000000IMUX_G2_FAN[1]
001000000001DBL_W0[8]
001000000010OMUX_SW5
001000000100DBL_S0[8]
001000001000DBL_E0[9]
001000010000DBL_W1[7]
001000100000DBL_N1[9]
001001000000DBL_W2[9]
001010000000DBL_N2[9]
010000000001DBL_N0[7]
010000000010DBL_E2[9]
010000000100DBL_E2[8]
010000001000DBL_W2[8]
010000010000DBL_N1[7]
010000100000DBL_W1[8]
010001000000DBL_W1[9]
010010000000DBL_N2[8]
100000000001DBL_W2[7]
100000000010DBL_N0[9]
100000000100DBL_S2[9]
100000001000DBL_S2[8]
100000010000DBL_S1[9]
100000100000DBL_E1[8]
100001000000DBL_N2[7]
100010000000DBL_N1[8]
virtex2 INT_CNR switchbox INT muxes IMUX_G3_DATA[3]
BitsDestination
MAIN[9][73]MAIN[9][74]MAIN[8][74]MAIN[8][73]MAIN[10][72]MAIN[10][74]MAIN[11][72]MAIN[11][74]MAIN[13][72]MAIN[12][72]MAIN[12][74]MAIN[13][74]IMUX_G3_DATA[3]
Source
000000000000PULLUP
000100000001OMUX_S5
000100000010OMUX_W14
000100000100OMUX_ES7
000100001000OMUX_E13
000100010000IMUX_G1_FAN[1]
000100100000DBL_S1[8]
000101000000DBL_E1[9]
000110000000IMUX_G2_FAN[1]
001000000001DBL_W0[8]
001000000010OMUX_SW5
001000000100DBL_S0[8]
001000001000DBL_E0[9]
001000010000DBL_W1[7]
001000100000DBL_N1[9]
001001000000DBL_W2[9]
001010000000DBL_N2[9]
010000000001DBL_N0[7]
010000000010DBL_E2[9]
010000000100DBL_E2[8]
010000001000DBL_W2[8]
010000010000DBL_N1[7]
010000100000DBL_W1[8]
010001000000DBL_W1[9]
010010000000DBL_N2[8]
100000000001DBL_W2[7]
100000000010DBL_N0[9]
100000000100DBL_S2[9]
100000001000DBL_S2[8]
100000010000DBL_S1[9]
100000100000DBL_E1[8]
100001000000DBL_N2[7]
100010000000DBL_N1[8]
virtex2 INT_CNR switchbox INT muxes IMUX_G3_DATA[4]
BitsDestination
MAIN[9][71]MAIN[9][68]MAIN[8][68]MAIN[8][71]MAIN[10][70]MAIN[10][68]MAIN[11][70]MAIN[11][68]MAIN[13][70]MAIN[12][70]MAIN[12][68]MAIN[13][68]IMUX_G3_DATA[4]
Source
000000000000PULLUP
000100000001OMUX_S5
000100000010OMUX_W14
000100000100OMUX_ES7
000100001000OMUX_E13
000100010000IMUX_G1_FAN[1]
000100100000DBL_S1[8]
000101000000DBL_E1[9]
000110000000IMUX_G2_FAN[1]
001000000001DBL_W0[8]
001000000010OMUX_SW5
001000000100DBL_S0[8]
001000001000DBL_E0[9]
001000010000DBL_W1[7]
001000100000DBL_N1[9]
001001000000DBL_W2[9]
001010000000DBL_N2[9]
010000000001DBL_N0[7]
010000000010DBL_E2[9]
010000000100DBL_E2[8]
010000001000DBL_W2[8]
010000010000DBL_N1[7]
010000100000DBL_W1[8]
010001000000DBL_W1[9]
010010000000DBL_N2[8]
100000000001DBL_W2[7]
100000000010DBL_N0[9]
100000000100DBL_S2[9]
100000001000DBL_S2[8]
100000010000DBL_S1[9]
100000100000DBL_E1[8]
100001000000DBL_N2[7]
100010000000DBL_N1[8]
virtex2 INT_CNR switchbox INT muxes IMUX_G3_DATA[5]
BitsDestination
MAIN[9][70]MAIN[9][69]MAIN[8][69]MAIN[8][70]MAIN[10][71]MAIN[10][69]MAIN[11][71]MAIN[11][69]MAIN[13][71]MAIN[12][71]MAIN[12][69]MAIN[13][69]IMUX_G3_DATA[5]
Source
000000000000PULLUP
000100000001OMUX_S5
000100000010OMUX_W14
000100000100OMUX_ES7
000100001000OMUX_E13
000100010000IMUX_G1_FAN[1]
000100100000DBL_S1[8]
000101000000DBL_E1[9]
000110000000IMUX_G2_FAN[1]
001000000001DBL_W0[8]
001000000010OMUX_SW5
001000000100DBL_S0[8]
001000001000DBL_E0[9]
001000010000DBL_W1[7]
001000100000DBL_N1[9]
001001000000DBL_W2[9]
001010000000DBL_N2[9]
010000000001DBL_N0[7]
010000000010DBL_E2[9]
010000000100DBL_E2[8]
010000001000DBL_W2[8]
010000010000DBL_N1[7]
010000100000DBL_W1[8]
010001000000DBL_W1[9]
010010000000DBL_N2[8]
100000000001DBL_W2[7]
100000000010DBL_N0[9]
100000000100DBL_S2[9]
100000001000DBL_S2[8]
100000010000DBL_S1[9]
100000100000DBL_E1[8]
100001000000DBL_N2[7]
100010000000DBL_N1[8]
virtex2 INT_CNR switchbox INT muxes IMUX_G3_DATA[6]
BitsDestination
MAIN[9][64]MAIN[9][67]MAIN[8][67]MAIN[8][64]MAIN[10][65]MAIN[10][67]MAIN[11][65]MAIN[11][67]MAIN[13][65]MAIN[12][65]MAIN[12][67]MAIN[13][67]IMUX_G3_DATA[6]
Source
000000000000PULLUP
000100000001OMUX_S5
000100000010OMUX_W14
000100000100OMUX_ES7
000100001000OMUX_E13
000100010000IMUX_G1_FAN[1]
000100100000DBL_S1[8]
000101000000DBL_E1[9]
000110000000IMUX_G2_FAN[1]
001000000001DBL_W0[8]
001000000010OMUX_SW5
001000000100DBL_S0[8]
001000001000DBL_E0[9]
001000010000DBL_W1[7]
001000100000DBL_N1[9]
001001000000DBL_W2[9]
001010000000DBL_N2[9]
010000000001DBL_N0[7]
010000000010DBL_E2[9]
010000000100DBL_E2[8]
010000001000DBL_W2[8]
010000010000DBL_N1[7]
010000100000DBL_W1[8]
010001000000DBL_W1[9]
010010000000DBL_N2[8]
100000000001DBL_W2[7]
100000000010DBL_N0[9]
100000000100DBL_S2[9]
100000001000DBL_S2[8]
100000010000DBL_S1[9]
100000100000DBL_E1[8]
100001000000DBL_N2[7]
100010000000DBL_N1[8]
virtex2 INT_CNR switchbox INT muxes IMUX_G3_DATA[7]
BitsDestination
MAIN[9][65]MAIN[9][66]MAIN[8][66]MAIN[8][65]MAIN[10][64]MAIN[10][66]MAIN[11][64]MAIN[11][66]MAIN[13][64]MAIN[12][64]MAIN[12][66]MAIN[13][66]IMUX_G3_DATA[7]
Source
000000000000PULLUP
000100000001OMUX_S5
000100000010OMUX_W14
000100000100OMUX_ES7
000100001000OMUX_E13
000100010000IMUX_G1_FAN[1]
000100100000DBL_S1[8]
000101000000DBL_E1[9]
000110000000IMUX_G2_FAN[1]
001000000001DBL_W0[8]
001000000010OMUX_SW5
001000000100DBL_S0[8]
001000001000DBL_E0[9]
001000010000DBL_W1[7]
001000100000DBL_N1[9]
001001000000DBL_W2[9]
001010000000DBL_N2[9]
010000000001DBL_N0[7]
010000000010DBL_E2[9]
010000000100DBL_E2[8]
010000001000DBL_W2[8]
010000010000DBL_N1[7]
010000100000DBL_W1[8]
010001000000DBL_W1[9]
010010000000DBL_N2[8]
100000000001DBL_W2[7]
100000000010DBL_N0[9]
100000000100DBL_S2[9]
100000001000DBL_S2[8]
100000010000DBL_S1[9]
100000100000DBL_E1[8]
100001000000DBL_N2[7]
100010000000DBL_N1[8]

Bitstream

virtex2 INT_CNR rect MAIN
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21
B79 - - - - INT: mux IMUX_CE[2] bit 5 INT: mux IMUX_CE[3] bit 1 INT: mux OMUX[14] bit 0 INT: mux OMUX[15] bit 6 INT: mux IMUX_G3_DATA[0] bit 8 INT: mux IMUX_G3_DATA[0] bit 11 INT: mux IMUX_G3_DATA[1] bit 7 INT: mux IMUX_G3_DATA[1] bit 5 INT: mux IMUX_G3_DATA[1] bit 2 INT: mux IMUX_G3_DATA[1] bit 3 INT: mux DBL_E0[9] bit 0 INT: mux DBL_W0[9] bit 7 INT: mux DBL_E0[9] bit 5 INT: mux DBL_E0[9] bit 7 INT: mux HEX_W0[9] bit 0 INT: mux HEX_W0[9] bit 3 INT: mux HEX_W0[9] bit 4 INT: mux LV[18] bit 1
B78 - - - - INT: !invert IMUX_CE_OPTINV[3] ← IMUX_CE[3] INT: mux IMUX_CE[3] bit 3 INT: mux OMUX[15] bit 9 INT: mux OMUX[15] bit 7 INT: mux IMUX_G3_DATA[1] bit 8 INT: mux IMUX_G3_DATA[1] bit 11 INT: mux IMUX_G3_DATA[0] bit 7 INT: mux IMUX_G3_DATA[0] bit 5 INT: mux IMUX_G3_DATA[0] bit 2 INT: mux IMUX_G3_DATA[0] bit 3 INT: mux DBL_E0[9] bit 1 INT: mux DBL_W0[9] bit 4 INT: mux DBL_W0[9] bit 3 INT: mux DBL_W0[9] bit 0 INT: mux HEX_E0[9] bit 1 INT: mux HEX_E0[9] bit 3 INT: mux HEX_E0[9] bit 5 INT: mux HEX_W0[9] bit 6
B77 - - - - INT: mux IMUX_CE[3] bit 0 INT: mux IMUX_CE[3] bit 2 INT: mux OMUX[15] bit 0 INT: mux OMUX[15] bit 8 INT: mux IMUX_G3_DATA[1] bit 9 INT: mux IMUX_G3_DATA[1] bit 10 INT: mux IMUX_G3_DATA[1] bit 6 INT: mux IMUX_G3_DATA[1] bit 4 INT: mux IMUX_G3_DATA[1] bit 1 INT: mux IMUX_G3_DATA[1] bit 0 INT: mux DBL_W0[9] bit 5 INT: mux DBL_E0[9] bit 3 INT: mux DBL_W0[9] bit 2 INT: mux DBL_W0[9] bit 1 INT: mux HEX_W0[9] bit 2 INT: mux HEX_W0[9] bit 1 INT: mux HEX_E0[9] bit 6 INT: mux LV[18] bit 3
B76 - - - - INT: mux IMUX_CE[3] bit 4 INT: mux IMUX_CE[3] bit 5 INT: mux OMUX[14] bit 1 INT: mux OMUX[15] bit 1 INT: mux IMUX_G3_DATA[0] bit 9 INT: mux IMUX_G3_DATA[0] bit 10 INT: mux IMUX_G3_DATA[0] bit 6 INT: mux IMUX_G3_DATA[0] bit 4 INT: mux IMUX_G3_DATA[0] bit 1 INT: mux IMUX_G3_DATA[0] bit 0 INT: mux DBL_W0[9] bit 6 INT: mux DBL_E0[9] bit 2 INT: mux DBL_E0[9] bit 4 INT: mux DBL_E0[9] bit 6 INT: mux HEX_E0[9] bit 2 INT: mux HEX_E0[9] bit 0 INT: mux HEX_E0[9] bit 4 INT: mux HEX_W0[9] bit 5
B75 - - - - INT: mux IMUX_CE[2] bit 4 INT: mux IMUX_CE[2] bit 7 INT: mux OMUX[15] bit 2 INT: mux OMUX[14] bit 2 INT: mux IMUX_G3_DATA[2] bit 9 INT: mux IMUX_G3_DATA[2] bit 10 INT: mux IMUX_G3_DATA[2] bit 6 INT: mux IMUX_G3_DATA[2] bit 4 INT: mux IMUX_G3_DATA[2] bit 1 INT: mux IMUX_G3_DATA[2] bit 0 INT: mux DBL_S0[9] bit 4 INT: mux DBL_N0[9] bit 2 INT: mux DBL_S0[9] bit 0 INT: mux DBL_S0[9] bit 3 INT: mux HEX_N0[9] bit 1 INT: mux HEX_N0[9] bit 3 INT: mux HEX_N0[9] bit 5 INT: mux LV[6] bit 0
B74 - - - - INT: mux IMUX_CE[3] bit 7 INT: mux IMUX_CE[3] bit 6 INT: mux OMUX[15] bit 3 INT: mux OMUX[14] bit 3 INT: mux IMUX_G3_DATA[3] bit 9 INT: mux IMUX_G3_DATA[3] bit 10 INT: mux IMUX_G3_DATA[3] bit 6 INT: mux IMUX_G3_DATA[3] bit 4 INT: mux IMUX_G3_DATA[3] bit 1 INT: mux IMUX_G3_DATA[3] bit 0 INT: mux DBL_S0[9] bit 5 INT: mux DBL_N0[9] bit 0 INT: mux DBL_N0[9] bit 7 INT: mux DBL_N0[9] bit 5 INT: mux HEX_S0[9] bit 1 INT: mux HEX_S0[9] bit 2 INT: mux HEX_S0[9] bit 4 INT: mux HEX_N0[9] bit 4
B73 - - - - INT: mux IMUX_CE[2] bit 0 INT: mux IMUX_CE[2] bit 1 INT: mux OMUX[14] bit 4 INT: mux OMUX[15] bit 4 INT: mux IMUX_G3_DATA[3] bit 8 INT: mux IMUX_G3_DATA[3] bit 11 INT: mux IMUX_G3_DATA[2] bit 7 INT: mux IMUX_G3_DATA[2] bit 5 INT: mux IMUX_G3_DATA[2] bit 2 INT: mux IMUX_G3_DATA[2] bit 3 INT: mux DBL_N0[9] bit 1 INT: mux DBL_S0[9] bit 6 INT: mux DBL_N0[9] bit 6 INT: mux DBL_N0[9] bit 4 INT: mux HEX_N0[9] bit 2 INT: mux HEX_N0[9] bit 0 INT: mux HEX_S0[9] bit 5 INT: mux LV[6] bit 6
B72 - - - - INT: !invert IMUX_CE_OPTINV[2] ← IMUX_CE[2] INT: mux IMUX_CE[2] bit 3 INT: mux OMUX[15] bit 5 INT: mux OMUX[14] bit 8 INT: mux IMUX_G3_DATA[2] bit 8 INT: mux IMUX_G3_DATA[2] bit 11 INT: mux IMUX_G3_DATA[3] bit 7 INT: mux IMUX_G3_DATA[3] bit 5 INT: mux IMUX_G3_DATA[3] bit 2 INT: mux IMUX_G3_DATA[3] bit 3 INT: mux DBL_N0[9] bit 3 INT: mux DBL_S0[9] bit 7 INT: mux DBL_S0[9] bit 1 INT: mux DBL_S0[9] bit 2 INT: mux HEX_S0[9] bit 3 INT: mux HEX_S0[9] bit 0 INT: mux HEX_S0[9] bit 6 INT: mux HEX_N0[9] bit 6
B71 - - - - INT: mux IMUX_CE[2] bit 6 INT: mux IMUX_CE[2] bit 2 INT: mux OMUX[14] bit 9 INT: mux OMUX[14] bit 7 INT: mux IMUX_G3_DATA[4] bit 8 INT: mux IMUX_G3_DATA[4] bit 11 INT: mux IMUX_G3_DATA[5] bit 7 INT: mux IMUX_G3_DATA[5] bit 5 INT: mux IMUX_G3_DATA[5] bit 2 INT: mux IMUX_G3_DATA[5] bit 3 INT: mux DBL_E0[8] bit 2 INT: mux DBL_W0[8] bit 3 INT: mux DBL_E0[8] bit 4 INT: mux DBL_E0[8] bit 7 INT: mux HEX_E0[8] bit 0 INT: mux HEX_E0[8] bit 3 INT: mux HEX_E0[8] bit 4 INT: mux LV[6] bit 2
B70 - - - - INT: mux IMUX_CE[1] bit 5 INT: mux IMUX_CE[1] bit 2 INT: mux OMUX[14] bit 5 INT: mux OMUX[14] bit 6 INT: mux IMUX_G3_DATA[5] bit 8 INT: mux IMUX_G3_DATA[5] bit 11 INT: mux IMUX_G3_DATA[4] bit 7 INT: mux IMUX_G3_DATA[4] bit 5 INT: mux IMUX_G3_DATA[4] bit 2 INT: mux IMUX_G3_DATA[4] bit 3 INT: mux DBL_E0[8] bit 0 INT: mux DBL_W0[8] bit 0 INT: mux DBL_W0[8] bit 7 INT: mux DBL_W0[8] bit 4 INT: mux HEX_W0[8] bit 0 INT: mux HEX_W0[8] bit 3 INT: mux HEX_W0[8] bit 4 INT: mux HEX_E0[8] bit 5
B69 - - - - INT: !invert IMUX_CE_OPTINV[1] ← IMUX_CE[1] INT: mux IMUX_CE[1] bit 3 INT: mux OMUX[12] bit 1 INT: mux OMUX[13] bit 6 INT: mux IMUX_G3_DATA[5] bit 9 INT: mux IMUX_G3_DATA[5] bit 10 INT: mux IMUX_G3_DATA[5] bit 6 INT: mux IMUX_G3_DATA[5] bit 4 INT: mux IMUX_G3_DATA[5] bit 1 INT: mux IMUX_G3_DATA[5] bit 0 INT: mux DBL_W0[8] bit 2 INT: mux DBL_E0[8] bit 3 INT: mux DBL_W0[8] bit 6 INT: mux DBL_W0[8] bit 5 INT: mux HEX_E0[8] bit 2 INT: mux HEX_E0[8] bit 1 INT: mux HEX_W0[8] bit 5 INT: mux LV[6] bit 3
B68 - - - - INT: mux IMUX_CE[1] bit 1 INT: mux IMUX_CE[1] bit 0 INT: mux OMUX[13] bit 9 INT: mux OMUX[13] bit 7 INT: mux IMUX_G3_DATA[4] bit 9 INT: mux IMUX_G3_DATA[4] bit 10 INT: mux IMUX_G3_DATA[4] bit 6 INT: mux IMUX_G3_DATA[4] bit 4 INT: mux IMUX_G3_DATA[4] bit 1 INT: mux IMUX_G3_DATA[4] bit 0 INT: mux DBL_W0[8] bit 1 INT: mux DBL_E0[8] bit 1 INT: mux DBL_E0[8] bit 5 INT: mux DBL_E0[8] bit 6 INT: mux HEX_W0[8] bit 2 INT: mux HEX_W0[8] bit 1 INT: mux HEX_W0[8] bit 6 INT: mux HEX_E0[8] bit 6
B67 - - - - INT: mux IMUX_CE[0] bit 4 INT: mux IMUX_CE[0] bit 5 INT: mux OMUX[13] bit 1 INT: mux OMUX[13] bit 8 INT: mux IMUX_G3_DATA[6] bit 9 INT: mux IMUX_G3_DATA[6] bit 10 INT: mux IMUX_G3_DATA[6] bit 6 INT: mux IMUX_G3_DATA[6] bit 4 INT: mux IMUX_G3_DATA[6] bit 1 INT: mux IMUX_G3_DATA[6] bit 0 INT: mux DBL_S0[8] bit 3 INT: mux DBL_N0[8] bit 1 INT: mux DBL_S0[8] bit 5 INT: mux DBL_S0[8] bit 7 INT: mux HEX_S0[8] bit 1 INT: mux HEX_S0[8] bit 3 INT: mux HEX_S0[8] bit 5 INT: mux LV[18] bit 6
B66 - - - - INT: mux IMUX_CE[1] bit 6 INT: mux IMUX_CE[1] bit 4 INT: mux OMUX[12] bit 0 INT: mux OMUX[13] bit 0 INT: mux IMUX_G3_DATA[7] bit 9 INT: mux IMUX_G3_DATA[7] bit 10 INT: mux IMUX_G3_DATA[7] bit 6 INT: mux IMUX_G3_DATA[7] bit 4 INT: mux IMUX_G3_DATA[7] bit 1 INT: mux IMUX_G3_DATA[7] bit 0 INT: mux DBL_S0[8] bit 0 INT: mux DBL_N0[8] bit 0 INT: mux DBL_N0[8] bit 7 INT: mux DBL_N0[8] bit 5 INT: mux HEX_N0[8] bit 1 INT: mux HEX_N0[8] bit 2 INT: mux HEX_N0[8] bit 5 INT: mux HEX_S0[8] bit 4
B65 - - - - INT: mux IMUX_CE[0] bit 6 INT: mux IMUX_CE[0] bit 7 INT: mux OMUX[13] bit 2 INT: mux OMUX[12] bit 2 INT: mux IMUX_G3_DATA[7] bit 8 INT: mux IMUX_G3_DATA[7] bit 11 INT: mux IMUX_G3_DATA[6] bit 7 INT: mux IMUX_G3_DATA[6] bit 5 INT: mux IMUX_G3_DATA[6] bit 2 INT: mux IMUX_G3_DATA[6] bit 3 INT: mux DBL_N0[8] bit 3 INT: mux DBL_S0[8] bit 1 INT: mux DBL_N0[8] bit 6 INT: mux DBL_N0[8] bit 4 INT: mux HEX_S0[8] bit 2 INT: mux HEX_S0[8] bit 0 INT: mux HEX_N0[8] bit 4 INT: mux LV[6] bit 1
B64 - - - - INT: mux IMUX_CE[0] bit 1 INT: mux IMUX_CE[0] bit 2 INT: mux OMUX[13] bit 3 INT: mux OMUX[12] bit 3 INT: mux IMUX_G3_DATA[6] bit 8 INT: mux IMUX_G3_DATA[6] bit 11 INT: mux IMUX_G3_DATA[7] bit 7 INT: mux IMUX_G3_DATA[7] bit 5 INT: mux IMUX_G3_DATA[7] bit 2 INT: mux IMUX_G3_DATA[7] bit 3 INT: mux DBL_N0[8] bit 2 INT: mux DBL_S0[8] bit 2 INT: mux DBL_S0[8] bit 4 INT: mux DBL_S0[8] bit 6 INT: mux HEX_N0[8] bit 3 INT: mux HEX_N0[8] bit 0 INT: mux HEX_N0[8] bit 6 INT: mux HEX_S0[8] bit 6
B63 - - - - INT: !invert IMUX_CE_OPTINV[0] ← IMUX_CE[0] INT: mux IMUX_CE[0] bit 3 INT: mux OMUX[12] bit 4 INT: mux OMUX[13] bit 4 INT: mux IMUX_G3_FAN[0] bit 8 INT: mux IMUX_G3_FAN[0] bit 11 INT: mux IMUX_G3_FAN[1] bit 7 INT: mux IMUX_G3_FAN[1] bit 5 INT: mux IMUX_G3_FAN[1] bit 2 INT: mux IMUX_G3_FAN[1] bit 3 INT: mux DBL_E0[7] bit 2 INT: mux DBL_W0[7] bit 3 INT: mux DBL_E0[7] bit 4 INT: mux DBL_E0[7] bit 7 INT: mux HEX_W0[7] bit 0 INT: mux HEX_W0[7] bit 3 INT: mux HEX_W0[7] bit 4 INT: mux LV[18] bit 0
B62 - - - - INT: mux IMUX_CE[1] bit 7 INT: mux IMUX_CE[0] bit 0 INT: mux OMUX[13] bit 5 INT: mux OMUX[12] bit 8 INT: mux IMUX_G3_FAN[1] bit 8 INT: mux IMUX_G3_FAN[1] bit 11 INT: mux IMUX_G3_FAN[0] bit 7 INT: mux IMUX_G3_FAN[0] bit 5 INT: mux IMUX_G3_FAN[0] bit 2 INT: mux IMUX_G3_FAN[0] bit 3 INT: mux DBL_E0[7] bit 0 INT: mux DBL_W0[7] bit 0 INT: mux DBL_W0[7] bit 7 INT: mux DBL_W0[7] bit 4 INT: mux HEX_E0[7] bit 0 INT: mux HEX_E0[7] bit 3 INT: mux HEX_E0[7] bit 4 INT: mux HEX_W0[7] bit 5
B61 - - - - INT: mux IMUX_CLK[2] bit 0 INT: mux IMUX_CLK[3] bit 7 INT: mux OMUX[12] bit 9 INT: mux OMUX[12] bit 7 INT: mux IMUX_G3_FAN[1] bit 9 INT: mux IMUX_G3_FAN[1] bit 10 INT: mux IMUX_G3_FAN[1] bit 6 INT: mux IMUX_G3_FAN[1] bit 4 INT: mux IMUX_G3_FAN[1] bit 1 INT: mux IMUX_G3_FAN[1] bit 0 INT: mux DBL_W0[7] bit 2 INT: mux DBL_E0[7] bit 3 INT: mux DBL_W0[7] bit 6 INT: mux DBL_W0[7] bit 5 INT: mux HEX_W0[7] bit 2 INT: mux HEX_W0[7] bit 1 INT: mux HEX_E0[7] bit 5 INT: mux LV[6] bit 5
B60 - - - - INT: invert IMUX_CLK_OPTINV[3] ← IMUX_CLK[3] INT: mux IMUX_CLK[3] bit 9 INT: mux OMUX[12] bit 5 INT: mux OMUX[12] bit 6 INT: mux IMUX_G3_FAN[0] bit 9 INT: mux IMUX_G3_FAN[0] bit 10 INT: mux IMUX_G3_FAN[0] bit 6 INT: mux IMUX_G3_FAN[0] bit 4 INT: mux IMUX_G3_FAN[0] bit 1 INT: mux IMUX_G3_FAN[0] bit 0 INT: mux DBL_W0[7] bit 1 INT: mux DBL_E0[7] bit 1 INT: mux DBL_E0[7] bit 5 INT: mux DBL_E0[7] bit 6 INT: mux HEX_E0[7] bit 2 INT: mux HEX_E0[7] bit 1 INT: mux HEX_E0[7] bit 6 INT: mux HEX_W0[7] bit 6
B59 - - - - INT: mux IMUX_CLK[3] bit 6 INT: mux IMUX_CLK[3] bit 8 INT: mux OMUX[10] bit 1 INT: mux OMUX[11] bit 6 INT: mux IMUX_G2_FAN[0] bit 9 INT: mux IMUX_G2_FAN[0] bit 10 INT: mux IMUX_G2_FAN[0] bit 6 INT: mux IMUX_G2_FAN[0] bit 5 INT: mux IMUX_G2_FAN[0] bit 1 INT: mux IMUX_G2_FAN[0] bit 3 INT: mux DBL_S0[7] bit 4 INT: mux DBL_N0[7] bit 6 INT: mux DBL_S0[7] bit 1 INT: mux DBL_S0[7] bit 3 INT: mux HEX_N0[7] bit 1 INT: mux HEX_N0[7] bit 3 INT: mux HEX_N0[7] bit 6 INT: mux LV[18] bit 2
B58 - - - - INT: mux IMUX_CLK[3] bit 3 INT: mux IMUX_CLK[3] bit 0 INT: mux OMUX[11] bit 9 INT: mux OMUX[11] bit 7 INT: mux IMUX_G2_FAN[1] bit 9 INT: mux IMUX_G2_FAN[1] bit 10 INT: mux IMUX_G2_FAN[1] bit 6 INT: mux IMUX_G2_FAN[1] bit 5 INT: mux IMUX_G2_FAN[1] bit 1 INT: mux IMUX_G2_FAN[1] bit 3 INT: mux DBL_S0[7] bit 5 INT: mux DBL_N0[7] bit 5 INT: mux DBL_N0[7] bit 3 INT: mux DBL_N0[7] bit 1 INT: mux HEX_S0[7] bit 1 INT: mux HEX_S0[7] bit 2 INT: mux HEX_S0[7] bit 5 INT: mux HEX_N0[7] bit 5
B57 - - - - INT: mux IMUX_CLK[2] bit 3 INT: mux IMUX_CLK[2] bit 1 INT: mux OMUX[11] bit 1 INT: mux OMUX[11] bit 8 INT: mux IMUX_G2_FAN[1] bit 8 INT: mux IMUX_G2_FAN[1] bit 11 INT: mux IMUX_G2_FAN[0] bit 7 INT: mux IMUX_G2_FAN[0] bit 4 INT: mux IMUX_G2_FAN[0] bit 0 INT: mux IMUX_G2_FAN[0] bit 2 INT: mux DBL_N0[7] bit 4 INT: mux DBL_S0[7] bit 6 INT: mux DBL_N0[7] bit 2 INT: mux DBL_N0[7] bit 0 INT: mux HEX_N0[7] bit 2 INT: mux HEX_N0[7] bit 0 INT: mux HEX_S0[7] bit 6 INT: mux LV[18] bit 4
B56 - - - - INT: mux IMUX_CLK[3] bit 1 INT: mux IMUX_CLK[3] bit 2 INT: mux OMUX[10] bit 0 INT: mux OMUX[11] bit 0 INT: mux IMUX_G2_FAN[0] bit 8 INT: mux IMUX_G2_FAN[0] bit 11 INT: mux IMUX_G2_FAN[1] bit 7 INT: mux IMUX_G2_FAN[1] bit 4 INT: mux IMUX_G2_FAN[1] bit 0 INT: mux IMUX_G2_FAN[1] bit 2 INT: mux DBL_N0[7] bit 7 INT: mux DBL_S0[7] bit 7 INT: mux DBL_S0[7] bit 0 INT: mux DBL_S0[7] bit 2 INT: mux HEX_S0[7] bit 3 INT: mux HEX_S0[7] bit 0 INT: mux HEX_S0[7] bit 4 INT: mux HEX_N0[7] bit 4
B55 - - - - INT: mux IMUX_CLK[2] bit 4 INT: mux IMUX_CLK[2] bit 2 INT: mux OMUX[11] bit 2 INT: mux OMUX[10] bit 2 INT: mux IMUX_G2_DATA[6] bit 8 INT: mux IMUX_G2_DATA[6] bit 11 INT: mux IMUX_G2_DATA[7] bit 7 INT: mux IMUX_G2_DATA[7] bit 4 INT: mux IMUX_G2_DATA[7] bit 0 INT: mux IMUX_G2_DATA[7] bit 2 INT: mux DBL_E0[6] bit 1 INT: mux DBL_W0[6] bit 7 INT: mux DBL_E0[6] bit 5 INT: mux DBL_E0[6] bit 7 INT: mux HEX_E0[6] bit 1 INT: mux HEX_E0[6] bit 3 INT: mux HEX_E0[6] bit 5 INT: mux LV[6] bit 4
B54 - - - - INT: mux IMUX_CLK[3] bit 4 INT: mux IMUX_CLK[2] bit 9 INT: mux OMUX[11] bit 3 INT: mux OMUX[10] bit 3 INT: mux IMUX_G2_DATA[7] bit 8 INT: mux IMUX_G2_DATA[7] bit 11 INT: mux IMUX_G2_DATA[6] bit 7 INT: mux IMUX_G2_DATA[6] bit 4 INT: mux IMUX_G2_DATA[6] bit 0 INT: mux IMUX_G2_DATA[6] bit 2 INT: mux DBL_E0[6] bit 0 INT: mux DBL_W0[6] bit 5 INT: mux DBL_W0[6] bit 3 INT: mux DBL_W0[6] bit 0 INT: mux HEX_W0[6] bit 1 INT: mux HEX_W0[6] bit 3 INT: mux HEX_W0[6] bit 4 INT: mux HEX_E0[6] bit 4
B53 - - - - INT: mux IMUX_CLK[2] bit 6 INT: mux IMUX_CLK[2] bit 8 INT: mux OMUX[10] bit 4 INT: mux OMUX[11] bit 4 INT: mux IMUX_G2_DATA[7] bit 9 INT: mux IMUX_G2_DATA[7] bit 10 INT: mux IMUX_G2_DATA[7] bit 6 INT: mux IMUX_G2_DATA[7] bit 5 INT: mux IMUX_G2_DATA[7] bit 1 INT: mux IMUX_G2_DATA[7] bit 3 INT: mux DBL_W0[6] bit 4 INT: mux DBL_E0[6] bit 3 INT: mux DBL_W0[6] bit 2 INT: mux DBL_W0[6] bit 1 INT: mux HEX_E0[6] bit 2 INT: mux HEX_E0[6] bit 0 INT: mux HEX_W0[6] bit 5 INT: mux LV[18] bit 5
B52 - - - - INT: invert IMUX_CLK_OPTINV[2] ← IMUX_CLK[2] INT: mux IMUX_CLK[3] bit 5 INT: mux OMUX[11] bit 5 INT: mux OMUX[10] bit 8 INT: mux IMUX_G2_DATA[6] bit 9 INT: mux IMUX_G2_DATA[6] bit 10 INT: mux IMUX_G2_DATA[6] bit 6 INT: mux IMUX_G2_DATA[6] bit 5 INT: mux IMUX_G2_DATA[6] bit 1 INT: mux IMUX_G2_DATA[6] bit 3 INT: mux DBL_W0[6] bit 6 INT: mux DBL_E0[6] bit 2 INT: mux DBL_E0[6] bit 4 INT: mux DBL_E0[6] bit 6 INT: mux HEX_W0[6] bit 2 INT: mux HEX_W0[6] bit 0 INT: mux HEX_W0[6] bit 6 INT: mux HEX_E0[6] bit 6
B51 - - - - INT: mux IMUX_CLK[2] bit 5 INT: mux IMUX_CLK[2] bit 7 INT: mux OMUX[10] bit 9 INT: mux OMUX[10] bit 7 INT: mux IMUX_G2_DATA[4] bit 9 INT: mux IMUX_G2_DATA[4] bit 10 INT: mux IMUX_G2_DATA[4] bit 6 INT: mux IMUX_G2_DATA[4] bit 5 INT: mux IMUX_G2_DATA[4] bit 1 INT: mux IMUX_G2_DATA[4] bit 3 INT: mux DBL_S0[6] bit 3 INT: mux DBL_N0[6] bit 1 INT: mux DBL_S0[6] bit 4 INT: mux DBL_S0[6] bit 7 INT: mux HEX_S0[6] bit 0 INT: mux HEX_S0[6] bit 3 INT: mux HEX_S0[6] bit 4 INT: mux LH[0] bit 0
B50 - - - - INT: mux IMUX_CLK[1] bit 5 INT: mux IMUX_CLK[1] bit 7 INT: mux OMUX[10] bit 5 INT: mux OMUX[10] bit 6 INT: mux IMUX_G2_DATA[5] bit 9 INT: mux IMUX_G2_DATA[5] bit 10 INT: mux IMUX_G2_DATA[5] bit 6 INT: mux IMUX_G2_DATA[5] bit 5 INT: mux IMUX_G2_DATA[5] bit 1 INT: mux IMUX_G2_DATA[5] bit 3 INT: mux DBL_S0[6] bit 0 INT: mux DBL_N0[6] bit 0 INT: mux DBL_N0[6] bit 7 INT: mux DBL_N0[6] bit 4 INT: mux HEX_N0[6] bit 0 INT: mux HEX_N0[6] bit 2 INT: mux HEX_N0[6] bit 4 INT: mux HEX_S0[6] bit 5
B49 - - - - INT: invert IMUX_CLK_OPTINV[1] ← IMUX_CLK[1] INT: mux IMUX_CLK[0] bit 5 INT: mux OMUX[8] bit 0 INT: mux OMUX[9] bit 6 INT: mux IMUX_G2_DATA[5] bit 8 INT: mux IMUX_G2_DATA[5] bit 11 INT: mux IMUX_G2_DATA[4] bit 7 INT: mux IMUX_G2_DATA[4] bit 4 INT: mux IMUX_G2_DATA[4] bit 0 INT: mux IMUX_G2_DATA[4] bit 2 INT: mux DBL_N0[6] bit 3 INT: mux DBL_S0[6] bit 1 INT: mux DBL_N0[6] bit 6 INT: mux DBL_N0[6] bit 5 INT: mux HEX_S0[6] bit 2 INT: mux HEX_S0[6] bit 1 INT: mux HEX_N0[6] bit 5 INT: mux LH[0] bit 1
B48 - - - - INT: mux IMUX_CLK[1] bit 6 INT: mux IMUX_CLK[1] bit 8 INT: mux OMUX[9] bit 9 INT: mux OMUX[9] bit 7 INT: mux IMUX_G2_DATA[4] bit 8 INT: mux IMUX_G2_DATA[4] bit 11 INT: mux IMUX_G2_DATA[5] bit 7 INT: mux IMUX_G2_DATA[5] bit 4 INT: mux IMUX_G2_DATA[5] bit 0 INT: mux IMUX_G2_DATA[5] bit 2 INT: mux DBL_N0[6] bit 2 INT: mux DBL_S0[6] bit 2 INT: mux DBL_S0[6] bit 5 INT: mux DBL_S0[6] bit 6 INT: mux HEX_N0[6] bit 3 INT: mux HEX_N0[6] bit 1 INT: mux HEX_N0[6] bit 6 INT: mux HEX_S0[6] bit 6
B47 - - - - INT: mux IMUX_CLK[0] bit 4 INT: mux IMUX_CLK[1] bit 9 INT: mux OMUX[9] bit 0 INT: mux OMUX[9] bit 8 INT: mux IMUX_G2_DATA[2] bit 8 INT: mux IMUX_G2_DATA[2] bit 11 INT: mux IMUX_G2_DATA[3] bit 7 INT: mux IMUX_G2_DATA[3] bit 4 INT: mux IMUX_G2_DATA[3] bit 0 INT: mux IMUX_G2_DATA[3] bit 2 INT: mux DBL_E0[5] bit 2 INT: mux DBL_W0[5] bit 3 INT: mux DBL_E0[5] bit 4 INT: mux DBL_E0[5] bit 7 INT: mux HEX_W0[5] bit 1 INT: mux HEX_W0[5] bit 3 INT: mux HEX_W0[5] bit 5 INT: mux LH[0] bit 2
B46 - - - - INT: mux IMUX_CLK[1] bit 4 INT: mux IMUX_CLK[1] bit 2 INT: mux OMUX[8] bit 1 INT: mux OMUX[9] bit 1 INT: mux IMUX_G2_DATA[3] bit 8 INT: mux IMUX_G2_DATA[3] bit 11 INT: mux IMUX_G2_DATA[2] bit 7 INT: mux IMUX_G2_DATA[2] bit 4 INT: mux IMUX_G2_DATA[2] bit 0 INT: mux IMUX_G2_DATA[2] bit 2 INT: mux DBL_E0[5] bit 0 INT: mux DBL_W0[5] bit 0 INT: mux DBL_W0[5] bit 7 INT: mux DBL_W0[5] bit 5 INT: mux HEX_E0[5] bit 0 INT: mux HEX_E0[5] bit 3 INT: mux HEX_E0[5] bit 4 INT: mux HEX_W0[5] bit 4
B45 - - - - INT: mux IMUX_CLK[0] bit 1 INT: mux IMUX_CLK[0] bit 2 INT: mux OMUX[9] bit 2 INT: mux OMUX[8] bit 2 INT: mux IMUX_G2_DATA[3] bit 9 INT: mux IMUX_G2_DATA[3] bit 10 INT: mux IMUX_G2_DATA[3] bit 6 INT: mux IMUX_G2_DATA[3] bit 5 INT: mux IMUX_G2_DATA[3] bit 1 INT: mux IMUX_G2_DATA[3] bit 3 INT: mux DBL_W0[5] bit 2 INT: mux DBL_E0[5] bit 3 INT: mux DBL_W0[5] bit 6 INT: mux DBL_W0[5] bit 4 INT: mux HEX_W0[5] bit 2 INT: mux HEX_W0[5] bit 0 INT: mux HEX_E0[5] bit 5 INT: mux LH[12] bit 1
B44 - - - - INT: mux IMUX_CLK[1] bit 3 INT: mux IMUX_CLK[1] bit 1 INT: mux OMUX[9] bit 3 INT: mux OMUX[8] bit 3 INT: mux IMUX_G2_DATA[2] bit 9 INT: mux IMUX_G2_DATA[2] bit 10 INT: mux IMUX_G2_DATA[2] bit 6 INT: mux IMUX_G2_DATA[2] bit 5 INT: mux IMUX_G2_DATA[2] bit 1 INT: mux IMUX_G2_DATA[2] bit 3 INT: mux DBL_W0[5] bit 1 INT: mux DBL_E0[5] bit 1 INT: mux DBL_E0[5] bit 5 INT: mux DBL_E0[5] bit 6 INT: mux HEX_E0[5] bit 2 INT: mux HEX_E0[5] bit 1 INT: mux HEX_E0[5] bit 6 INT: mux HEX_W0[5] bit 6
B43 - - - - INT: mux IMUX_CLK[0] bit 3 INT: mux IMUX_CLK[0] bit 0 INT: mux OMUX[8] bit 4 INT: mux OMUX[9] bit 4 INT: mux IMUX_G2_DATA[0] bit 9 INT: mux IMUX_G2_DATA[0] bit 10 INT: mux IMUX_G2_DATA[0] bit 6 INT: mux IMUX_G2_DATA[0] bit 5 INT: mux IMUX_G2_DATA[0] bit 1 INT: mux IMUX_G2_DATA[0] bit 3 INT: mux DBL_S0[5] bit 3 INT: mux DBL_N0[5] bit 1 INT: mux DBL_S0[5] bit 4 INT: mux DBL_S0[5] bit 7 INT: mux HEX_N0[5] bit 1 INT: mux HEX_N0[5] bit 3 INT: mux HEX_N0[5] bit 5 INT: mux LH[12] bit 0
B42 - - - - INT: mux IMUX_CLK[0] bit 6 INT: mux IMUX_CLK[0] bit 8 INT: mux OMUX[9] bit 5 INT: mux OMUX[8] bit 8 INT: mux IMUX_G2_DATA[1] bit 9 INT: mux IMUX_G2_DATA[1] bit 10 INT: mux IMUX_G2_DATA[1] bit 6 INT: mux IMUX_G2_DATA[1] bit 5 INT: mux IMUX_G2_DATA[1] bit 1 INT: mux IMUX_G2_DATA[1] bit 3 INT: mux DBL_S0[5] bit 0 INT: mux DBL_N0[5] bit 0 INT: mux DBL_N0[5] bit 7 INT: mux DBL_N0[5] bit 5 INT: mux HEX_S0[5] bit 0 INT: mux HEX_S0[5] bit 2 INT: mux HEX_S0[5] bit 4 INT: mux HEX_N0[5] bit 4
B41 - - - - INT: invert IMUX_CLK_OPTINV[0] ← IMUX_CLK[0] INT: mux IMUX_CLK[0] bit 9 INT: mux OMUX[8] bit 9 INT: mux OMUX[8] bit 7 INT: mux IMUX_G2_DATA[1] bit 8 INT: mux IMUX_G2_DATA[1] bit 11 INT: mux IMUX_G2_DATA[0] bit 7 INT: mux IMUX_G2_DATA[0] bit 4 INT: mux IMUX_G2_DATA[0] bit 0 INT: mux IMUX_G2_DATA[0] bit 2 INT: mux DBL_N0[5] bit 3 INT: mux DBL_S0[5] bit 1 INT: mux DBL_N0[5] bit 6 INT: mux DBL_N0[5] bit 4 INT: mux HEX_N0[5] bit 2 INT: mux HEX_N0[5] bit 0 INT: mux HEX_S0[5] bit 5 INT: mux LH[12] bit 2
B40 - - - - INT: mux IMUX_CLK[1] bit 0 INT: mux IMUX_CLK[0] bit 7 INT: mux OMUX[8] bit 5 INT: mux OMUX[8] bit 6 INT: mux IMUX_G2_DATA[0] bit 8 INT: mux IMUX_G2_DATA[0] bit 11 INT: mux IMUX_G2_DATA[1] bit 7 INT: mux IMUX_G2_DATA[1] bit 4 INT: mux IMUX_G2_DATA[1] bit 0 INT: mux IMUX_G2_DATA[1] bit 2 INT: mux DBL_N0[5] bit 2 INT: mux DBL_S0[5] bit 2 INT: mux DBL_S0[5] bit 5 INT: mux DBL_S0[5] bit 6 INT: mux HEX_S0[5] bit 3 INT: mux HEX_S0[5] bit 1 INT: mux HEX_S0[5] bit 6 INT: mux HEX_N0[5] bit 6
B39 - - - - - INT: mux IMUX_TS[0] bit 7 INT: mux OMUX[6] bit 0 INT: mux OMUX[7] bit 6 INT: mux IMUX_G1_DATA[0] bit 9 INT: mux IMUX_G1_DATA[0] bit 11 INT: mux IMUX_G1_DATA[1] bit 7 INT: mux IMUX_G1_DATA[1] bit 5 INT: mux IMUX_G1_DATA[1] bit 1 INT: mux IMUX_G1_DATA[1] bit 2 INT: mux DBL_E0[4] bit 2 INT: mux DBL_W0[4] bit 3 INT: mux DBL_E0[4] bit 5 INT: mux DBL_E0[4] bit 7 INT: mux HEX_E0[4] bit 1 INT: mux HEX_E0[4] bit 3 INT: mux HEX_E0[4] bit 5 INT: mux LH[18] bit 2
B38 - - - - INT: invert IMUX_TS_OPTINV[0] ← IMUX_TS[0] INT: mux IMUX_TS[0] bit 5 INT: mux OMUX[7] bit 9 INT: mux OMUX[7] bit 7 INT: mux IMUX_G1_DATA[1] bit 9 INT: mux IMUX_G1_DATA[1] bit 11 INT: mux IMUX_G1_DATA[0] bit 7 INT: mux IMUX_G1_DATA[0] bit 5 INT: mux IMUX_G1_DATA[0] bit 1 INT: mux IMUX_G1_DATA[0] bit 2 INT: mux DBL_E0[4] bit 0 INT: mux DBL_W0[4] bit 0 INT: mux DBL_W0[4] bit 7 INT: mux DBL_W0[4] bit 5 INT: mux HEX_W0[4] bit 1 INT: mux HEX_W0[4] bit 3 INT: mux HEX_W0[4] bit 5 INT: mux HEX_E0[4] bit 4
B37 - - - - INT: mux IMUX_TS[0] bit 8 INT: mux IMUX_TS[0] bit 6 INT: mux OMUX[7] bit 0 INT: mux OMUX[7] bit 8 INT: mux IMUX_G1_DATA[1] bit 8 INT: mux IMUX_G1_DATA[1] bit 10 INT: mux IMUX_G1_DATA[1] bit 6 INT: mux IMUX_G1_DATA[1] bit 4 INT: mux IMUX_G1_DATA[1] bit 0 INT: mux IMUX_G1_DATA[1] bit 3 INT: mux DBL_W0[4] bit 2 INT: mux DBL_E0[4] bit 3 INT: mux DBL_W0[4] bit 6 INT: mux DBL_W0[4] bit 4 INT: mux HEX_E0[4] bit 2 INT: mux HEX_E0[4] bit 0 INT: mux HEX_W0[4] bit 4 INT: mux LH[18] bit 1
B36 - - - - INT: mux IMUX_TS[0] bit 0 - INT: mux OMUX[6] bit 1 INT: mux OMUX[7] bit 1 INT: mux IMUX_G1_DATA[0] bit 8 INT: mux IMUX_G1_DATA[0] bit 10 INT: mux IMUX_G1_DATA[0] bit 6 INT: mux IMUX_G1_DATA[0] bit 4 INT: mux IMUX_G1_DATA[0] bit 0 INT: mux IMUX_G1_DATA[0] bit 3 INT: mux DBL_W0[4] bit 1 INT: mux DBL_E0[4] bit 1 INT: mux DBL_E0[4] bit 4 INT: mux DBL_E0[4] bit 6 INT: mux HEX_W0[4] bit 2 INT: mux HEX_W0[4] bit 0 INT: mux HEX_W0[4] bit 6 INT: mux HEX_E0[4] bit 6
B35 - - - - INT: mux IMUX_TS[1] bit 0 INT: mux IMUX_TS[1] bit 1 INT: mux OMUX[7] bit 2 INT: mux OMUX[6] bit 2 INT: mux IMUX_G1_DATA[2] bit 8 INT: mux IMUX_G1_DATA[2] bit 10 INT: mux IMUX_G1_DATA[2] bit 6 INT: mux IMUX_G1_DATA[2] bit 4 INT: mux IMUX_G1_DATA[2] bit 0 INT: mux IMUX_G1_DATA[2] bit 3 INT: mux DBL_S0[4] bit 3 INT: mux DBL_N0[4] bit 1 INT: mux DBL_S0[4] bit 4 INT: mux DBL_S0[4] bit 7 INT: mux HEX_S0[4] bit 0 INT: mux HEX_S0[4] bit 3 INT: mux HEX_S0[4] bit 4 INT: mux LH[18] bit 0
B34 - - - - INT: mux IMUX_TS[0] bit 1 INT: mux IMUX_TS[0] bit 2 INT: mux OMUX[7] bit 3 INT: mux OMUX[6] bit 3 INT: mux IMUX_G1_DATA[3] bit 8 INT: mux IMUX_G1_DATA[3] bit 10 INT: mux IMUX_G1_DATA[3] bit 6 INT: mux IMUX_G1_DATA[3] bit 4 INT: mux IMUX_G1_DATA[3] bit 0 INT: mux IMUX_G1_DATA[3] bit 3 INT: mux DBL_S0[4] bit 0 INT: mux DBL_N0[4] bit 0 INT: mux DBL_N0[4] bit 7 INT: mux DBL_N0[4] bit 4 INT: mux HEX_N0[4] bit 0 INT: mux HEX_N0[4] bit 2 INT: mux HEX_N0[4] bit 4 INT: mux HEX_S0[4] bit 5
B33 - - - - INT: mux IMUX_TS[1] bit 3 INT: mux IMUX_TS[1] bit 2 INT: mux OMUX[6] bit 4 INT: mux OMUX[7] bit 4 INT: mux IMUX_G1_DATA[3] bit 9 INT: mux IMUX_G1_DATA[3] bit 11 INT: mux IMUX_G1_DATA[2] bit 7 INT: mux IMUX_G1_DATA[2] bit 5 INT: mux IMUX_G1_DATA[2] bit 1 INT: mux IMUX_G1_DATA[2] bit 2 INT: mux DBL_N0[4] bit 3 INT: mux DBL_S0[4] bit 1 INT: mux DBL_N0[4] bit 6 INT: mux DBL_N0[4] bit 5 INT: mux HEX_S0[4] bit 2 INT: mux HEX_S0[4] bit 1 INT: mux HEX_N0[4] bit 5 INT: mux LH[6] bit 1
B32 - - - - INT: mux IMUX_TS[0] bit 3 INT: mux IMUX_TS[1] bit 5 INT: mux OMUX[7] bit 5 INT: mux OMUX[6] bit 8 INT: mux IMUX_G1_DATA[2] bit 9 INT: mux IMUX_G1_DATA[2] bit 11 INT: mux IMUX_G1_DATA[3] bit 7 INT: mux IMUX_G1_DATA[3] bit 5 INT: mux IMUX_G1_DATA[3] bit 1 INT: mux IMUX_G1_DATA[3] bit 2 INT: mux DBL_N0[4] bit 2 INT: mux DBL_S0[4] bit 2 INT: mux DBL_S0[4] bit 5 INT: mux DBL_S0[4] bit 6 INT: mux HEX_N0[4] bit 3 INT: mux HEX_N0[4] bit 1 INT: mux HEX_N0[4] bit 6 INT: mux HEX_S0[4] bit 6
B31 - - - - INT: mux IMUX_TS[1] bit 8 INT: mux IMUX_TS[1] bit 6 INT: mux OMUX[6] bit 9 INT: mux OMUX[6] bit 7 INT: mux IMUX_G1_DATA[4] bit 9 INT: mux IMUX_G1_DATA[4] bit 11 INT: mux IMUX_G1_DATA[5] bit 7 INT: mux IMUX_G1_DATA[5] bit 5 INT: mux IMUX_G1_DATA[5] bit 1 INT: mux IMUX_G1_DATA[5] bit 2 INT: mux DBL_E0[3] bit 2 INT: mux DBL_W0[3] bit 3 INT: mux DBL_E0[3] bit 4 INT: mux DBL_E0[3] bit 7 INT: mux HEX_W0[3] bit 1 INT: mux HEX_W0[3] bit 3 INT: mux HEX_W0[3] bit 5 INT: mux LH[6] bit 2
B30 - - - - INT: invert IMUX_TS_OPTINV[1] ← IMUX_TS[1] INT: mux IMUX_TS[0] bit 4 INT: mux OMUX[6] bit 5 INT: mux OMUX[6] bit 6 INT: mux IMUX_G1_DATA[5] bit 9 INT: mux IMUX_G1_DATA[5] bit 11 INT: mux IMUX_G1_DATA[4] bit 7 INT: mux IMUX_G1_DATA[4] bit 5 INT: mux IMUX_G1_DATA[4] bit 1 INT: mux IMUX_G1_DATA[4] bit 2 INT: mux DBL_E0[3] bit 0 INT: mux DBL_W0[3] bit 0 INT: mux DBL_W0[3] bit 7 INT: mux DBL_W0[3] bit 5 INT: mux HEX_E0[3] bit 0 INT: mux HEX_E0[3] bit 3 INT: mux HEX_E0[3] bit 4 INT: mux HEX_W0[3] bit 4
B29 - - - - INT: mux IMUX_TS[1] bit 4 INT: mux IMUX_TS[1] bit 7 INT: mux OMUX[4] bit 0 INT: mux OMUX[5] bit 6 INT: mux IMUX_G1_DATA[5] bit 8 INT: mux IMUX_G1_DATA[5] bit 10 INT: mux IMUX_G1_DATA[5] bit 6 INT: mux IMUX_G1_DATA[5] bit 4 INT: mux IMUX_G1_DATA[5] bit 0 INT: mux IMUX_G1_DATA[5] bit 3 INT: mux DBL_W0[3] bit 2 INT: mux DBL_E0[3] bit 3 INT: mux DBL_W0[3] bit 6 INT: mux DBL_W0[3] bit 4 INT: mux HEX_W0[3] bit 2 INT: mux HEX_W0[3] bit 0 INT: mux HEX_E0[3] bit 5 INT: mux LH[6] bit 0
B28 - - - - INT: mux IMUX_TI[1] bit 5 INT: mux IMUX_TI[1] bit 9 INT: mux OMUX[5] bit 9 INT: mux OMUX[5] bit 7 INT: mux IMUX_G1_DATA[4] bit 8 INT: mux IMUX_G1_DATA[4] bit 10 INT: mux IMUX_G1_DATA[4] bit 6 INT: mux IMUX_G1_DATA[4] bit 4 INT: mux IMUX_G1_DATA[4] bit 0 INT: mux IMUX_G1_DATA[4] bit 3 INT: mux DBL_W0[3] bit 1 INT: mux DBL_E0[3] bit 1 INT: mux DBL_E0[3] bit 5 INT: mux DBL_E0[3] bit 6 INT: mux HEX_E0[3] bit 2 INT: mux HEX_E0[3] bit 1 INT: mux HEX_E0[3] bit 6 INT: mux HEX_W0[3] bit 6
B27 - - - - INT: !invert IMUX_TI_OPTINV[1] ← IMUX_TI[1] INT: mux IMUX_TI[0] bit 5 INT: mux OMUX[5] bit 0 INT: mux OMUX[5] bit 8 INT: mux IMUX_G1_DATA[6] bit 8 INT: mux IMUX_G1_DATA[6] bit 10 INT: mux IMUX_G1_DATA[6] bit 6 INT: mux IMUX_G1_DATA[6] bit 4 INT: mux IMUX_G1_DATA[6] bit 0 INT: mux IMUX_G1_DATA[6] bit 3 INT: mux DBL_S0[3] bit 3 INT: mux DBL_N0[3] bit 1 INT: mux DBL_S0[3] bit 5 INT: mux DBL_S0[3] bit 7 INT: mux HEX_N0[3] bit 0 INT: mux HEX_N0[3] bit 3 INT: mux HEX_N0[3] bit 4 INT: mux LV[12] bit 4
B26 - - - - INT: mux IMUX_TI[1] bit 7 INT: mux IMUX_TI[1] bit 6 INT: mux OMUX[4] bit 1 INT: mux OMUX[5] bit 1 INT: mux IMUX_G1_DATA[7] bit 8 INT: mux IMUX_G1_DATA[7] bit 10 INT: mux IMUX_G1_DATA[7] bit 6 INT: mux IMUX_G1_DATA[7] bit 4 INT: mux IMUX_G1_DATA[7] bit 0 INT: mux IMUX_G1_DATA[7] bit 3 INT: mux DBL_S0[3] bit 0 INT: mux DBL_N0[3] bit 0 INT: mux DBL_N0[3] bit 7 INT: mux DBL_N0[3] bit 4 INT: mux HEX_S0[3] bit 1 INT: mux HEX_S0[3] bit 2 INT: mux HEX_S0[3] bit 5 INT: mux HEX_N0[3] bit 5
B25 - - - - INT: mux IMUX_TI[0] bit 4 INT: mux IMUX_TI[1] bit 8 INT: mux OMUX[5] bit 2 INT: mux OMUX[4] bit 2 INT: mux IMUX_G1_DATA[7] bit 9 INT: mux IMUX_G1_DATA[7] bit 11 INT: mux IMUX_G1_DATA[6] bit 7 INT: mux IMUX_G1_DATA[6] bit 5 INT: mux IMUX_G1_DATA[6] bit 1 INT: mux IMUX_G1_DATA[6] bit 2 INT: mux DBL_N0[3] bit 3 INT: mux DBL_S0[3] bit 1 INT: mux DBL_N0[3] bit 6 INT: mux DBL_N0[3] bit 5 INT: mux HEX_N0[3] bit 2 INT: mux HEX_N0[3] bit 1 INT: mux HEX_S0[3] bit 4 INT: mux LV[0] bit 3
B24 - - - - INT: mux IMUX_TI[1] bit 4 INT: mux IMUX_TI[1] bit 2 INT: mux OMUX[5] bit 3 INT: mux OMUX[4] bit 3 INT: mux IMUX_G1_DATA[6] bit 9 INT: mux IMUX_G1_DATA[6] bit 11 INT: mux IMUX_G1_DATA[7] bit 7 INT: mux IMUX_G1_DATA[7] bit 5 INT: mux IMUX_G1_DATA[7] bit 1 INT: mux IMUX_G1_DATA[7] bit 2 INT: mux DBL_N0[3] bit 2 INT: mux DBL_S0[3] bit 2 INT: mux DBL_S0[3] bit 4 INT: mux DBL_S0[3] bit 6 INT: mux HEX_S0[3] bit 3 INT: mux HEX_S0[3] bit 0 INT: mux HEX_S0[3] bit 6 INT: mux HEX_N0[3] bit 6
B23 - - - - INT: mux IMUX_TI[0] bit 3 INT: mux IMUX_TI[0] bit 2 INT: mux OMUX[4] bit 4 INT: mux OMUX[5] bit 4 INT: mux IMUX_G1_FAN[0] bit 9 INT: mux IMUX_G1_FAN[0] bit 11 INT: mux IMUX_G1_FAN[1] bit 7 INT: mux IMUX_G1_FAN[1] bit 5 INT: mux IMUX_G1_FAN[1] bit 1 INT: mux IMUX_G1_FAN[1] bit 2 INT: mux DBL_E0[2] bit 4 INT: mux DBL_W0[2] bit 7 INT: mux DBL_E0[2] bit 1 INT: mux DBL_E0[2] bit 3 INT: mux HEX_E0[2] bit 1 INT: mux HEX_E0[2] bit 3 INT: mux HEX_E0[2] bit 5 INT: mux LV[12] bit 3
B22 - - - - INT: mux IMUX_TI[1] bit 1 INT: mux IMUX_TI[1] bit 3 INT: mux OMUX[5] bit 5 INT: mux OMUX[4] bit 8 INT: mux IMUX_G1_FAN[1] bit 9 INT: mux IMUX_G1_FAN[1] bit 11 INT: mux IMUX_G1_FAN[0] bit 7 INT: mux IMUX_G1_FAN[0] bit 5 INT: mux IMUX_G1_FAN[0] bit 1 INT: mux IMUX_G1_FAN[0] bit 2 INT: mux DBL_E0[2] bit 5 INT: mux DBL_W0[2] bit 5 INT: mux DBL_W0[2] bit 3 INT: mux DBL_W0[2] bit 1 INT: mux HEX_W0[2] bit 1 INT: mux HEX_W0[2] bit 3 INT: mux HEX_W0[2] bit 6 INT: mux HEX_E0[2] bit 6
B21 - - - - INT: mux IMUX_TI[0] bit 1 INT: mux IMUX_TI[0] bit 0 INT: mux OMUX[4] bit 9 INT: mux OMUX[4] bit 7 INT: mux IMUX_G1_FAN[1] bit 8 INT: mux IMUX_G1_FAN[1] bit 10 INT: mux IMUX_G1_FAN[1] bit 6 INT: mux IMUX_G1_FAN[1] bit 4 INT: mux IMUX_G1_FAN[1] bit 0 INT: mux IMUX_G1_FAN[1] bit 3 INT: mux DBL_W0[2] bit 4 INT: mux DBL_E0[2] bit 7 INT: mux DBL_W0[2] bit 2 INT: mux DBL_W0[2] bit 0 INT: mux HEX_E0[2] bit 2 INT: mux HEX_E0[2] bit 0 INT: mux HEX_W0[2] bit 5 INT: mux LV[0] bit 2
B20 - - - - INT: mux IMUX_TI[0] bit 7 INT: mux IMUX_TI[0] bit 6 INT: mux OMUX[4] bit 5 INT: mux OMUX[4] bit 6 INT: mux IMUX_G1_FAN[0] bit 8 INT: mux IMUX_G1_FAN[0] bit 10 INT: mux IMUX_G1_FAN[0] bit 6 INT: mux IMUX_G1_FAN[0] bit 4 INT: mux IMUX_G1_FAN[0] bit 0 INT: mux IMUX_G1_FAN[0] bit 3 INT: mux DBL_W0[2] bit 6 INT: mux DBL_E0[2] bit 6 INT: mux DBL_E0[2] bit 0 INT: mux DBL_E0[2] bit 2 INT: mux HEX_W0[2] bit 2 INT: mux HEX_W0[2] bit 0 INT: mux HEX_W0[2] bit 4 INT: mux HEX_E0[2] bit 4
B19 - - - - INT: !invert IMUX_TI_OPTINV[0] ← IMUX_TI[0] INT: mux IMUX_TI[0] bit 8 INT: mux OMUX[2] bit 0 INT: mux OMUX[3] bit 6 INT: mux IMUX_G0_FAN[0] bit 9 INT: mux IMUX_G0_FAN[0] bit 10 INT: mux IMUX_G0_FAN[0] bit 6 INT: mux IMUX_G0_FAN[0] bit 5 INT: mux IMUX_G0_FAN[0] bit 2 INT: mux IMUX_G0_FAN[0] bit 1 INT: mux DBL_S0[2] bit 4 INT: mux DBL_N0[2] bit 6 INT: mux DBL_S0[2] bit 0 INT: mux DBL_S0[2] bit 3 INT: mux HEX_S0[2] bit 0 INT: mux HEX_S0[2] bit 3 INT: mux HEX_S0[2] bit 5 INT: mux LV[0] bit 4
B18 - - - - INT: mux IMUX_TI[1] bit 0 INT: mux IMUX_TI[0] bit 9 INT: mux OMUX[3] bit 9 INT: mux OMUX[3] bit 7 INT: mux IMUX_G0_FAN[1] bit 9 INT: mux IMUX_G0_FAN[1] bit 10 INT: mux IMUX_G0_FAN[1] bit 6 INT: mux IMUX_G0_FAN[1] bit 5 INT: mux IMUX_G0_FAN[1] bit 2 INT: mux IMUX_G0_FAN[1] bit 1 INT: mux DBL_S0[2] bit 5 INT: mux DBL_N0[2] bit 5 INT: mux DBL_N0[2] bit 3 INT: mux DBL_N0[2] bit 0 INT: mux HEX_N0[2] bit 1 INT: mux HEX_N0[2] bit 2 INT: mux HEX_N0[2] bit 4 INT: mux HEX_S0[2] bit 4
B17 - - - - INT: mux IMUX_SR[3] bit 5 INT: mux IMUX_SR[1] bit 1 INT: mux OMUX[3] bit 0 INT: mux OMUX[3] bit 8 INT: mux IMUX_G0_FAN[1] bit 8 INT: mux IMUX_G0_FAN[1] bit 11 INT: mux IMUX_G0_FAN[0] bit 7 INT: mux IMUX_G0_FAN[0] bit 4 INT: mux IMUX_G0_FAN[0] bit 0 INT: mux IMUX_G0_FAN[0] bit 3 INT: mux DBL_N0[2] bit 4 INT: mux DBL_S0[2] bit 6 INT: mux DBL_N0[2] bit 2 INT: mux DBL_N0[2] bit 1 INT: mux HEX_S0[2] bit 2 INT: mux HEX_S0[2] bit 1 INT: mux HEX_N0[2] bit 5 INT: mux LV[12] bit 2
B16 - - - - INT: !invert IMUX_SR_OPTINV[1] ← IMUX_SR[1] INT: mux IMUX_SR[1] bit 3 INT: mux OMUX[2] bit 1 INT: mux OMUX[3] bit 1 INT: mux IMUX_G0_FAN[0] bit 8 INT: mux IMUX_G0_FAN[0] bit 11 INT: mux IMUX_G0_FAN[1] bit 7 INT: mux IMUX_G0_FAN[1] bit 4 INT: mux IMUX_G0_FAN[1] bit 0 INT: mux IMUX_G0_FAN[1] bit 3 INT: mux DBL_N0[2] bit 7 INT: mux DBL_S0[2] bit 7 INT: mux DBL_S0[2] bit 1 INT: mux DBL_S0[2] bit 2 INT: mux HEX_N0[2] bit 3 INT: mux HEX_N0[2] bit 0 INT: mux HEX_N0[2] bit 6 INT: mux HEX_S0[2] bit 6
B15 - - - - INT: mux IMUX_SR[1] bit 0 INT: mux IMUX_SR[1] bit 2 INT: mux OMUX[3] bit 2 INT: mux OMUX[2] bit 2 INT: mux IMUX_G0_DATA[6] bit 8 INT: mux IMUX_G0_DATA[6] bit 11 INT: mux IMUX_G0_DATA[7] bit 7 INT: mux IMUX_G0_DATA[7] bit 4 INT: mux IMUX_G0_DATA[7] bit 0 INT: mux IMUX_G0_DATA[7] bit 3 INT: mux DBL_E0[1] bit 2 INT: mux DBL_W0[1] bit 3 INT: mux DBL_E0[1] bit 4 INT: mux DBL_E0[1] bit 7 INT: mux HEX_W0[1] bit 1 INT: mux HEX_W0[1] bit 2 INT: mux HEX_W0[1] bit 5 INT: mux LV[12] bit 0
B14 - - - - INT: mux IMUX_SR[1] bit 4 INT: mux IMUX_SR[1] bit 5 INT: mux OMUX[3] bit 3 INT: mux OMUX[2] bit 3 INT: mux IMUX_G0_DATA[7] bit 8 INT: mux IMUX_G0_DATA[7] bit 11 INT: mux IMUX_G0_DATA[6] bit 7 INT: mux IMUX_G0_DATA[6] bit 4 INT: mux IMUX_G0_DATA[6] bit 0 INT: mux IMUX_G0_DATA[6] bit 3 INT: mux DBL_E0[1] bit 0 INT: mux DBL_W0[1] bit 0 INT: mux DBL_W0[1] bit 6 INT: mux DBL_W0[1] bit 5 INT: mux HEX_E0[1] bit 0 INT: mux HEX_E0[1] bit 3 INT: mux HEX_E0[1] bit 4 INT: mux HEX_W0[1] bit 4
B13 - - - - INT: mux IMUX_SR[3] bit 4 INT: mux IMUX_SR[3] bit 7 INT: mux OMUX[2] bit 4 INT: mux OMUX[3] bit 4 INT: mux IMUX_G0_DATA[7] bit 9 INT: mux IMUX_G0_DATA[7] bit 10 INT: mux IMUX_G0_DATA[7] bit 6 INT: mux IMUX_G0_DATA[7] bit 5 INT: mux IMUX_G0_DATA[7] bit 2 INT: mux IMUX_G0_DATA[7] bit 1 INT: mux DBL_W0[1] bit 2 INT: mux DBL_E0[1] bit 3 INT: mux DBL_W0[1] bit 7 INT: mux DBL_W0[1] bit 4 INT: mux HEX_W0[1] bit 3 INT: mux HEX_W0[1] bit 0 INT: mux HEX_E0[1] bit 5 INT: mux LV[12] bit 6
B12 - - - - INT: mux IMUX_SR[1] bit 7 INT: mux IMUX_SR[1] bit 6 INT: mux OMUX[3] bit 5 INT: mux OMUX[2] bit 8 INT: mux IMUX_G0_DATA[6] bit 9 INT: mux IMUX_G0_DATA[6] bit 10 INT: mux IMUX_G0_DATA[6] bit 6 INT: mux IMUX_G0_DATA[6] bit 5 INT: mux IMUX_G0_DATA[6] bit 2 INT: mux IMUX_G0_DATA[6] bit 1 INT: mux DBL_W0[1] bit 1 INT: mux DBL_E0[1] bit 1 INT: mux DBL_E0[1] bit 5 INT: mux DBL_E0[1] bit 6 INT: mux HEX_E0[1] bit 2 INT: mux HEX_E0[1] bit 1 INT: mux HEX_E0[1] bit 6 INT: mux HEX_W0[1] bit 6
B11 - - - - INT: mux IMUX_SR[3] bit 0 INT: mux IMUX_SR[3] bit 1 INT: mux OMUX[2] bit 9 INT: mux OMUX[2] bit 7 INT: mux IMUX_G0_DATA[4] bit 9 INT: mux IMUX_G0_DATA[4] bit 10 INT: mux IMUX_G0_DATA[4] bit 6 INT: mux IMUX_G0_DATA[4] bit 5 INT: mux IMUX_G0_DATA[4] bit 2 INT: mux IMUX_G0_DATA[4] bit 1 INT: mux DBL_S0[1] bit 3 INT: mux DBL_N0[1] bit 1 INT: mux DBL_S0[1] bit 4 INT: mux DBL_S0[1] bit 7 INT: mux HEX_N0[1] bit 0 INT: mux HEX_N0[1] bit 3 INT: mux HEX_N0[1] bit 4 INT: mux LV[0] bit 1
B10 - - - - INT: !invert IMUX_SR_OPTINV[3] ← IMUX_SR[3] INT: mux IMUX_SR[3] bit 3 INT: mux OMUX[2] bit 5 INT: mux OMUX[2] bit 6 INT: mux IMUX_G0_DATA[5] bit 9 INT: mux IMUX_G0_DATA[5] bit 10 INT: mux IMUX_G0_DATA[5] bit 6 INT: mux IMUX_G0_DATA[5] bit 5 INT: mux IMUX_G0_DATA[5] bit 2 INT: mux IMUX_G0_DATA[5] bit 1 INT: mux DBL_S0[1] bit 0 INT: mux DBL_N0[1] bit 0 INT: mux DBL_N0[1] bit 7 INT: mux DBL_N0[1] bit 4 INT: mux HEX_S0[1] bit 0 INT: mux HEX_S0[1] bit 2 INT: mux HEX_S0[1] bit 4 INT: mux HEX_N0[1] bit 5
B9 - - - - INT: mux IMUX_SR[3] bit 6 INT: mux IMUX_SR[3] bit 2 INT: mux OMUX[0] bit 0 INT: mux OMUX[1] bit 6 INT: mux IMUX_G0_DATA[5] bit 8 INT: mux IMUX_G0_DATA[5] bit 11 INT: mux IMUX_G0_DATA[4] bit 7 INT: mux IMUX_G0_DATA[4] bit 4 INT: mux IMUX_G0_DATA[4] bit 0 INT: mux IMUX_G0_DATA[4] bit 3 INT: mux DBL_N0[1] bit 3 INT: mux DBL_S0[1] bit 1 INT: mux DBL_N0[1] bit 6 INT: mux DBL_N0[1] bit 5 INT: mux HEX_N0[1] bit 2 INT: mux HEX_N0[1] bit 1 INT: mux HEX_S0[1] bit 5 INT: mux LV[0] bit 5
B8 - - - - INT: mux IMUX_SR[2] bit 5 INT: mux IMUX_SR[2] bit 2 INT: mux OMUX[1] bit 9 INT: mux OMUX[1] bit 7 INT: mux IMUX_G0_DATA[4] bit 8 INT: mux IMUX_G0_DATA[4] bit 11 INT: mux IMUX_G0_DATA[5] bit 7 INT: mux IMUX_G0_DATA[5] bit 4 INT: mux IMUX_G0_DATA[5] bit 0 INT: mux IMUX_G0_DATA[5] bit 3 INT: mux DBL_N0[1] bit 2 INT: mux DBL_S0[1] bit 2 INT: mux DBL_S0[1] bit 5 INT: mux DBL_S0[1] bit 6 INT: mux HEX_S0[1] bit 3 INT: mux HEX_S0[1] bit 1 INT: mux HEX_S0[1] bit 6 INT: mux HEX_N0[1] bit 6
B7 - - - - INT: !invert IMUX_SR_OPTINV[2] ← IMUX_SR[2] INT: mux IMUX_SR[2] bit 3 INT: mux OMUX[1] bit 0 INT: mux OMUX[1] bit 8 INT: mux IMUX_G0_DATA[2] bit 8 INT: mux IMUX_G0_DATA[2] bit 11 INT: mux IMUX_G0_DATA[3] bit 7 INT: mux IMUX_G0_DATA[3] bit 4 INT: mux IMUX_G0_DATA[3] bit 0 INT: mux IMUX_G0_DATA[3] bit 3 INT: mux DBL_E0[0] bit 2 INT: mux DBL_W0[0] bit 3 INT: mux DBL_E0[0] bit 4 INT: mux DBL_E0[0] bit 7 INT: mux HEX_E0[0] bit 0 INT: mux HEX_E0[0] bit 3 INT: mux HEX_E0[0] bit 4 INT: mux LV[0] bit 6
B6 - - - - INT: mux IMUX_SR[2] bit 1 INT: mux IMUX_SR[2] bit 0 INT: mux OMUX[0] bit 1 INT: mux OMUX[1] bit 1 INT: mux IMUX_G0_DATA[3] bit 8 INT: mux IMUX_G0_DATA[3] bit 11 INT: mux IMUX_G0_DATA[2] bit 7 INT: mux IMUX_G0_DATA[2] bit 4 INT: mux IMUX_G0_DATA[2] bit 0 INT: mux IMUX_G0_DATA[2] bit 3 INT: mux DBL_E0[0] bit 0 INT: mux DBL_W0[0] bit 0 INT: mux DBL_W0[0] bit 6 INT: mux DBL_W0[0] bit 5 INT: mux HEX_W0[0] bit 1 INT: mux HEX_W0[0] bit 2 INT: mux HEX_W0[0] bit 5 INT: mux HEX_E0[0] bit 5
B5 - - - - INT: mux IMUX_SR[0] bit 4 INT: mux IMUX_SR[0] bit 5 INT: mux OMUX[1] bit 2 INT: mux OMUX[0] bit 2 INT: mux IMUX_G0_DATA[3] bit 9 INT: mux IMUX_G0_DATA[3] bit 10 INT: mux IMUX_G0_DATA[3] bit 6 INT: mux IMUX_G0_DATA[3] bit 5 INT: mux IMUX_G0_DATA[3] bit 2 INT: mux IMUX_G0_DATA[3] bit 1 INT: mux DBL_W0[0] bit 2 INT: mux DBL_E0[0] bit 3 INT: mux DBL_W0[0] bit 7 INT: mux DBL_W0[0] bit 4 INT: mux HEX_E0[0] bit 2 INT: mux HEX_E0[0] bit 1 INT: mux HEX_W0[0] bit 4 INT: mux LV[0] bit 0
B4 - - - - INT: mux IMUX_SR[2] bit 6 INT: mux IMUX_SR[2] bit 4 INT: mux OMUX[1] bit 3 INT: mux OMUX[0] bit 3 INT: mux IMUX_G0_DATA[2] bit 9 INT: mux IMUX_G0_DATA[2] bit 10 INT: mux IMUX_G0_DATA[2] bit 6 INT: mux IMUX_G0_DATA[2] bit 5 INT: mux IMUX_G0_DATA[2] bit 2 INT: mux IMUX_G0_DATA[2] bit 1 INT: mux DBL_W0[0] bit 1 INT: mux DBL_E0[0] bit 1 INT: mux DBL_E0[0] bit 5 INT: mux DBL_E0[0] bit 6 INT: mux HEX_W0[0] bit 3 INT: mux HEX_W0[0] bit 0 INT: mux HEX_W0[0] bit 6 INT: mux HEX_E0[0] bit 6
B3 - - - - INT: mux IMUX_SR[0] bit 6 INT: mux IMUX_SR[0] bit 7 INT: mux OMUX[0] bit 4 INT: mux OMUX[1] bit 4 INT: mux IMUX_G0_DATA[0] bit 9 INT: mux IMUX_G0_DATA[0] bit 10 INT: mux IMUX_G0_DATA[0] bit 6 INT: mux IMUX_G0_DATA[0] bit 5 INT: mux IMUX_G0_DATA[0] bit 2 INT: mux IMUX_G0_DATA[0] bit 1 INT: mux DBL_S0[0] bit 4 INT: mux DBL_N0[0] bit 6 INT: mux DBL_S0[0] bit 1 INT: mux DBL_S0[0] bit 3 INT: mux HEX_S0[0] bit 1 INT: mux HEX_S0[0] bit 3 INT: mux HEX_S0[0] bit 6 INT: mux LV[12] bit 1
B2 - - - - INT: mux IMUX_SR[0] bit 1 INT: mux IMUX_SR[0] bit 2 INT: mux OMUX[1] bit 5 INT: mux OMUX[0] bit 8 INT: mux IMUX_G0_DATA[1] bit 9 INT: mux IMUX_G0_DATA[1] bit 10 INT: mux IMUX_G0_DATA[1] bit 6 INT: mux IMUX_G0_DATA[1] bit 5 INT: mux IMUX_G0_DATA[1] bit 2 INT: mux IMUX_G0_DATA[1] bit 1 INT: mux DBL_S0[0] bit 5 INT: mux DBL_N0[0] bit 5 INT: mux DBL_N0[0] bit 3 INT: mux DBL_N0[0] bit 1 INT: mux HEX_N0[0] bit 1 INT: mux HEX_N0[0] bit 2 INT: mux HEX_N0[0] bit 5 INT: mux HEX_S0[0] bit 5
B1 - - - - INT: !invert IMUX_SR_OPTINV[0] ← IMUX_SR[0] INT: mux IMUX_SR[0] bit 3 INT: mux OMUX[0] bit 9 INT: mux OMUX[0] bit 7 INT: mux IMUX_G0_DATA[1] bit 8 INT: mux IMUX_G0_DATA[1] bit 11 INT: mux IMUX_G0_DATA[0] bit 7 INT: mux IMUX_G0_DATA[0] bit 4 INT: mux IMUX_G0_DATA[0] bit 0 INT: mux IMUX_G0_DATA[0] bit 3 INT: mux DBL_N0[0] bit 4 INT: mux DBL_S0[0] bit 6 INT: mux DBL_N0[0] bit 2 INT: mux DBL_N0[0] bit 0 INT: mux HEX_S0[0] bit 2 INT: mux HEX_S0[0] bit 0 INT: mux HEX_N0[0] bit 6 INT: mux LV[12] bit 5
B0 - - - - INT: mux IMUX_SR[2] bit 7 INT: mux IMUX_SR[0] bit 0 INT: mux OMUX[0] bit 5 INT: mux OMUX[0] bit 6 INT: mux IMUX_G0_DATA[0] bit 8 INT: mux IMUX_G0_DATA[0] bit 11 INT: mux IMUX_G0_DATA[1] bit 7 INT: mux IMUX_G0_DATA[1] bit 4 INT: mux IMUX_G0_DATA[1] bit 0 INT: mux IMUX_G0_DATA[1] bit 3 INT: mux DBL_N0[0] bit 7 INT: mux DBL_S0[0] bit 7 INT: mux DBL_S0[0] bit 0 INT: mux DBL_S0[0] bit 2 INT: mux HEX_N0[0] bit 3 INT: mux HEX_N0[0] bit 0 INT: mux HEX_N0[0] bit 4 INT: mux HEX_S0[0] bit 4

INT_PPC

Used with the PPC_* tiles, and also for most of the interconnect for the multi-gigabit transceiver tiles.

Tile INT_PPC

Cells: 1

Switchbox INT

virtex2 INT_PPC switchbox INT programmable inverters
DestinationSourceBit
IMUX_CLK_OPTINV[0]IMUX_CLK[0]MAIN[4][41]
IMUX_CLK_OPTINV[1]IMUX_CLK[1]MAIN[4][49]
IMUX_CLK_OPTINV[2]IMUX_CLK[2]MAIN[4][52]
IMUX_CLK_OPTINV[3]IMUX_CLK[3]MAIN[4][60]
IMUX_SR_OPTINV[0]IMUX_SR[0]!MAIN[4][1]
IMUX_SR_OPTINV[1]IMUX_SR[1]!MAIN[4][16]
IMUX_SR_OPTINV[2]IMUX_SR[2]!MAIN[4][7]
IMUX_SR_OPTINV[3]IMUX_SR[3]!MAIN[4][10]
IMUX_CE_OPTINV[0]IMUX_CE[0]!MAIN[4][63]
IMUX_CE_OPTINV[1]IMUX_CE[1]!MAIN[4][69]
IMUX_CE_OPTINV[2]IMUX_CE[2]!MAIN[4][72]
IMUX_CE_OPTINV[3]IMUX_CE[3]!MAIN[4][78]
IMUX_TI_OPTINV[0]IMUX_TI[0]!MAIN[4][19]
IMUX_TI_OPTINV[1]IMUX_TI[1]!MAIN[4][27]
IMUX_TS_OPTINV[0]IMUX_TS[0]MAIN[4][38]
IMUX_TS_OPTINV[1]IMUX_TS[1]MAIN[4][30]
virtex2 INT_PPC switchbox INT muxes OMUX[0]
BitsDestination
MAIN[6][1]MAIN[7][2]MAIN[7][1]MAIN[7][0]MAIN[6][0]MAIN[6][3]MAIN[7][4]MAIN[7][5]MAIN[6][6]MAIN[6][9]OMUX[0]
Source
0000000000off
0001000001IMUX_SR[0]
0001000010IMUX_SR[2]
0001000100IMUX_G0_DATA[0]
0001001000IMUX_G0_DATA[1]
0001010000IMUX_G0_DATA[2]
0001100000IMUX_G0_DATA[3]
0010000001OUT_FAN[0]
0010000010OUT_FAN[1]
0010000100OUT_FAN[2]
0010001000OUT_FAN[3]
0010010000OUT_FAN[4]
0010100000OUT_FAN[5]
0100000001OUT_FAN[6]
0100000010OUT_FAN[7]
0100000100OUT_SEC[8]
0100001000OUT_SEC[9]
0100010000OUT_SEC[10]
0100100000OUT_SEC[11]
1000000001OUT_SEC[12]
1000000010OUT_SEC[13]
1000000100OUT_SEC[14]
1000001000OUT_SEC[15]
1000010000OUT_TEST[1]
1000100000OUT_TEST[0]
virtex2 INT_PPC switchbox INT muxes OMUX[1]
BitsDestination
MAIN[6][8]MAIN[7][7]MAIN[7][8]MAIN[7][9]MAIN[6][2]MAIN[7][3]MAIN[6][4]MAIN[6][5]MAIN[7][6]MAIN[6][7]OMUX[1]
Source
0000000000off
0001000001IMUX_SR[0]
0001000010IMUX_SR[2]
0001000100IMUX_G0_DATA[0]
0001001000IMUX_G0_DATA[1]
0001010000IMUX_G0_DATA[2]
0001100000IMUX_G0_DATA[3]
0010000001OUT_FAN[0]
0010000010OUT_FAN[1]
0010000100OUT_FAN[2]
0010001000OUT_FAN[3]
0010010000OUT_FAN[4]
0010100000OUT_FAN[5]
0100000001OUT_FAN[6]
0100000010OUT_FAN[7]
0100000100OUT_SEC[8]
0100001000OUT_SEC[9]
0100010000OUT_SEC[10]
0100100000OUT_SEC[11]
1000000001OUT_SEC[12]
1000000010OUT_SEC[13]
1000000100OUT_SEC[14]
1000001000OUT_SEC[15]
1000010000OUT_TEST[1]
1000100000OUT_TEST[0]
virtex2 INT_PPC switchbox INT muxes OMUX[2]
BitsDestination
MAIN[6][11]MAIN[7][12]MAIN[7][11]MAIN[7][10]MAIN[6][10]MAIN[6][13]MAIN[7][14]MAIN[7][15]MAIN[6][16]MAIN[6][19]OMUX[2]
Source
0000000000off
0001000001IMUX_SR[1]
0001000010IMUX_SR[3]
0001000100IMUX_G0_DATA[4]
0001001000IMUX_G0_DATA[5]
0001010000IMUX_G0_DATA[6]
0001100000IMUX_G0_DATA[7]
0010000001OUT_FAN[0]
0010000010OUT_FAN[1]
0010000100OUT_FAN[2]
0010001000OUT_FAN[3]
0010010000OUT_FAN[4]
0010100000OUT_FAN[5]
0100000001OUT_FAN[6]
0100000010OUT_FAN[7]
0100000100OUT_SEC[8]
0100001000OUT_SEC[9]
0100010000OUT_SEC[10]
0100100000OUT_SEC[11]
1000000001OUT_SEC[12]
1000000010OUT_SEC[13]
1000000100OUT_SEC[14]
1000001000OUT_SEC[15]
1000010000OUT_TEST[3]
1000100000OUT_TEST[2]
virtex2 INT_PPC switchbox INT muxes OMUX[3]
BitsDestination
MAIN[6][18]MAIN[7][17]MAIN[7][18]MAIN[7][19]MAIN[6][12]MAIN[7][13]MAIN[6][14]MAIN[6][15]MAIN[7][16]MAIN[6][17]OMUX[3]
Source
0000000000off
0001000001IMUX_SR[1]
0001000010IMUX_SR[3]
0001000100IMUX_G0_DATA[4]
0001001000IMUX_G0_DATA[5]
0001010000IMUX_G0_DATA[6]
0001100000IMUX_G0_DATA[7]
0010000001OUT_FAN[0]
0010000010OUT_FAN[1]
0010000100OUT_FAN[2]
0010001000OUT_FAN[3]
0010010000OUT_FAN[4]
0010100000OUT_FAN[5]
0100000001OUT_FAN[6]
0100000010OUT_FAN[7]
0100000100OUT_SEC[8]
0100001000OUT_SEC[9]
0100010000OUT_SEC[10]
0100100000OUT_SEC[11]
1000000001OUT_SEC[12]
1000000010OUT_SEC[13]
1000000100OUT_SEC[14]
1000001000OUT_SEC[15]
1000010000OUT_TEST[3]
1000100000OUT_TEST[2]
virtex2 INT_PPC switchbox INT muxes OMUX[4]
BitsDestination
MAIN[6][21]MAIN[7][22]MAIN[7][21]MAIN[7][20]MAIN[6][20]MAIN[6][23]MAIN[7][24]MAIN[7][25]MAIN[6][26]MAIN[6][29]OMUX[4]
Source
0000000000off
0001000001IMUX_TI[0]
0001000010IMUX_TI[1]
0001000100IMUX_G1_DATA[4]
0001001000IMUX_G1_DATA[5]
0001010000IMUX_G1_DATA[6]
0001100000IMUX_G1_DATA[7]
0010000001OUT_FAN[0]
0010000010OUT_FAN[1]
0010000100OUT_FAN[2]
0010001000OUT_FAN[3]
0010010000OUT_FAN[4]
0010100000OUT_FAN[5]
0100000001OUT_FAN[6]
0100000010OUT_FAN[7]
0100000100OUT_SEC[8]
0100001000OUT_SEC[9]
0100010000OUT_SEC[10]
0100100000OUT_SEC[11]
1000000001OUT_SEC[12]
1000000010OUT_SEC[13]
1000000100OUT_SEC[14]
1000001000OUT_SEC[15]
1000010000OUT_TEST[5]
1000100000OUT_TEST[4]
virtex2 INT_PPC switchbox INT muxes OMUX[5]
BitsDestination
MAIN[6][28]MAIN[7][27]MAIN[7][28]MAIN[7][29]MAIN[6][22]MAIN[7][23]MAIN[6][24]MAIN[6][25]MAIN[7][26]MAIN[6][27]OMUX[5]
Source
0000000000off
0001000001IMUX_TI[0]
0001000010IMUX_TI[1]
0001000100IMUX_G1_DATA[4]
0001001000IMUX_G1_DATA[5]
0001010000IMUX_G1_DATA[6]
0001100000IMUX_G1_DATA[7]
0010000001OUT_FAN[0]
0010000010OUT_FAN[1]
0010000100OUT_FAN[2]
0010001000OUT_FAN[3]
0010010000OUT_FAN[4]
0010100000OUT_FAN[5]
0100000001OUT_FAN[6]
0100000010OUT_FAN[7]
0100000100OUT_SEC[8]
0100001000OUT_SEC[9]
0100010000OUT_SEC[10]
0100100000OUT_SEC[11]
1000000001OUT_SEC[12]
1000000010OUT_SEC[13]
1000000100OUT_SEC[14]
1000001000OUT_SEC[15]
1000010000OUT_TEST[5]
1000100000OUT_TEST[4]
virtex2 INT_PPC switchbox INT muxes OMUX[6]
BitsDestination
MAIN[6][31]MAIN[7][32]MAIN[7][31]MAIN[7][30]MAIN[6][30]MAIN[6][33]MAIN[7][34]MAIN[7][35]MAIN[6][36]MAIN[6][39]OMUX[6]
Source
0000000000off
0001000001IMUX_TS[0]
0001000010IMUX_TS[1]
0001000100IMUX_G1_DATA[0]
0001001000IMUX_G1_DATA[1]
0001010000IMUX_G1_DATA[2]
0001100000IMUX_G1_DATA[3]
0010000001OUT_FAN[0]
0010000010OUT_FAN[1]
0010000100OUT_FAN[2]
0010001000OUT_FAN[3]
0010010000OUT_FAN[4]
0010100000OUT_FAN[5]
0100000001OUT_FAN[6]
0100000010OUT_FAN[7]
0100000100OUT_SEC[8]
0100001000OUT_SEC[9]
0100010000OUT_SEC[10]
0100100000OUT_SEC[11]
1000000001OUT_SEC[12]
1000000010OUT_SEC[13]
1000000100OUT_SEC[14]
1000001000OUT_SEC[15]
1000010000OUT_TEST[7]
1000100000OUT_TEST[6]
virtex2 INT_PPC switchbox INT muxes OMUX[7]
BitsDestination
MAIN[6][38]MAIN[7][37]MAIN[7][38]MAIN[7][39]MAIN[6][32]MAIN[7][33]MAIN[6][34]MAIN[6][35]MAIN[7][36]MAIN[6][37]OMUX[7]
Source
0000000000off
0001000001IMUX_TS[0]
0001000010IMUX_TS[1]
0001000100IMUX_G1_DATA[0]
0001001000IMUX_G1_DATA[1]
0001010000IMUX_G1_DATA[2]
0001100000IMUX_G1_DATA[3]
0010000001OUT_FAN[0]
0010000010OUT_FAN[1]
0010000100OUT_FAN[2]
0010001000OUT_FAN[3]
0010010000OUT_FAN[4]
0010100000OUT_FAN[5]
0100000001OUT_FAN[6]
0100000010OUT_FAN[7]
0100000100OUT_SEC[8]
0100001000OUT_SEC[9]
0100010000OUT_SEC[10]
0100100000OUT_SEC[11]
1000000001OUT_SEC[12]
1000000010OUT_SEC[13]
1000000100OUT_SEC[14]
1000001000OUT_SEC[15]
1000010000OUT_TEST[7]
1000100000OUT_TEST[6]
virtex2 INT_PPC switchbox INT muxes OMUX[8]
BitsDestination
MAIN[6][41]MAIN[7][42]MAIN[7][41]MAIN[7][40]MAIN[6][40]MAIN[6][43]MAIN[7][44]MAIN[7][45]MAIN[6][46]MAIN[6][49]OMUX[8]
Source
0000000000off
0001000001IMUX_CLK[0]
0001000010IMUX_CLK[1]
0001000100IMUX_G2_DATA[0]
0001001000IMUX_G2_DATA[1]
0001010000IMUX_G2_DATA[2]
0001100000IMUX_G2_DATA[3]
0010000001OUT_FAN[0]
0010000010OUT_FAN[1]
0010000100OUT_FAN[2]
0010001000OUT_FAN[3]
0010010000OUT_FAN[4]
0010100000OUT_FAN[5]
0100000001OUT_FAN[6]
0100000010OUT_FAN[7]
0100000100OUT_SEC[8]
0100001000OUT_SEC[9]
0100010000OUT_SEC[10]
0100100000OUT_SEC[11]
1000000001OUT_SEC[12]
1000000010OUT_SEC[13]
1000000100OUT_SEC[14]
1000001000OUT_SEC[15]
1000010000OUT_TEST[9]
1000100000OUT_TEST[8]
virtex2 INT_PPC switchbox INT muxes OMUX[9]
BitsDestination
MAIN[6][48]MAIN[7][47]MAIN[7][48]MAIN[7][49]MAIN[6][42]MAIN[7][43]MAIN[6][44]MAIN[6][45]MAIN[7][46]MAIN[6][47]OMUX[9]
Source
0000000000off
0001000001IMUX_CLK[0]
0001000010IMUX_CLK[1]
0001000100IMUX_G2_DATA[0]
0001001000IMUX_G2_DATA[1]
0001010000IMUX_G2_DATA[2]
0001100000IMUX_G2_DATA[3]
0010000001OUT_FAN[0]
0010000010OUT_FAN[1]
0010000100OUT_FAN[2]
0010001000OUT_FAN[3]
0010010000OUT_FAN[4]
0010100000OUT_FAN[5]
0100000001OUT_FAN[6]
0100000010OUT_FAN[7]
0100000100OUT_SEC[8]
0100001000OUT_SEC[9]
0100010000OUT_SEC[10]
0100100000OUT_SEC[11]
1000000001OUT_SEC[12]
1000000010OUT_SEC[13]
1000000100OUT_SEC[14]
1000001000OUT_SEC[15]
1000010000OUT_TEST[9]
1000100000OUT_TEST[8]
virtex2 INT_PPC switchbox INT muxes OMUX[10]
BitsDestination
MAIN[6][51]MAIN[7][52]MAIN[7][51]MAIN[7][50]MAIN[6][50]MAIN[6][53]MAIN[7][54]MAIN[7][55]MAIN[6][59]MAIN[6][56]OMUX[10]
Source
0000000000off
0001000001IMUX_CLK[2]
0001000010IMUX_CLK[3]
0001000100IMUX_G2_DATA[4]
0001001000IMUX_G2_DATA[5]
0001010000IMUX_G2_DATA[6]
0001100000IMUX_G2_DATA[7]
0010000001OUT_FAN[1]
0010000010OUT_FAN[0]
0010000100OUT_FAN[2]
0010001000OUT_FAN[3]
0010010000OUT_FAN[4]
0010100000OUT_FAN[5]
0100000001OUT_FAN[7]
0100000010OUT_FAN[6]
0100000100OUT_SEC[8]
0100001000OUT_SEC[9]
0100010000OUT_SEC[10]
0100100000OUT_SEC[11]
1000000001OUT_SEC[13]
1000000010OUT_SEC[12]
1000000100OUT_SEC[14]
1000001000OUT_SEC[15]
1000010000OUT_TEST[11]
1000100000OUT_TEST[10]
virtex2 INT_PPC switchbox INT muxes OMUX[11]
BitsDestination
MAIN[6][58]MAIN[7][57]MAIN[7][58]MAIN[7][59]MAIN[6][52]MAIN[7][53]MAIN[6][54]MAIN[6][55]MAIN[6][57]MAIN[7][56]OMUX[11]
Source
0000000000off
0001000001IMUX_CLK[2]
0001000010IMUX_CLK[3]
0001000100IMUX_G2_DATA[4]
0001001000IMUX_G2_DATA[5]
0001010000IMUX_G2_DATA[6]
0001100000IMUX_G2_DATA[7]
0010000001OUT_FAN[1]
0010000010OUT_FAN[0]
0010000100OUT_FAN[2]
0010001000OUT_FAN[3]
0010010000OUT_FAN[4]
0010100000OUT_FAN[5]
0100000001OUT_FAN[7]
0100000010OUT_FAN[6]
0100000100OUT_SEC[8]
0100001000OUT_SEC[9]
0100010000OUT_SEC[10]
0100100000OUT_SEC[11]
1000000001OUT_SEC[13]
1000000010OUT_SEC[12]
1000000100OUT_SEC[14]
1000001000OUT_SEC[15]
1000010000OUT_TEST[11]
1000100000OUT_TEST[10]
virtex2 INT_PPC switchbox INT muxes OMUX[12]
BitsDestination
MAIN[6][61]MAIN[7][62]MAIN[7][61]MAIN[7][60]MAIN[6][60]MAIN[6][63]MAIN[7][64]MAIN[7][65]MAIN[6][69]MAIN[6][66]OMUX[12]
Source
0000000000off
0001000001IMUX_CE[0]
0001000010IMUX_CE[1]
0001000100IMUX_G3_DATA[4]
0001001000IMUX_G3_DATA[5]
0001010000IMUX_G3_DATA[6]
0001100000IMUX_G3_DATA[7]
0010000001OUT_FAN[1]
0010000010OUT_FAN[0]
0010000100OUT_FAN[2]
0010001000OUT_FAN[3]
0010010000OUT_FAN[4]
0010100000OUT_FAN[5]
0100000001OUT_FAN[7]
0100000010OUT_FAN[6]
0100000100OUT_SEC[8]
0100001000OUT_SEC[9]
0100010000OUT_SEC[10]
0100100000OUT_SEC[11]
1000000001OUT_SEC[13]
1000000010OUT_SEC[12]
1000000100OUT_SEC[14]
1000001000OUT_SEC[15]
1000010000OUT_TEST[13]
1000100000OUT_TEST[12]
virtex2 INT_PPC switchbox INT muxes OMUX[13]
BitsDestination
MAIN[6][68]MAIN[7][67]MAIN[7][68]MAIN[7][69]MAIN[6][62]MAIN[7][63]MAIN[6][64]MAIN[6][65]MAIN[6][67]MAIN[7][66]OMUX[13]
Source
0000000000off
0001000001IMUX_CE[0]
0001000010IMUX_CE[1]
0001000100IMUX_G3_DATA[4]
0001001000IMUX_G3_DATA[5]
0001010000IMUX_G3_DATA[6]
0001100000IMUX_G3_DATA[7]
0010000001OUT_FAN[1]
0010000010OUT_FAN[0]
0010000100OUT_FAN[2]
0010001000OUT_FAN[3]
0010010000OUT_FAN[4]
0010100000OUT_FAN[5]
0100000001OUT_FAN[7]
0100000010OUT_FAN[6]
0100000100OUT_SEC[8]
0100001000OUT_SEC[9]
0100010000OUT_SEC[10]
0100100000OUT_SEC[11]
1000000001OUT_SEC[13]
1000000010OUT_SEC[12]
1000000100OUT_SEC[14]
1000001000OUT_SEC[15]
1000010000OUT_TEST[13]
1000100000OUT_TEST[12]
virtex2 INT_PPC switchbox INT muxes OMUX[14]
BitsDestination
MAIN[6][71]MAIN[7][72]MAIN[7][71]MAIN[7][70]MAIN[6][70]MAIN[6][73]MAIN[7][74]MAIN[7][75]MAIN[6][76]MAIN[6][79]OMUX[14]
Source
0000000000off
0001000001IMUX_CE[2]
0001000010IMUX_CE[3]
0001000100IMUX_G3_DATA[0]
0001001000IMUX_G3_DATA[1]
0001010000IMUX_G3_DATA[2]
0001100000IMUX_G3_DATA[3]
0010000001OUT_FAN[0]
0010000010OUT_FAN[1]
0010000100OUT_FAN[2]
0010001000OUT_FAN[3]
0010010000OUT_FAN[4]
0010100000OUT_FAN[5]
0100000001OUT_FAN[6]
0100000010OUT_FAN[7]
0100000100OUT_SEC[8]
0100001000OUT_SEC[9]
0100010000OUT_SEC[10]
0100100000OUT_SEC[11]
1000000001OUT_SEC[12]
1000000010OUT_SEC[13]
1000000100OUT_SEC[14]
1000001000OUT_SEC[15]
1000010000OUT_TEST[15]
1000100000OUT_TEST[14]
virtex2 INT_PPC switchbox INT muxes OMUX[15]
BitsDestination
MAIN[6][78]MAIN[7][77]MAIN[7][78]MAIN[7][79]MAIN[6][72]MAIN[7][73]MAIN[6][74]MAIN[6][75]MAIN[7][76]MAIN[6][77]OMUX[15]
Source
0000000000off
0001000001IMUX_CE[2]
0001000010IMUX_CE[3]
0001000100IMUX_G3_DATA[0]
0001001000IMUX_G3_DATA[1]
0001010000IMUX_G3_DATA[2]
0001100000IMUX_G3_DATA[3]
0010000001OUT_FAN[0]
0010000010OUT_FAN[1]
0010000100OUT_FAN[2]
0010001000OUT_FAN[3]
0010010000OUT_FAN[4]
0010100000OUT_FAN[5]
0100000001OUT_FAN[6]
0100000010OUT_FAN[7]
0100000100OUT_SEC[8]
0100001000OUT_SEC[9]
0100010000OUT_SEC[10]
0100100000OUT_SEC[11]
1000000001OUT_SEC[12]
1000000010OUT_SEC[13]
1000000100OUT_SEC[14]
1000001000OUT_SEC[15]
1000010000OUT_TEST[15]
1000100000OUT_TEST[14]
virtex2 INT_PPC switchbox INT muxes DBL_W0[0]
BitsDestination
MAIN[16][5]MAIN[16][6]MAIN[17][6]MAIN[17][5]MAIN[15][7]MAIN[14][5]MAIN[14][4]MAIN[15][6]DBL_W0[0]
Source
00000000off
00010001OMUX_S0
00010010HEX_E6[0]
00010100OUT_FAN[3]
00011000HEX_N6[0]
00100001OMUX_NW10
00100010HEX_S6[1]
00100100OUT_FAN[4]
00101000HEX_W6[0]
01000001DBL_W2[0]
01000010HEX_N3[0]
01000100HEX_S3[0]
01001000DBL_N3[9]
10000001DBL_W2_N[8]
10000010DBL_S1[0]
10000100DBL_S2[2]
10001000DBL_N1[0]
virtex2 INT_PPC switchbox INT muxes DBL_W0[1]
BitsDestination
MAIN[16][13]MAIN[16][14]MAIN[17][14]MAIN[17][13]MAIN[15][15]MAIN[14][13]MAIN[14][12]MAIN[15][14]DBL_W0[1]
Source
00000000off
00010001OMUX[2]
00010010HEX_E6[1]
00010100OUT_FAN[2]
00011000HEX_N6[1]
00100001OMUX_W1
00100010HEX_S6[2]
00100100OUT_FAN[5]
00101000HEX_W6[1]
01000001DBL_W2[1]
01000010HEX_N3[1]
01000100HEX_S3[1]
01001000DBL_N2[0]
10000001DBL_W2_N[9]
10000010DBL_S1[1]
10000100DBL_S2[3]
10001000DBL_N1[1]
virtex2 INT_PPC switchbox INT muxes DBL_W0[2]
BitsDestination
MAIN[15][23]MAIN[14][20]MAIN[15][22]MAIN[14][21]MAIN[16][22]MAIN[16][21]MAIN[17][22]MAIN[17][21]DBL_W0[2]
Source
00000000off
00010001OMUX[4]
00010010OUT_FAN[3]
00010100DBL_S2[4]
00011000HEX_S3[2]
00100001OMUX[6]
00100010OMUX_WN14
00100100DBL_W2[0]
00101000DBL_W2[2]
01000001HEX_E6[2]
01000010HEX_S6[3]
01000100DBL_S1[2]
01001000HEX_N3[2]
10000001HEX_N6[2]
10000010HEX_W6[2]
10000100DBL_N1[2]
10001000DBL_N2[1]
virtex2 INT_PPC switchbox INT muxes DBL_W0[3]
BitsDestination
MAIN[16][30]MAIN[16][29]MAIN[17][30]MAIN[17][29]MAIN[15][31]MAIN[14][29]MAIN[14][28]MAIN[15][30]DBL_W0[3]
Source
00000000off
00010001OMUX_W6
00010010HEX_E6[3]
00010100OUT_FAN[4]
00011000HEX_N6[3]
00100001OMUX_NW10
00100010HEX_S6[4]
00100100OUT_FAN[2]
00101000HEX_W6[3]
01000001DBL_W2[1]
01000010DBL_S1[3]
01000100DBL_S2[5]
01001000DBL_N1[3]
10000001DBL_W2[3]
10000010HEX_N3[3]
10000100HEX_S3[3]
10001000DBL_N2[2]
virtex2 INT_PPC switchbox INT muxes DBL_W0[4]
BitsDestination
MAIN[16][38]MAIN[16][37]MAIN[17][38]MAIN[17][37]MAIN[15][39]MAIN[14][37]MAIN[14][36]MAIN[15][38]DBL_W0[4]
Source
00000000off
00010001OMUX_WS1
00010010HEX_E6[4]
00010100OUT_FAN[5]
00011000HEX_N6[4]
00100001OMUX_N12
00100010HEX_S6[5]
00100100OUT_FAN[6]
00101000HEX_W6[4]
01000001DBL_W2[2]
01000010DBL_S1[4]
01000100DBL_S2[6]
01001000DBL_N1[4]
10000001DBL_W2[4]
10000010HEX_N3[4]
10000100HEX_S3[4]
10001000DBL_N2[3]
virtex2 INT_PPC switchbox INT muxes DBL_W0[5]
BitsDestination
MAIN[16][46]MAIN[16][45]MAIN[17][46]MAIN[17][45]MAIN[15][47]MAIN[14][45]MAIN[14][44]MAIN[15][46]DBL_W0[5]
Source
00000000off
00010001OMUX_S3
00010010HEX_E6[5]
00010100OUT_FAN[1]
00011000HEX_N6[5]
00100001OMUX_WN14
00100010HEX_S6[6]
00100100OUT_FAN[7]
00101000HEX_W6[5]
01000001DBL_W2[3]
01000010DBL_S1[5]
01000100DBL_S2[7]
01001000DBL_N1[5]
10000001DBL_W2[5]
10000010HEX_N3[5]
10000100HEX_S3[5]
10001000DBL_N2[4]
virtex2 INT_PPC switchbox INT muxes DBL_W0[6]
BitsDestination
MAIN[15][55]MAIN[14][52]MAIN[15][54]MAIN[14][53]MAIN[16][54]MAIN[16][53]MAIN[17][53]MAIN[17][54]DBL_W0[6]
Source
00000000off
00010001OMUX[11]
00010010OUT_FAN[0]
00010100DBL_S2[8]
00011000HEX_S3[6]
00100001OMUX_W9
00100010OMUX_SW5
00100100DBL_W2[4]
00101000DBL_W2[6]
01000001HEX_S6[7]
01000010HEX_E6[6]
01000100DBL_S1[6]
01001000HEX_N3[6]
10000001HEX_W6[6]
10000010HEX_N6[6]
10000100DBL_N1[6]
10001000DBL_N2[5]
virtex2 INT_PPC switchbox INT muxes DBL_W0[7]
BitsDestination
MAIN[16][62]MAIN[16][61]MAIN[17][61]MAIN[17][62]MAIN[15][63]MAIN[14][61]MAIN[14][60]MAIN[15][62]DBL_W0[7]
Source
00000000off
00010001OMUX[9]
00010010HEX_S6[8]
00010100OUT_FAN[1]
00011000HEX_W6[7]
00100001OMUX_WS1
00100010HEX_E6[7]
00100100OUT_FAN[6]
00101000HEX_N6[7]
01000001DBL_W2[5]
01000010DBL_S1[7]
01000100DBL_S2[9]
01001000DBL_N1[7]
10000001DBL_W2[7]
10000010HEX_N3[7]
10000100HEX_S3[7]
10001000DBL_N2[6]
virtex2 INT_PPC switchbox INT muxes DBL_W0[8]
BitsDestination
MAIN[16][70]MAIN[16][69]MAIN[17][69]MAIN[17][70]MAIN[15][71]MAIN[14][69]MAIN[14][68]MAIN[15][70]DBL_W0[8]
Source
00000000off
00010001OMUX[13]
00010010HEX_S6[9]
00010100OUT_FAN[0]
00011000HEX_W6[8]
00100001OMUX_W14
00100010HEX_E6[8]
00100100OUT_FAN[7]
00101000HEX_N6[8]
01000001DBL_W2[6]
01000010DBL_S1[8]
01000100DBL_S3[0]
01001000DBL_N1[8]
10000001DBL_W2[8]
10000010HEX_N3[8]
10000100HEX_S3[8]
10001000DBL_N2[7]
virtex2 INT_PPC switchbox INT muxes DBL_W0[9]
BitsDestination
MAIN[15][79]MAIN[14][76]MAIN[14][77]MAIN[15][78]MAIN[16][78]MAIN[16][77]MAIN[17][77]MAIN[17][78]DBL_W0[9]
Source
00000000off
00010001OMUX[13]
00010010OMUX_SW5
00010100DBL_W2[7]
00011000DBL_W2[9]
00100001OMUX_S0
00100010OMUX[15]
00100100DBL_S3[1]
00101000HEX_S3[9]
01000001HEX_S7[0]
01000010HEX_E6[9]
01000100DBL_S1[9]
01001000HEX_N3[9]
10000001HEX_W6[9]
10000010HEX_N6[9]
10000100DBL_N1[9]
10001000DBL_N2[8]
virtex2 INT_PPC switchbox INT muxes DBL_E0[0]
BitsDestination
MAIN[17][7]MAIN[17][4]MAIN[16][4]MAIN[16][7]MAIN[15][5]MAIN[14][7]MAIN[15][4]MAIN[14][6]DBL_E0[0]
Source
00000000off
00010001OMUX_E2
00010010HEX_S6[1]
00010100OUT_FAN[4]
00011000HEX_W6[0]
00100001OMUX_EN8
00100010HEX_E6[0]
00100100OUT_FAN[3]
00101000HEX_N6[0]
01000001DBL_E2[0]
01000010DBL_S1[0]
01000100DBL_S2[2]
01001000DBL_N1[0]
10000001DBL_E2[2]
10000010HEX_N3[0]
10000100HEX_S3[0]
10001000DBL_N3[9]
virtex2 INT_PPC switchbox INT muxes DBL_E0[1]
BitsDestination
MAIN[17][15]MAIN[17][12]MAIN[16][12]MAIN[16][15]MAIN[15][13]MAIN[14][15]MAIN[15][12]MAIN[14][14]DBL_E0[1]
Source
00000000off
00010001OMUX_S4
00010010HEX_S6[2]
00010100OUT_FAN[5]
00011000HEX_W6[1]
00100001OMUX_N10
00100010HEX_E6[1]
00100100OUT_FAN[2]
00101000HEX_N6[1]
01000001DBL_E2[1]
01000010DBL_S1[1]
01000100DBL_S2[3]
01001000DBL_N1[1]
10000001DBL_E2[3]
10000010HEX_N3[1]
10000100HEX_S3[1]
10001000DBL_N2[0]
virtex2 INT_PPC switchbox INT muxes DBL_E0[2]
BitsDestination
MAIN[15][21]MAIN[15][20]MAIN[14][22]MAIN[14][23]MAIN[17][23]MAIN[17][20]MAIN[16][23]MAIN[16][20]DBL_E0[2]
Source
00000000off
00010001OMUX[4]
00010010OUT_FAN[3]
00010100DBL_S2[4]
00011000HEX_S3[2]
00100001OMUX_NE12
00100010OMUX[6]
00100100DBL_E2[2]
00101000DBL_E2[4]
01000001HEX_E6[2]
01000010HEX_S6[3]
01000100DBL_S1[2]
01001000HEX_N3[2]
10000001HEX_N6[2]
10000010HEX_W6[2]
10000100DBL_N1[2]
10001000DBL_N2[1]
virtex2 INT_PPC switchbox INT muxes DBL_E0[3]
BitsDestination
MAIN[17][31]MAIN[17][28]MAIN[16][28]MAIN[16][31]MAIN[15][29]MAIN[14][31]MAIN[15][28]MAIN[14][30]DBL_E0[3]
Source
00000000off
00010001OMUX_SE3
00010010HEX_S6[4]
00010100OUT_FAN[2]
00011000HEX_W6[3]
00100001OMUX_EN8
00100010HEX_E6[3]
00100100OUT_FAN[4]
00101000HEX_N6[3]
01000001DBL_E2[3]
01000010DBL_S1[3]
01000100DBL_S2[5]
01001000DBL_N1[3]
10000001DBL_E2[5]
10000010HEX_N3[3]
10000100HEX_S3[3]
10001000DBL_N2[2]
virtex2 INT_PPC switchbox INT muxes DBL_E0[4]
BitsDestination
MAIN[17][39]MAIN[17][36]MAIN[16][39]MAIN[16][36]MAIN[15][37]MAIN[14][39]MAIN[15][36]MAIN[14][38]DBL_E0[4]
Source
00000000off
00010001OMUX_E7
00010010HEX_E6[4]
00010100OUT_FAN[5]
00011000HEX_N6[4]
00100001OMUX_E8
00100010HEX_S6[5]
00100100OUT_FAN[6]
00101000HEX_W6[4]
01000001DBL_E2[4]
01000010DBL_S1[4]
01000100DBL_S2[6]
01001000DBL_N1[4]
10000001DBL_E2[6]
10000010HEX_N3[4]
10000100HEX_S3[4]
10001000DBL_N2[3]
virtex2 INT_PPC switchbox INT muxes DBL_E0[5]
BitsDestination
MAIN[17][47]MAIN[17][44]MAIN[16][44]MAIN[16][47]MAIN[15][45]MAIN[14][47]MAIN[15][44]MAIN[14][46]DBL_E0[5]
Source
00000000off
00010001OMUX_ES7
00010010HEX_S6[6]
00010100OUT_FAN[7]
00011000HEX_W6[5]
00100001OMUX_NE12
00100010HEX_E6[5]
00100100OUT_FAN[1]
00101000HEX_N6[5]
01000001DBL_E2[5]
01000010DBL_S1[5]
01000100DBL_S2[7]
01001000DBL_N1[5]
10000001DBL_E2[7]
10000010HEX_N3[5]
10000100HEX_S3[5]
10001000DBL_N2[4]
virtex2 INT_PPC switchbox INT muxes DBL_E0[6]
BitsDestination
MAIN[17][55]MAIN[17][52]MAIN[16][55]MAIN[16][52]MAIN[15][53]MAIN[15][52]MAIN[14][55]MAIN[14][54]DBL_E0[6]
Source
00000000off
00010001OMUX[9]
00010010OUT_FAN[0]
00010100HEX_E6[6]
00011000HEX_N6[6]
00100001OMUX_SE3
00100010OMUX[11]
00100100HEX_S6[7]
00101000HEX_W6[6]
01000001DBL_E2[6]
01000010DBL_S2[8]
01000100DBL_S1[6]
01001000DBL_N1[6]
10000001DBL_E2[8]
10000010HEX_S3[6]
10000100HEX_N3[6]
10001000DBL_N2[5]
virtex2 INT_PPC switchbox INT muxes DBL_E0[7]
BitsDestination
MAIN[17][63]MAIN[17][60]MAIN[16][60]MAIN[16][63]MAIN[15][61]MAIN[14][63]MAIN[15][60]MAIN[14][62]DBL_E0[7]
Source
00000000off
00010001OMUX_S5
00010010HEX_S6[8]
00010100OUT_FAN[1]
00011000HEX_W6[7]
00100001OMUX_N11
00100010HEX_E6[7]
00100100OUT_FAN[6]
00101000HEX_N6[7]
01000001DBL_E2[7]
01000010DBL_S1[7]
01000100DBL_S2[9]
01001000DBL_N1[7]
10000001DBL_E2[9]
10000010HEX_N3[7]
10000100HEX_S3[7]
10001000DBL_N2[6]
virtex2 INT_PPC switchbox INT muxes DBL_E0[8]
BitsDestination
MAIN[17][71]MAIN[17][68]MAIN[16][68]MAIN[16][71]MAIN[15][69]MAIN[14][71]MAIN[15][68]MAIN[14][70]DBL_E0[8]
Source
00000000off
00010001OMUX_ES7
00010010HEX_S6[9]
00010100OUT_FAN[0]
00011000HEX_W6[8]
00100001OMUX_E13
00100010HEX_E6[8]
00100100OUT_FAN[7]
00101000HEX_N6[8]
01000001DBL_E2[8]
01000010DBL_S1[8]
01000100DBL_S3[0]
01001000DBL_N1[8]
10000001DBL_E2_S[0]
10000010HEX_N3[8]
10000100HEX_S3[8]
10001000DBL_N2[7]
virtex2 INT_PPC switchbox INT muxes DBL_E0[9]
BitsDestination
MAIN[17][79]MAIN[17][76]MAIN[16][79]MAIN[16][76]MAIN[15][77]MAIN[15][76]MAIN[14][78]MAIN[14][79]DBL_E0[9]
Source
00000000off
00010001OMUX[15]
00010010OMUX_N15
00010100HEX_E6[9]
00011000HEX_N6[9]
00100001OMUX_S0
00100010OMUX_S2
00100100HEX_S7[0]
00101000HEX_W6[9]
01000001DBL_S3[1]
01000010DBL_E2[9]
01000100DBL_S1[9]
01001000DBL_N1[9]
10000001HEX_S3[9]
10000010DBL_E2_S[1]
10000100HEX_N3[9]
10001000DBL_N2[8]
virtex2 INT_PPC switchbox INT muxes DBL_S0[0]
BitsDestination
MAIN[15][0]MAIN[15][1]MAIN[14][2]MAIN[14][3]MAIN[17][3]MAIN[17][0]MAIN[16][3]MAIN[16][0]DBL_S0[0]
Source
00000000off
00010001OMUX[0]
00010010OUT_FAN[3]
00010100DBL_E2[1]
00011000HEX_E3[0]
00100001OMUX[2]
00100010OMUX_S0
00100100DBL_S2[0]
00101000DBL_S2[2]
01000001HEX_W6_N[9]
01000010HEX_N6[0]
01000100DBL_W1[0]
01001000DBL_W2_N[8]
10000001HEX_S6[0]
10000010HEX_E6[0]
10000100DBL_E1[0]
10001000HEX_W3[0]
virtex2 INT_PPC switchbox INT muxes DBL_S0[1]
BitsDestination
MAIN[17][11]MAIN[17][8]MAIN[16][8]MAIN[16][11]MAIN[14][11]MAIN[15][8]MAIN[15][9]MAIN[14][10]DBL_S0[1]
Source
00000000off
00010001OMUX[2]
00010010HEX_N6[1]
00010100HEX_E6[1]
00011000OUT_FAN[2]
00100001OMUX_E2
00100010HEX_W6[0]
00100100HEX_S6[1]
00101000OUT_FAN[4]
01000001DBL_S2[1]
01000010DBL_W1[1]
01000100DBL_E1[1]
01001000DBL_E2[2]
10000001DBL_S2[3]
10000010DBL_W2_N[9]
10000100HEX_W3[1]
10001000HEX_E3[1]
virtex2 INT_PPC switchbox INT muxes DBL_S0[2]
BitsDestination
MAIN[15][16]MAIN[15][17]MAIN[14][18]MAIN[14][19]MAIN[17][19]MAIN[17][16]MAIN[16][16]MAIN[16][19]DBL_S0[2]
Source
00000000off
00010001OMUX[4]
00010010OUT_FAN[5]
00010100DBL_E2[3]
00011000HEX_E3[2]
00100001OMUX[6]
00100010OMUX_S4
00100100DBL_S2[2]
00101000DBL_S2[4]
01000001HEX_N6[2]
01000010HEX_W6[1]
01000100DBL_W1[2]
01001000DBL_W2[0]
10000001HEX_E6[2]
10000010HEX_S6[2]
10000100DBL_E1[2]
10001000HEX_W3[2]
virtex2 INT_PPC switchbox INT muxes DBL_S0[3]
BitsDestination
MAIN[17][27]MAIN[17][24]MAIN[16][27]MAIN[16][24]MAIN[14][27]MAIN[15][24]MAIN[15][25]MAIN[14][26]DBL_S0[3]
Source
00000000off
00010001OMUX[6]
00010010HEX_W6[2]
00010100HEX_S6[3]
00011000OUT_FAN[3]
00100001OMUX_W6
00100010HEX_N6[3]
00100100HEX_E6[3]
00101000OUT_FAN[4]
01000001DBL_S2[3]
01000010DBL_W1[3]
01000100DBL_E1[3]
01001000DBL_E2[4]
10000001DBL_S2[5]
10000010DBL_W2[1]
10000100HEX_W3[3]
10001000HEX_E3[3]
virtex2 INT_PPC switchbox INT muxes DBL_S0[4]
BitsDestination
MAIN[17][35]MAIN[17][32]MAIN[16][32]MAIN[16][35]MAIN[14][35]MAIN[15][32]MAIN[15][33]MAIN[14][34]DBL_S0[4]
Source
00000000off
00010001OMUX_WS1
00010010HEX_N6[4]
00010100HEX_E6[4]
00011000OUT_FAN[5]
00100001OMUX_SE3
00100010HEX_W6[3]
00100100HEX_S6[4]
00101000OUT_FAN[2]
01000001DBL_S2[4]
01000010DBL_W1[4]
01000100DBL_E1[4]
01001000DBL_E2[5]
10000001DBL_S2[6]
10000010DBL_W2[2]
10000100HEX_W3[4]
10001000HEX_E3[4]
virtex2 INT_PPC switchbox INT muxes DBL_S0[5]
BitsDestination
MAIN[17][43]MAIN[17][40]MAIN[16][40]MAIN[16][43]MAIN[14][43]MAIN[15][40]MAIN[15][41]MAIN[14][42]DBL_S0[5]
Source
00000000off
00010001OMUX_S3
00010010HEX_N6[5]
00010100HEX_E6[5]
00011000OUT_FAN[1]
00100001OMUX_E8
00100010HEX_W6[4]
00100100HEX_S6[5]
00101000OUT_FAN[6]
01000001DBL_S2[5]
01000010DBL_W1[5]
01000100DBL_E1[5]
01001000DBL_E2[6]
10000001DBL_S2[7]
10000010DBL_W2[3]
10000100HEX_W3[5]
10001000HEX_E3[5]
virtex2 INT_PPC switchbox INT muxes DBL_S0[6]
BitsDestination
MAIN[17][51]MAIN[17][48]MAIN[16][48]MAIN[16][51]MAIN[14][51]MAIN[15][48]MAIN[15][49]MAIN[14][50]DBL_S0[6]
Source
00000000off
00010001OMUX_SW5
00010010HEX_N6[6]
00010100HEX_E6[6]
00011000OUT_FAN[0]
00100001OMUX_ES7
00100010HEX_W6[5]
00100100HEX_S6[6]
00101000OUT_FAN[7]
01000001DBL_S2[6]
01000010DBL_W1[6]
01000100DBL_E1[6]
01001000DBL_E2[7]
10000001DBL_S2[8]
10000010DBL_W2[4]
10000100HEX_W3[6]
10001000HEX_E3[6]
virtex2 INT_PPC switchbox INT muxes DBL_S0[7]
BitsDestination
MAIN[15][56]MAIN[15][57]MAIN[14][58]MAIN[14][59]MAIN[17][59]MAIN[17][56]MAIN[16][59]MAIN[16][56]DBL_S0[7]
Source
00000000off
00010001OMUX[11]
00010010OUT_FAN[6]
00010100DBL_E2[8]
00011000HEX_E3[7]
00100001OMUX_SE3
00100010OMUX_WS1
00100100DBL_S2[7]
00101000DBL_S2[9]
01000001HEX_W6[6]
01000010HEX_N6[7]
01000100DBL_W1[7]
01001000DBL_W2[5]
10000001HEX_S6[7]
10000010HEX_E6[7]
10000100DBL_E1[7]
10001000HEX_W3[7]
virtex2 INT_PPC switchbox INT muxes DBL_S0[8]
BitsDestination
MAIN[17][67]MAIN[17][64]MAIN[16][67]MAIN[16][64]MAIN[14][67]MAIN[15][64]MAIN[15][65]MAIN[14][66]DBL_S0[8]
Source
00000000off
00010001OMUX_S5
00010010HEX_W6[7]
00010100HEX_S6[8]
00011000OUT_FAN[1]
00100001OMUX_W14
00100010HEX_N6[8]
00100100HEX_E6[8]
00101000OUT_FAN[7]
01000001DBL_S2[8]
01000010DBL_W1[8]
01000100DBL_E1[8]
01001000DBL_E2[9]
10000001DBL_S3[0]
10000010DBL_W2[6]
10000100HEX_W3[8]
10001000HEX_E3[8]
virtex2 INT_PPC switchbox INT muxes DBL_S0[9]
BitsDestination
MAIN[15][72]MAIN[15][73]MAIN[14][74]MAIN[14][75]MAIN[17][75]MAIN[17][72]MAIN[16][72]MAIN[16][75]DBL_S0[9]
Source
00000000off
00010001OMUX[15]
00010010OUT_FAN[0]
00010100DBL_E2_S[0]
00011000HEX_E3[9]
00100001OMUX_SW5
00100010OMUX_ES7
00100100DBL_S2[9]
00101000DBL_S3[1]
01000001HEX_N6[9]
01000010HEX_W6[8]
01000100DBL_W1[9]
01001000DBL_W2[7]
10000001HEX_E6[9]
10000010HEX_S6[9]
10000100DBL_E1[9]
10001000HEX_W3[9]
virtex2 INT_PPC switchbox INT muxes DBL_N0[0]
BitsDestination
MAIN[14][0]MAIN[15][3]MAIN[15][2]MAIN[14][1]MAIN[16][2]MAIN[16][1]MAIN[17][2]MAIN[17][1]DBL_N0[0]
Source
00000000off
00010001OMUX[0]
00010010OUT_FAN[3]
00010100DBL_E2[1]
00011000HEX_E3[0]
00100001OMUX_N13
00100010OMUX_EN8
00100100DBL_N3[8]
00101000DBL_N2[0]
01000001HEX_W6_N[9]
01000010HEX_N6[0]
01000100DBL_W1[0]
01001000DBL_W2_N[8]
10000001HEX_S6[0]
10000010HEX_E6[0]
10000100DBL_E1[0]
10001000HEX_W3[0]
virtex2 INT_PPC switchbox INT muxes DBL_N0[1]
BitsDestination
MAIN[16][10]MAIN[16][9]MAIN[17][9]MAIN[17][10]MAIN[14][9]MAIN[14][8]MAIN[15][11]MAIN[15][10]DBL_N0[1]
Source
00000000off
00010001OMUX_N10
00010010HEX_N6[1]
00010100HEX_E6[1]
00011000OUT_FAN[2]
00100001OMUX_NW10
00100010HEX_W6[0]
00100100HEX_S6[1]
00101000OUT_FAN[4]
01000001DBL_N3[9]
01000010DBL_W1[1]
01000100DBL_E1[1]
01001000DBL_E2[2]
10000001DBL_N2[1]
10000010DBL_W2_N[9]
10000100HEX_W3[1]
10001000HEX_E3[1]
virtex2 INT_PPC switchbox INT muxes DBL_N0[2]
BitsDestination
MAIN[14][16]MAIN[15][19]MAIN[15][18]MAIN[14][17]MAIN[16][18]MAIN[16][17]MAIN[17][17]MAIN[17][18]DBL_N0[2]
Source
00000000off
00010001OMUX[4]
00010010OUT_FAN[5]
00010100DBL_E2[3]
00011000HEX_E3[2]
00100001OMUX_NE12
00100010OMUX_W1
00100100DBL_N2[0]
00101000DBL_N2[2]
01000001HEX_N6[2]
01000010HEX_W6[1]
01000100DBL_W1[2]
01001000DBL_W2[0]
10000001HEX_E6[2]
10000010HEX_S6[2]
10000100DBL_E1[2]
10001000HEX_W3[2]
virtex2 INT_PPC switchbox INT muxes DBL_N0[3]
BitsDestination
MAIN[16][26]MAIN[16][25]MAIN[17][25]MAIN[17][26]MAIN[14][25]MAIN[14][24]MAIN[15][27]MAIN[15][26]DBL_N0[3]
Source
00000000off
00010001OMUX_EN8
00010010HEX_N6[3]
00010100HEX_E6[3]
00011000OUT_FAN[4]
00100001OMUX_WN14
00100010HEX_W6[2]
00100100HEX_S6[3]
00101000OUT_FAN[3]
01000001DBL_N2[1]
01000010DBL_W1[3]
01000100DBL_E1[3]
01001000DBL_E2[4]
10000001DBL_N2[3]
10000010DBL_W2[1]
10000100HEX_W3[3]
10001000HEX_E3[3]
virtex2 INT_PPC switchbox INT muxes DBL_N0[4]
BitsDestination
MAIN[16][34]MAIN[16][33]MAIN[17][33]MAIN[17][34]MAIN[14][33]MAIN[14][32]MAIN[15][35]MAIN[15][34]DBL_N0[4]
Source
00000000off
00010001OMUX_E7
00010010HEX_N6[4]
00010100HEX_E6[4]
00011000OUT_FAN[5]
00100001OMUX_NW10
00100010HEX_W6[3]
00100100HEX_S6[4]
00101000OUT_FAN[2]
01000001DBL_N2[2]
01000010DBL_W1[4]
01000100DBL_E1[4]
01001000DBL_E2[5]
10000001DBL_N2[4]
10000010DBL_W2[2]
10000100HEX_W3[4]
10001000HEX_E3[4]
virtex2 INT_PPC switchbox INT muxes DBL_N0[5]
BitsDestination
MAIN[16][42]MAIN[16][41]MAIN[17][42]MAIN[17][41]MAIN[14][41]MAIN[14][40]MAIN[15][43]MAIN[15][42]DBL_N0[5]
Source
00000000off
00010001OMUX_N12
00010010HEX_W6[4]
00010100HEX_S6[5]
00011000OUT_FAN[6]
00100001OMUX_NE12
00100010HEX_N6[5]
00100100HEX_E6[5]
00101000OUT_FAN[1]
01000001DBL_N2[3]
01000010DBL_W1[5]
01000100DBL_E1[5]
01001000DBL_E2[6]
10000001DBL_N2[5]
10000010DBL_W2[3]
10000100HEX_W3[5]
10001000HEX_E3[5]
virtex2 INT_PPC switchbox INT muxes DBL_N0[6]
BitsDestination
MAIN[16][50]MAIN[16][49]MAIN[17][49]MAIN[17][50]MAIN[14][49]MAIN[14][48]MAIN[15][51]MAIN[15][50]DBL_N0[6]
Source
00000000off
00010001OMUX[9]
00010010HEX_N6[6]
00010100HEX_E6[6]
00011000OUT_FAN[0]
00100001OMUX_WN14
00100010HEX_W6[5]
00100100HEX_S6[6]
00101000OUT_FAN[7]
01000001DBL_N2[4]
01000010DBL_W1[6]
01000100DBL_E1[6]
01001000DBL_E2[7]
10000001DBL_N2[6]
10000010DBL_W2[4]
10000100HEX_W3[6]
10001000HEX_E3[6]
virtex2 INT_PPC switchbox INT muxes DBL_N0[7]
BitsDestination
MAIN[14][56]MAIN[15][59]MAIN[15][58]MAIN[14][57]MAIN[16][58]MAIN[16][57]MAIN[17][58]MAIN[17][57]DBL_N0[7]
Source
00000000off
00010001OMUX[11]
00010010OUT_FAN[6]
00010100DBL_E2[8]
00011000HEX_E3[7]
00100001OMUX_W9
00100010OMUX_N11
00100100DBL_N2[5]
00101000DBL_N2[7]
01000001HEX_W6[6]
01000010HEX_N6[7]
01000100DBL_W1[7]
01001000DBL_W2[5]
10000001HEX_S6[7]
10000010HEX_E6[7]
10000100DBL_E1[7]
10001000HEX_W3[7]
virtex2 INT_PPC switchbox INT muxes DBL_N0[8]
BitsDestination
MAIN[16][66]MAIN[16][65]MAIN[17][66]MAIN[17][65]MAIN[14][65]MAIN[14][64]MAIN[15][67]MAIN[15][66]DBL_N0[8]
Source
00000000off
00010001OMUX[9]
00010010HEX_W6[7]
00010100HEX_S6[8]
00011000OUT_FAN[1]
00100001OMUX_E13
00100010HEX_N6[8]
00100100HEX_E6[8]
00101000OUT_FAN[7]
01000001DBL_N2[6]
01000010DBL_W1[8]
01000100DBL_E1[8]
01001000DBL_E2[9]
10000001DBL_N2[8]
10000010DBL_W2[6]
10000100HEX_W3[8]
10001000HEX_E3[8]
virtex2 INT_PPC switchbox INT muxes DBL_N0[9]
BitsDestination
MAIN[16][74]MAIN[16][73]MAIN[17][74]MAIN[17][73]MAIN[14][72]MAIN[15][75]MAIN[14][73]MAIN[15][74]DBL_N0[9]
Source
00000000off
00010001OMUX[13]
00010010OUT_FAN[0]
00010100HEX_W6[8]
00011000HEX_S6[9]
00100001OMUX_N15
00100010OMUX[15]
00100100HEX_N6[9]
00101000HEX_E6[9]
01000001DBL_N2[7]
01000010DBL_E2_S[0]
01000100DBL_W1[9]
01001000DBL_E1[9]
10000001DBL_N2[9]
10000010HEX_E3[9]
10000100DBL_W2[7]
10001000HEX_W3[9]
virtex2 INT_PPC switchbox INT muxes HEX_W0[0]
BitsDestination
MAIN[20][4]MAIN[20][6]MAIN[20][5]MAIN[18][4]MAIN[19][6]MAIN[18][6]MAIN[19][4]HEX_W0[0]
Source
0000000off
0010001OMUX_S0
0010010HEX_S3[0]
0010100HEX_N3[0]
0011000LH[6]
0100001OUT_FAN[4]
0100010OMUX_NW10
0100100HEX_W6[0]
0101000HEX_W6_N[8]
1000001OUT_FAN[3]
1000010LH[18]
1000100HEX_N7[9]
1001000HEX_S6[2]
virtex2 INT_PPC switchbox INT muxes HEX_W0[1]
BitsDestination
MAIN[21][12]MAIN[20][15]MAIN[21][14]MAIN[18][13]MAIN[19][15]MAIN[18][15]MAIN[19][13]HEX_W0[1]
Source
0000000off
0010001OMUX[2]
0010010OUT_FAN[5]
0010100HEX_W6[1]
0011000HEX_W6_N[9]
0100001LH[0]
0100010OMUX_W1
0100100HEX_S3[1]
0101000HEX_N3[1]
1000001OUT_FAN[2]
1000010LH[12]
1000100HEX_N6[0]
1001000HEX_S6[3]
virtex2 INT_PPC switchbox INT muxes HEX_W0[2]
BitsDestination
MAIN[20][22]MAIN[20][21]MAIN[20][20]MAIN[19][22]MAIN[18][20]MAIN[18][22]MAIN[19][20]HEX_W0[2]
Source
0000000off
0010001OMUX[4]
0010010LH[18]
0010100HEX_S6[4]
0011000HEX_N6[1]
0100001OMUX[6]
0100010HEX_S3[2]
0100100LH[6]
0101000HEX_N3[2]
1000001OUT_FAN[3]
1000010OMUX_WN14
1000100HEX_W6[0]
1001000HEX_W6[2]
virtex2 INT_PPC switchbox INT muxes HEX_W0[3]
BitsDestination
MAIN[21][28]MAIN[20][31]MAIN[21][30]MAIN[19][31]MAIN[18][29]MAIN[18][31]MAIN[19][29]HEX_W0[3]
Source
0000000off
0010001OMUX_W6
0010010OUT_FAN[2]
0010100HEX_W6[1]
0011000HEX_W6[3]
0100001LH[0]
0100010OMUX_NW10
0100100HEX_N3[3]
0101000HEX_S3[3]
1000001OUT_FAN[4]
1000010LH[12]
1000100HEX_S6[5]
1001000HEX_N6[2]
virtex2 INT_PPC switchbox INT muxes HEX_W0[4]
BitsDestination
MAIN[20][36]MAIN[20][38]MAIN[20][37]MAIN[19][38]MAIN[18][36]MAIN[18][38]MAIN[19][36]HEX_W0[4]
Source
0000000off
0010001OMUX_WS1
0010010HEX_S3[4]
0010100LH[6]
0011000HEX_N3[4]
0100001OUT_FAN[6]
0100010OMUX_N12
0100100HEX_W6[2]
0101000HEX_W6[4]
1000001OUT_FAN[5]
1000010LH[18]
1000100HEX_S6[6]
1001000HEX_N6[3]
virtex2 INT_PPC switchbox INT muxes HEX_W0[5]
BitsDestination
MAIN[21][44]MAIN[20][47]MAIN[21][46]MAIN[19][47]MAIN[18][45]MAIN[18][47]MAIN[19][45]HEX_W0[5]
Source
0000000off
0010001OMUX_S3
0010010OUT_FAN[7]
0010100HEX_W6[3]
0011000HEX_W6[5]
0100001LH[0]
0100010OMUX_WN14
0100100HEX_N3[5]
0101000HEX_S3[5]
1000001OUT_FAN[1]
1000010LH[12]
1000100HEX_S6[7]
1001000HEX_N6[4]
virtex2 INT_PPC switchbox INT muxes HEX_W0[6]
BitsDestination
MAIN[20][52]MAIN[20][53]MAIN[20][54]MAIN[19][54]MAIN[18][52]MAIN[18][54]MAIN[19][52]HEX_W0[6]
Source
0000000off
0010001OMUX[11]
0010010OMUX_W9
0010100HEX_W6[4]
0011000HEX_W6[6]
0100001OMUX_SW5
0100010HEX_S3[6]
0100100LH[6]
0101000HEX_N3[6]
1000001OUT_FAN[0]
1000010LH[18]
1000100HEX_S6[8]
1001000HEX_N6[5]
virtex2 INT_PPC switchbox INT muxes HEX_W0[7]
BitsDestination
MAIN[21][60]MAIN[21][62]MAIN[20][63]MAIN[19][63]MAIN[18][61]MAIN[19][61]MAIN[18][63]HEX_W0[7]
Source
0000000off
0010001OMUX[9]
0010010LH[0]
0010100HEX_N3[7]
0011000HEX_S3[7]
0100001OUT_FAN[1]
0100010OMUX_WS1
0100100HEX_W6[5]
0101000HEX_W6[7]
1000001LH[12]
1000010OUT_FAN[6]
1000100HEX_S6[9]
1001000HEX_N6[6]
virtex2 INT_PPC switchbox INT muxes HEX_W0[8]
BitsDestination
MAIN[20][68]MAIN[20][69]MAIN[20][70]MAIN[19][70]MAIN[18][68]MAIN[19][68]MAIN[18][70]HEX_W0[8]
Source
0000000off
0010001OMUX[13]
0010010OUT_FAN[0]
0010100HEX_W6[6]
0011000HEX_W6[8]
0100001HEX_S3[8]
0100010OMUX_W14
0100100LH[6]
0101000HEX_N3[8]
1000001LH[18]
1000010OUT_FAN[7]
1000100HEX_S7[0]
1001000HEX_N6[7]
virtex2 INT_PPC switchbox INT muxes HEX_W0[9]
BitsDestination
MAIN[21][78]MAIN[21][76]MAIN[20][79]MAIN[19][79]MAIN[18][77]MAIN[19][77]MAIN[18][79]HEX_W0[9]
Source
0000000off
0010001OMUX[13]
0010010LH[0]
0010100HEX_N3[9]
0011000HEX_S3[9]
0100001LH[12]
0100010OMUX[15]
0100100HEX_S7[1]
0101000HEX_N6[8]
1000001OMUX_S0
1000010OMUX_SW5
1000100HEX_W6[7]
1001000HEX_W6[9]
virtex2 INT_PPC switchbox INT muxes HEX_E0[0]
BitsDestination
MAIN[21][4]MAIN[21][6]MAIN[20][7]MAIN[19][7]MAIN[18][5]MAIN[19][5]MAIN[18][7]HEX_E0[0]
Source
0000000off
0010001OMUX_E2
0010010LH[6]
0010100HEX_N3[0]
0011000HEX_S3[0]
0100001OUT_FAN[4]
0100010OMUX_EN8
0100100HEX_E6[0]
0101000HEX_E6[2]
1000001LH[18]
1000010OUT_FAN[3]
1000100HEX_S6[2]
1001000HEX_N7[9]
virtex2 INT_PPC switchbox INT muxes HEX_E0[1]
BitsDestination
MAIN[20][12]MAIN[20][13]MAIN[20][14]MAIN[19][14]MAIN[18][12]MAIN[19][12]MAIN[18][14]HEX_E0[1]
Source
0000000off
0010001OMUX_S4
0010010OUT_FAN[5]
0010100HEX_E6[1]
0011000HEX_E6[3]
0100001HEX_S3[1]
0100010OMUX_N10
0100100LH[0]
0101000HEX_N3[1]
1000001LH[12]
1000010OUT_FAN[2]
1000100HEX_S6[3]
1001000HEX_N6[0]
virtex2 INT_PPC switchbox INT muxes HEX_E0[2]
BitsDestination
MAIN[21][22]MAIN[20][23]MAIN[21][20]MAIN[19][23]MAIN[18][21]MAIN[18][23]MAIN[19][21]HEX_E0[2]
Source
0000000off
0010001OMUX[4]
0010010LH[18]
0010100HEX_S6[4]
0011000HEX_N6[1]
0100001LH[6]
0100010OMUX[6]
0100100HEX_N3[2]
0101000HEX_S3[2]
1000001OMUX_NE12
1000010OUT_FAN[3]
1000100HEX_E6[2]
1001000HEX_E6[4]
virtex2 INT_PPC switchbox INT muxes HEX_E0[3]
BitsDestination
MAIN[20][28]MAIN[20][29]MAIN[20][30]MAIN[19][30]MAIN[18][28]MAIN[19][28]MAIN[18][30]HEX_E0[3]
Source
0000000off
0010001OMUX_SE3
0010010OUT_FAN[2]
0010100HEX_E6[3]
0011000HEX_E6[5]
0100001HEX_S3[3]
0100010OMUX_EN8
0100100LH[0]
0101000HEX_N3[3]
1000001LH[12]
1000010OUT_FAN[4]
1000100HEX_S6[5]
1001000HEX_N6[2]
virtex2 INT_PPC switchbox INT muxes HEX_E0[4]
BitsDestination
MAIN[21][36]MAIN[20][39]MAIN[21][38]MAIN[19][39]MAIN[18][37]MAIN[18][39]MAIN[19][37]HEX_E0[4]
Source
0000000off
0010001OMUX_E7
0010010OUT_FAN[6]
0010100HEX_E6[4]
0011000HEX_E6[6]
0100001LH[6]
0100010OMUX_E8
0100100HEX_N3[4]
0101000HEX_S3[4]
1000001OUT_FAN[5]
1000010LH[18]
1000100HEX_S6[6]
1001000HEX_N6[3]
virtex2 INT_PPC switchbox INT muxes HEX_E0[5]
BitsDestination
MAIN[20][44]MAIN[20][45]MAIN[20][46]MAIN[19][46]MAIN[18][44]MAIN[19][44]MAIN[18][46]HEX_E0[5]
Source
0000000off
0010001OMUX_ES7
0010010OUT_FAN[7]
0010100HEX_E6[5]
0011000HEX_E6[7]
0100001HEX_S3[5]
0100010OMUX_NE12
0100100LH[0]
0101000HEX_N3[5]
1000001LH[12]
1000010OUT_FAN[1]
1000100HEX_S6[7]
1001000HEX_N6[4]
virtex2 INT_PPC switchbox INT muxes HEX_E0[6]
BitsDestination
MAIN[21][52]MAIN[20][55]MAIN[21][54]MAIN[19][55]MAIN[18][53]MAIN[18][55]MAIN[19][53]HEX_E0[6]
Source
0000000off
0010001OMUX[9]
0010010OMUX[11]
0010100HEX_E6[6]
0011000HEX_E6[8]
0100001LH[6]
0100010OMUX_SE3
0100100HEX_N3[6]
0101000HEX_S3[6]
1000001OUT_FAN[0]
1000010LH[18]
1000100HEX_S6[8]
1001000HEX_N6[5]
virtex2 INT_PPC switchbox INT muxes HEX_E0[7]
BitsDestination
MAIN[20][60]MAIN[20][61]MAIN[20][62]MAIN[19][62]MAIN[18][60]MAIN[19][60]MAIN[18][62]HEX_E0[7]
Source
0000000off
0010001OMUX_S5
0010010OUT_FAN[1]
0010100HEX_E6[7]
0011000HEX_E6[9]
0100001HEX_S3[7]
0100010OMUX_N11
0100100LH[0]
0101000HEX_N3[7]
1000001LH[12]
1000010OUT_FAN[6]
1000100HEX_S6[9]
1001000HEX_N6[6]
virtex2 INT_PPC switchbox INT muxes HEX_E0[8]
BitsDestination
MAIN[21][68]MAIN[21][70]MAIN[20][71]MAIN[19][71]MAIN[18][69]MAIN[19][69]MAIN[18][71]HEX_E0[8]
Source
0000000off
0010001OMUX_ES7
0010010LH[6]
0010100HEX_N3[8]
0011000HEX_S3[8]
0100001OUT_FAN[0]
0100010OMUX_E13
0100100HEX_E6[8]
0101000HEX_E6_S[0]
1000001LH[18]
1000010OUT_FAN[7]
1000100HEX_S7[0]
1001000HEX_N6[7]
virtex2 INT_PPC switchbox INT muxes HEX_E0[9]
BitsDestination
MAIN[20][77]MAIN[20][78]MAIN[20][76]MAIN[19][78]MAIN[18][76]MAIN[18][78]MAIN[19][76]HEX_E0[9]
Source
0000000off
0010001OMUX[15]
0010010LH[12]
0010100HEX_S7[1]
0011000HEX_N6[8]
0100001OMUX_S0
0100010OMUX_S2
0100100HEX_E6[9]
0101000HEX_E6_S[1]
1000001OMUX_N15
1000010HEX_S3[9]
1000100LH[0]
1001000HEX_N3[9]
virtex2 INT_PPC switchbox INT muxes HEX_S0[0]
BitsDestination
MAIN[20][3]MAIN[21][2]MAIN[21][0]MAIN[19][3]MAIN[18][1]MAIN[18][3]MAIN[19][1]HEX_S0[0]
Source
0000000off
0010001OMUX[0]
0010010LV[0]
0010100HEX_E6[1]
0011000HEX_W6_N[8]
0100001OMUX[2]
0100010OUT_FAN[3]
0100100HEX_S6[0]
0101000HEX_S6[2]
1000001LV[12]
1000010OMUX_S0
1000100HEX_W3[0]
1001000HEX_E3[0]
virtex2 INT_PPC switchbox INT muxes HEX_S0[1]
BitsDestination
MAIN[20][8]MAIN[20][9]MAIN[20][10]MAIN[18][8]MAIN[19][10]MAIN[19][8]MAIN[18][10]HEX_S0[1]
Source
0000000off
0010001OMUX[2]
0010010OUT_FAN[2]
0010100HEX_S6[3]
0011000HEX_S6[1]
0100001HEX_E3[1]
0100010OMUX_E2
0100100HEX_W3[1]
0101000LV[18]
1000001LV[6]
1000010OUT_FAN[4]
1000100HEX_W6_N[9]
1001000HEX_E6[2]
virtex2 INT_PPC switchbox INT muxes HEX_S0[2]
BitsDestination
MAIN[21][16]MAIN[20][19]MAIN[21][18]MAIN[19][19]MAIN[18][17]MAIN[19][17]MAIN[18][19]HEX_S0[2]
Source
0000000off
0010001OMUX[4]
0010010OMUX_S4
0010100HEX_S6[2]
0011000HEX_S6[4]
0100001OMUX[6]
0100010LV[12]
0100100HEX_W3[2]
0101000HEX_E3[2]
1000001LV[0]
1000010OUT_FAN[5]
1000100HEX_E6[3]
1001000HEX_W6[0]
virtex2 INT_PPC switchbox INT muxes HEX_S0[3]
BitsDestination
MAIN[20][24]MAIN[20][26]MAIN[20][25]MAIN[18][24]MAIN[19][26]MAIN[18][26]MAIN[19][24]HEX_S0[3]
Source
0000000off
0010001OMUX[6]
0010010HEX_E3[3]
0010100HEX_W3[3]
0011000LV[18]
0100001OUT_FAN[4]
0100010OMUX_W6
0100100HEX_S6[5]
0101000HEX_S6[3]
1000001OUT_FAN[3]
1000010LV[6]
1000100HEX_W6[1]
1001000HEX_E6[4]
virtex2 INT_PPC switchbox INT muxes HEX_S0[4]
BitsDestination
MAIN[21][32]MAIN[21][34]MAIN[20][35]MAIN[19][35]MAIN[18][33]MAIN[19][33]MAIN[18][35]HEX_S0[4]
Source
0000000off
0010001OMUX_WS1
0010010LV[12]
0010100HEX_W3[4]
0011000HEX_E3[4]
0100001OUT_FAN[5]
0100010OMUX_SE3
0100100HEX_S6[4]
0101000HEX_S6[6]
1000001LV[0]
1000010OUT_FAN[2]
1000100HEX_E6[5]
1001000HEX_W6[2]
virtex2 INT_PPC switchbox INT muxes HEX_S0[5]
BitsDestination
MAIN[20][40]MAIN[20][41]MAIN[20][42]MAIN[18][40]MAIN[19][42]MAIN[19][40]MAIN[18][42]HEX_S0[5]
Source
0000000off
0010001OMUX_S3
0010010OUT_FAN[1]
0010100HEX_S6[7]
0011000HEX_S6[5]
0100001HEX_E3[5]
0100010OMUX_E8
0100100HEX_W3[5]
0101000LV[18]
1000001LV[6]
1000010OUT_FAN[6]
1000100HEX_W6[3]
1001000HEX_E6[6]
virtex2 INT_PPC switchbox INT muxes HEX_S0[6]
BitsDestination
MAIN[21][48]MAIN[21][50]MAIN[20][51]MAIN[19][51]MAIN[18][49]MAIN[19][49]MAIN[18][51]HEX_S0[6]
Source
0000000off
0010001OMUX_SW5
0010010LV[12]
0010100HEX_W3[6]
0011000HEX_E3[6]
0100001OUT_FAN[0]
0100010OMUX_ES7
0100100HEX_S6[6]
0101000HEX_S6[8]
1000001LV[0]
1000010OUT_FAN[7]
1000100HEX_E6[7]
1001000HEX_W6[4]
virtex2 INT_PPC switchbox INT muxes HEX_S0[7]
BitsDestination
MAIN[20][57]MAIN[20][58]MAIN[20][56]MAIN[18][56]MAIN[19][58]MAIN[18][58]MAIN[19][56]HEX_S0[7]
Source
0000000off
0010001OMUX[11]
0010010LV[6]
0010100HEX_W6[5]
0011000HEX_E6[8]
0100001OUT_FAN[6]
0100010OMUX_WS1
0100100HEX_S6[9]
0101000HEX_S6[7]
1000001OMUX_SE3
1000010HEX_E3[7]
1000100HEX_W3[7]
1001000LV[18]
virtex2 INT_PPC switchbox INT muxes HEX_S0[8]
BitsDestination
MAIN[21][64]MAIN[20][67]MAIN[21][66]MAIN[19][67]MAIN[18][65]MAIN[18][67]MAIN[19][65]HEX_S0[8]
Source
0000000off
0010001OMUX_S5
0010010OUT_FAN[7]
0010100HEX_S6[8]
0011000HEX_S7[0]
0100001LV[12]
0100010OMUX_W14
0100100HEX_W3[8]
0101000HEX_E3[8]
1000001OUT_FAN[1]
1000010LV[0]
1000100HEX_E6[9]
1001000HEX_W6[6]
virtex2 INT_PPC switchbox INT muxes HEX_S0[9]
BitsDestination
MAIN[20][72]MAIN[20][73]MAIN[20][74]MAIN[18][72]MAIN[19][74]MAIN[18][74]MAIN[19][72]HEX_S0[9]
Source
0000000off
0010001OMUX[15]
0010010OMUX_SW5
0010100HEX_S7[1]
0011000HEX_S6[9]
0100001OMUX_ES7
0100010HEX_E3[9]
0100100HEX_W3[9]
0101000LV[18]
1000001OUT_FAN[0]
1000010LV[6]
1000100HEX_W6[7]
1001000HEX_E6_S[0]
virtex2 INT_PPC switchbox INT muxes HEX_N0[0]
BitsDestination
MAIN[20][1]MAIN[20][2]MAIN[20][0]MAIN[18][0]MAIN[19][2]MAIN[18][2]MAIN[19][0]HEX_N0[0]
Source
0000000off
0010001OMUX[0]
0010010LV[0]
0010100HEX_W6_N[8]
0011000HEX_E6[1]
0100001OUT_FAN[3]
0100010OMUX_EN8
0100100HEX_N6[0]
0101000HEX_N7[8]
1000001OMUX_N13
1000010HEX_E3[0]
1000100HEX_W3[0]
1001000LV[12]
virtex2 INT_PPC switchbox INT muxes HEX_N0[1]
BitsDestination
MAIN[21][8]MAIN[21][10]MAIN[20][11]MAIN[19][11]MAIN[18][9]MAIN[19][9]MAIN[18][11]HEX_N0[1]
Source
0000000off
0010001OMUX_N10
0010010LV[18]
0010100HEX_W3[1]
0011000HEX_E3[1]
0100001OUT_FAN[2]
0100010OMUX_NW10
0100100HEX_N7[9]
0101000HEX_N6[1]
1000001LV[6]
1000010OUT_FAN[4]
1000100HEX_E6[2]
1001000HEX_W6_N[9]
virtex2 INT_PPC switchbox INT muxes HEX_N0[2]
BitsDestination
MAIN[20][16]MAIN[20][17]MAIN[20][18]MAIN[18][16]MAIN[19][18]MAIN[18][18]MAIN[19][16]HEX_N0[2]
Source
0000000off
0010001OMUX[4]
0010010OMUX_NE12
0010100HEX_N6[2]
0011000HEX_N6[0]
0100001OMUX_W1
0100010HEX_E3[2]
0100100HEX_W3[2]
0101000LV[12]
1000001OUT_FAN[5]
1000010LV[0]
1000100HEX_W6[0]
1001000HEX_E6[3]
virtex2 INT_PPC switchbox INT muxes HEX_N0[3]
BitsDestination
MAIN[21][24]MAIN[21][26]MAIN[20][27]MAIN[19][27]MAIN[18][25]MAIN[19][25]MAIN[18][27]HEX_N0[3]
Source
0000000off
0010001OMUX_EN8
0010010LV[18]
0010100HEX_W3[3]
0011000HEX_E3[3]
0100001OUT_FAN[4]
0100010OMUX_WN14
0100100HEX_N6[1]
0101000HEX_N6[3]
1000001LV[6]
1000010OUT_FAN[3]
1000100HEX_E6[4]
1001000HEX_W6[1]
virtex2 INT_PPC switchbox INT muxes HEX_N0[4]
BitsDestination
MAIN[20][32]MAIN[20][33]MAIN[20][34]MAIN[18][32]MAIN[19][34]MAIN[19][32]MAIN[18][34]HEX_N0[4]
Source
0000000off
0010001OMUX_E7
0010010OUT_FAN[5]
0010100HEX_N6[4]
0011000HEX_N6[2]
0100001HEX_E3[4]
0100010OMUX_NW10
0100100HEX_W3[4]
0101000LV[12]
1000001LV[0]
1000010OUT_FAN[2]
1000100HEX_W6[2]
1001000HEX_E6[5]
virtex2 INT_PPC switchbox INT muxes HEX_N0[5]
BitsDestination
MAIN[21][40]MAIN[20][43]MAIN[21][42]MAIN[19][43]MAIN[18][41]MAIN[18][43]MAIN[19][41]HEX_N0[5]
Source
0000000off
0010001OMUX_N12
0010010OUT_FAN[1]
0010100HEX_N6[3]
0011000HEX_N6[5]
0100001LV[18]
0100010OMUX_NE12
0100100HEX_W3[5]
0101000HEX_E3[5]
1000001OUT_FAN[6]
1000010LV[6]
1000100HEX_E6[6]
1001000HEX_W6[3]
virtex2 INT_PPC switchbox INT muxes HEX_N0[6]
BitsDestination
MAIN[20][48]MAIN[20][49]MAIN[20][50]MAIN[18][48]MAIN[19][50]MAIN[19][48]MAIN[18][50]HEX_N0[6]
Source
0000000off
0010001OMUX[9]
0010010OUT_FAN[0]
0010100HEX_N6[6]
0011000HEX_N6[4]
0100001HEX_E3[6]
0100010OMUX_WN14
0100100HEX_W3[6]
0101000LV[12]
1000001LV[0]
1000010OUT_FAN[7]
1000100HEX_W6[4]
1001000HEX_E6[7]
virtex2 INT_PPC switchbox INT muxes HEX_N0[7]
BitsDestination
MAIN[20][59]MAIN[21][58]MAIN[21][56]MAIN[19][59]MAIN[18][57]MAIN[18][59]MAIN[19][57]HEX_N0[7]
Source
0000000off
0010001OMUX[11]
0010010LV[6]
0010100HEX_E6[8]
0011000HEX_W6[5]
0100001OMUX_W9
0100010OUT_FAN[6]
0100100HEX_N6[5]
0101000HEX_N6[7]
1000001LV[18]
1000010OMUX_N11
1000100HEX_W3[7]
1001000HEX_E3[7]
virtex2 INT_PPC switchbox INT muxes HEX_N0[8]
BitsDestination
MAIN[20][64]MAIN[20][66]MAIN[20][65]MAIN[18][64]MAIN[19][66]MAIN[18][66]MAIN[19][64]HEX_N0[8]
Source
0000000off
0010001OMUX[9]
0010010HEX_E3[8]
0010100HEX_W3[8]
0011000LV[12]
0100001OUT_FAN[7]
0100010OMUX_E13
0100100HEX_N6[8]
0101000HEX_N6[6]
1000001OUT_FAN[1]
1000010LV[0]
1000100HEX_W6[6]
1001000HEX_E6[9]
virtex2 INT_PPC switchbox INT muxes HEX_N0[9]
BitsDestination
MAIN[21][72]MAIN[20][75]MAIN[21][74]MAIN[19][75]MAIN[18][73]MAIN[18][75]MAIN[19][73]HEX_N0[9]
Source
0000000off
0010001OMUX[13]
0010010OMUX[15]
0010100HEX_N6[7]
0011000HEX_N6[9]
0100001LV[18]
0100010OMUX_N15
0100100HEX_W3[9]
0101000HEX_E3[9]
1000001OUT_FAN[0]
1000010LV[6]
1000100HEX_E6_S[0]
1001000HEX_W6[7]
virtex2 INT_PPC switchbox INT muxes LH[0]
BitsDestination
MAIN[21][47]MAIN[21][49]MAIN[21][51]LH[0]
Source
000off
001DBL_W1[5]
011OMUX_S4
101DBL_E1[6]
111OMUX[11]
virtex2 INT_PPC switchbox INT muxes LH[6]
BitsDestination
MAIN[21][31]MAIN[21][33]MAIN[21][29]LH[6]
Source
000off
001OMUX[4]
011OMUX_N15
101DBL_E1[4]
111DBL_W1[3]
virtex2 INT_PPC switchbox INT muxes LH[12]
BitsDestination
MAIN[21][41]MAIN[21][45]MAIN[21][43]LH[12]
Source
000off
001DBL_W1[5]
011OMUX_S4
101DBL_E1[6]
111OMUX[11]
virtex2 INT_PPC switchbox INT muxes LH[18]
BitsDestination
MAIN[21][39]MAIN[21][37]MAIN[21][35]LH[18]
Source
000off
001OMUX[4]
011OMUX_N15
101DBL_E1[4]
111DBL_W1[3]
virtex2 INT_PPC switchbox INT muxes LV[0]
BitsDestination
MAIN[21][7]MAIN[21][9]MAIN[21][19]MAIN[21][25]MAIN[21][21]MAIN[21][11]MAIN[21][5]LV[0]
Source
0000000off
0000011HEX_E1[1]
0000101OMUX_E2
0001001DBL_W1[1]
0010001HEX_E6[1]
0100001HEX_E4[1]
1000011OMUX[0]
1000101HEX_E2[1]
1001001HEX_E5[1]
1010001DBL_E1[2]
1100001HEX_E3[1]
virtex2 INT_PPC switchbox INT muxes LV[6]
BitsDestination
MAIN[21][73]MAIN[21][61]MAIN[21][55]MAIN[21][69]MAIN[21][71]MAIN[21][65]MAIN[21][75]LV[6]
Source
0000000off
0000011OMUX_W9
0000101DBL_W1[7]
0001001HEX_W5[7]
0010001HEX_W3[7]
0100001HEX_W4[7]
1000011OMUX[15]
1000101HEX_W2[7]
1001001DBL_E1[8]
1010001HEX_W0[7]
1100001HEX_W1[7]
virtex2 INT_PPC switchbox INT muxes LV[12]
BitsDestination
MAIN[21][13]MAIN[21][1]MAIN[21][27]MAIN[21][23]MAIN[21][17]MAIN[21][3]MAIN[21][15]LV[12]
Source
0000000off
0000011HEX_E1[1]
0000101OMUX_E2
0001001DBL_W1[1]
0010001HEX_E6[1]
0100001HEX_E4[1]
1000011OMUX[0]
1000101HEX_E2[1]
1001001HEX_E5[1]
1010001DBL_E1[2]
1100001HEX_E3[1]
virtex2 INT_PPC switchbox INT muxes LV[18]
BitsDestination
MAIN[21][67]MAIN[21][53]MAIN[21][57]MAIN[21][77]MAIN[21][59]MAIN[21][79]MAIN[21][63]LV[18]
Source
0000000off
0000011OMUX_W9
0000101DBL_W1[7]
0001001HEX_W5[7]
0010001HEX_W3[7]
0100001HEX_W4[7]
1000011OMUX[15]
1000101HEX_W2[7]
1001001DBL_E1[8]
1010001HEX_W0[7]
1100001HEX_W1[7]
virtex2 INT_PPC switchbox INT muxes IMUX_CLK[0]
BitsDestination
MAIN[5][41]MAIN[5][42]MAIN[5][40]MAIN[4][42]MAIN[5][49]MAIN[4][47]MAIN[4][43]MAIN[5][45]MAIN[4][45]MAIN[5][43]IMUX_CLK[0]
Source
0000000000PULLUP
0001000001GCLK[0]
0001000010GCLK[1]
0001000100GCLK[2]
0001001000HEX_N0[6]
0001010000HEX_N3[6]
0001100000HEX_S4[6]
0010000001GCLK[3]
0010000010HEX_S3[6]
0010000100GCLK[4]
0010001000HEX_S6[6]
0010010000HEX_N1[6]
0010100000HEX_N4[6]
0100000001GCLK[5]
0100000010HEX_N2[6]
0100000100HEX_N5[6]
0100001000GCLK[6]
0100010000HEX_S5[6]
0100100000HEX_S2[6]
1000000001GCLK[7]
1000000010DBL_W1[5]
1000000100DBL_E0[5]
1000001000DBL_E1[5]
1000010000DBL_W2[5]
1000100000HEX_S1[6]
virtex2 INT_PPC switchbox INT muxes IMUX_CLK[1]
BitsDestination
MAIN[5][47]MAIN[5][48]MAIN[5][50]MAIN[4][48]MAIN[4][50]MAIN[4][46]MAIN[4][44]MAIN[5][46]MAIN[5][44]MAIN[4][40]IMUX_CLK[1]
Source
0000000000PULLUP
0001000001GCLK[0]
0001000010GCLK[1]
0001000100GCLK[2]
0001001000HEX_N0[6]
0001010000HEX_N3[6]
0001100000HEX_S4[6]
0010000001GCLK[3]
0010000010HEX_S3[6]
0010000100GCLK[4]
0010001000HEX_S6[6]
0010010000HEX_N1[6]
0010100000HEX_N4[6]
0100000001GCLK[5]
0100000010HEX_N2[6]
0100000100HEX_N5[6]
0100001000GCLK[6]
0100010000HEX_S5[6]
0100100000HEX_S2[6]
1000000001GCLK[7]
1000000010DBL_W1[5]
1000000100DBL_E0[5]
1000001000DBL_E1[5]
1000010000DBL_W2[5]
1000100000HEX_S1[6]
virtex2 INT_PPC switchbox INT muxes IMUX_CLK[2]
BitsDestination
MAIN[5][54]MAIN[5][53]MAIN[5][51]MAIN[4][53]MAIN[4][51]MAIN[4][55]MAIN[4][57]MAIN[5][55]MAIN[5][57]MAIN[4][61]IMUX_CLK[2]
Source
0000000000PULLUP
0001000001GCLK[0]
0001000010GCLK[1]
0001000100GCLK[2]
0001001000HEX_N0[6]
0001010000HEX_N3[6]
0001100000HEX_S4[6]
0010000001GCLK[3]
0010000010HEX_S3[6]
0010000100GCLK[4]
0010001000HEX_S6[6]
0010010000HEX_N1[6]
0010100000HEX_N4[6]
0100000001GCLK[5]
0100000010HEX_N2[6]
0100000100HEX_N5[6]
0100001000GCLK[6]
0100010000HEX_S5[6]
0100100000HEX_S2[6]
1000000001GCLK[7]
1000000010DBL_W2[6]
1000000100DBL_E0[6]
1000001000DBL_E1[6]
1000010000DBL_W1[6]
1000100000HEX_S1[6]
virtex2 INT_PPC switchbox INT muxes IMUX_CLK[3]
BitsDestination
MAIN[5][60]MAIN[5][59]MAIN[5][61]MAIN[4][59]MAIN[5][52]MAIN[4][54]MAIN[4][58]MAIN[5][56]MAIN[4][56]MAIN[5][58]IMUX_CLK[3]
Source
0000000000PULLUP
0001000001GCLK[0]
0001000010GCLK[1]
0001000100GCLK[2]
0001001000HEX_N0[6]
0001010000HEX_N3[6]
0001100000HEX_S4[6]
0010000001GCLK[3]
0010000010HEX_S3[6]
0010000100GCLK[4]
0010001000HEX_S6[6]
0010010000HEX_N1[6]
0010100000HEX_N4[6]
0100000001GCLK[5]
0100000010HEX_N2[6]
0100000100HEX_N5[6]
0100001000GCLK[6]
0100010000HEX_S5[6]
0100100000HEX_S2[6]
1000000001GCLK[7]
1000000010DBL_W2[6]
1000000100DBL_E0[6]
1000001000DBL_E1[6]
1000010000DBL_W1[6]
1000100000HEX_S1[6]
virtex2 INT_PPC switchbox INT muxes IMUX_SR[0]
BitsDestination
MAIN[5][3]MAIN[4][3]MAIN[5][5]MAIN[4][5]MAIN[5][1]MAIN[5][2]MAIN[4][2]MAIN[5][0]IMUX_SR[0]
Source
00000000PULLUP
00010001DBL_W1[0]
00010010HEX_N1[0]
00010100HEX_N5[0]
00011000HEX_S4[0]
00100001DBL_W2[0]
00100010HEX_S5[0]
00100100HEX_S1[0]
00101000HEX_N3[0]
01000001HEX_N2[0]
01000010DBL_E0[0]
01000100HEX_S2[0]
01001000HEX_N0[0]
10000001HEX_S3[0]
10000010DBL_E1[0]
10000100HEX_N4[0]
10001000HEX_S6[0]
virtex2 INT_PPC switchbox INT muxes IMUX_SR[1]
BitsDestination
MAIN[4][12]MAIN[5][12]MAIN[5][14]MAIN[4][14]MAIN[5][16]MAIN[5][15]MAIN[5][17]MAIN[4][15]IMUX_SR[1]
Source
00000000PULLUP
00010001DBL_W1[1]
00010010HEX_N2[0]
00010100HEX_S2[0]
00011000HEX_N0[0]
00100001DBL_W2[1]
00100010HEX_S3[0]
00100100HEX_N4[0]
00101000HEX_S6[0]
01000001HEX_S5[0]
01000010DBL_E0[1]
01000100HEX_S1[0]
01001000HEX_N3[0]
10000001HEX_N1[0]
10000010DBL_E1[1]
10000100HEX_N5[0]
10001000HEX_S4[0]
virtex2 INT_PPC switchbox INT muxes IMUX_SR[2]
BitsDestination
MAIN[4][0]MAIN[4][4]MAIN[4][8]MAIN[5][4]MAIN[5][7]MAIN[5][8]MAIN[4][6]MAIN[5][6]IMUX_SR[2]
Source
00000000PULLUP
00010001DBL_W1[0]
00010010HEX_N1[0]
00010100HEX_N5[0]
00011000HEX_S4[0]
00100001DBL_W2[0]
00100010HEX_S5[0]
00100100HEX_S1[0]
00101000HEX_N3[0]
01000001HEX_N2[0]
01000010DBL_E0[0]
01000100HEX_S2[0]
01001000HEX_N0[0]
10000001HEX_S3[0]
10000010DBL_E1[0]
10000100HEX_N4[0]
10001000HEX_S6[0]
virtex2 INT_PPC switchbox INT muxes IMUX_SR[3]
BitsDestination
MAIN[5][13]MAIN[4][9]MAIN[4][17]MAIN[4][13]MAIN[5][10]MAIN[5][9]MAIN[5][11]MAIN[4][11]IMUX_SR[3]
Source
00000000PULLUP
00010001DBL_W1[1]
00010010HEX_N2[0]
00010100HEX_S2[0]
00011000HEX_N0[0]
00100001DBL_W2[1]
00100010HEX_S3[0]
00100100HEX_N4[0]
00101000HEX_S6[0]
01000001HEX_S5[0]
01000010DBL_E0[1]
01000100HEX_S1[0]
01001000HEX_N3[0]
10000001HEX_N1[0]
10000010DBL_E1[1]
10000100HEX_N5[0]
10001000HEX_S4[0]
virtex2 INT_PPC switchbox INT muxes IMUX_CE[0]
BitsDestination
MAIN[5][65]MAIN[4][65]MAIN[5][67]MAIN[4][67]MAIN[5][63]MAIN[5][64]MAIN[4][64]MAIN[5][62]IMUX_CE[0]
Source
00000000PULLUP
00010001DBL_W1[8]
00010010HEX_N0[9]
00010100HEX_N2[9]
00011000HEX_N3[9]
00100001DBL_W2[8]
00100010HEX_S6[9]
00100100HEX_S4[9]
00101000HEX_S3[9]
01000001HEX_S1[9]
01000010DBL_E0[8]
01000100HEX_S2[9]
01001000HEX_S5[9]
10000001HEX_N5[9]
10000010DBL_E1[8]
10000100HEX_N4[9]
10001000HEX_N1[9]
virtex2 INT_PPC switchbox INT muxes IMUX_CE[1]
BitsDestination
MAIN[4][62]MAIN[4][66]MAIN[4][70]MAIN[5][66]MAIN[5][69]MAIN[5][70]MAIN[4][68]MAIN[5][68]IMUX_CE[1]
Source
00000000PULLUP
00010001DBL_W1[8]
00010010HEX_N0[9]
00010100HEX_N2[9]
00011000HEX_N3[9]
00100001DBL_W2[8]
00100010HEX_S6[9]
00100100HEX_S4[9]
00101000HEX_S3[9]
01000001HEX_S1[9]
01000010DBL_E0[8]
01000100HEX_S2[9]
01001000HEX_S5[9]
10000001HEX_N5[9]
10000010DBL_E1[8]
10000100HEX_N4[9]
10001000HEX_N1[9]
virtex2 INT_PPC switchbox INT muxes IMUX_CE[2]
BitsDestination
MAIN[5][75]MAIN[4][71]MAIN[4][79]MAIN[4][75]MAIN[5][72]MAIN[5][71]MAIN[5][73]MAIN[4][73]IMUX_CE[2]
Source
00000000PULLUP
00010001DBL_W1[9]
00010010HEX_S1[9]
00010100HEX_S2[9]
00011000HEX_S5[9]
00100001DBL_W2[9]
00100010HEX_N5[9]
00100100HEX_N4[9]
00101000HEX_N1[9]
01000001HEX_S6[9]
01000010DBL_E0[9]
01000100HEX_S4[9]
01001000HEX_S3[9]
10000001HEX_N0[9]
10000010DBL_E1[9]
10000100HEX_N2[9]
10001000HEX_N3[9]
virtex2 INT_PPC switchbox INT muxes IMUX_CE[3]
BitsDestination
MAIN[4][74]MAIN[5][74]MAIN[5][76]MAIN[4][76]MAIN[5][78]MAIN[5][77]MAIN[5][79]MAIN[4][77]IMUX_CE[3]
Source
00000000PULLUP
00010001DBL_W1[9]
00010010HEX_S1[9]
00010100HEX_S2[9]
00011000HEX_S5[9]
00100001DBL_W2[9]
00100010HEX_N5[9]
00100100HEX_N4[9]
00101000HEX_N1[9]
01000001HEX_S6[9]
01000010DBL_E0[9]
01000100HEX_S4[9]
01001000HEX_S3[9]
10000001HEX_N0[9]
10000010DBL_E1[9]
10000100HEX_N2[9]
10001000HEX_N3[9]
virtex2 INT_PPC switchbox INT muxes IMUX_TI[0]
BitsDestination
MAIN[5][18]MAIN[5][19]MAIN[4][20]MAIN[5][20]MAIN[5][27]MAIN[4][25]MAIN[4][23]MAIN[5][23]MAIN[4][21]MAIN[5][21]IMUX_TI[0]
Source
0000000000PULLUP
0001000001OMUX[2]
0001000010OMUX[3]
0001000100HEX_N5[3]
0001001000HEX_N2[3]
0001010000HEX_S5[3]
0001100000HEX_S2[3]
0010000001OMUX[4]
0010000010HEX_N0[3]
0010000100DBL_W1[2]
0010001000DBL_W2[2]
0010010000HEX_N3[3]
0010100000HEX_S4[3]
0100000001OMUX[5]
0100000010DBL_W2[3]
0100000100DBL_W1[3]
0100001000DBL_E1[3]
0100010000DBL_E0[3]
0100100000HEX_S1[3]
1000000001DBL_E0[2]
1000000010HEX_S6[3]
1000000100DBL_E1[2]
1000001000HEX_S3[3]
1000010000HEX_N1[3]
1000100000HEX_N4[3]
virtex2 INT_PPC switchbox INT muxes IMUX_TI[1]
BitsDestination
MAIN[5][28]MAIN[5][25]MAIN[4][26]MAIN[5][26]MAIN[4][28]MAIN[4][24]MAIN[5][22]MAIN[5][24]MAIN[4][22]MAIN[4][18]IMUX_TI[1]
Source
0000000000PULLUP
0001000001OMUX[2]
0001000010OMUX[3]
0001000100HEX_N5[3]
0001001000HEX_N2[3]
0001010000HEX_S5[3]
0001100000HEX_S2[3]
0010000001OMUX[4]
0010000010HEX_N0[3]
0010000100DBL_W1[2]
0010001000DBL_W2[2]
0010010000HEX_N3[3]
0010100000HEX_S4[3]
0100000001OMUX[5]
0100000010DBL_W2[3]
0100000100DBL_W1[3]
0100001000DBL_E1[3]
0100010000DBL_E0[3]
0100100000HEX_S1[3]
1000000001DBL_E0[2]
1000000010HEX_S6[3]
1000000100DBL_E1[2]
1000001000HEX_S3[3]
1000010000HEX_N1[3]
1000100000HEX_N4[3]
virtex2 INT_PPC switchbox INT muxes IMUX_TS[0]
BitsDestination
MAIN[4][37]MAIN[5][39]MAIN[5][37]MAIN[5][38]MAIN[5][30]MAIN[4][32]MAIN[5][34]MAIN[4][34]MAIN[4][36]IMUX_TS[0]
Source
000000000PULLUP
000100001DBL_W1[4]
000100010HEX_N2[3]
000100100DBL_E0[4]
000101000DBL_E1[4]
000110000HEX_S1[3]
001000010DBL_W2[4]
001000100HEX_N5[3]
001001000HEX_S5[3]
001010000HEX_S2[3]
010000001HEX_S6[3]
010000010HEX_S3[3]
010001000HEX_N1[3]
010010000HEX_N4[3]
100000001HEX_N0[3]
100001000HEX_N3[3]
100010000HEX_S4[3]
virtex2 INT_PPC switchbox INT muxes IMUX_TS[1]
BitsDestination
MAIN[4][31]MAIN[5][29]MAIN[5][31]MAIN[5][32]MAIN[4][29]MAIN[4][33]MAIN[5][33]MAIN[5][35]MAIN[4][35]IMUX_TS[1]
Source
000000000PULLUP
000100001DBL_W1[4]
000100010HEX_N2[3]
000100100DBL_E0[4]
000101000DBL_E1[4]
000110000HEX_S1[3]
001000010DBL_W2[4]
001000100HEX_N5[3]
001001000HEX_S5[3]
001010000HEX_S2[3]
010000001HEX_S6[3]
010000010HEX_S3[3]
010001000HEX_N1[3]
010010000HEX_N4[3]
100000001HEX_N0[3]
100001000HEX_N3[3]
100010000HEX_S4[3]
virtex2 INT_PPC switchbox INT muxes IMUX_G0_FAN[0]
BitsDestination
MAIN[9][16]MAIN[9][19]MAIN[8][19]MAIN[8][16]MAIN[10][17]MAIN[10][19]MAIN[11][19]MAIN[11][17]MAIN[13][17]MAIN[12][19]MAIN[13][19]MAIN[12][17]IMUX_G0_FAN[0]
Source
000000000000off
000100000001OMUX_W1
000100000010OMUX_E2
000100000100OMUX_NW10
000100001000OMUX_N10
000100010000DBL_S1[0]
000100100000IMUX_G1_FAN[0]
000101000000DBL_N2[0]
000110000000IMUX_G2_FAN[0]
001000000001DBL_E0[1]
001000000010DBL_S0[0]
001000000100OMUX_EN8
001000001000DBL_W0[0]
001000010000DBL_N1[1]
001000100000DBL_S1[2]
001001000000DBL_W2[1]
001010000000DBL_S1[1]
010000000001DBL_E2[1]
010000000010DBL_S0[2]
010000000100DBL_E2[0]
010000001000DBL_E2[2]
010000010000DBL_W1[0]
010000100000DBL_E1[2]
010001000000DBL_E1[1]
010010000000DBL_N2[1]
100000000001DBL_S2[0]
100000000010DBL_S2[2]
100000000100DBL_N0[1]
100000001000DBL_S2[1]
100000010000DBL_E1[0]
100000100000DBL_W1[1]
100001000000DBL_W2[0]
100010000000DBL_N1[0]
virtex2 INT_PPC switchbox INT muxes IMUX_G0_FAN[1]
BitsDestination
MAIN[9][17]MAIN[9][18]MAIN[8][18]MAIN[8][17]MAIN[10][16]MAIN[10][18]MAIN[11][18]MAIN[11][16]MAIN[13][16]MAIN[12][18]MAIN[13][18]MAIN[12][16]IMUX_G0_FAN[1]
Source
000000000000off
000100000001OMUX_W1
000100000010OMUX_E2
000100000100OMUX_NW10
000100001000OMUX_N10
000100010000DBL_S1[0]
000100100000IMUX_G1_FAN[0]
000101000000DBL_N2[0]
000110000000IMUX_G2_FAN[0]
001000000001DBL_E0[1]
001000000010DBL_S0[0]
001000000100OMUX_EN8
001000001000DBL_W0[0]
001000010000DBL_N1[1]
001000100000DBL_S1[2]
001001000000DBL_W2[1]
001010000000DBL_S1[1]
010000000001DBL_E2[1]
010000000010DBL_S0[2]
010000000100DBL_E2[0]
010000001000DBL_E2[2]
010000010000DBL_W1[0]
010000100000DBL_E1[2]
010001000000DBL_E1[1]
010010000000DBL_N2[1]
100000000001DBL_S2[0]
100000000010DBL_S2[2]
100000000100DBL_N0[1]
100000001000DBL_S2[1]
100000010000DBL_E1[0]
100000100000DBL_W1[1]
100001000000DBL_W2[0]
100010000000DBL_N1[0]
virtex2 INT_PPC switchbox INT muxes IMUX_G0_DATA[0]
BitsDestination
MAIN[9][0]MAIN[9][3]MAIN[8][3]MAIN[8][0]MAIN[10][1]MAIN[10][3]MAIN[11][3]MAIN[11][1]MAIN[13][1]MAIN[12][3]MAIN[13][3]MAIN[12][1]IMUX_G0_DATA[0]
Source
000000000000PULLUP
000100000001OMUX_W1
000100000010OMUX_E2
000100000100OMUX_NW10
000100001000OMUX_N10
000100010000DBL_S1[0]
000100100000IMUX_G1_FAN[0]
000101000000DBL_N2[0]
000110000000IMUX_G2_FAN[0]
001000000001DBL_E0[1]
001000000010DBL_S0[0]
001000000100OMUX_EN8
001000001000DBL_W0[0]
001000010000DBL_N1[1]
001000100000DBL_S1[2]
001001000000DBL_W2[1]
001010000000DBL_S1[1]
010000000001DBL_E2[1]
010000000010DBL_S0[2]
010000000100DBL_E2[0]
010000001000DBL_E2[2]
010000010000DBL_W1[0]
010000100000DBL_E1[2]
010001000000DBL_E1[1]
010010000000DBL_N2[1]
100000000001DBL_S2[0]
100000000010DBL_S2[2]
100000000100DBL_N0[1]
100000001000DBL_S2[1]
100000010000DBL_E1[0]
100000100000DBL_W1[1]
100001000000DBL_W2[0]
100010000000DBL_N1[0]
virtex2 INT_PPC switchbox INT muxes IMUX_G0_DATA[1]
BitsDestination
MAIN[9][1]MAIN[9][2]MAIN[8][2]MAIN[8][1]MAIN[10][0]MAIN[10][2]MAIN[11][2]MAIN[11][0]MAIN[13][0]MAIN[12][2]MAIN[13][2]MAIN[12][0]IMUX_G0_DATA[1]
Source
000000000000PULLUP
000100000001OMUX_W1
000100000010OMUX_E2
000100000100OMUX_NW10
000100001000OMUX_N10
000100010000DBL_S1[0]
000100100000IMUX_G1_FAN[0]
000101000000DBL_N2[0]
000110000000IMUX_G2_FAN[0]
001000000001DBL_E0[1]
001000000010DBL_S0[0]
001000000100OMUX_EN8
001000001000DBL_W0[0]
001000010000DBL_N1[1]
001000100000DBL_S1[2]
001001000000DBL_W2[1]
001010000000DBL_S1[1]
010000000001DBL_E2[1]
010000000010DBL_S0[2]
010000000100DBL_E2[0]
010000001000DBL_E2[2]
010000010000DBL_W1[0]
010000100000DBL_E1[2]
010001000000DBL_E1[1]
010010000000DBL_N2[1]
100000000001DBL_S2[0]
100000000010DBL_S2[2]
100000000100DBL_N0[1]
100000001000DBL_S2[1]
100000010000DBL_E1[0]
100000100000DBL_W1[1]
100001000000DBL_W2[0]
100010000000DBL_N1[0]
virtex2 INT_PPC switchbox INT muxes IMUX_G0_DATA[2]
BitsDestination
MAIN[9][7]MAIN[9][4]MAIN[8][4]MAIN[8][7]MAIN[10][6]MAIN[10][4]MAIN[11][4]MAIN[11][6]MAIN[13][6]MAIN[12][4]MAIN[13][4]MAIN[12][6]IMUX_G0_DATA[2]
Source
000000000000PULLUP
000100000001OMUX_W1
000100000010OMUX_E2
000100000100OMUX_NW10
000100001000OMUX_N10
000100010000DBL_S1[0]
000100100000IMUX_G1_FAN[0]
000101000000DBL_N2[0]
000110000000IMUX_G2_FAN[0]
001000000001DBL_E0[1]
001000000010DBL_S0[0]
001000000100OMUX_EN8
001000001000DBL_W0[0]
001000010000DBL_N1[1]
001000100000DBL_S1[2]
001001000000DBL_W2[1]
001010000000DBL_S1[1]
010000000001DBL_E2[1]
010000000010DBL_S0[2]
010000000100DBL_E2[0]
010000001000DBL_E2[2]
010000010000DBL_W1[0]
010000100000DBL_E1[2]
010001000000DBL_E1[1]
010010000000DBL_N2[1]
100000000001DBL_S2[0]
100000000010DBL_S2[2]
100000000100DBL_N0[1]
100000001000DBL_S2[1]
100000010000DBL_E1[0]
100000100000DBL_W1[1]
100001000000DBL_W2[0]
100010000000DBL_N1[0]
virtex2 INT_PPC switchbox INT muxes IMUX_G0_DATA[3]
BitsDestination
MAIN[9][6]MAIN[9][5]MAIN[8][5]MAIN[8][6]MAIN[10][7]MAIN[10][5]MAIN[11][5]MAIN[11][7]MAIN[13][7]MAIN[12][5]MAIN[13][5]MAIN[12][7]IMUX_G0_DATA[3]
Source
000000000000PULLUP
000100000001OMUX_W1
000100000010OMUX_E2
000100000100OMUX_NW10
000100001000OMUX_N10
000100010000DBL_S1[0]
000100100000IMUX_G1_FAN[0]
000101000000DBL_N2[0]
000110000000IMUX_G2_FAN[0]
001000000001DBL_E0[1]
001000000010DBL_S0[0]
001000000100OMUX_EN8
001000001000DBL_W0[0]
001000010000DBL_N1[1]
001000100000DBL_S1[2]
001001000000DBL_W2[1]
001010000000DBL_S1[1]
010000000001DBL_E2[1]
010000000010DBL_S0[2]
010000000100DBL_E2[0]
010000001000DBL_E2[2]
010000010000DBL_W1[0]
010000100000DBL_E1[2]
010001000000DBL_E1[1]
010010000000DBL_N2[1]
100000000001DBL_S2[0]
100000000010DBL_S2[2]
100000000100DBL_N0[1]
100000001000DBL_S2[1]
100000010000DBL_E1[0]
100000100000DBL_W1[1]
100001000000DBL_W2[0]
100010000000DBL_N1[0]
virtex2 INT_PPC switchbox INT muxes IMUX_G0_DATA[4]
BitsDestination
MAIN[9][8]MAIN[9][11]MAIN[8][11]MAIN[8][8]MAIN[10][9]MAIN[10][11]MAIN[11][11]MAIN[11][9]MAIN[13][9]MAIN[12][11]MAIN[13][11]MAIN[12][9]IMUX_G0_DATA[4]
Source
000000000000PULLUP
000100000001OMUX_W1
000100000010OMUX_E2
000100000100OMUX_NW10
000100001000OMUX_N10
000100010000DBL_S1[0]
000100100000IMUX_G1_FAN[0]
000101000000DBL_N2[0]
000110000000IMUX_G2_FAN[0]
001000000001DBL_E0[1]
001000000010DBL_S0[0]
001000000100OMUX_EN8
001000001000DBL_W0[0]
001000010000DBL_N1[1]
001000100000DBL_S1[2]
001001000000DBL_W2[1]
001010000000DBL_S1[1]
010000000001DBL_E2[1]
010000000010DBL_S0[2]
010000000100DBL_E2[0]
010000001000DBL_E2[2]
010000010000DBL_W1[0]
010000100000DBL_E1[2]
010001000000DBL_E1[1]
010010000000DBL_N2[1]
100000000001DBL_S2[0]
100000000010DBL_S2[2]
100000000100DBL_N0[1]
100000001000DBL_S2[1]
100000010000DBL_E1[0]
100000100000DBL_W1[1]
100001000000DBL_W2[0]
100010000000DBL_N1[0]
virtex2 INT_PPC switchbox INT muxes IMUX_G0_DATA[5]
BitsDestination
MAIN[9][9]MAIN[9][10]MAIN[8][10]MAIN[8][9]MAIN[10][8]MAIN[10][10]MAIN[11][10]MAIN[11][8]MAIN[13][8]MAIN[12][10]MAIN[13][10]MAIN[12][8]IMUX_G0_DATA[5]
Source
000000000000PULLUP
000100000001OMUX_W1
000100000010OMUX_E2
000100000100OMUX_NW10
000100001000OMUX_N10
000100010000DBL_S1[0]
000100100000IMUX_G1_FAN[0]
000101000000DBL_N2[0]
000110000000IMUX_G2_FAN[0]
001000000001DBL_E0[1]
001000000010DBL_S0[0]
001000000100OMUX_EN8
001000001000DBL_W0[0]
001000010000DBL_N1[1]
001000100000DBL_S1[2]
001001000000DBL_W2[1]
001010000000DBL_S1[1]
010000000001DBL_E2[1]
010000000010DBL_S0[2]
010000000100DBL_E2[0]
010000001000DBL_E2[2]
010000010000DBL_W1[0]
010000100000DBL_E1[2]
010001000000DBL_E1[1]
010010000000DBL_N2[1]
100000000001DBL_S2[0]
100000000010DBL_S2[2]
100000000100DBL_N0[1]
100000001000DBL_S2[1]
100000010000DBL_E1[0]
100000100000DBL_W1[1]
100001000000DBL_W2[0]
100010000000DBL_N1[0]
virtex2 INT_PPC switchbox INT muxes IMUX_G0_DATA[6]
BitsDestination
MAIN[9][15]MAIN[9][12]MAIN[8][12]MAIN[8][15]MAIN[10][14]MAIN[10][12]MAIN[11][12]MAIN[11][14]MAIN[13][14]MAIN[12][12]MAIN[13][12]MAIN[12][14]IMUX_G0_DATA[6]
Source
000000000000PULLUP
000100000001OMUX_W1
000100000010OMUX_E2
000100000100OMUX_NW10
000100001000OMUX_N10
000100010000DBL_S1[0]
000100100000IMUX_G1_FAN[0]
000101000000DBL_N2[0]
000110000000IMUX_G2_FAN[0]
001000000001DBL_E0[1]
001000000010DBL_S0[0]
001000000100OMUX_EN8
001000001000DBL_W0[0]
001000010000DBL_N1[1]
001000100000DBL_S1[2]
001001000000DBL_W2[1]
001010000000DBL_S1[1]
010000000001DBL_E2[1]
010000000010DBL_S0[2]
010000000100DBL_E2[0]
010000001000DBL_E2[2]
010000010000DBL_W1[0]
010000100000DBL_E1[2]
010001000000DBL_E1[1]
010010000000DBL_N2[1]
100000000001DBL_S2[0]
100000000010DBL_S2[2]
100000000100DBL_N0[1]
100000001000DBL_S2[1]
100000010000DBL_E1[0]
100000100000DBL_W1[1]
100001000000DBL_W2[0]
100010000000DBL_N1[0]
virtex2 INT_PPC switchbox INT muxes IMUX_G0_DATA[7]
BitsDestination
MAIN[9][14]MAIN[9][13]MAIN[8][13]MAIN[8][14]MAIN[10][15]MAIN[10][13]MAIN[11][13]MAIN[11][15]MAIN[13][15]MAIN[12][13]MAIN[13][13]MAIN[12][15]IMUX_G0_DATA[7]
Source
000000000000PULLUP
000100000001OMUX_W1
000100000010OMUX_E2
000100000100OMUX_NW10
000100001000OMUX_N10
000100010000DBL_S1[0]
000100100000IMUX_G1_FAN[0]
000101000000DBL_N2[0]
000110000000IMUX_G2_FAN[0]
001000000001DBL_E0[1]
001000000010DBL_S0[0]
001000000100OMUX_EN8
001000001000DBL_W0[0]
001000010000DBL_N1[1]
001000100000DBL_S1[2]
001001000000DBL_W2[1]
001010000000DBL_S1[1]
010000000001DBL_E2[1]
010000000010DBL_S0[2]
010000000100DBL_E2[0]
010000001000DBL_E2[2]
010000010000DBL_W1[0]
010000100000DBL_E1[2]
010001000000DBL_E1[1]
010010000000DBL_N2[1]
100000000001DBL_S2[0]
100000000010DBL_S2[2]
100000000100DBL_N0[1]
100000001000DBL_S2[1]
100000010000DBL_E1[0]
100000100000DBL_W1[1]
100001000000DBL_W2[0]
100010000000DBL_N1[0]
virtex2 INT_PPC switchbox INT muxes IMUX_G1_FAN[0]
BitsDestination
MAIN[9][23]MAIN[9][20]MAIN[8][23]MAIN[8][20]MAIN[10][22]MAIN[10][20]MAIN[11][22]MAIN[11][20]MAIN[13][20]MAIN[13][22]MAIN[12][22]MAIN[12][20]IMUX_G1_FAN[0]
Source
000000000000off
000100000001OMUX_W6
000100000010DBL_S0[4]
000100000100DBL_W0[4]
000100001000DBL_E0[3]
000100010000DBL_W1[2]
000100100000DBL_N1[4]
000101000000DBL_W2[4]
000110000000DBL_N2[4]
001000000001OMUX_N12
001000000010OMUX_E7
001000000100OMUX_NE12
001000001000OMUX_WN14
001000010000IMUX_G3_FAN[1]
001000100000DBL_S1[3]
001001000000DBL_E1[4]
001010000000IMUX_G0_FAN[1]
010000000001DBL_E2[4]
010000000010DBL_E2[3]
010000000100DBL_W2[3]
010000001000DBL_W0[2]
010000010000DBL_N1[2]
010000100000DBL_W1[3]
010001000000DBL_W1[4]
010010000000DBL_N2[3]
100000000001DBL_N0[3]
100000000010DBL_S2[4]
100000000100DBL_S2[3]
100000001000DBL_W2[2]
100000010000DBL_S1[4]
100000100000DBL_E1[3]
100001000000DBL_N2[2]
100010000000DBL_N1[3]
virtex2 INT_PPC switchbox INT muxes IMUX_G1_FAN[1]
BitsDestination
MAIN[9][22]MAIN[9][21]MAIN[8][22]MAIN[8][21]MAIN[10][23]MAIN[10][21]MAIN[11][23]MAIN[11][21]MAIN[13][21]MAIN[13][23]MAIN[12][23]MAIN[12][21]IMUX_G1_FAN[1]
Source
000000000000off
000100000001OMUX_W6
000100000010DBL_S0[4]
000100000100DBL_W0[4]
000100001000DBL_E0[3]
000100010000DBL_W1[2]
000100100000DBL_N1[4]
000101000000DBL_W2[4]
000110000000DBL_N2[4]
001000000001OMUX_N12
001000000010OMUX_E7
001000000100OMUX_NE12
001000001000OMUX_WN14
001000010000IMUX_G3_FAN[1]
001000100000DBL_S1[3]
001001000000DBL_E1[4]
001010000000IMUX_G0_FAN[1]
010000000001DBL_E2[4]
010000000010DBL_E2[3]
010000000100DBL_W2[3]
010000001000DBL_W0[2]
010000010000DBL_N1[2]
010000100000DBL_W1[3]
010001000000DBL_W1[4]
010010000000DBL_N2[3]
100000000001DBL_N0[3]
100000000010DBL_S2[4]
100000000100DBL_S2[3]
100000001000DBL_W2[2]
100000010000DBL_S1[4]
100000100000DBL_E1[3]
100001000000DBL_N2[2]
100010000000DBL_N1[3]
virtex2 INT_PPC switchbox INT muxes IMUX_G1_DATA[0]
BitsDestination
MAIN[9][39]MAIN[9][36]MAIN[8][39]MAIN[8][36]MAIN[10][38]MAIN[10][36]MAIN[11][38]MAIN[11][36]MAIN[13][36]MAIN[13][38]MAIN[12][38]MAIN[12][36]IMUX_G1_DATA[0]
Source
000000000000PULLUP
000100000001OMUX_W6
000100000010DBL_S0[4]
000100000100DBL_W0[4]
000100001000DBL_E0[3]
000100010000DBL_W1[2]
000100100000DBL_N1[4]
000101000000DBL_W2[4]
000110000000DBL_N2[4]
001000000001OMUX_N12
001000000010OMUX_E7
001000000100OMUX_NE12
001000001000OMUX_WN14
001000010000IMUX_G3_FAN[1]
001000100000DBL_S1[3]
001001000000DBL_E1[4]
001010000000IMUX_G0_FAN[1]
010000000001DBL_E2[4]
010000000010DBL_E2[3]
010000000100DBL_W2[3]
010000001000DBL_W0[2]
010000010000DBL_N1[2]
010000100000DBL_W1[3]
010001000000DBL_W1[4]
010010000000DBL_N2[3]
100000000001DBL_N0[3]
100000000010DBL_S2[4]
100000000100DBL_S2[3]
100000001000DBL_W2[2]
100000010000DBL_S1[4]
100000100000DBL_E1[3]
100001000000DBL_N2[2]
100010000000DBL_N1[3]
virtex2 INT_PPC switchbox INT muxes IMUX_G1_DATA[1]
BitsDestination
MAIN[9][38]MAIN[9][37]MAIN[8][38]MAIN[8][37]MAIN[10][39]MAIN[10][37]MAIN[11][39]MAIN[11][37]MAIN[13][37]MAIN[13][39]MAIN[12][39]MAIN[12][37]IMUX_G1_DATA[1]
Source
000000000000PULLUP
000100000001OMUX_W6
000100000010DBL_S0[4]
000100000100DBL_W0[4]
000100001000DBL_E0[3]
000100010000DBL_W1[2]
000100100000DBL_N1[4]
000101000000DBL_W2[4]
000110000000DBL_N2[4]
001000000001OMUX_N12
001000000010OMUX_E7
001000000100OMUX_NE12
001000001000OMUX_WN14
001000010000IMUX_G3_FAN[1]
001000100000DBL_S1[3]
001001000000DBL_E1[4]
001010000000IMUX_G0_FAN[1]
010000000001DBL_E2[4]
010000000010DBL_E2[3]
010000000100DBL_W2[3]
010000001000DBL_W0[2]
010000010000DBL_N1[2]
010000100000DBL_W1[3]
010001000000DBL_W1[4]
010010000000DBL_N2[3]
100000000001DBL_N0[3]
100000000010DBL_S2[4]
100000000100DBL_S2[3]
100000001000DBL_W2[2]
100000010000DBL_S1[4]
100000100000DBL_E1[3]
100001000000DBL_N2[2]
100010000000DBL_N1[3]
virtex2 INT_PPC switchbox INT muxes IMUX_G1_DATA[2]
BitsDestination
MAIN[9][32]MAIN[9][35]MAIN[8][32]MAIN[8][35]MAIN[10][33]MAIN[10][35]MAIN[11][33]MAIN[11][35]MAIN[13][35]MAIN[13][33]MAIN[12][33]MAIN[12][35]IMUX_G1_DATA[2]
Source
000000000000PULLUP
000100000001OMUX_W6
000100000010DBL_S0[4]
000100000100DBL_W0[4]
000100001000DBL_E0[3]
000100010000DBL_W1[2]
000100100000DBL_N1[4]
000101000000DBL_W2[4]
000110000000DBL_N2[4]
001000000001OMUX_N12
001000000010OMUX_E7
001000000100OMUX_NE12
001000001000OMUX_WN14
001000010000IMUX_G3_FAN[1]
001000100000DBL_S1[3]
001001000000DBL_E1[4]
001010000000IMUX_G0_FAN[1]
010000000001DBL_E2[4]
010000000010DBL_E2[3]
010000000100DBL_W2[3]
010000001000DBL_W0[2]
010000010000DBL_N1[2]
010000100000DBL_W1[3]
010001000000DBL_W1[4]
010010000000DBL_N2[3]
100000000001DBL_N0[3]
100000000010DBL_S2[4]
100000000100DBL_S2[3]
100000001000DBL_W2[2]
100000010000DBL_S1[4]
100000100000DBL_E1[3]
100001000000DBL_N2[2]
100010000000DBL_N1[3]
virtex2 INT_PPC switchbox INT muxes IMUX_G1_DATA[3]
BitsDestination
MAIN[9][33]MAIN[9][34]MAIN[8][33]MAIN[8][34]MAIN[10][32]MAIN[10][34]MAIN[11][32]MAIN[11][34]MAIN[13][34]MAIN[13][32]MAIN[12][32]MAIN[12][34]IMUX_G1_DATA[3]
Source
000000000000PULLUP
000100000001OMUX_W6
000100000010DBL_S0[4]
000100000100DBL_W0[4]
000100001000DBL_E0[3]
000100010000DBL_W1[2]
000100100000DBL_N1[4]
000101000000DBL_W2[4]
000110000000DBL_N2[4]
001000000001OMUX_N12
001000000010OMUX_E7
001000000100OMUX_NE12
001000001000OMUX_WN14
001000010000IMUX_G3_FAN[1]
001000100000DBL_S1[3]
001001000000DBL_E1[4]
001010000000IMUX_G0_FAN[1]
010000000001DBL_E2[4]
010000000010DBL_E2[3]
010000000100DBL_W2[3]
010000001000DBL_W0[2]
010000010000DBL_N1[2]
010000100000DBL_W1[3]
010001000000DBL_W1[4]
010010000000DBL_N2[3]
100000000001DBL_N0[3]
100000000010DBL_S2[4]
100000000100DBL_S2[3]
100000001000DBL_W2[2]
100000010000DBL_S1[4]
100000100000DBL_E1[3]
100001000000DBL_N2[2]
100010000000DBL_N1[3]
virtex2 INT_PPC switchbox INT muxes IMUX_G1_DATA[4]
BitsDestination
MAIN[9][31]MAIN[9][28]MAIN[8][31]MAIN[8][28]MAIN[10][30]MAIN[10][28]MAIN[11][30]MAIN[11][28]MAIN[13][28]MAIN[13][30]MAIN[12][30]MAIN[12][28]IMUX_G1_DATA[4]
Source
000000000000PULLUP
000100000001OMUX_W6
000100000010DBL_S0[4]
000100000100DBL_W0[4]
000100001000DBL_E0[3]
000100010000DBL_W1[2]
000100100000DBL_N1[4]
000101000000DBL_W2[4]
000110000000DBL_N2[4]
001000000001OMUX_N12
001000000010OMUX_E7
001000000100OMUX_NE12
001000001000OMUX_WN14
001000010000IMUX_G3_FAN[1]
001000100000DBL_S1[3]
001001000000DBL_E1[4]
001010000000IMUX_G0_FAN[1]
010000000001DBL_E2[4]
010000000010DBL_E2[3]
010000000100DBL_W2[3]
010000001000DBL_W0[2]
010000010000DBL_N1[2]
010000100000DBL_W1[3]
010001000000DBL_W1[4]
010010000000DBL_N2[3]
100000000001DBL_N0[3]
100000000010DBL_S2[4]
100000000100DBL_S2[3]
100000001000DBL_W2[2]
100000010000DBL_S1[4]
100000100000DBL_E1[3]
100001000000DBL_N2[2]
100010000000DBL_N1[3]
virtex2 INT_PPC switchbox INT muxes IMUX_G1_DATA[5]
BitsDestination
MAIN[9][30]MAIN[9][29]MAIN[8][30]MAIN[8][29]MAIN[10][31]MAIN[10][29]MAIN[11][31]MAIN[11][29]MAIN[13][29]MAIN[13][31]MAIN[12][31]MAIN[12][29]IMUX_G1_DATA[5]
Source
000000000000PULLUP
000100000001OMUX_W6
000100000010DBL_S0[4]
000100000100DBL_W0[4]
000100001000DBL_E0[3]
000100010000DBL_W1[2]
000100100000DBL_N1[4]
000101000000DBL_W2[4]
000110000000DBL_N2[4]
001000000001OMUX_N12
001000000010OMUX_E7
001000000100OMUX_NE12
001000001000OMUX_WN14
001000010000IMUX_G3_FAN[1]
001000100000DBL_S1[3]
001001000000DBL_E1[4]
001010000000IMUX_G0_FAN[1]
010000000001DBL_E2[4]
010000000010DBL_E2[3]
010000000100DBL_W2[3]
010000001000DBL_W0[2]
010000010000DBL_N1[2]
010000100000DBL_W1[3]
010001000000DBL_W1[4]
010010000000DBL_N2[3]
100000000001DBL_N0[3]
100000000010DBL_S2[4]
100000000100DBL_S2[3]
100000001000DBL_W2[2]
100000010000DBL_S1[4]
100000100000DBL_E1[3]
100001000000DBL_N2[2]
100010000000DBL_N1[3]
virtex2 INT_PPC switchbox INT muxes IMUX_G1_DATA[6]
BitsDestination
MAIN[9][24]MAIN[9][27]MAIN[8][24]MAIN[8][27]MAIN[10][25]MAIN[10][27]MAIN[11][25]MAIN[11][27]MAIN[13][27]MAIN[13][25]MAIN[12][25]MAIN[12][27]IMUX_G1_DATA[6]
Source
000000000000PULLUP
000100000001OMUX_W6
000100000010DBL_S0[4]
000100000100DBL_W0[4]
000100001000DBL_E0[3]
000100010000DBL_W1[2]
000100100000DBL_N1[4]
000101000000DBL_W2[4]
000110000000DBL_N2[4]
001000000001OMUX_N12
001000000010OMUX_E7
001000000100OMUX_NE12
001000001000OMUX_WN14
001000010000IMUX_G3_FAN[1]
001000100000DBL_S1[3]
001001000000DBL_E1[4]
001010000000IMUX_G0_FAN[1]
010000000001DBL_E2[4]
010000000010DBL_E2[3]
010000000100DBL_W2[3]
010000001000DBL_W0[2]
010000010000DBL_N1[2]
010000100000DBL_W1[3]
010001000000DBL_W1[4]
010010000000DBL_N2[3]
100000000001DBL_N0[3]
100000000010DBL_S2[4]
100000000100DBL_S2[3]
100000001000DBL_W2[2]
100000010000DBL_S1[4]
100000100000DBL_E1[3]
100001000000DBL_N2[2]
100010000000DBL_N1[3]
virtex2 INT_PPC switchbox INT muxes IMUX_G1_DATA[7]
BitsDestination
MAIN[9][25]MAIN[9][26]MAIN[8][25]MAIN[8][26]MAIN[10][24]MAIN[10][26]MAIN[11][24]MAIN[11][26]MAIN[13][26]MAIN[13][24]MAIN[12][24]MAIN[12][26]IMUX_G1_DATA[7]
Source
000000000000PULLUP
000100000001OMUX_W6
000100000010DBL_S0[4]
000100000100DBL_W0[4]
000100001000DBL_E0[3]
000100010000DBL_W1[2]
000100100000DBL_N1[4]
000101000000DBL_W2[4]
000110000000DBL_N2[4]
001000000001OMUX_N12
001000000010OMUX_E7
001000000100OMUX_NE12
001000001000OMUX_WN14
001000010000IMUX_G3_FAN[1]
001000100000DBL_S1[3]
001001000000DBL_E1[4]
001010000000IMUX_G0_FAN[1]
010000000001DBL_E2[4]
010000000010DBL_E2[3]
010000000100DBL_W2[3]
010000001000DBL_W0[2]
010000010000DBL_N1[2]
010000100000DBL_W1[3]
010001000000DBL_W1[4]
010010000000DBL_N2[3]
100000000001DBL_N0[3]
100000000010DBL_S2[4]
100000000100DBL_S2[3]
100000001000DBL_W2[2]
100000010000DBL_S1[4]
100000100000DBL_E1[3]
100001000000DBL_N2[2]
100010000000DBL_N1[3]
virtex2 INT_PPC switchbox INT muxes IMUX_G2_FAN[0]
BitsDestination
MAIN[9][56]MAIN[9][59]MAIN[8][59]MAIN[8][56]MAIN[10][57]MAIN[10][59]MAIN[11][59]MAIN[11][57]MAIN[13][59]MAIN[13][57]MAIN[12][59]MAIN[12][57]IMUX_G2_FAN[0]
Source
000000000000off
000100000001OMUX_WS1
000100000010OMUX_E8
000100000100OMUX_SE3
000100001000OMUX_W9
000100010000DBL_S1[5]
000100100000IMUX_G3_FAN[0]
000101000000DBL_N2[5]
000110000000IMUX_G0_FAN[0]
001000000001DBL_E0[5]
001000000010OMUX_S3
001000000100DBL_W0[6]
001000001000DBL_S0[6]
001000010000DBL_N1[6]
001000100000DBL_S1[7]
001001000000DBL_W2[6]
001010000000DBL_S1[6]
010000000001DBL_E2[6]
010000000010DBL_E2[5]
010000000100DBL_E2[7]
010000001000DBL_E0[7]
010000010000DBL_W1[5]
010000100000DBL_E1[7]
010001000000DBL_E1[6]
010010000000DBL_N2[6]
100000000001DBL_S2[5]
100000000010DBL_N0[5]
100000000100DBL_S2[6]
100000001000DBL_S2[7]
100000010000DBL_E1[5]
100000100000DBL_W1[6]
100001000000DBL_W2[5]
100010000000DBL_N1[5]
virtex2 INT_PPC switchbox INT muxes IMUX_G2_FAN[1]
BitsDestination
MAIN[9][57]MAIN[9][58]MAIN[8][58]MAIN[8][57]MAIN[10][56]MAIN[10][58]MAIN[11][58]MAIN[11][56]MAIN[13][58]MAIN[13][56]MAIN[12][58]MAIN[12][56]IMUX_G2_FAN[1]
Source
000000000000off
000100000001OMUX_WS1
000100000010OMUX_E8
000100000100OMUX_SE3
000100001000OMUX_W9
000100010000DBL_S1[5]
000100100000IMUX_G3_FAN[0]
000101000000DBL_N2[5]
000110000000IMUX_G0_FAN[0]
001000000001DBL_E0[5]
001000000010OMUX_S3
001000000100DBL_W0[6]
001000001000DBL_S0[6]
001000010000DBL_N1[6]
001000100000DBL_S1[7]
001001000000DBL_W2[6]
001010000000DBL_S1[6]
010000000001DBL_E2[6]
010000000010DBL_E2[5]
010000000100DBL_E2[7]
010000001000DBL_E0[7]
010000010000DBL_W1[5]
010000100000DBL_E1[7]
010001000000DBL_E1[6]
010010000000DBL_N2[6]
100000000001DBL_S2[5]
100000000010DBL_N0[5]
100000000100DBL_S2[6]
100000001000DBL_S2[7]
100000010000DBL_E1[5]
100000100000DBL_W1[6]
100001000000DBL_W2[5]
100010000000DBL_N1[5]
virtex2 INT_PPC switchbox INT muxes IMUX_G2_DATA[0]
BitsDestination
MAIN[9][40]MAIN[9][43]MAIN[8][43]MAIN[8][40]MAIN[10][41]MAIN[10][43]MAIN[11][43]MAIN[11][41]MAIN[13][43]MAIN[13][41]MAIN[12][43]MAIN[12][41]IMUX_G2_DATA[0]
Source
000000000000PULLUP
000100000001OMUX_WS1
000100000010OMUX_E8
000100000100OMUX_SE3
000100001000OMUX_W9
000100010000DBL_S1[5]
000100100000IMUX_G3_FAN[0]
000101000000DBL_N2[5]
000110000000IMUX_G0_FAN[0]
001000000001DBL_E0[5]
001000000010OMUX_S3
001000000100DBL_W0[6]
001000001000DBL_S0[6]
001000010000DBL_N1[6]
001000100000DBL_S1[7]
001001000000DBL_W2[6]
001010000000DBL_S1[6]
010000000001DBL_E2[6]
010000000010DBL_E2[5]
010000000100DBL_E2[7]
010000001000DBL_E0[7]
010000010000DBL_W1[5]
010000100000DBL_E1[7]
010001000000DBL_E1[6]
010010000000DBL_N2[6]
100000000001DBL_S2[5]
100000000010DBL_N0[5]
100000000100DBL_S2[6]
100000001000DBL_S2[7]
100000010000DBL_E1[5]
100000100000DBL_W1[6]
100001000000DBL_W2[5]
100010000000DBL_N1[5]
virtex2 INT_PPC switchbox INT muxes IMUX_G2_DATA[1]
BitsDestination
MAIN[9][41]MAIN[9][42]MAIN[8][42]MAIN[8][41]MAIN[10][40]MAIN[10][42]MAIN[11][42]MAIN[11][40]MAIN[13][42]MAIN[13][40]MAIN[12][42]MAIN[12][40]IMUX_G2_DATA[1]
Source
000000000000PULLUP
000100000001OMUX_WS1
000100000010OMUX_E8
000100000100OMUX_SE3
000100001000OMUX_W9
000100010000DBL_S1[5]
000100100000IMUX_G3_FAN[0]
000101000000DBL_N2[5]
000110000000IMUX_G0_FAN[0]
001000000001DBL_E0[5]
001000000010OMUX_S3
001000000100DBL_W0[6]
001000001000DBL_S0[6]
001000010000DBL_N1[6]
001000100000DBL_S1[7]
001001000000DBL_W2[6]
001010000000DBL_S1[6]
010000000001DBL_E2[6]
010000000010DBL_E2[5]
010000000100DBL_E2[7]
010000001000DBL_E0[7]
010000010000DBL_W1[5]
010000100000DBL_E1[7]
010001000000DBL_E1[6]
010010000000DBL_N2[6]
100000000001DBL_S2[5]
100000000010DBL_N0[5]
100000000100DBL_S2[6]
100000001000DBL_S2[7]
100000010000DBL_E1[5]
100000100000DBL_W1[6]
100001000000DBL_W2[5]
100010000000DBL_N1[5]
virtex2 INT_PPC switchbox INT muxes IMUX_G2_DATA[2]
BitsDestination
MAIN[9][47]MAIN[9][44]MAIN[8][44]MAIN[8][47]MAIN[10][46]MAIN[10][44]MAIN[11][44]MAIN[11][46]MAIN[13][44]MAIN[13][46]MAIN[12][44]MAIN[12][46]IMUX_G2_DATA[2]
Source
000000000000PULLUP
000100000001OMUX_WS1
000100000010OMUX_E8
000100000100OMUX_SE3
000100001000OMUX_W9
000100010000DBL_S1[5]
000100100000IMUX_G3_FAN[0]
000101000000DBL_N2[5]
000110000000IMUX_G0_FAN[0]
001000000001DBL_E0[5]
001000000010OMUX_S3
001000000100DBL_W0[6]
001000001000DBL_S0[6]
001000010000DBL_N1[6]
001000100000DBL_S1[7]
001001000000DBL_W2[6]
001010000000DBL_S1[6]
010000000001DBL_E2[6]
010000000010DBL_E2[5]
010000000100DBL_E2[7]
010000001000DBL_E0[7]
010000010000DBL_W1[5]
010000100000DBL_E1[7]
010001000000DBL_E1[6]
010010000000DBL_N2[6]
100000000001DBL_S2[5]
100000000010DBL_N0[5]
100000000100DBL_S2[6]
100000001000DBL_S2[7]
100000010000DBL_E1[5]
100000100000DBL_W1[6]
100001000000DBL_W2[5]
100010000000DBL_N1[5]
virtex2 INT_PPC switchbox INT muxes IMUX_G2_DATA[3]
BitsDestination
MAIN[9][46]MAIN[9][45]MAIN[8][45]MAIN[8][46]MAIN[10][47]MAIN[10][45]MAIN[11][45]MAIN[11][47]MAIN[13][45]MAIN[13][47]MAIN[12][45]MAIN[12][47]IMUX_G2_DATA[3]
Source
000000000000PULLUP
000100000001OMUX_WS1
000100000010OMUX_E8
000100000100OMUX_SE3
000100001000OMUX_W9
000100010000DBL_S1[5]
000100100000IMUX_G3_FAN[0]
000101000000DBL_N2[5]
000110000000IMUX_G0_FAN[0]
001000000001DBL_E0[5]
001000000010OMUX_S3
001000000100DBL_W0[6]
001000001000DBL_S0[6]
001000010000DBL_N1[6]
001000100000DBL_S1[7]
001001000000DBL_W2[6]
001010000000DBL_S1[6]
010000000001DBL_E2[6]
010000000010DBL_E2[5]
010000000100DBL_E2[7]
010000001000DBL_E0[7]
010000010000DBL_W1[5]
010000100000DBL_E1[7]
010001000000DBL_E1[6]
010010000000DBL_N2[6]
100000000001DBL_S2[5]
100000000010DBL_N0[5]
100000000100DBL_S2[6]
100000001000DBL_S2[7]
100000010000DBL_E1[5]
100000100000DBL_W1[6]
100001000000DBL_W2[5]
100010000000DBL_N1[5]
virtex2 INT_PPC switchbox INT muxes IMUX_G2_DATA[4]
BitsDestination
MAIN[9][48]MAIN[9][51]MAIN[8][51]MAIN[8][48]MAIN[10][49]MAIN[10][51]MAIN[11][51]MAIN[11][49]MAIN[13][51]MAIN[13][49]MAIN[12][51]MAIN[12][49]IMUX_G2_DATA[4]
Source
000000000000PULLUP
000100000001OMUX_WS1
000100000010OMUX_E8
000100000100OMUX_SE3
000100001000OMUX_W9
000100010000DBL_S1[5]
000100100000IMUX_G3_FAN[0]
000101000000DBL_N2[5]
000110000000IMUX_G0_FAN[0]
001000000001DBL_E0[5]
001000000010OMUX_S3
001000000100DBL_W0[6]
001000001000DBL_S0[6]
001000010000DBL_N1[6]
001000100000DBL_S1[7]
001001000000DBL_W2[6]
001010000000DBL_S1[6]
010000000001DBL_E2[6]
010000000010DBL_E2[5]
010000000100DBL_E2[7]
010000001000DBL_E0[7]
010000010000DBL_W1[5]
010000100000DBL_E1[7]
010001000000DBL_E1[6]
010010000000DBL_N2[6]
100000000001DBL_S2[5]
100000000010DBL_N0[5]
100000000100DBL_S2[6]
100000001000DBL_S2[7]
100000010000DBL_E1[5]
100000100000DBL_W1[6]
100001000000DBL_W2[5]
100010000000DBL_N1[5]
virtex2 INT_PPC switchbox INT muxes IMUX_G2_DATA[5]
BitsDestination
MAIN[9][49]MAIN[9][50]MAIN[8][50]MAIN[8][49]MAIN[10][48]MAIN[10][50]MAIN[11][50]MAIN[11][48]MAIN[13][50]MAIN[13][48]MAIN[12][50]MAIN[12][48]IMUX_G2_DATA[5]
Source
000000000000PULLUP
000100000001OMUX_WS1
000100000010OMUX_E8
000100000100OMUX_SE3
000100001000OMUX_W9
000100010000DBL_S1[5]
000100100000IMUX_G3_FAN[0]
000101000000DBL_N2[5]
000110000000IMUX_G0_FAN[0]
001000000001DBL_E0[5]
001000000010OMUX_S3
001000000100DBL_W0[6]
001000001000DBL_S0[6]
001000010000DBL_N1[6]
001000100000DBL_S1[7]
001001000000DBL_W2[6]
001010000000DBL_S1[6]
010000000001DBL_E2[6]
010000000010DBL_E2[5]
010000000100DBL_E2[7]
010000001000DBL_E0[7]
010000010000DBL_W1[5]
010000100000DBL_E1[7]
010001000000DBL_E1[6]
010010000000DBL_N2[6]
100000000001DBL_S2[5]
100000000010DBL_N0[5]
100000000100DBL_S2[6]
100000001000DBL_S2[7]
100000010000DBL_E1[5]
100000100000DBL_W1[6]
100001000000DBL_W2[5]
100010000000DBL_N1[5]
virtex2 INT_PPC switchbox INT muxes IMUX_G2_DATA[6]
BitsDestination
MAIN[9][55]MAIN[9][52]MAIN[8][52]MAIN[8][55]MAIN[10][54]MAIN[10][52]MAIN[11][52]MAIN[11][54]MAIN[13][52]MAIN[13][54]MAIN[12][52]MAIN[12][54]IMUX_G2_DATA[6]
Source
000000000000PULLUP
000100000001OMUX_WS1
000100000010OMUX_E8
000100000100OMUX_SE3
000100001000OMUX_W9
000100010000DBL_S1[5]
000100100000IMUX_G3_FAN[0]
000101000000DBL_N2[5]
000110000000IMUX_G0_FAN[0]
001000000001DBL_E0[5]
001000000010OMUX_S3
001000000100DBL_W0[6]
001000001000DBL_S0[6]
001000010000DBL_N1[6]
001000100000DBL_S1[7]
001001000000DBL_W2[6]
001010000000DBL_S1[6]
010000000001DBL_E2[6]
010000000010DBL_E2[5]
010000000100DBL_E2[7]
010000001000DBL_E0[7]
010000010000DBL_W1[5]
010000100000DBL_E1[7]
010001000000DBL_E1[6]
010010000000DBL_N2[6]
100000000001DBL_S2[5]
100000000010DBL_N0[5]
100000000100DBL_S2[6]
100000001000DBL_S2[7]
100000010000DBL_E1[5]
100000100000DBL_W1[6]
100001000000DBL_W2[5]
100010000000DBL_N1[5]
virtex2 INT_PPC switchbox INT muxes IMUX_G2_DATA[7]
BitsDestination
MAIN[9][54]MAIN[9][53]MAIN[8][53]MAIN[8][54]MAIN[10][55]MAIN[10][53]MAIN[11][53]MAIN[11][55]MAIN[13][53]MAIN[13][55]MAIN[12][53]MAIN[12][55]IMUX_G2_DATA[7]
Source
000000000000PULLUP
000100000001OMUX_WS1
000100000010OMUX_E8
000100000100OMUX_SE3
000100001000OMUX_W9
000100010000DBL_S1[5]
000100100000IMUX_G3_FAN[0]
000101000000DBL_N2[5]
000110000000IMUX_G0_FAN[0]
001000000001DBL_E0[5]
001000000010OMUX_S3
001000000100DBL_W0[6]
001000001000DBL_S0[6]
001000010000DBL_N1[6]
001000100000DBL_S1[7]
001001000000DBL_W2[6]
001010000000DBL_S1[6]
010000000001DBL_E2[6]
010000000010DBL_E2[5]
010000000100DBL_E2[7]
010000001000DBL_E0[7]
010000010000DBL_W1[5]
010000100000DBL_E1[7]
010001000000DBL_E1[6]
010010000000DBL_N2[6]
100000000001DBL_S2[5]
100000000010DBL_N0[5]
100000000100DBL_S2[6]
100000001000DBL_S2[7]
100000010000DBL_E1[5]
100000100000DBL_W1[6]
100001000000DBL_W2[5]
100010000000DBL_N1[5]
virtex2 INT_PPC switchbox INT muxes IMUX_G3_FAN[0]
BitsDestination
MAIN[9][63]MAIN[9][60]MAIN[8][60]MAIN[8][63]MAIN[10][62]MAIN[10][60]MAIN[11][62]MAIN[11][60]MAIN[13][62]MAIN[12][62]MAIN[12][60]MAIN[13][60]IMUX_G3_FAN[0]
Source
000000000000off
000100000001OMUX_S5
000100000010OMUX_W14
000100000100OMUX_ES7
000100001000OMUX_E13
000100010000IMUX_G1_FAN[1]
000100100000DBL_S1[8]
000101000000DBL_E1[9]
000110000000IMUX_G2_FAN[1]
001000000001DBL_W0[8]
001000000010OMUX_SW5
001000000100DBL_S0[8]
001000001000DBL_E0[9]
001000010000DBL_W1[7]
001000100000DBL_N1[9]
001001000000DBL_W2[9]
001010000000DBL_N2[9]
010000000001DBL_N0[7]
010000000010DBL_E2[9]
010000000100DBL_E2[8]
010000001000DBL_W2[8]
010000010000DBL_N1[7]
010000100000DBL_W1[8]
010001000000DBL_W1[9]
010010000000DBL_N2[8]
100000000001DBL_W2[7]
100000000010DBL_N0[9]
100000000100DBL_S2[9]
100000001000DBL_S2[8]
100000010000DBL_S1[9]
100000100000DBL_E1[8]
100001000000DBL_N2[7]
100010000000DBL_N1[8]
virtex2 INT_PPC switchbox INT muxes IMUX_G3_FAN[1]
BitsDestination
MAIN[9][62]MAIN[9][61]MAIN[8][61]MAIN[8][62]MAIN[10][63]MAIN[10][61]MAIN[11][63]MAIN[11][61]MAIN[13][63]MAIN[12][63]MAIN[12][61]MAIN[13][61]IMUX_G3_FAN[1]
Source
000000000000off
000100000001OMUX_S5
000100000010OMUX_W14
000100000100OMUX_ES7
000100001000OMUX_E13
000100010000IMUX_G1_FAN[1]
000100100000DBL_S1[8]
000101000000DBL_E1[9]
000110000000IMUX_G2_FAN[1]
001000000001DBL_W0[8]
001000000010OMUX_SW5
001000000100DBL_S0[8]
001000001000DBL_E0[9]
001000010000DBL_W1[7]
001000100000DBL_N1[9]
001001000000DBL_W2[9]
001010000000DBL_N2[9]
010000000001DBL_N0[7]
010000000010DBL_E2[9]
010000000100DBL_E2[8]
010000001000DBL_W2[8]
010000010000DBL_N1[7]
010000100000DBL_W1[8]
010001000000DBL_W1[9]
010010000000DBL_N2[8]
100000000001DBL_W2[7]
100000000010DBL_N0[9]
100000000100DBL_S2[9]
100000001000DBL_S2[8]
100000010000DBL_S1[9]
100000100000DBL_E1[8]
100001000000DBL_N2[7]
100010000000DBL_N1[8]
virtex2 INT_PPC switchbox INT muxes IMUX_G3_DATA[0]
BitsDestination
MAIN[9][79]MAIN[9][76]MAIN[8][76]MAIN[8][79]MAIN[10][78]MAIN[10][76]MAIN[11][78]MAIN[11][76]MAIN[13][78]MAIN[12][78]MAIN[12][76]MAIN[13][76]IMUX_G3_DATA[0]
Source
000000000000PULLUP
000100000001OMUX_S5
000100000010OMUX_W14
000100000100OMUX_ES7
000100001000OMUX_E13
000100010000IMUX_G1_FAN[1]
000100100000DBL_S1[8]
000101000000DBL_E1[9]
000110000000IMUX_G2_FAN[1]
001000000001DBL_W0[8]
001000000010OMUX_SW5
001000000100DBL_S0[8]
001000001000DBL_E0[9]
001000010000DBL_W1[7]
001000100000DBL_N1[9]
001001000000DBL_W2[9]
001010000000DBL_N2[9]
010000000001DBL_N0[7]
010000000010DBL_E2[9]
010000000100DBL_E2[8]
010000001000DBL_W2[8]
010000010000DBL_N1[7]
010000100000DBL_W1[8]
010001000000DBL_W1[9]
010010000000DBL_N2[8]
100000000001DBL_W2[7]
100000000010DBL_N0[9]
100000000100DBL_S2[9]
100000001000DBL_S2[8]
100000010000DBL_S1[9]
100000100000DBL_E1[8]
100001000000DBL_N2[7]
100010000000DBL_N1[8]
virtex2 INT_PPC switchbox INT muxes IMUX_G3_DATA[1]
BitsDestination
MAIN[9][78]MAIN[9][77]MAIN[8][77]MAIN[8][78]MAIN[10][79]MAIN[10][77]MAIN[11][79]MAIN[11][77]MAIN[13][79]MAIN[12][79]MAIN[12][77]MAIN[13][77]IMUX_G3_DATA[1]
Source
000000000000PULLUP
000100000001OMUX_S5
000100000010OMUX_W14
000100000100OMUX_ES7
000100001000OMUX_E13
000100010000IMUX_G1_FAN[1]
000100100000DBL_S1[8]
000101000000DBL_E1[9]
000110000000IMUX_G2_FAN[1]
001000000001DBL_W0[8]
001000000010OMUX_SW5
001000000100DBL_S0[8]
001000001000DBL_E0[9]
001000010000DBL_W1[7]
001000100000DBL_N1[9]
001001000000DBL_W2[9]
001010000000DBL_N2[9]
010000000001DBL_N0[7]
010000000010DBL_E2[9]
010000000100DBL_E2[8]
010000001000DBL_W2[8]
010000010000DBL_N1[7]
010000100000DBL_W1[8]
010001000000DBL_W1[9]
010010000000DBL_N2[8]
100000000001DBL_W2[7]
100000000010DBL_N0[9]
100000000100DBL_S2[9]
100000001000DBL_S2[8]
100000010000DBL_S1[9]
100000100000DBL_E1[8]
100001000000DBL_N2[7]
100010000000DBL_N1[8]
virtex2 INT_PPC switchbox INT muxes IMUX_G3_DATA[2]
BitsDestination
MAIN[9][72]MAIN[9][75]MAIN[8][75]MAIN[8][72]MAIN[10][73]MAIN[10][75]MAIN[11][73]MAIN[11][75]MAIN[13][73]MAIN[12][73]MAIN[12][75]MAIN[13][75]IMUX_G3_DATA[2]
Source
000000000000PULLUP
000100000001OMUX_S5
000100000010OMUX_W14
000100000100OMUX_ES7
000100001000OMUX_E13
000100010000IMUX_G1_FAN[1]
000100100000DBL_S1[8]
000101000000DBL_E1[9]
000110000000IMUX_G2_FAN[1]
001000000001DBL_W0[8]
001000000010OMUX_SW5
001000000100DBL_S0[8]
001000001000DBL_E0[9]
001000010000DBL_W1[7]
001000100000DBL_N1[9]
001001000000DBL_W2[9]
001010000000DBL_N2[9]
010000000001DBL_N0[7]
010000000010DBL_E2[9]
010000000100DBL_E2[8]
010000001000DBL_W2[8]
010000010000DBL_N1[7]
010000100000DBL_W1[8]
010001000000DBL_W1[9]
010010000000DBL_N2[8]
100000000001DBL_W2[7]
100000000010DBL_N0[9]
100000000100DBL_S2[9]
100000001000DBL_S2[8]
100000010000DBL_S1[9]
100000100000DBL_E1[8]
100001000000DBL_N2[7]
100010000000DBL_N1[8]
virtex2 INT_PPC switchbox INT muxes IMUX_G3_DATA[3]
BitsDestination
MAIN[9][73]MAIN[9][74]MAIN[8][74]MAIN[8][73]MAIN[10][72]MAIN[10][74]MAIN[11][72]MAIN[11][74]MAIN[13][72]MAIN[12][72]MAIN[12][74]MAIN[13][74]IMUX_G3_DATA[3]
Source
000000000000PULLUP
000100000001OMUX_S5
000100000010OMUX_W14
000100000100OMUX_ES7
000100001000OMUX_E13
000100010000IMUX_G1_FAN[1]
000100100000DBL_S1[8]
000101000000DBL_E1[9]
000110000000IMUX_G2_FAN[1]
001000000001DBL_W0[8]
001000000010OMUX_SW5
001000000100DBL_S0[8]
001000001000DBL_E0[9]
001000010000DBL_W1[7]
001000100000DBL_N1[9]
001001000000DBL_W2[9]
001010000000DBL_N2[9]
010000000001DBL_N0[7]
010000000010DBL_E2[9]
010000000100DBL_E2[8]
010000001000DBL_W2[8]
010000010000DBL_N1[7]
010000100000DBL_W1[8]
010001000000DBL_W1[9]
010010000000DBL_N2[8]
100000000001DBL_W2[7]
100000000010DBL_N0[9]
100000000100DBL_S2[9]
100000001000DBL_S2[8]
100000010000DBL_S1[9]
100000100000DBL_E1[8]
100001000000DBL_N2[7]
100010000000DBL_N1[8]
virtex2 INT_PPC switchbox INT muxes IMUX_G3_DATA[4]
BitsDestination
MAIN[9][71]MAIN[9][68]MAIN[8][68]MAIN[8][71]MAIN[10][70]MAIN[10][68]MAIN[11][70]MAIN[11][68]MAIN[13][70]MAIN[12][70]MAIN[12][68]MAIN[13][68]IMUX_G3_DATA[4]
Source
000000000000PULLUP
000100000001OMUX_S5
000100000010OMUX_W14
000100000100OMUX_ES7
000100001000OMUX_E13
000100010000IMUX_G1_FAN[1]
000100100000DBL_S1[8]
000101000000DBL_E1[9]
000110000000IMUX_G2_FAN[1]
001000000001DBL_W0[8]
001000000010OMUX_SW5
001000000100DBL_S0[8]
001000001000DBL_E0[9]
001000010000DBL_W1[7]
001000100000DBL_N1[9]
001001000000DBL_W2[9]
001010000000DBL_N2[9]
010000000001DBL_N0[7]
010000000010DBL_E2[9]
010000000100DBL_E2[8]
010000001000DBL_W2[8]
010000010000DBL_N1[7]
010000100000DBL_W1[8]
010001000000DBL_W1[9]
010010000000DBL_N2[8]
100000000001DBL_W2[7]
100000000010DBL_N0[9]
100000000100DBL_S2[9]
100000001000DBL_S2[8]
100000010000DBL_S1[9]
100000100000DBL_E1[8]
100001000000DBL_N2[7]
100010000000DBL_N1[8]
virtex2 INT_PPC switchbox INT muxes IMUX_G3_DATA[5]
BitsDestination
MAIN[9][70]MAIN[9][69]MAIN[8][69]MAIN[8][70]MAIN[10][71]MAIN[10][69]MAIN[11][71]MAIN[11][69]MAIN[13][71]MAIN[12][71]MAIN[12][69]MAIN[13][69]IMUX_G3_DATA[5]
Source
000000000000PULLUP
000100000001OMUX_S5
000100000010OMUX_W14
000100000100OMUX_ES7
000100001000OMUX_E13
000100010000IMUX_G1_FAN[1]
000100100000DBL_S1[8]
000101000000DBL_E1[9]
000110000000IMUX_G2_FAN[1]
001000000001DBL_W0[8]
001000000010OMUX_SW5
001000000100DBL_S0[8]
001000001000DBL_E0[9]
001000010000DBL_W1[7]
001000100000DBL_N1[9]
001001000000DBL_W2[9]
001010000000DBL_N2[9]
010000000001DBL_N0[7]
010000000010DBL_E2[9]
010000000100DBL_E2[8]
010000001000DBL_W2[8]
010000010000DBL_N1[7]
010000100000DBL_W1[8]
010001000000DBL_W1[9]
010010000000DBL_N2[8]
100000000001DBL_W2[7]
100000000010DBL_N0[9]
100000000100DBL_S2[9]
100000001000DBL_S2[8]
100000010000DBL_S1[9]
100000100000DBL_E1[8]
100001000000DBL_N2[7]
100010000000DBL_N1[8]
virtex2 INT_PPC switchbox INT muxes IMUX_G3_DATA[6]
BitsDestination
MAIN[9][64]MAIN[9][67]MAIN[8][67]MAIN[8][64]MAIN[10][65]MAIN[10][67]MAIN[11][65]MAIN[11][67]MAIN[13][65]MAIN[12][65]MAIN[12][67]MAIN[13][67]IMUX_G3_DATA[6]
Source
000000000000PULLUP
000100000001OMUX_S5
000100000010OMUX_W14
000100000100OMUX_ES7
000100001000OMUX_E13
000100010000IMUX_G1_FAN[1]
000100100000DBL_S1[8]
000101000000DBL_E1[9]
000110000000IMUX_G2_FAN[1]
001000000001DBL_W0[8]
001000000010OMUX_SW5
001000000100DBL_S0[8]
001000001000DBL_E0[9]
001000010000DBL_W1[7]
001000100000DBL_N1[9]
001001000000DBL_W2[9]
001010000000DBL_N2[9]
010000000001DBL_N0[7]
010000000010DBL_E2[9]
010000000100DBL_E2[8]
010000001000DBL_W2[8]
010000010000DBL_N1[7]
010000100000DBL_W1[8]
010001000000DBL_W1[9]
010010000000DBL_N2[8]
100000000001DBL_W2[7]
100000000010DBL_N0[9]
100000000100DBL_S2[9]
100000001000DBL_S2[8]
100000010000DBL_S1[9]
100000100000DBL_E1[8]
100001000000DBL_N2[7]
100010000000DBL_N1[8]
virtex2 INT_PPC switchbox INT muxes IMUX_G3_DATA[7]
BitsDestination
MAIN[9][65]MAIN[9][66]MAIN[8][66]MAIN[8][65]MAIN[10][64]MAIN[10][66]MAIN[11][64]MAIN[11][66]MAIN[13][64]MAIN[12][64]MAIN[12][66]MAIN[13][66]IMUX_G3_DATA[7]
Source
000000000000PULLUP
000100000001OMUX_S5
000100000010OMUX_W14
000100000100OMUX_ES7
000100001000OMUX_E13
000100010000IMUX_G1_FAN[1]
000100100000DBL_S1[8]
000101000000DBL_E1[9]
000110000000IMUX_G2_FAN[1]
001000000001DBL_W0[8]
001000000010OMUX_SW5
001000000100DBL_S0[8]
001000001000DBL_E0[9]
001000010000DBL_W1[7]
001000100000DBL_N1[9]
001001000000DBL_W2[9]
001010000000DBL_N2[9]
010000000001DBL_N0[7]
010000000010DBL_E2[9]
010000000100DBL_E2[8]
010000001000DBL_W2[8]
010000010000DBL_N1[7]
010000100000DBL_W1[8]
010001000000DBL_W1[9]
010010000000DBL_N2[8]
100000000001DBL_W2[7]
100000000010DBL_N0[9]
100000000100DBL_S2[9]
100000001000DBL_S2[8]
100000010000DBL_S1[9]
100000100000DBL_E1[8]
100001000000DBL_N2[7]
100010000000DBL_N1[8]

Bitstream

virtex2 INT_PPC rect MAIN
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21
B79 - - - - INT: mux IMUX_CE[2] bit 5 INT: mux IMUX_CE[3] bit 1 INT: mux OMUX[14] bit 0 INT: mux OMUX[15] bit 6 INT: mux IMUX_G3_DATA[0] bit 8 INT: mux IMUX_G3_DATA[0] bit 11 INT: mux IMUX_G3_DATA[1] bit 7 INT: mux IMUX_G3_DATA[1] bit 5 INT: mux IMUX_G3_DATA[1] bit 2 INT: mux IMUX_G3_DATA[1] bit 3 INT: mux DBL_E0[9] bit 0 INT: mux DBL_W0[9] bit 7 INT: mux DBL_E0[9] bit 5 INT: mux DBL_E0[9] bit 7 INT: mux HEX_W0[9] bit 0 INT: mux HEX_W0[9] bit 3 INT: mux HEX_W0[9] bit 4 INT: mux LV[18] bit 1
B78 - - - - INT: !invert IMUX_CE_OPTINV[3] ← IMUX_CE[3] INT: mux IMUX_CE[3] bit 3 INT: mux OMUX[15] bit 9 INT: mux OMUX[15] bit 7 INT: mux IMUX_G3_DATA[1] bit 8 INT: mux IMUX_G3_DATA[1] bit 11 INT: mux IMUX_G3_DATA[0] bit 7 INT: mux IMUX_G3_DATA[0] bit 5 INT: mux IMUX_G3_DATA[0] bit 2 INT: mux IMUX_G3_DATA[0] bit 3 INT: mux DBL_E0[9] bit 1 INT: mux DBL_W0[9] bit 4 INT: mux DBL_W0[9] bit 3 INT: mux DBL_W0[9] bit 0 INT: mux HEX_E0[9] bit 1 INT: mux HEX_E0[9] bit 3 INT: mux HEX_E0[9] bit 5 INT: mux HEX_W0[9] bit 6
B77 - - - - INT: mux IMUX_CE[3] bit 0 INT: mux IMUX_CE[3] bit 2 INT: mux OMUX[15] bit 0 INT: mux OMUX[15] bit 8 INT: mux IMUX_G3_DATA[1] bit 9 INT: mux IMUX_G3_DATA[1] bit 10 INT: mux IMUX_G3_DATA[1] bit 6 INT: mux IMUX_G3_DATA[1] bit 4 INT: mux IMUX_G3_DATA[1] bit 1 INT: mux IMUX_G3_DATA[1] bit 0 INT: mux DBL_W0[9] bit 5 INT: mux DBL_E0[9] bit 3 INT: mux DBL_W0[9] bit 2 INT: mux DBL_W0[9] bit 1 INT: mux HEX_W0[9] bit 2 INT: mux HEX_W0[9] bit 1 INT: mux HEX_E0[9] bit 6 INT: mux LV[18] bit 3
B76 - - - - INT: mux IMUX_CE[3] bit 4 INT: mux IMUX_CE[3] bit 5 INT: mux OMUX[14] bit 1 INT: mux OMUX[15] bit 1 INT: mux IMUX_G3_DATA[0] bit 9 INT: mux IMUX_G3_DATA[0] bit 10 INT: mux IMUX_G3_DATA[0] bit 6 INT: mux IMUX_G3_DATA[0] bit 4 INT: mux IMUX_G3_DATA[0] bit 1 INT: mux IMUX_G3_DATA[0] bit 0 INT: mux DBL_W0[9] bit 6 INT: mux DBL_E0[9] bit 2 INT: mux DBL_E0[9] bit 4 INT: mux DBL_E0[9] bit 6 INT: mux HEX_E0[9] bit 2 INT: mux HEX_E0[9] bit 0 INT: mux HEX_E0[9] bit 4 INT: mux HEX_W0[9] bit 5
B75 - - - - INT: mux IMUX_CE[2] bit 4 INT: mux IMUX_CE[2] bit 7 INT: mux OMUX[15] bit 2 INT: mux OMUX[14] bit 2 INT: mux IMUX_G3_DATA[2] bit 9 INT: mux IMUX_G3_DATA[2] bit 10 INT: mux IMUX_G3_DATA[2] bit 6 INT: mux IMUX_G3_DATA[2] bit 4 INT: mux IMUX_G3_DATA[2] bit 1 INT: mux IMUX_G3_DATA[2] bit 0 INT: mux DBL_S0[9] bit 4 INT: mux DBL_N0[9] bit 2 INT: mux DBL_S0[9] bit 0 INT: mux DBL_S0[9] bit 3 INT: mux HEX_N0[9] bit 1 INT: mux HEX_N0[9] bit 3 INT: mux HEX_N0[9] bit 5 INT: mux LV[6] bit 0
B74 - - - - INT: mux IMUX_CE[3] bit 7 INT: mux IMUX_CE[3] bit 6 INT: mux OMUX[15] bit 3 INT: mux OMUX[14] bit 3 INT: mux IMUX_G3_DATA[3] bit 9 INT: mux IMUX_G3_DATA[3] bit 10 INT: mux IMUX_G3_DATA[3] bit 6 INT: mux IMUX_G3_DATA[3] bit 4 INT: mux IMUX_G3_DATA[3] bit 1 INT: mux IMUX_G3_DATA[3] bit 0 INT: mux DBL_S0[9] bit 5 INT: mux DBL_N0[9] bit 0 INT: mux DBL_N0[9] bit 7 INT: mux DBL_N0[9] bit 5 INT: mux HEX_S0[9] bit 1 INT: mux HEX_S0[9] bit 2 INT: mux HEX_S0[9] bit 4 INT: mux HEX_N0[9] bit 4
B73 - - - - INT: mux IMUX_CE[2] bit 0 INT: mux IMUX_CE[2] bit 1 INT: mux OMUX[14] bit 4 INT: mux OMUX[15] bit 4 INT: mux IMUX_G3_DATA[3] bit 8 INT: mux IMUX_G3_DATA[3] bit 11 INT: mux IMUX_G3_DATA[2] bit 7 INT: mux IMUX_G3_DATA[2] bit 5 INT: mux IMUX_G3_DATA[2] bit 2 INT: mux IMUX_G3_DATA[2] bit 3 INT: mux DBL_N0[9] bit 1 INT: mux DBL_S0[9] bit 6 INT: mux DBL_N0[9] bit 6 INT: mux DBL_N0[9] bit 4 INT: mux HEX_N0[9] bit 2 INT: mux HEX_N0[9] bit 0 INT: mux HEX_S0[9] bit 5 INT: mux LV[6] bit 6
B72 - - - - INT: !invert IMUX_CE_OPTINV[2] ← IMUX_CE[2] INT: mux IMUX_CE[2] bit 3 INT: mux OMUX[15] bit 5 INT: mux OMUX[14] bit 8 INT: mux IMUX_G3_DATA[2] bit 8 INT: mux IMUX_G3_DATA[2] bit 11 INT: mux IMUX_G3_DATA[3] bit 7 INT: mux IMUX_G3_DATA[3] bit 5 INT: mux IMUX_G3_DATA[3] bit 2 INT: mux IMUX_G3_DATA[3] bit 3 INT: mux DBL_N0[9] bit 3 INT: mux DBL_S0[9] bit 7 INT: mux DBL_S0[9] bit 1 INT: mux DBL_S0[9] bit 2 INT: mux HEX_S0[9] bit 3 INT: mux HEX_S0[9] bit 0 INT: mux HEX_S0[9] bit 6 INT: mux HEX_N0[9] bit 6
B71 - - - - INT: mux IMUX_CE[2] bit 6 INT: mux IMUX_CE[2] bit 2 INT: mux OMUX[14] bit 9 INT: mux OMUX[14] bit 7 INT: mux IMUX_G3_DATA[4] bit 8 INT: mux IMUX_G3_DATA[4] bit 11 INT: mux IMUX_G3_DATA[5] bit 7 INT: mux IMUX_G3_DATA[5] bit 5 INT: mux IMUX_G3_DATA[5] bit 2 INT: mux IMUX_G3_DATA[5] bit 3 INT: mux DBL_E0[8] bit 2 INT: mux DBL_W0[8] bit 3 INT: mux DBL_E0[8] bit 4 INT: mux DBL_E0[8] bit 7 INT: mux HEX_E0[8] bit 0 INT: mux HEX_E0[8] bit 3 INT: mux HEX_E0[8] bit 4 INT: mux LV[6] bit 2
B70 - - - - INT: mux IMUX_CE[1] bit 5 INT: mux IMUX_CE[1] bit 2 INT: mux OMUX[14] bit 5 INT: mux OMUX[14] bit 6 INT: mux IMUX_G3_DATA[5] bit 8 INT: mux IMUX_G3_DATA[5] bit 11 INT: mux IMUX_G3_DATA[4] bit 7 INT: mux IMUX_G3_DATA[4] bit 5 INT: mux IMUX_G3_DATA[4] bit 2 INT: mux IMUX_G3_DATA[4] bit 3 INT: mux DBL_E0[8] bit 0 INT: mux DBL_W0[8] bit 0 INT: mux DBL_W0[8] bit 7 INT: mux DBL_W0[8] bit 4 INT: mux HEX_W0[8] bit 0 INT: mux HEX_W0[8] bit 3 INT: mux HEX_W0[8] bit 4 INT: mux HEX_E0[8] bit 5
B69 - - - - INT: !invert IMUX_CE_OPTINV[1] ← IMUX_CE[1] INT: mux IMUX_CE[1] bit 3 INT: mux OMUX[12] bit 1 INT: mux OMUX[13] bit 6 INT: mux IMUX_G3_DATA[5] bit 9 INT: mux IMUX_G3_DATA[5] bit 10 INT: mux IMUX_G3_DATA[5] bit 6 INT: mux IMUX_G3_DATA[5] bit 4 INT: mux IMUX_G3_DATA[5] bit 1 INT: mux IMUX_G3_DATA[5] bit 0 INT: mux DBL_W0[8] bit 2 INT: mux DBL_E0[8] bit 3 INT: mux DBL_W0[8] bit 6 INT: mux DBL_W0[8] bit 5 INT: mux HEX_E0[8] bit 2 INT: mux HEX_E0[8] bit 1 INT: mux HEX_W0[8] bit 5 INT: mux LV[6] bit 3
B68 - - - - INT: mux IMUX_CE[1] bit 1 INT: mux IMUX_CE[1] bit 0 INT: mux OMUX[13] bit 9 INT: mux OMUX[13] bit 7 INT: mux IMUX_G3_DATA[4] bit 9 INT: mux IMUX_G3_DATA[4] bit 10 INT: mux IMUX_G3_DATA[4] bit 6 INT: mux IMUX_G3_DATA[4] bit 4 INT: mux IMUX_G3_DATA[4] bit 1 INT: mux IMUX_G3_DATA[4] bit 0 INT: mux DBL_W0[8] bit 1 INT: mux DBL_E0[8] bit 1 INT: mux DBL_E0[8] bit 5 INT: mux DBL_E0[8] bit 6 INT: mux HEX_W0[8] bit 2 INT: mux HEX_W0[8] bit 1 INT: mux HEX_W0[8] bit 6 INT: mux HEX_E0[8] bit 6
B67 - - - - INT: mux IMUX_CE[0] bit 4 INT: mux IMUX_CE[0] bit 5 INT: mux OMUX[13] bit 1 INT: mux OMUX[13] bit 8 INT: mux IMUX_G3_DATA[6] bit 9 INT: mux IMUX_G3_DATA[6] bit 10 INT: mux IMUX_G3_DATA[6] bit 6 INT: mux IMUX_G3_DATA[6] bit 4 INT: mux IMUX_G3_DATA[6] bit 1 INT: mux IMUX_G3_DATA[6] bit 0 INT: mux DBL_S0[8] bit 3 INT: mux DBL_N0[8] bit 1 INT: mux DBL_S0[8] bit 5 INT: mux DBL_S0[8] bit 7 INT: mux HEX_S0[8] bit 1 INT: mux HEX_S0[8] bit 3 INT: mux HEX_S0[8] bit 5 INT: mux LV[18] bit 6
B66 - - - - INT: mux IMUX_CE[1] bit 6 INT: mux IMUX_CE[1] bit 4 INT: mux OMUX[12] bit 0 INT: mux OMUX[13] bit 0 INT: mux IMUX_G3_DATA[7] bit 9 INT: mux IMUX_G3_DATA[7] bit 10 INT: mux IMUX_G3_DATA[7] bit 6 INT: mux IMUX_G3_DATA[7] bit 4 INT: mux IMUX_G3_DATA[7] bit 1 INT: mux IMUX_G3_DATA[7] bit 0 INT: mux DBL_S0[8] bit 0 INT: mux DBL_N0[8] bit 0 INT: mux DBL_N0[8] bit 7 INT: mux DBL_N0[8] bit 5 INT: mux HEX_N0[8] bit 1 INT: mux HEX_N0[8] bit 2 INT: mux HEX_N0[8] bit 5 INT: mux HEX_S0[8] bit 4
B65 - - - - INT: mux IMUX_CE[0] bit 6 INT: mux IMUX_CE[0] bit 7 INT: mux OMUX[13] bit 2 INT: mux OMUX[12] bit 2 INT: mux IMUX_G3_DATA[7] bit 8 INT: mux IMUX_G3_DATA[7] bit 11 INT: mux IMUX_G3_DATA[6] bit 7 INT: mux IMUX_G3_DATA[6] bit 5 INT: mux IMUX_G3_DATA[6] bit 2 INT: mux IMUX_G3_DATA[6] bit 3 INT: mux DBL_N0[8] bit 3 INT: mux DBL_S0[8] bit 1 INT: mux DBL_N0[8] bit 6 INT: mux DBL_N0[8] bit 4 INT: mux HEX_S0[8] bit 2 INT: mux HEX_S0[8] bit 0 INT: mux HEX_N0[8] bit 4 INT: mux LV[6] bit 1
B64 - - - - INT: mux IMUX_CE[0] bit 1 INT: mux IMUX_CE[0] bit 2 INT: mux OMUX[13] bit 3 INT: mux OMUX[12] bit 3 INT: mux IMUX_G3_DATA[6] bit 8 INT: mux IMUX_G3_DATA[6] bit 11 INT: mux IMUX_G3_DATA[7] bit 7 INT: mux IMUX_G3_DATA[7] bit 5 INT: mux IMUX_G3_DATA[7] bit 2 INT: mux IMUX_G3_DATA[7] bit 3 INT: mux DBL_N0[8] bit 2 INT: mux DBL_S0[8] bit 2 INT: mux DBL_S0[8] bit 4 INT: mux DBL_S0[8] bit 6 INT: mux HEX_N0[8] bit 3 INT: mux HEX_N0[8] bit 0 INT: mux HEX_N0[8] bit 6 INT: mux HEX_S0[8] bit 6
B63 - - - - INT: !invert IMUX_CE_OPTINV[0] ← IMUX_CE[0] INT: mux IMUX_CE[0] bit 3 INT: mux OMUX[12] bit 4 INT: mux OMUX[13] bit 4 INT: mux IMUX_G3_FAN[0] bit 8 INT: mux IMUX_G3_FAN[0] bit 11 INT: mux IMUX_G3_FAN[1] bit 7 INT: mux IMUX_G3_FAN[1] bit 5 INT: mux IMUX_G3_FAN[1] bit 2 INT: mux IMUX_G3_FAN[1] bit 3 INT: mux DBL_E0[7] bit 2 INT: mux DBL_W0[7] bit 3 INT: mux DBL_E0[7] bit 4 INT: mux DBL_E0[7] bit 7 INT: mux HEX_W0[7] bit 0 INT: mux HEX_W0[7] bit 3 INT: mux HEX_W0[7] bit 4 INT: mux LV[18] bit 0
B62 - - - - INT: mux IMUX_CE[1] bit 7 INT: mux IMUX_CE[0] bit 0 INT: mux OMUX[13] bit 5 INT: mux OMUX[12] bit 8 INT: mux IMUX_G3_FAN[1] bit 8 INT: mux IMUX_G3_FAN[1] bit 11 INT: mux IMUX_G3_FAN[0] bit 7 INT: mux IMUX_G3_FAN[0] bit 5 INT: mux IMUX_G3_FAN[0] bit 2 INT: mux IMUX_G3_FAN[0] bit 3 INT: mux DBL_E0[7] bit 0 INT: mux DBL_W0[7] bit 0 INT: mux DBL_W0[7] bit 7 INT: mux DBL_W0[7] bit 4 INT: mux HEX_E0[7] bit 0 INT: mux HEX_E0[7] bit 3 INT: mux HEX_E0[7] bit 4 INT: mux HEX_W0[7] bit 5
B61 - - - - INT: mux IMUX_CLK[2] bit 0 INT: mux IMUX_CLK[3] bit 7 INT: mux OMUX[12] bit 9 INT: mux OMUX[12] bit 7 INT: mux IMUX_G3_FAN[1] bit 9 INT: mux IMUX_G3_FAN[1] bit 10 INT: mux IMUX_G3_FAN[1] bit 6 INT: mux IMUX_G3_FAN[1] bit 4 INT: mux IMUX_G3_FAN[1] bit 1 INT: mux IMUX_G3_FAN[1] bit 0 INT: mux DBL_W0[7] bit 2 INT: mux DBL_E0[7] bit 3 INT: mux DBL_W0[7] bit 6 INT: mux DBL_W0[7] bit 5 INT: mux HEX_W0[7] bit 2 INT: mux HEX_W0[7] bit 1 INT: mux HEX_E0[7] bit 5 INT: mux LV[6] bit 5
B60 - - - - INT: invert IMUX_CLK_OPTINV[3] ← IMUX_CLK[3] INT: mux IMUX_CLK[3] bit 9 INT: mux OMUX[12] bit 5 INT: mux OMUX[12] bit 6 INT: mux IMUX_G3_FAN[0] bit 9 INT: mux IMUX_G3_FAN[0] bit 10 INT: mux IMUX_G3_FAN[0] bit 6 INT: mux IMUX_G3_FAN[0] bit 4 INT: mux IMUX_G3_FAN[0] bit 1 INT: mux IMUX_G3_FAN[0] bit 0 INT: mux DBL_W0[7] bit 1 INT: mux DBL_E0[7] bit 1 INT: mux DBL_E0[7] bit 5 INT: mux DBL_E0[7] bit 6 INT: mux HEX_E0[7] bit 2 INT: mux HEX_E0[7] bit 1 INT: mux HEX_E0[7] bit 6 INT: mux HEX_W0[7] bit 6
B59 - - - - INT: mux IMUX_CLK[3] bit 6 INT: mux IMUX_CLK[3] bit 8 INT: mux OMUX[10] bit 1 INT: mux OMUX[11] bit 6 INT: mux IMUX_G2_FAN[0] bit 9 INT: mux IMUX_G2_FAN[0] bit 10 INT: mux IMUX_G2_FAN[0] bit 6 INT: mux IMUX_G2_FAN[0] bit 5 INT: mux IMUX_G2_FAN[0] bit 1 INT: mux IMUX_G2_FAN[0] bit 3 INT: mux DBL_S0[7] bit 4 INT: mux DBL_N0[7] bit 6 INT: mux DBL_S0[7] bit 1 INT: mux DBL_S0[7] bit 3 INT: mux HEX_N0[7] bit 1 INT: mux HEX_N0[7] bit 3 INT: mux HEX_N0[7] bit 6 INT: mux LV[18] bit 2
B58 - - - - INT: mux IMUX_CLK[3] bit 3 INT: mux IMUX_CLK[3] bit 0 INT: mux OMUX[11] bit 9 INT: mux OMUX[11] bit 7 INT: mux IMUX_G2_FAN[1] bit 9 INT: mux IMUX_G2_FAN[1] bit 10 INT: mux IMUX_G2_FAN[1] bit 6 INT: mux IMUX_G2_FAN[1] bit 5 INT: mux IMUX_G2_FAN[1] bit 1 INT: mux IMUX_G2_FAN[1] bit 3 INT: mux DBL_S0[7] bit 5 INT: mux DBL_N0[7] bit 5 INT: mux DBL_N0[7] bit 3 INT: mux DBL_N0[7] bit 1 INT: mux HEX_S0[7] bit 1 INT: mux HEX_S0[7] bit 2 INT: mux HEX_S0[7] bit 5 INT: mux HEX_N0[7] bit 5
B57 - - - - INT: mux IMUX_CLK[2] bit 3 INT: mux IMUX_CLK[2] bit 1 INT: mux OMUX[11] bit 1 INT: mux OMUX[11] bit 8 INT: mux IMUX_G2_FAN[1] bit 8 INT: mux IMUX_G2_FAN[1] bit 11 INT: mux IMUX_G2_FAN[0] bit 7 INT: mux IMUX_G2_FAN[0] bit 4 INT: mux IMUX_G2_FAN[0] bit 0 INT: mux IMUX_G2_FAN[0] bit 2 INT: mux DBL_N0[7] bit 4 INT: mux DBL_S0[7] bit 6 INT: mux DBL_N0[7] bit 2 INT: mux DBL_N0[7] bit 0 INT: mux HEX_N0[7] bit 2 INT: mux HEX_N0[7] bit 0 INT: mux HEX_S0[7] bit 6 INT: mux LV[18] bit 4
B56 - - - - INT: mux IMUX_CLK[3] bit 1 INT: mux IMUX_CLK[3] bit 2 INT: mux OMUX[10] bit 0 INT: mux OMUX[11] bit 0 INT: mux IMUX_G2_FAN[0] bit 8 INT: mux IMUX_G2_FAN[0] bit 11 INT: mux IMUX_G2_FAN[1] bit 7 INT: mux IMUX_G2_FAN[1] bit 4 INT: mux IMUX_G2_FAN[1] bit 0 INT: mux IMUX_G2_FAN[1] bit 2 INT: mux DBL_N0[7] bit 7 INT: mux DBL_S0[7] bit 7 INT: mux DBL_S0[7] bit 0 INT: mux DBL_S0[7] bit 2 INT: mux HEX_S0[7] bit 3 INT: mux HEX_S0[7] bit 0 INT: mux HEX_S0[7] bit 4 INT: mux HEX_N0[7] bit 4
B55 - - - - INT: mux IMUX_CLK[2] bit 4 INT: mux IMUX_CLK[2] bit 2 INT: mux OMUX[11] bit 2 INT: mux OMUX[10] bit 2 INT: mux IMUX_G2_DATA[6] bit 8 INT: mux IMUX_G2_DATA[6] bit 11 INT: mux IMUX_G2_DATA[7] bit 7 INT: mux IMUX_G2_DATA[7] bit 4 INT: mux IMUX_G2_DATA[7] bit 0 INT: mux IMUX_G2_DATA[7] bit 2 INT: mux DBL_E0[6] bit 1 INT: mux DBL_W0[6] bit 7 INT: mux DBL_E0[6] bit 5 INT: mux DBL_E0[6] bit 7 INT: mux HEX_E0[6] bit 1 INT: mux HEX_E0[6] bit 3 INT: mux HEX_E0[6] bit 5 INT: mux LV[6] bit 4
B54 - - - - INT: mux IMUX_CLK[3] bit 4 INT: mux IMUX_CLK[2] bit 9 INT: mux OMUX[11] bit 3 INT: mux OMUX[10] bit 3 INT: mux IMUX_G2_DATA[7] bit 8 INT: mux IMUX_G2_DATA[7] bit 11 INT: mux IMUX_G2_DATA[6] bit 7 INT: mux IMUX_G2_DATA[6] bit 4 INT: mux IMUX_G2_DATA[6] bit 0 INT: mux IMUX_G2_DATA[6] bit 2 INT: mux DBL_E0[6] bit 0 INT: mux DBL_W0[6] bit 5 INT: mux DBL_W0[6] bit 3 INT: mux DBL_W0[6] bit 0 INT: mux HEX_W0[6] bit 1 INT: mux HEX_W0[6] bit 3 INT: mux HEX_W0[6] bit 4 INT: mux HEX_E0[6] bit 4
B53 - - - - INT: mux IMUX_CLK[2] bit 6 INT: mux IMUX_CLK[2] bit 8 INT: mux OMUX[10] bit 4 INT: mux OMUX[11] bit 4 INT: mux IMUX_G2_DATA[7] bit 9 INT: mux IMUX_G2_DATA[7] bit 10 INT: mux IMUX_G2_DATA[7] bit 6 INT: mux IMUX_G2_DATA[7] bit 5 INT: mux IMUX_G2_DATA[7] bit 1 INT: mux IMUX_G2_DATA[7] bit 3 INT: mux DBL_W0[6] bit 4 INT: mux DBL_E0[6] bit 3 INT: mux DBL_W0[6] bit 2 INT: mux DBL_W0[6] bit 1 INT: mux HEX_E0[6] bit 2 INT: mux HEX_E0[6] bit 0 INT: mux HEX_W0[6] bit 5 INT: mux LV[18] bit 5
B52 - - - - INT: invert IMUX_CLK_OPTINV[2] ← IMUX_CLK[2] INT: mux IMUX_CLK[3] bit 5 INT: mux OMUX[11] bit 5 INT: mux OMUX[10] bit 8 INT: mux IMUX_G2_DATA[6] bit 9 INT: mux IMUX_G2_DATA[6] bit 10 INT: mux IMUX_G2_DATA[6] bit 6 INT: mux IMUX_G2_DATA[6] bit 5 INT: mux IMUX_G2_DATA[6] bit 1 INT: mux IMUX_G2_DATA[6] bit 3 INT: mux DBL_W0[6] bit 6 INT: mux DBL_E0[6] bit 2 INT: mux DBL_E0[6] bit 4 INT: mux DBL_E0[6] bit 6 INT: mux HEX_W0[6] bit 2 INT: mux HEX_W0[6] bit 0 INT: mux HEX_W0[6] bit 6 INT: mux HEX_E0[6] bit 6
B51 - - - - INT: mux IMUX_CLK[2] bit 5 INT: mux IMUX_CLK[2] bit 7 INT: mux OMUX[10] bit 9 INT: mux OMUX[10] bit 7 INT: mux IMUX_G2_DATA[4] bit 9 INT: mux IMUX_G2_DATA[4] bit 10 INT: mux IMUX_G2_DATA[4] bit 6 INT: mux IMUX_G2_DATA[4] bit 5 INT: mux IMUX_G2_DATA[4] bit 1 INT: mux IMUX_G2_DATA[4] bit 3 INT: mux DBL_S0[6] bit 3 INT: mux DBL_N0[6] bit 1 INT: mux DBL_S0[6] bit 4 INT: mux DBL_S0[6] bit 7 INT: mux HEX_S0[6] bit 0 INT: mux HEX_S0[6] bit 3 INT: mux HEX_S0[6] bit 4 INT: mux LH[0] bit 0
B50 - - - - INT: mux IMUX_CLK[1] bit 5 INT: mux IMUX_CLK[1] bit 7 INT: mux OMUX[10] bit 5 INT: mux OMUX[10] bit 6 INT: mux IMUX_G2_DATA[5] bit 9 INT: mux IMUX_G2_DATA[5] bit 10 INT: mux IMUX_G2_DATA[5] bit 6 INT: mux IMUX_G2_DATA[5] bit 5 INT: mux IMUX_G2_DATA[5] bit 1 INT: mux IMUX_G2_DATA[5] bit 3 INT: mux DBL_S0[6] bit 0 INT: mux DBL_N0[6] bit 0 INT: mux DBL_N0[6] bit 7 INT: mux DBL_N0[6] bit 4 INT: mux HEX_N0[6] bit 0 INT: mux HEX_N0[6] bit 2 INT: mux HEX_N0[6] bit 4 INT: mux HEX_S0[6] bit 5
B49 - - - - INT: invert IMUX_CLK_OPTINV[1] ← IMUX_CLK[1] INT: mux IMUX_CLK[0] bit 5 INT: mux OMUX[8] bit 0 INT: mux OMUX[9] bit 6 INT: mux IMUX_G2_DATA[5] bit 8 INT: mux IMUX_G2_DATA[5] bit 11 INT: mux IMUX_G2_DATA[4] bit 7 INT: mux IMUX_G2_DATA[4] bit 4 INT: mux IMUX_G2_DATA[4] bit 0 INT: mux IMUX_G2_DATA[4] bit 2 INT: mux DBL_N0[6] bit 3 INT: mux DBL_S0[6] bit 1 INT: mux DBL_N0[6] bit 6 INT: mux DBL_N0[6] bit 5 INT: mux HEX_S0[6] bit 2 INT: mux HEX_S0[6] bit 1 INT: mux HEX_N0[6] bit 5 INT: mux LH[0] bit 1
B48 - - - - INT: mux IMUX_CLK[1] bit 6 INT: mux IMUX_CLK[1] bit 8 INT: mux OMUX[9] bit 9 INT: mux OMUX[9] bit 7 INT: mux IMUX_G2_DATA[4] bit 8 INT: mux IMUX_G2_DATA[4] bit 11 INT: mux IMUX_G2_DATA[5] bit 7 INT: mux IMUX_G2_DATA[5] bit 4 INT: mux IMUX_G2_DATA[5] bit 0 INT: mux IMUX_G2_DATA[5] bit 2 INT: mux DBL_N0[6] bit 2 INT: mux DBL_S0[6] bit 2 INT: mux DBL_S0[6] bit 5 INT: mux DBL_S0[6] bit 6 INT: mux HEX_N0[6] bit 3 INT: mux HEX_N0[6] bit 1 INT: mux HEX_N0[6] bit 6 INT: mux HEX_S0[6] bit 6
B47 - - - - INT: mux IMUX_CLK[0] bit 4 INT: mux IMUX_CLK[1] bit 9 INT: mux OMUX[9] bit 0 INT: mux OMUX[9] bit 8 INT: mux IMUX_G2_DATA[2] bit 8 INT: mux IMUX_G2_DATA[2] bit 11 INT: mux IMUX_G2_DATA[3] bit 7 INT: mux IMUX_G2_DATA[3] bit 4 INT: mux IMUX_G2_DATA[3] bit 0 INT: mux IMUX_G2_DATA[3] bit 2 INT: mux DBL_E0[5] bit 2 INT: mux DBL_W0[5] bit 3 INT: mux DBL_E0[5] bit 4 INT: mux DBL_E0[5] bit 7 INT: mux HEX_W0[5] bit 1 INT: mux HEX_W0[5] bit 3 INT: mux HEX_W0[5] bit 5 INT: mux LH[0] bit 2
B46 - - - - INT: mux IMUX_CLK[1] bit 4 INT: mux IMUX_CLK[1] bit 2 INT: mux OMUX[8] bit 1 INT: mux OMUX[9] bit 1 INT: mux IMUX_G2_DATA[3] bit 8 INT: mux IMUX_G2_DATA[3] bit 11 INT: mux IMUX_G2_DATA[2] bit 7 INT: mux IMUX_G2_DATA[2] bit 4 INT: mux IMUX_G2_DATA[2] bit 0 INT: mux IMUX_G2_DATA[2] bit 2 INT: mux DBL_E0[5] bit 0 INT: mux DBL_W0[5] bit 0 INT: mux DBL_W0[5] bit 7 INT: mux DBL_W0[5] bit 5 INT: mux HEX_E0[5] bit 0 INT: mux HEX_E0[5] bit 3 INT: mux HEX_E0[5] bit 4 INT: mux HEX_W0[5] bit 4
B45 - - - - INT: mux IMUX_CLK[0] bit 1 INT: mux IMUX_CLK[0] bit 2 INT: mux OMUX[9] bit 2 INT: mux OMUX[8] bit 2 INT: mux IMUX_G2_DATA[3] bit 9 INT: mux IMUX_G2_DATA[3] bit 10 INT: mux IMUX_G2_DATA[3] bit 6 INT: mux IMUX_G2_DATA[3] bit 5 INT: mux IMUX_G2_DATA[3] bit 1 INT: mux IMUX_G2_DATA[3] bit 3 INT: mux DBL_W0[5] bit 2 INT: mux DBL_E0[5] bit 3 INT: mux DBL_W0[5] bit 6 INT: mux DBL_W0[5] bit 4 INT: mux HEX_W0[5] bit 2 INT: mux HEX_W0[5] bit 0 INT: mux HEX_E0[5] bit 5 INT: mux LH[12] bit 1
B44 - - - - INT: mux IMUX_CLK[1] bit 3 INT: mux IMUX_CLK[1] bit 1 INT: mux OMUX[9] bit 3 INT: mux OMUX[8] bit 3 INT: mux IMUX_G2_DATA[2] bit 9 INT: mux IMUX_G2_DATA[2] bit 10 INT: mux IMUX_G2_DATA[2] bit 6 INT: mux IMUX_G2_DATA[2] bit 5 INT: mux IMUX_G2_DATA[2] bit 1 INT: mux IMUX_G2_DATA[2] bit 3 INT: mux DBL_W0[5] bit 1 INT: mux DBL_E0[5] bit 1 INT: mux DBL_E0[5] bit 5 INT: mux DBL_E0[5] bit 6 INT: mux HEX_E0[5] bit 2 INT: mux HEX_E0[5] bit 1 INT: mux HEX_E0[5] bit 6 INT: mux HEX_W0[5] bit 6
B43 - - - - INT: mux IMUX_CLK[0] bit 3 INT: mux IMUX_CLK[0] bit 0 INT: mux OMUX[8] bit 4 INT: mux OMUX[9] bit 4 INT: mux IMUX_G2_DATA[0] bit 9 INT: mux IMUX_G2_DATA[0] bit 10 INT: mux IMUX_G2_DATA[0] bit 6 INT: mux IMUX_G2_DATA[0] bit 5 INT: mux IMUX_G2_DATA[0] bit 1 INT: mux IMUX_G2_DATA[0] bit 3 INT: mux DBL_S0[5] bit 3 INT: mux DBL_N0[5] bit 1 INT: mux DBL_S0[5] bit 4 INT: mux DBL_S0[5] bit 7 INT: mux HEX_N0[5] bit 1 INT: mux HEX_N0[5] bit 3 INT: mux HEX_N0[5] bit 5 INT: mux LH[12] bit 0
B42 - - - - INT: mux IMUX_CLK[0] bit 6 INT: mux IMUX_CLK[0] bit 8 INT: mux OMUX[9] bit 5 INT: mux OMUX[8] bit 8 INT: mux IMUX_G2_DATA[1] bit 9 INT: mux IMUX_G2_DATA[1] bit 10 INT: mux IMUX_G2_DATA[1] bit 6 INT: mux IMUX_G2_DATA[1] bit 5 INT: mux IMUX_G2_DATA[1] bit 1 INT: mux IMUX_G2_DATA[1] bit 3 INT: mux DBL_S0[5] bit 0 INT: mux DBL_N0[5] bit 0 INT: mux DBL_N0[5] bit 7 INT: mux DBL_N0[5] bit 5 INT: mux HEX_S0[5] bit 0 INT: mux HEX_S0[5] bit 2 INT: mux HEX_S0[5] bit 4 INT: mux HEX_N0[5] bit 4
B41 - - - - INT: invert IMUX_CLK_OPTINV[0] ← IMUX_CLK[0] INT: mux IMUX_CLK[0] bit 9 INT: mux OMUX[8] bit 9 INT: mux OMUX[8] bit 7 INT: mux IMUX_G2_DATA[1] bit 8 INT: mux IMUX_G2_DATA[1] bit 11 INT: mux IMUX_G2_DATA[0] bit 7 INT: mux IMUX_G2_DATA[0] bit 4 INT: mux IMUX_G2_DATA[0] bit 0 INT: mux IMUX_G2_DATA[0] bit 2 INT: mux DBL_N0[5] bit 3 INT: mux DBL_S0[5] bit 1 INT: mux DBL_N0[5] bit 6 INT: mux DBL_N0[5] bit 4 INT: mux HEX_N0[5] bit 2 INT: mux HEX_N0[5] bit 0 INT: mux HEX_S0[5] bit 5 INT: mux LH[12] bit 2
B40 - - - - INT: mux IMUX_CLK[1] bit 0 INT: mux IMUX_CLK[0] bit 7 INT: mux OMUX[8] bit 5 INT: mux OMUX[8] bit 6 INT: mux IMUX_G2_DATA[0] bit 8 INT: mux IMUX_G2_DATA[0] bit 11 INT: mux IMUX_G2_DATA[1] bit 7 INT: mux IMUX_G2_DATA[1] bit 4 INT: mux IMUX_G2_DATA[1] bit 0 INT: mux IMUX_G2_DATA[1] bit 2 INT: mux DBL_N0[5] bit 2 INT: mux DBL_S0[5] bit 2 INT: mux DBL_S0[5] bit 5 INT: mux DBL_S0[5] bit 6 INT: mux HEX_S0[5] bit 3 INT: mux HEX_S0[5] bit 1 INT: mux HEX_S0[5] bit 6 INT: mux HEX_N0[5] bit 6
B39 - - - - - INT: mux IMUX_TS[0] bit 7 INT: mux OMUX[6] bit 0 INT: mux OMUX[7] bit 6 INT: mux IMUX_G1_DATA[0] bit 9 INT: mux IMUX_G1_DATA[0] bit 11 INT: mux IMUX_G1_DATA[1] bit 7 INT: mux IMUX_G1_DATA[1] bit 5 INT: mux IMUX_G1_DATA[1] bit 1 INT: mux IMUX_G1_DATA[1] bit 2 INT: mux DBL_E0[4] bit 2 INT: mux DBL_W0[4] bit 3 INT: mux DBL_E0[4] bit 5 INT: mux DBL_E0[4] bit 7 INT: mux HEX_E0[4] bit 1 INT: mux HEX_E0[4] bit 3 INT: mux HEX_E0[4] bit 5 INT: mux LH[18] bit 2
B38 - - - - INT: invert IMUX_TS_OPTINV[0] ← IMUX_TS[0] INT: mux IMUX_TS[0] bit 5 INT: mux OMUX[7] bit 9 INT: mux OMUX[7] bit 7 INT: mux IMUX_G1_DATA[1] bit 9 INT: mux IMUX_G1_DATA[1] bit 11 INT: mux IMUX_G1_DATA[0] bit 7 INT: mux IMUX_G1_DATA[0] bit 5 INT: mux IMUX_G1_DATA[0] bit 1 INT: mux IMUX_G1_DATA[0] bit 2 INT: mux DBL_E0[4] bit 0 INT: mux DBL_W0[4] bit 0 INT: mux DBL_W0[4] bit 7 INT: mux DBL_W0[4] bit 5 INT: mux HEX_W0[4] bit 1 INT: mux HEX_W0[4] bit 3 INT: mux HEX_W0[4] bit 5 INT: mux HEX_E0[4] bit 4
B37 - - - - INT: mux IMUX_TS[0] bit 8 INT: mux IMUX_TS[0] bit 6 INT: mux OMUX[7] bit 0 INT: mux OMUX[7] bit 8 INT: mux IMUX_G1_DATA[1] bit 8 INT: mux IMUX_G1_DATA[1] bit 10 INT: mux IMUX_G1_DATA[1] bit 6 INT: mux IMUX_G1_DATA[1] bit 4 INT: mux IMUX_G1_DATA[1] bit 0 INT: mux IMUX_G1_DATA[1] bit 3 INT: mux DBL_W0[4] bit 2 INT: mux DBL_E0[4] bit 3 INT: mux DBL_W0[4] bit 6 INT: mux DBL_W0[4] bit 4 INT: mux HEX_E0[4] bit 2 INT: mux HEX_E0[4] bit 0 INT: mux HEX_W0[4] bit 4 INT: mux LH[18] bit 1
B36 - - - - INT: mux IMUX_TS[0] bit 0 - INT: mux OMUX[6] bit 1 INT: mux OMUX[7] bit 1 INT: mux IMUX_G1_DATA[0] bit 8 INT: mux IMUX_G1_DATA[0] bit 10 INT: mux IMUX_G1_DATA[0] bit 6 INT: mux IMUX_G1_DATA[0] bit 4 INT: mux IMUX_G1_DATA[0] bit 0 INT: mux IMUX_G1_DATA[0] bit 3 INT: mux DBL_W0[4] bit 1 INT: mux DBL_E0[4] bit 1 INT: mux DBL_E0[4] bit 4 INT: mux DBL_E0[4] bit 6 INT: mux HEX_W0[4] bit 2 INT: mux HEX_W0[4] bit 0 INT: mux HEX_W0[4] bit 6 INT: mux HEX_E0[4] bit 6
B35 - - - - INT: mux IMUX_TS[1] bit 0 INT: mux IMUX_TS[1] bit 1 INT: mux OMUX[7] bit 2 INT: mux OMUX[6] bit 2 INT: mux IMUX_G1_DATA[2] bit 8 INT: mux IMUX_G1_DATA[2] bit 10 INT: mux IMUX_G1_DATA[2] bit 6 INT: mux IMUX_G1_DATA[2] bit 4 INT: mux IMUX_G1_DATA[2] bit 0 INT: mux IMUX_G1_DATA[2] bit 3 INT: mux DBL_S0[4] bit 3 INT: mux DBL_N0[4] bit 1 INT: mux DBL_S0[4] bit 4 INT: mux DBL_S0[4] bit 7 INT: mux HEX_S0[4] bit 0 INT: mux HEX_S0[4] bit 3 INT: mux HEX_S0[4] bit 4 INT: mux LH[18] bit 0
B34 - - - - INT: mux IMUX_TS[0] bit 1 INT: mux IMUX_TS[0] bit 2 INT: mux OMUX[7] bit 3 INT: mux OMUX[6] bit 3 INT: mux IMUX_G1_DATA[3] bit 8 INT: mux IMUX_G1_DATA[3] bit 10 INT: mux IMUX_G1_DATA[3] bit 6 INT: mux IMUX_G1_DATA[3] bit 4 INT: mux IMUX_G1_DATA[3] bit 0 INT: mux IMUX_G1_DATA[3] bit 3 INT: mux DBL_S0[4] bit 0 INT: mux DBL_N0[4] bit 0 INT: mux DBL_N0[4] bit 7 INT: mux DBL_N0[4] bit 4 INT: mux HEX_N0[4] bit 0 INT: mux HEX_N0[4] bit 2 INT: mux HEX_N0[4] bit 4 INT: mux HEX_S0[4] bit 5
B33 - - - - INT: mux IMUX_TS[1] bit 3 INT: mux IMUX_TS[1] bit 2 INT: mux OMUX[6] bit 4 INT: mux OMUX[7] bit 4 INT: mux IMUX_G1_DATA[3] bit 9 INT: mux IMUX_G1_DATA[3] bit 11 INT: mux IMUX_G1_DATA[2] bit 7 INT: mux IMUX_G1_DATA[2] bit 5 INT: mux IMUX_G1_DATA[2] bit 1 INT: mux IMUX_G1_DATA[2] bit 2 INT: mux DBL_N0[4] bit 3 INT: mux DBL_S0[4] bit 1 INT: mux DBL_N0[4] bit 6 INT: mux DBL_N0[4] bit 5 INT: mux HEX_S0[4] bit 2 INT: mux HEX_S0[4] bit 1 INT: mux HEX_N0[4] bit 5 INT: mux LH[6] bit 1
B32 - - - - INT: mux IMUX_TS[0] bit 3 INT: mux IMUX_TS[1] bit 5 INT: mux OMUX[7] bit 5 INT: mux OMUX[6] bit 8 INT: mux IMUX_G1_DATA[2] bit 9 INT: mux IMUX_G1_DATA[2] bit 11 INT: mux IMUX_G1_DATA[3] bit 7 INT: mux IMUX_G1_DATA[3] bit 5 INT: mux IMUX_G1_DATA[3] bit 1 INT: mux IMUX_G1_DATA[3] bit 2 INT: mux DBL_N0[4] bit 2 INT: mux DBL_S0[4] bit 2 INT: mux DBL_S0[4] bit 5 INT: mux DBL_S0[4] bit 6 INT: mux HEX_N0[4] bit 3 INT: mux HEX_N0[4] bit 1 INT: mux HEX_N0[4] bit 6 INT: mux HEX_S0[4] bit 6
B31 - - - - INT: mux IMUX_TS[1] bit 8 INT: mux IMUX_TS[1] bit 6 INT: mux OMUX[6] bit 9 INT: mux OMUX[6] bit 7 INT: mux IMUX_G1_DATA[4] bit 9 INT: mux IMUX_G1_DATA[4] bit 11 INT: mux IMUX_G1_DATA[5] bit 7 INT: mux IMUX_G1_DATA[5] bit 5 INT: mux IMUX_G1_DATA[5] bit 1 INT: mux IMUX_G1_DATA[5] bit 2 INT: mux DBL_E0[3] bit 2 INT: mux DBL_W0[3] bit 3 INT: mux DBL_E0[3] bit 4 INT: mux DBL_E0[3] bit 7 INT: mux HEX_W0[3] bit 1 INT: mux HEX_W0[3] bit 3 INT: mux HEX_W0[3] bit 5 INT: mux LH[6] bit 2
B30 - - - - INT: invert IMUX_TS_OPTINV[1] ← IMUX_TS[1] INT: mux IMUX_TS[0] bit 4 INT: mux OMUX[6] bit 5 INT: mux OMUX[6] bit 6 INT: mux IMUX_G1_DATA[5] bit 9 INT: mux IMUX_G1_DATA[5] bit 11 INT: mux IMUX_G1_DATA[4] bit 7 INT: mux IMUX_G1_DATA[4] bit 5 INT: mux IMUX_G1_DATA[4] bit 1 INT: mux IMUX_G1_DATA[4] bit 2 INT: mux DBL_E0[3] bit 0 INT: mux DBL_W0[3] bit 0 INT: mux DBL_W0[3] bit 7 INT: mux DBL_W0[3] bit 5 INT: mux HEX_E0[3] bit 0 INT: mux HEX_E0[3] bit 3 INT: mux HEX_E0[3] bit 4 INT: mux HEX_W0[3] bit 4
B29 - - - - INT: mux IMUX_TS[1] bit 4 INT: mux IMUX_TS[1] bit 7 INT: mux OMUX[4] bit 0 INT: mux OMUX[5] bit 6 INT: mux IMUX_G1_DATA[5] bit 8 INT: mux IMUX_G1_DATA[5] bit 10 INT: mux IMUX_G1_DATA[5] bit 6 INT: mux IMUX_G1_DATA[5] bit 4 INT: mux IMUX_G1_DATA[5] bit 0 INT: mux IMUX_G1_DATA[5] bit 3 INT: mux DBL_W0[3] bit 2 INT: mux DBL_E0[3] bit 3 INT: mux DBL_W0[3] bit 6 INT: mux DBL_W0[3] bit 4 INT: mux HEX_W0[3] bit 2 INT: mux HEX_W0[3] bit 0 INT: mux HEX_E0[3] bit 5 INT: mux LH[6] bit 0
B28 - - - - INT: mux IMUX_TI[1] bit 5 INT: mux IMUX_TI[1] bit 9 INT: mux OMUX[5] bit 9 INT: mux OMUX[5] bit 7 INT: mux IMUX_G1_DATA[4] bit 8 INT: mux IMUX_G1_DATA[4] bit 10 INT: mux IMUX_G1_DATA[4] bit 6 INT: mux IMUX_G1_DATA[4] bit 4 INT: mux IMUX_G1_DATA[4] bit 0 INT: mux IMUX_G1_DATA[4] bit 3 INT: mux DBL_W0[3] bit 1 INT: mux DBL_E0[3] bit 1 INT: mux DBL_E0[3] bit 5 INT: mux DBL_E0[3] bit 6 INT: mux HEX_E0[3] bit 2 INT: mux HEX_E0[3] bit 1 INT: mux HEX_E0[3] bit 6 INT: mux HEX_W0[3] bit 6
B27 - - - - INT: !invert IMUX_TI_OPTINV[1] ← IMUX_TI[1] INT: mux IMUX_TI[0] bit 5 INT: mux OMUX[5] bit 0 INT: mux OMUX[5] bit 8 INT: mux IMUX_G1_DATA[6] bit 8 INT: mux IMUX_G1_DATA[6] bit 10 INT: mux IMUX_G1_DATA[6] bit 6 INT: mux IMUX_G1_DATA[6] bit 4 INT: mux IMUX_G1_DATA[6] bit 0 INT: mux IMUX_G1_DATA[6] bit 3 INT: mux DBL_S0[3] bit 3 INT: mux DBL_N0[3] bit 1 INT: mux DBL_S0[3] bit 5 INT: mux DBL_S0[3] bit 7 INT: mux HEX_N0[3] bit 0 INT: mux HEX_N0[3] bit 3 INT: mux HEX_N0[3] bit 4 INT: mux LV[12] bit 4
B26 - - - - INT: mux IMUX_TI[1] bit 7 INT: mux IMUX_TI[1] bit 6 INT: mux OMUX[4] bit 1 INT: mux OMUX[5] bit 1 INT: mux IMUX_G1_DATA[7] bit 8 INT: mux IMUX_G1_DATA[7] bit 10 INT: mux IMUX_G1_DATA[7] bit 6 INT: mux IMUX_G1_DATA[7] bit 4 INT: mux IMUX_G1_DATA[7] bit 0 INT: mux IMUX_G1_DATA[7] bit 3 INT: mux DBL_S0[3] bit 0 INT: mux DBL_N0[3] bit 0 INT: mux DBL_N0[3] bit 7 INT: mux DBL_N0[3] bit 4 INT: mux HEX_S0[3] bit 1 INT: mux HEX_S0[3] bit 2 INT: mux HEX_S0[3] bit 5 INT: mux HEX_N0[3] bit 5
B25 - - - - INT: mux IMUX_TI[0] bit 4 INT: mux IMUX_TI[1] bit 8 INT: mux OMUX[5] bit 2 INT: mux OMUX[4] bit 2 INT: mux IMUX_G1_DATA[7] bit 9 INT: mux IMUX_G1_DATA[7] bit 11 INT: mux IMUX_G1_DATA[6] bit 7 INT: mux IMUX_G1_DATA[6] bit 5 INT: mux IMUX_G1_DATA[6] bit 1 INT: mux IMUX_G1_DATA[6] bit 2 INT: mux DBL_N0[3] bit 3 INT: mux DBL_S0[3] bit 1 INT: mux DBL_N0[3] bit 6 INT: mux DBL_N0[3] bit 5 INT: mux HEX_N0[3] bit 2 INT: mux HEX_N0[3] bit 1 INT: mux HEX_S0[3] bit 4 INT: mux LV[0] bit 3
B24 - - - - INT: mux IMUX_TI[1] bit 4 INT: mux IMUX_TI[1] bit 2 INT: mux OMUX[5] bit 3 INT: mux OMUX[4] bit 3 INT: mux IMUX_G1_DATA[6] bit 9 INT: mux IMUX_G1_DATA[6] bit 11 INT: mux IMUX_G1_DATA[7] bit 7 INT: mux IMUX_G1_DATA[7] bit 5 INT: mux IMUX_G1_DATA[7] bit 1 INT: mux IMUX_G1_DATA[7] bit 2 INT: mux DBL_N0[3] bit 2 INT: mux DBL_S0[3] bit 2 INT: mux DBL_S0[3] bit 4 INT: mux DBL_S0[3] bit 6 INT: mux HEX_S0[3] bit 3 INT: mux HEX_S0[3] bit 0 INT: mux HEX_S0[3] bit 6 INT: mux HEX_N0[3] bit 6
B23 - - - - INT: mux IMUX_TI[0] bit 3 INT: mux IMUX_TI[0] bit 2 INT: mux OMUX[4] bit 4 INT: mux OMUX[5] bit 4 INT: mux IMUX_G1_FAN[0] bit 9 INT: mux IMUX_G1_FAN[0] bit 11 INT: mux IMUX_G1_FAN[1] bit 7 INT: mux IMUX_G1_FAN[1] bit 5 INT: mux IMUX_G1_FAN[1] bit 1 INT: mux IMUX_G1_FAN[1] bit 2 INT: mux DBL_E0[2] bit 4 INT: mux DBL_W0[2] bit 7 INT: mux DBL_E0[2] bit 1 INT: mux DBL_E0[2] bit 3 INT: mux HEX_E0[2] bit 1 INT: mux HEX_E0[2] bit 3 INT: mux HEX_E0[2] bit 5 INT: mux LV[12] bit 3
B22 - - - - INT: mux IMUX_TI[1] bit 1 INT: mux IMUX_TI[1] bit 3 INT: mux OMUX[5] bit 5 INT: mux OMUX[4] bit 8 INT: mux IMUX_G1_FAN[1] bit 9 INT: mux IMUX_G1_FAN[1] bit 11 INT: mux IMUX_G1_FAN[0] bit 7 INT: mux IMUX_G1_FAN[0] bit 5 INT: mux IMUX_G1_FAN[0] bit 1 INT: mux IMUX_G1_FAN[0] bit 2 INT: mux DBL_E0[2] bit 5 INT: mux DBL_W0[2] bit 5 INT: mux DBL_W0[2] bit 3 INT: mux DBL_W0[2] bit 1 INT: mux HEX_W0[2] bit 1 INT: mux HEX_W0[2] bit 3 INT: mux HEX_W0[2] bit 6 INT: mux HEX_E0[2] bit 6
B21 - - - - INT: mux IMUX_TI[0] bit 1 INT: mux IMUX_TI[0] bit 0 INT: mux OMUX[4] bit 9 INT: mux OMUX[4] bit 7 INT: mux IMUX_G1_FAN[1] bit 8 INT: mux IMUX_G1_FAN[1] bit 10 INT: mux IMUX_G1_FAN[1] bit 6 INT: mux IMUX_G1_FAN[1] bit 4 INT: mux IMUX_G1_FAN[1] bit 0 INT: mux IMUX_G1_FAN[1] bit 3 INT: mux DBL_W0[2] bit 4 INT: mux DBL_E0[2] bit 7 INT: mux DBL_W0[2] bit 2 INT: mux DBL_W0[2] bit 0 INT: mux HEX_E0[2] bit 2 INT: mux HEX_E0[2] bit 0 INT: mux HEX_W0[2] bit 5 INT: mux LV[0] bit 2
B20 - - - - INT: mux IMUX_TI[0] bit 7 INT: mux IMUX_TI[0] bit 6 INT: mux OMUX[4] bit 5 INT: mux OMUX[4] bit 6 INT: mux IMUX_G1_FAN[0] bit 8 INT: mux IMUX_G1_FAN[0] bit 10 INT: mux IMUX_G1_FAN[0] bit 6 INT: mux IMUX_G1_FAN[0] bit 4 INT: mux IMUX_G1_FAN[0] bit 0 INT: mux IMUX_G1_FAN[0] bit 3 INT: mux DBL_W0[2] bit 6 INT: mux DBL_E0[2] bit 6 INT: mux DBL_E0[2] bit 0 INT: mux DBL_E0[2] bit 2 INT: mux HEX_W0[2] bit 2 INT: mux HEX_W0[2] bit 0 INT: mux HEX_W0[2] bit 4 INT: mux HEX_E0[2] bit 4
B19 - - - - INT: !invert IMUX_TI_OPTINV[0] ← IMUX_TI[0] INT: mux IMUX_TI[0] bit 8 INT: mux OMUX[2] bit 0 INT: mux OMUX[3] bit 6 INT: mux IMUX_G0_FAN[0] bit 9 INT: mux IMUX_G0_FAN[0] bit 10 INT: mux IMUX_G0_FAN[0] bit 6 INT: mux IMUX_G0_FAN[0] bit 5 INT: mux IMUX_G0_FAN[0] bit 2 INT: mux IMUX_G0_FAN[0] bit 1 INT: mux DBL_S0[2] bit 4 INT: mux DBL_N0[2] bit 6 INT: mux DBL_S0[2] bit 0 INT: mux DBL_S0[2] bit 3 INT: mux HEX_S0[2] bit 0 INT: mux HEX_S0[2] bit 3 INT: mux HEX_S0[2] bit 5 INT: mux LV[0] bit 4
B18 - - - - INT: mux IMUX_TI[1] bit 0 INT: mux IMUX_TI[0] bit 9 INT: mux OMUX[3] bit 9 INT: mux OMUX[3] bit 7 INT: mux IMUX_G0_FAN[1] bit 9 INT: mux IMUX_G0_FAN[1] bit 10 INT: mux IMUX_G0_FAN[1] bit 6 INT: mux IMUX_G0_FAN[1] bit 5 INT: mux IMUX_G0_FAN[1] bit 2 INT: mux IMUX_G0_FAN[1] bit 1 INT: mux DBL_S0[2] bit 5 INT: mux DBL_N0[2] bit 5 INT: mux DBL_N0[2] bit 3 INT: mux DBL_N0[2] bit 0 INT: mux HEX_N0[2] bit 1 INT: mux HEX_N0[2] bit 2 INT: mux HEX_N0[2] bit 4 INT: mux HEX_S0[2] bit 4
B17 - - - - INT: mux IMUX_SR[3] bit 5 INT: mux IMUX_SR[1] bit 1 INT: mux OMUX[3] bit 0 INT: mux OMUX[3] bit 8 INT: mux IMUX_G0_FAN[1] bit 8 INT: mux IMUX_G0_FAN[1] bit 11 INT: mux IMUX_G0_FAN[0] bit 7 INT: mux IMUX_G0_FAN[0] bit 4 INT: mux IMUX_G0_FAN[0] bit 0 INT: mux IMUX_G0_FAN[0] bit 3 INT: mux DBL_N0[2] bit 4 INT: mux DBL_S0[2] bit 6 INT: mux DBL_N0[2] bit 2 INT: mux DBL_N0[2] bit 1 INT: mux HEX_S0[2] bit 2 INT: mux HEX_S0[2] bit 1 INT: mux HEX_N0[2] bit 5 INT: mux LV[12] bit 2
B16 - - - - INT: !invert IMUX_SR_OPTINV[1] ← IMUX_SR[1] INT: mux IMUX_SR[1] bit 3 INT: mux OMUX[2] bit 1 INT: mux OMUX[3] bit 1 INT: mux IMUX_G0_FAN[0] bit 8 INT: mux IMUX_G0_FAN[0] bit 11 INT: mux IMUX_G0_FAN[1] bit 7 INT: mux IMUX_G0_FAN[1] bit 4 INT: mux IMUX_G0_FAN[1] bit 0 INT: mux IMUX_G0_FAN[1] bit 3 INT: mux DBL_N0[2] bit 7 INT: mux DBL_S0[2] bit 7 INT: mux DBL_S0[2] bit 1 INT: mux DBL_S0[2] bit 2 INT: mux HEX_N0[2] bit 3 INT: mux HEX_N0[2] bit 0 INT: mux HEX_N0[2] bit 6 INT: mux HEX_S0[2] bit 6
B15 - - - - INT: mux IMUX_SR[1] bit 0 INT: mux IMUX_SR[1] bit 2 INT: mux OMUX[3] bit 2 INT: mux OMUX[2] bit 2 INT: mux IMUX_G0_DATA[6] bit 8 INT: mux IMUX_G0_DATA[6] bit 11 INT: mux IMUX_G0_DATA[7] bit 7 INT: mux IMUX_G0_DATA[7] bit 4 INT: mux IMUX_G0_DATA[7] bit 0 INT: mux IMUX_G0_DATA[7] bit 3 INT: mux DBL_E0[1] bit 2 INT: mux DBL_W0[1] bit 3 INT: mux DBL_E0[1] bit 4 INT: mux DBL_E0[1] bit 7 INT: mux HEX_W0[1] bit 1 INT: mux HEX_W0[1] bit 2 INT: mux HEX_W0[1] bit 5 INT: mux LV[12] bit 0
B14 - - - - INT: mux IMUX_SR[1] bit 4 INT: mux IMUX_SR[1] bit 5 INT: mux OMUX[3] bit 3 INT: mux OMUX[2] bit 3 INT: mux IMUX_G0_DATA[7] bit 8 INT: mux IMUX_G0_DATA[7] bit 11 INT: mux IMUX_G0_DATA[6] bit 7 INT: mux IMUX_G0_DATA[6] bit 4 INT: mux IMUX_G0_DATA[6] bit 0 INT: mux IMUX_G0_DATA[6] bit 3 INT: mux DBL_E0[1] bit 0 INT: mux DBL_W0[1] bit 0 INT: mux DBL_W0[1] bit 6 INT: mux DBL_W0[1] bit 5 INT: mux HEX_E0[1] bit 0 INT: mux HEX_E0[1] bit 3 INT: mux HEX_E0[1] bit 4 INT: mux HEX_W0[1] bit 4
B13 - - - - INT: mux IMUX_SR[3] bit 4 INT: mux IMUX_SR[3] bit 7 INT: mux OMUX[2] bit 4 INT: mux OMUX[3] bit 4 INT: mux IMUX_G0_DATA[7] bit 9 INT: mux IMUX_G0_DATA[7] bit 10 INT: mux IMUX_G0_DATA[7] bit 6 INT: mux IMUX_G0_DATA[7] bit 5 INT: mux IMUX_G0_DATA[7] bit 2 INT: mux IMUX_G0_DATA[7] bit 1 INT: mux DBL_W0[1] bit 2 INT: mux DBL_E0[1] bit 3 INT: mux DBL_W0[1] bit 7 INT: mux DBL_W0[1] bit 4 INT: mux HEX_W0[1] bit 3 INT: mux HEX_W0[1] bit 0 INT: mux HEX_E0[1] bit 5 INT: mux LV[12] bit 6
B12 - - - - INT: mux IMUX_SR[1] bit 7 INT: mux IMUX_SR[1] bit 6 INT: mux OMUX[3] bit 5 INT: mux OMUX[2] bit 8 INT: mux IMUX_G0_DATA[6] bit 9 INT: mux IMUX_G0_DATA[6] bit 10 INT: mux IMUX_G0_DATA[6] bit 6 INT: mux IMUX_G0_DATA[6] bit 5 INT: mux IMUX_G0_DATA[6] bit 2 INT: mux IMUX_G0_DATA[6] bit 1 INT: mux DBL_W0[1] bit 1 INT: mux DBL_E0[1] bit 1 INT: mux DBL_E0[1] bit 5 INT: mux DBL_E0[1] bit 6 INT: mux HEX_E0[1] bit 2 INT: mux HEX_E0[1] bit 1 INT: mux HEX_E0[1] bit 6 INT: mux HEX_W0[1] bit 6
B11 - - - - INT: mux IMUX_SR[3] bit 0 INT: mux IMUX_SR[3] bit 1 INT: mux OMUX[2] bit 9 INT: mux OMUX[2] bit 7 INT: mux IMUX_G0_DATA[4] bit 9 INT: mux IMUX_G0_DATA[4] bit 10 INT: mux IMUX_G0_DATA[4] bit 6 INT: mux IMUX_G0_DATA[4] bit 5 INT: mux IMUX_G0_DATA[4] bit 2 INT: mux IMUX_G0_DATA[4] bit 1 INT: mux DBL_S0[1] bit 3 INT: mux DBL_N0[1] bit 1 INT: mux DBL_S0[1] bit 4 INT: mux DBL_S0[1] bit 7 INT: mux HEX_N0[1] bit 0 INT: mux HEX_N0[1] bit 3 INT: mux HEX_N0[1] bit 4 INT: mux LV[0] bit 1
B10 - - - - INT: !invert IMUX_SR_OPTINV[3] ← IMUX_SR[3] INT: mux IMUX_SR[3] bit 3 INT: mux OMUX[2] bit 5 INT: mux OMUX[2] bit 6 INT: mux IMUX_G0_DATA[5] bit 9 INT: mux IMUX_G0_DATA[5] bit 10 INT: mux IMUX_G0_DATA[5] bit 6 INT: mux IMUX_G0_DATA[5] bit 5 INT: mux IMUX_G0_DATA[5] bit 2 INT: mux IMUX_G0_DATA[5] bit 1 INT: mux DBL_S0[1] bit 0 INT: mux DBL_N0[1] bit 0 INT: mux DBL_N0[1] bit 7 INT: mux DBL_N0[1] bit 4 INT: mux HEX_S0[1] bit 0 INT: mux HEX_S0[1] bit 2 INT: mux HEX_S0[1] bit 4 INT: mux HEX_N0[1] bit 5
B9 - - - - INT: mux IMUX_SR[3] bit 6 INT: mux IMUX_SR[3] bit 2 INT: mux OMUX[0] bit 0 INT: mux OMUX[1] bit 6 INT: mux IMUX_G0_DATA[5] bit 8 INT: mux IMUX_G0_DATA[5] bit 11 INT: mux IMUX_G0_DATA[4] bit 7 INT: mux IMUX_G0_DATA[4] bit 4 INT: mux IMUX_G0_DATA[4] bit 0 INT: mux IMUX_G0_DATA[4] bit 3 INT: mux DBL_N0[1] bit 3 INT: mux DBL_S0[1] bit 1 INT: mux DBL_N0[1] bit 6 INT: mux DBL_N0[1] bit 5 INT: mux HEX_N0[1] bit 2 INT: mux HEX_N0[1] bit 1 INT: mux HEX_S0[1] bit 5 INT: mux LV[0] bit 5
B8 - - - - INT: mux IMUX_SR[2] bit 5 INT: mux IMUX_SR[2] bit 2 INT: mux OMUX[1] bit 9 INT: mux OMUX[1] bit 7 INT: mux IMUX_G0_DATA[4] bit 8 INT: mux IMUX_G0_DATA[4] bit 11 INT: mux IMUX_G0_DATA[5] bit 7 INT: mux IMUX_G0_DATA[5] bit 4 INT: mux IMUX_G0_DATA[5] bit 0 INT: mux IMUX_G0_DATA[5] bit 3 INT: mux DBL_N0[1] bit 2 INT: mux DBL_S0[1] bit 2 INT: mux DBL_S0[1] bit 5 INT: mux DBL_S0[1] bit 6 INT: mux HEX_S0[1] bit 3 INT: mux HEX_S0[1] bit 1 INT: mux HEX_S0[1] bit 6 INT: mux HEX_N0[1] bit 6
B7 - - - - INT: !invert IMUX_SR_OPTINV[2] ← IMUX_SR[2] INT: mux IMUX_SR[2] bit 3 INT: mux OMUX[1] bit 0 INT: mux OMUX[1] bit 8 INT: mux IMUX_G0_DATA[2] bit 8 INT: mux IMUX_G0_DATA[2] bit 11 INT: mux IMUX_G0_DATA[3] bit 7 INT: mux IMUX_G0_DATA[3] bit 4 INT: mux IMUX_G0_DATA[3] bit 0 INT: mux IMUX_G0_DATA[3] bit 3 INT: mux DBL_E0[0] bit 2 INT: mux DBL_W0[0] bit 3 INT: mux DBL_E0[0] bit 4 INT: mux DBL_E0[0] bit 7 INT: mux HEX_E0[0] bit 0 INT: mux HEX_E0[0] bit 3 INT: mux HEX_E0[0] bit 4 INT: mux LV[0] bit 6
B6 - - - - INT: mux IMUX_SR[2] bit 1 INT: mux IMUX_SR[2] bit 0 INT: mux OMUX[0] bit 1 INT: mux OMUX[1] bit 1 INT: mux IMUX_G0_DATA[3] bit 8 INT: mux IMUX_G0_DATA[3] bit 11 INT: mux IMUX_G0_DATA[2] bit 7 INT: mux IMUX_G0_DATA[2] bit 4 INT: mux IMUX_G0_DATA[2] bit 0 INT: mux IMUX_G0_DATA[2] bit 3 INT: mux DBL_E0[0] bit 0 INT: mux DBL_W0[0] bit 0 INT: mux DBL_W0[0] bit 6 INT: mux DBL_W0[0] bit 5 INT: mux HEX_W0[0] bit 1 INT: mux HEX_W0[0] bit 2 INT: mux HEX_W0[0] bit 5 INT: mux HEX_E0[0] bit 5
B5 - - - - INT: mux IMUX_SR[0] bit 4 INT: mux IMUX_SR[0] bit 5 INT: mux OMUX[1] bit 2 INT: mux OMUX[0] bit 2 INT: mux IMUX_G0_DATA[3] bit 9 INT: mux IMUX_G0_DATA[3] bit 10 INT: mux IMUX_G0_DATA[3] bit 6 INT: mux IMUX_G0_DATA[3] bit 5 INT: mux IMUX_G0_DATA[3] bit 2 INT: mux IMUX_G0_DATA[3] bit 1 INT: mux DBL_W0[0] bit 2 INT: mux DBL_E0[0] bit 3 INT: mux DBL_W0[0] bit 7 INT: mux DBL_W0[0] bit 4 INT: mux HEX_E0[0] bit 2 INT: mux HEX_E0[0] bit 1 INT: mux HEX_W0[0] bit 4 INT: mux LV[0] bit 0
B4 - - - - INT: mux IMUX_SR[2] bit 6 INT: mux IMUX_SR[2] bit 4 INT: mux OMUX[1] bit 3 INT: mux OMUX[0] bit 3 INT: mux IMUX_G0_DATA[2] bit 9 INT: mux IMUX_G0_DATA[2] bit 10 INT: mux IMUX_G0_DATA[2] bit 6 INT: mux IMUX_G0_DATA[2] bit 5 INT: mux IMUX_G0_DATA[2] bit 2 INT: mux IMUX_G0_DATA[2] bit 1 INT: mux DBL_W0[0] bit 1 INT: mux DBL_E0[0] bit 1 INT: mux DBL_E0[0] bit 5 INT: mux DBL_E0[0] bit 6 INT: mux HEX_W0[0] bit 3 INT: mux HEX_W0[0] bit 0 INT: mux HEX_W0[0] bit 6 INT: mux HEX_E0[0] bit 6
B3 - - - - INT: mux IMUX_SR[0] bit 6 INT: mux IMUX_SR[0] bit 7 INT: mux OMUX[0] bit 4 INT: mux OMUX[1] bit 4 INT: mux IMUX_G0_DATA[0] bit 9 INT: mux IMUX_G0_DATA[0] bit 10 INT: mux IMUX_G0_DATA[0] bit 6 INT: mux IMUX_G0_DATA[0] bit 5 INT: mux IMUX_G0_DATA[0] bit 2 INT: mux IMUX_G0_DATA[0] bit 1 INT: mux DBL_S0[0] bit 4 INT: mux DBL_N0[0] bit 6 INT: mux DBL_S0[0] bit 1 INT: mux DBL_S0[0] bit 3 INT: mux HEX_S0[0] bit 1 INT: mux HEX_S0[0] bit 3 INT: mux HEX_S0[0] bit 6 INT: mux LV[12] bit 1
B2 - - - - INT: mux IMUX_SR[0] bit 1 INT: mux IMUX_SR[0] bit 2 INT: mux OMUX[1] bit 5 INT: mux OMUX[0] bit 8 INT: mux IMUX_G0_DATA[1] bit 9 INT: mux IMUX_G0_DATA[1] bit 10 INT: mux IMUX_G0_DATA[1] bit 6 INT: mux IMUX_G0_DATA[1] bit 5 INT: mux IMUX_G0_DATA[1] bit 2 INT: mux IMUX_G0_DATA[1] bit 1 INT: mux DBL_S0[0] bit 5 INT: mux DBL_N0[0] bit 5 INT: mux DBL_N0[0] bit 3 INT: mux DBL_N0[0] bit 1 INT: mux HEX_N0[0] bit 1 INT: mux HEX_N0[0] bit 2 INT: mux HEX_N0[0] bit 5 INT: mux HEX_S0[0] bit 5
B1 - - - - INT: !invert IMUX_SR_OPTINV[0] ← IMUX_SR[0] INT: mux IMUX_SR[0] bit 3 INT: mux OMUX[0] bit 9 INT: mux OMUX[0] bit 7 INT: mux IMUX_G0_DATA[1] bit 8 INT: mux IMUX_G0_DATA[1] bit 11 INT: mux IMUX_G0_DATA[0] bit 7 INT: mux IMUX_G0_DATA[0] bit 4 INT: mux IMUX_G0_DATA[0] bit 0 INT: mux IMUX_G0_DATA[0] bit 3 INT: mux DBL_N0[0] bit 4 INT: mux DBL_S0[0] bit 6 INT: mux DBL_N0[0] bit 2 INT: mux DBL_N0[0] bit 0 INT: mux HEX_S0[0] bit 2 INT: mux HEX_S0[0] bit 0 INT: mux HEX_N0[0] bit 6 INT: mux LV[12] bit 5
B0 - - - - INT: mux IMUX_SR[2] bit 7 INT: mux IMUX_SR[0] bit 0 INT: mux OMUX[0] bit 5 INT: mux OMUX[0] bit 6 INT: mux IMUX_G0_DATA[0] bit 8 INT: mux IMUX_G0_DATA[0] bit 11 INT: mux IMUX_G0_DATA[1] bit 7 INT: mux IMUX_G0_DATA[1] bit 4 INT: mux IMUX_G0_DATA[1] bit 0 INT: mux IMUX_G0_DATA[1] bit 3 INT: mux DBL_N0[0] bit 7 INT: mux DBL_S0[0] bit 7 INT: mux DBL_S0[0] bit 0 INT: mux DBL_S0[0] bit 2 INT: mux HEX_N0[0] bit 3 INT: mux HEX_N0[0] bit 0 INT: mux HEX_N0[0] bit 4 INT: mux HEX_S0[0] bit 4

INT_GT_CLKPAD

Used for the IO row of multi-gigabit transceiver tiles.

Tile INT_GT_CLKPAD

Cells: 1

Switchbox INT

virtex2 INT_GT_CLKPAD switchbox INT programmable inverters
DestinationSourceBit
IMUX_DCM_CLK_OPTINV[0]IMUX_DCM_CLK[0]MAIN[4][38]
IMUX_DCM_CLK_OPTINV[1]IMUX_DCM_CLK[1]MAIN[4][48]
IMUX_DCM_CLK_OPTINV[2]IMUX_DCM_CLK[2]MAIN[4][51]
IMUX_DCM_CLK_OPTINV[3]IMUX_DCM_CLK[3]MAIN[4][61]
IMUX_SR_OPTINV[0]IMUX_SR[0]!MAIN[4][1]
IMUX_SR_OPTINV[1]IMUX_SR[1]!MAIN[4][16]
IMUX_SR_OPTINV[2]IMUX_SR[2]!MAIN[4][7]
IMUX_SR_OPTINV[3]IMUX_SR[3]!MAIN[4][10]
IMUX_CE_OPTINV[2]IMUX_CE[2]!MAIN[4][72]
IMUX_CE_OPTINV[3]IMUX_CE[3]!MAIN[4][78]
IMUX_TI_OPTINV[0]IMUX_TI[0]!MAIN[4][19]
IMUX_TI_OPTINV[1]IMUX_TI[1]!MAIN[4][27]
virtex2 INT_GT_CLKPAD switchbox INT muxes OMUX[0]
BitsDestination
MAIN[6][1]MAIN[7][2]MAIN[7][1]MAIN[7][0]MAIN[6][0]MAIN[6][3]MAIN[7][4]MAIN[7][5]MAIN[6][6]MAIN[6][9]OMUX[0]
Source
0000000000off
0001000001IMUX_SR[0]
0001000010IMUX_SR[2]
0001000100IMUX_G0_DATA[0]
0001001000IMUX_G0_DATA[1]
0001010000IMUX_G0_DATA[2]
0001100000IMUX_G0_DATA[3]
0010000001OUT_FAN[0]
0010000010OUT_FAN[1]
0010000100OUT_FAN[2]
0010001000OUT_FAN[3]
0010010000OUT_FAN[4]
0010100000OUT_FAN[5]
0100000001OUT_FAN[6]
0100000010OUT_FAN[7]
0100000100OUT_SEC[8]
0100001000OUT_SEC[9]
0100010000OUT_SEC[10]
0100100000OUT_SEC[11]
1000000001OUT_SEC[12]
1000000010OUT_SEC[13]
1000000100OUT_SEC[14]
1000001000OUT_SEC[15]
1000010000OUT_TEST[1]
1000100000OUT_TEST[0]
virtex2 INT_GT_CLKPAD switchbox INT muxes OMUX[1]
BitsDestination
MAIN[6][8]MAIN[7][7]MAIN[7][8]MAIN[7][9]MAIN[6][2]MAIN[7][3]MAIN[6][4]MAIN[6][5]MAIN[7][6]MAIN[6][7]OMUX[1]
Source
0000000000off
0001000001IMUX_SR[0]
0001000010IMUX_SR[2]
0001000100IMUX_G0_DATA[0]
0001001000IMUX_G0_DATA[1]
0001010000IMUX_G0_DATA[2]
0001100000IMUX_G0_DATA[3]
0010000001OUT_FAN[0]
0010000010OUT_FAN[1]
0010000100OUT_FAN[2]
0010001000OUT_FAN[3]
0010010000OUT_FAN[4]
0010100000OUT_FAN[5]
0100000001OUT_FAN[6]
0100000010OUT_FAN[7]
0100000100OUT_SEC[8]
0100001000OUT_SEC[9]
0100010000OUT_SEC[10]
0100100000OUT_SEC[11]
1000000001OUT_SEC[12]
1000000010OUT_SEC[13]
1000000100OUT_SEC[14]
1000001000OUT_SEC[15]
1000010000OUT_TEST[1]
1000100000OUT_TEST[0]
virtex2 INT_GT_CLKPAD switchbox INT muxes OMUX[2]
BitsDestination
MAIN[6][11]MAIN[7][12]MAIN[7][11]MAIN[7][10]MAIN[6][10]MAIN[6][13]MAIN[7][14]MAIN[7][15]MAIN[6][16]MAIN[6][19]OMUX[2]
Source
0000000000off
0001000001IMUX_SR[1]
0001000010IMUX_SR[3]
0001000100IMUX_G0_DATA[4]
0001001000IMUX_G0_DATA[5]
0001010000IMUX_G0_DATA[6]
0001100000IMUX_G0_DATA[7]
0010000001OUT_FAN[0]
0010000010OUT_FAN[1]
0010000100OUT_FAN[2]
0010001000OUT_FAN[3]
0010010000OUT_FAN[4]
0010100000OUT_FAN[5]
0100000001OUT_FAN[6]
0100000010OUT_FAN[7]
0100000100OUT_SEC[8]
0100001000OUT_SEC[9]
0100010000OUT_SEC[10]
0100100000OUT_SEC[11]
1000000001OUT_SEC[12]
1000000010OUT_SEC[13]
1000000100OUT_SEC[14]
1000001000OUT_SEC[15]
1000010000OUT_TEST[3]
1000100000OUT_TEST[2]
virtex2 INT_GT_CLKPAD switchbox INT muxes OMUX[3]
BitsDestination
MAIN[6][18]MAIN[7][17]MAIN[7][18]MAIN[7][19]MAIN[6][12]MAIN[7][13]MAIN[6][14]MAIN[6][15]MAIN[7][16]MAIN[6][17]OMUX[3]
Source
0000000000off
0001000001IMUX_SR[1]
0001000010IMUX_SR[3]
0001000100IMUX_G0_DATA[4]
0001001000IMUX_G0_DATA[5]
0001010000IMUX_G0_DATA[6]
0001100000IMUX_G0_DATA[7]
0010000001OUT_FAN[0]
0010000010OUT_FAN[1]
0010000100OUT_FAN[2]
0010001000OUT_FAN[3]
0010010000OUT_FAN[4]
0010100000OUT_FAN[5]
0100000001OUT_FAN[6]
0100000010OUT_FAN[7]
0100000100OUT_SEC[8]
0100001000OUT_SEC[9]
0100010000OUT_SEC[10]
0100100000OUT_SEC[11]
1000000001OUT_SEC[12]
1000000010OUT_SEC[13]
1000000100OUT_SEC[14]
1000001000OUT_SEC[15]
1000010000OUT_TEST[3]
1000100000OUT_TEST[2]
virtex2 INT_GT_CLKPAD switchbox INT muxes OMUX[4]
BitsDestination
MAIN[6][21]MAIN[7][22]MAIN[7][21]MAIN[7][20]MAIN[6][20]MAIN[6][23]MAIN[7][24]MAIN[7][25]MAIN[6][26]MAIN[6][29]OMUX[4]
Source
0000000000off
0001000001IMUX_TI[0]
0001000010IMUX_TI[1]
0001000100IMUX_G1_DATA[4]
0001001000IMUX_G1_DATA[5]
0001010000IMUX_G1_DATA[6]
0001100000IMUX_G1_DATA[7]
0010000001OUT_FAN[0]
0010000010OUT_FAN[1]
0010000100OUT_FAN[2]
0010001000OUT_FAN[3]
0010010000OUT_FAN[4]
0010100000OUT_FAN[5]
0100000001OUT_FAN[6]
0100000010OUT_FAN[7]
0100000100OUT_SEC[8]
0100001000OUT_SEC[9]
0100010000OUT_SEC[10]
0100100000OUT_SEC[11]
1000000001OUT_SEC[12]
1000000010OUT_SEC[13]
1000000100OUT_SEC[14]
1000001000OUT_SEC[15]
1000010000OUT_TEST[5]
1000100000OUT_TEST[4]
virtex2 INT_GT_CLKPAD switchbox INT muxes OMUX[5]
BitsDestination
MAIN[6][28]MAIN[7][27]MAIN[7][28]MAIN[7][29]MAIN[6][22]MAIN[7][23]MAIN[6][24]MAIN[6][25]MAIN[7][26]MAIN[6][27]OMUX[5]
Source
0000000000off
0001000001IMUX_TI[0]
0001000010IMUX_TI[1]
0001000100IMUX_G1_DATA[4]
0001001000IMUX_G1_DATA[5]
0001010000IMUX_G1_DATA[6]
0001100000IMUX_G1_DATA[7]
0010000001OUT_FAN[0]
0010000010OUT_FAN[1]
0010000100OUT_FAN[2]
0010001000OUT_FAN[3]
0010010000OUT_FAN[4]
0010100000OUT_FAN[5]
0100000001OUT_FAN[6]
0100000010OUT_FAN[7]
0100000100OUT_SEC[8]
0100001000OUT_SEC[9]
0100010000OUT_SEC[10]
0100100000OUT_SEC[11]
1000000001OUT_SEC[12]
1000000010OUT_SEC[13]
1000000100OUT_SEC[14]
1000001000OUT_SEC[15]
1000010000OUT_TEST[5]
1000100000OUT_TEST[4]
virtex2 INT_GT_CLKPAD switchbox INT muxes OMUX[6]
BitsDestination
MAIN[6][31]MAIN[7][32]MAIN[7][31]MAIN[7][30]MAIN[6][30]MAIN[6][33]MAIN[7][34]MAIN[7][35]MAIN[6][36]MAIN[6][39]OMUX[6]
Source
0000000000off
0001000001IMUX_TS[0]
0001000010IMUX_TS[1]
0001000100IMUX_G1_DATA[0]
0001001000IMUX_G1_DATA[1]
0001010000IMUX_G1_DATA[2]
0001100000IMUX_G1_DATA[3]
0010000001OUT_FAN[0]
0010000010OUT_FAN[1]
0010000100OUT_FAN[2]
0010001000OUT_FAN[3]
0010010000OUT_FAN[4]
0010100000OUT_FAN[5]
0100000001OUT_FAN[6]
0100000010OUT_FAN[7]
0100000100OUT_SEC[8]
0100001000OUT_SEC[9]
0100010000OUT_SEC[10]
0100100000OUT_SEC[11]
1000000001OUT_SEC[12]
1000000010OUT_SEC[13]
1000000100OUT_SEC[14]
1000001000OUT_SEC[15]
1000010000OUT_TEST[7]
1000100000OUT_TEST[6]
virtex2 INT_GT_CLKPAD switchbox INT muxes OMUX[7]
BitsDestination
MAIN[6][38]MAIN[7][37]MAIN[7][38]MAIN[7][39]MAIN[6][32]MAIN[7][33]MAIN[6][34]MAIN[6][35]MAIN[7][36]MAIN[6][37]OMUX[7]
Source
0000000000off
0001000001IMUX_TS[0]
0001000010IMUX_TS[1]
0001000100IMUX_G1_DATA[0]
0001001000IMUX_G1_DATA[1]
0001010000IMUX_G1_DATA[2]
0001100000IMUX_G1_DATA[3]
0010000001OUT_FAN[0]
0010000010OUT_FAN[1]
0010000100OUT_FAN[2]
0010001000OUT_FAN[3]
0010010000OUT_FAN[4]
0010100000OUT_FAN[5]
0100000001OUT_FAN[6]
0100000010OUT_FAN[7]
0100000100OUT_SEC[8]
0100001000OUT_SEC[9]
0100010000OUT_SEC[10]
0100100000OUT_SEC[11]
1000000001OUT_SEC[12]
1000000010OUT_SEC[13]
1000000100OUT_SEC[14]
1000001000OUT_SEC[15]
1000010000OUT_TEST[7]
1000100000OUT_TEST[6]
virtex2 INT_GT_CLKPAD switchbox INT muxes OMUX[8]
BitsDestination
MAIN[6][41]MAIN[7][42]MAIN[7][41]MAIN[7][40]MAIN[6][40]MAIN[6][43]MAIN[7][44]MAIN[7][45]MAIN[6][46]MAIN[6][49]OMUX[8]
Source
0000000000off
0001000001IMUX_DCM_CLK[0]
0001000010IMUX_DCM_CLK[1]
0001000100IMUX_G2_DATA[0]
0001001000IMUX_G2_DATA[1]
0001010000IMUX_G2_DATA[2]
0001100000IMUX_G2_DATA[3]
0010000001OUT_FAN[0]
0010000010OUT_FAN[1]
0010000100OUT_FAN[2]
0010001000OUT_FAN[3]
0010010000OUT_FAN[4]
0010100000OUT_FAN[5]
0100000001OUT_FAN[6]
0100000010OUT_FAN[7]
0100000100OUT_SEC[8]
0100001000OUT_SEC[9]
0100010000OUT_SEC[10]
0100100000OUT_SEC[11]
1000000001OUT_SEC[12]
1000000010OUT_SEC[13]
1000000100OUT_SEC[14]
1000001000OUT_SEC[15]
1000010000OUT_TEST[9]
1000100000OUT_TEST[8]
virtex2 INT_GT_CLKPAD switchbox INT muxes OMUX[9]
BitsDestination
MAIN[6][48]MAIN[7][47]MAIN[7][48]MAIN[7][49]MAIN[6][42]MAIN[7][43]MAIN[6][44]MAIN[6][45]MAIN[7][46]MAIN[6][47]OMUX[9]
Source
0000000000off
0001000001IMUX_DCM_CLK[0]
0001000010IMUX_DCM_CLK[1]
0001000100IMUX_G2_DATA[0]
0001001000IMUX_G2_DATA[1]
0001010000IMUX_G2_DATA[2]
0001100000IMUX_G2_DATA[3]
0010000001OUT_FAN[0]
0010000010OUT_FAN[1]
0010000100OUT_FAN[2]
0010001000OUT_FAN[3]
0010010000OUT_FAN[4]
0010100000OUT_FAN[5]
0100000001OUT_FAN[6]
0100000010OUT_FAN[7]
0100000100OUT_SEC[8]
0100001000OUT_SEC[9]
0100010000OUT_SEC[10]
0100100000OUT_SEC[11]
1000000001OUT_SEC[12]
1000000010OUT_SEC[13]
1000000100OUT_SEC[14]
1000001000OUT_SEC[15]
1000010000OUT_TEST[9]
1000100000OUT_TEST[8]
virtex2 INT_GT_CLKPAD switchbox INT muxes OMUX[10]
BitsDestination
MAIN[6][51]MAIN[7][52]MAIN[7][51]MAIN[7][50]MAIN[6][50]MAIN[6][53]MAIN[7][54]MAIN[7][55]MAIN[6][59]MAIN[6][56]OMUX[10]
Source
0000000000off
0001000001IMUX_DCM_CLK[2]
0001000010IMUX_DCM_CLK[3]
0001000100IMUX_G2_DATA[4]
0001001000IMUX_G2_DATA[5]
0001010000IMUX_G2_DATA[6]
0001100000IMUX_G2_DATA[7]
0010000001OUT_FAN[1]
0010000010OUT_FAN[0]
0010000100OUT_FAN[2]
0010001000OUT_FAN[3]
0010010000OUT_FAN[4]
0010100000OUT_FAN[5]
0100000001OUT_FAN[7]
0100000010OUT_FAN[6]
0100000100OUT_SEC[8]
0100001000OUT_SEC[9]
0100010000OUT_SEC[10]
0100100000OUT_SEC[11]
1000000001OUT_SEC[13]
1000000010OUT_SEC[12]
1000000100OUT_SEC[14]
1000001000OUT_SEC[15]
1000010000OUT_TEST[11]
1000100000OUT_TEST[10]
virtex2 INT_GT_CLKPAD switchbox INT muxes OMUX[11]
BitsDestination
MAIN[6][58]MAIN[7][57]MAIN[7][58]MAIN[7][59]MAIN[6][52]MAIN[7][53]MAIN[6][54]MAIN[6][55]MAIN[6][57]MAIN[7][56]OMUX[11]
Source
0000000000off
0001000001IMUX_DCM_CLK[2]
0001000010IMUX_DCM_CLK[3]
0001000100IMUX_G2_DATA[4]
0001001000IMUX_G2_DATA[5]
0001010000IMUX_G2_DATA[6]
0001100000IMUX_G2_DATA[7]
0010000001OUT_FAN[1]
0010000010OUT_FAN[0]
0010000100OUT_FAN[2]
0010001000OUT_FAN[3]
0010010000OUT_FAN[4]
0010100000OUT_FAN[5]
0100000001OUT_FAN[7]
0100000010OUT_FAN[6]
0100000100OUT_SEC[8]
0100001000OUT_SEC[9]
0100010000OUT_SEC[10]
0100100000OUT_SEC[11]
1000000001OUT_SEC[13]
1000000010OUT_SEC[12]
1000000100OUT_SEC[14]
1000001000OUT_SEC[15]
1000010000OUT_TEST[11]
1000100000OUT_TEST[10]
virtex2 INT_GT_CLKPAD switchbox INT muxes OMUX[12]
BitsDestination
MAIN[6][61]MAIN[7][62]MAIN[7][61]MAIN[7][60]MAIN[6][60]MAIN[6][63]MAIN[7][64]MAIN[7][65]MAIN[6][69]MAIN[6][66]OMUX[12]
Source
0000000000off
0001000001IMUX_CE[0]
0001000010IMUX_CE[1]
0001000100IMUX_G3_DATA[4]
0001001000IMUX_G3_DATA[5]
0001010000IMUX_G3_DATA[6]
0001100000IMUX_G3_DATA[7]
0010000001OUT_FAN[1]
0010000010OUT_FAN[0]
0010000100OUT_FAN[2]
0010001000OUT_FAN[3]
0010010000OUT_FAN[4]
0010100000OUT_FAN[5]
0100000001OUT_FAN[7]
0100000010OUT_FAN[6]
0100000100OUT_SEC[8]
0100001000OUT_SEC[9]
0100010000OUT_SEC[10]
0100100000OUT_SEC[11]
1000000001OUT_SEC[13]
1000000010OUT_SEC[12]
1000000100OUT_SEC[14]
1000001000OUT_SEC[15]
1000010000OUT_TEST[13]
1000100000OUT_TEST[12]
virtex2 INT_GT_CLKPAD switchbox INT muxes OMUX[13]
BitsDestination
MAIN[6][68]MAIN[7][67]MAIN[7][68]MAIN[7][69]MAIN[6][62]MAIN[7][63]MAIN[6][64]MAIN[6][65]MAIN[6][67]MAIN[7][66]OMUX[13]
Source
0000000000off
0001000001IMUX_CE[0]
0001000010IMUX_CE[1]
0001000100IMUX_G3_DATA[4]
0001001000IMUX_G3_DATA[5]
0001010000IMUX_G3_DATA[6]
0001100000IMUX_G3_DATA[7]
0010000001OUT_FAN[1]
0010000010OUT_FAN[0]
0010000100OUT_FAN[2]
0010001000OUT_FAN[3]
0010010000OUT_FAN[4]
0010100000OUT_FAN[5]
0100000001OUT_FAN[7]
0100000010OUT_FAN[6]
0100000100OUT_SEC[8]
0100001000OUT_SEC[9]
0100010000OUT_SEC[10]
0100100000OUT_SEC[11]
1000000001OUT_SEC[13]
1000000010OUT_SEC[12]
1000000100OUT_SEC[14]
1000001000OUT_SEC[15]
1000010000OUT_TEST[13]
1000100000OUT_TEST[12]
virtex2 INT_GT_CLKPAD switchbox INT muxes OMUX[14]
BitsDestination
MAIN[6][71]MAIN[7][72]MAIN[7][71]MAIN[7][70]MAIN[6][70]MAIN[6][73]MAIN[7][74]MAIN[7][75]MAIN[6][76]MAIN[6][79]OMUX[14]
Source
0000000000off
0001000001IMUX_CE[2]
0001000010IMUX_CE[3]
0001000100IMUX_G3_DATA[0]
0001001000IMUX_G3_DATA[1]
0001010000IMUX_G3_DATA[2]
0001100000IMUX_G3_DATA[3]
0010000001OUT_FAN[0]
0010000010OUT_FAN[1]
0010000100OUT_FAN[2]
0010001000OUT_FAN[3]
0010010000OUT_FAN[4]
0010100000OUT_FAN[5]
0100000001OUT_FAN[6]
0100000010OUT_FAN[7]
0100000100OUT_SEC[8]
0100001000OUT_SEC[9]
0100010000OUT_SEC[10]
0100100000OUT_SEC[11]
1000000001OUT_SEC[12]
1000000010OUT_SEC[13]
1000000100OUT_SEC[14]
1000001000OUT_SEC[15]
1000010000OUT_TEST[15]
1000100000OUT_TEST[14]
virtex2 INT_GT_CLKPAD switchbox INT muxes OMUX[15]
BitsDestination
MAIN[6][78]MAIN[7][77]MAIN[7][78]MAIN[7][79]MAIN[6][72]MAIN[7][73]MAIN[6][74]MAIN[6][75]MAIN[7][76]MAIN[6][77]OMUX[15]
Source
0000000000off
0001000001IMUX_CE[2]
0001000010IMUX_CE[3]
0001000100IMUX_G3_DATA[0]
0001001000IMUX_G3_DATA[1]
0001010000IMUX_G3_DATA[2]
0001100000IMUX_G3_DATA[3]
0010000001OUT_FAN[0]
0010000010OUT_FAN[1]
0010000100OUT_FAN[2]
0010001000OUT_FAN[3]
0010010000OUT_FAN[4]
0010100000OUT_FAN[5]
0100000001OUT_FAN[6]
0100000010OUT_FAN[7]
0100000100OUT_SEC[8]
0100001000OUT_SEC[9]
0100010000OUT_SEC[10]
0100100000OUT_SEC[11]
1000000001OUT_SEC[12]
1000000010OUT_SEC[13]
1000000100OUT_SEC[14]
1000001000OUT_SEC[15]
1000010000OUT_TEST[15]
1000100000OUT_TEST[14]
virtex2 INT_GT_CLKPAD switchbox INT muxes DBL_W0[0]
BitsDestination
MAIN[16][5]MAIN[16][6]MAIN[17][6]MAIN[17][5]MAIN[15][7]MAIN[14][5]MAIN[14][4]MAIN[15][6]DBL_W0[0]
Source
00000000off
00010001OMUX_S0
00010010HEX_E6[0]
00010100OUT_FAN[3]
00011000HEX_N6[0]
00100001OMUX_NW10
00100010HEX_S6[1]
00100100OUT_FAN[4]
00101000HEX_W6[0]
01000001DBL_W2[0]
01000010HEX_N3[0]
01000100HEX_S3[0]
01001000DBL_N3[9]
10000001DBL_W2_N[8]
10000010DBL_S1[0]
10000100DBL_S2[2]
10001000DBL_N1[0]
virtex2 INT_GT_CLKPAD switchbox INT muxes DBL_W0[1]
BitsDestination
MAIN[16][13]MAIN[16][14]MAIN[17][14]MAIN[17][13]MAIN[15][15]MAIN[14][13]MAIN[14][12]MAIN[15][14]DBL_W0[1]
Source
00000000off
00010001OMUX[2]
00010010HEX_E6[1]
00010100OUT_FAN[2]
00011000HEX_N6[1]
00100001OMUX_W1
00100010HEX_S6[2]
00100100OUT_FAN[5]
00101000HEX_W6[1]
01000001DBL_W2[1]
01000010HEX_N3[1]
01000100HEX_S3[1]
01001000DBL_N2[0]
10000001DBL_W2_N[9]
10000010DBL_S1[1]
10000100DBL_S2[3]
10001000DBL_N1[1]
virtex2 INT_GT_CLKPAD switchbox INT muxes DBL_W0[2]
BitsDestination
MAIN[15][23]MAIN[14][20]MAIN[15][22]MAIN[14][21]MAIN[16][22]MAIN[16][21]MAIN[17][22]MAIN[17][21]DBL_W0[2]
Source
00000000off
00010001OMUX[4]
00010010OUT_FAN[3]
00010100DBL_S2[4]
00011000HEX_S3[2]
00100001OMUX[6]
00100010OMUX_WN14
00100100DBL_W2[0]
00101000DBL_W2[2]
01000001HEX_E6[2]
01000010HEX_S6[3]
01000100DBL_S1[2]
01001000HEX_N3[2]
10000001HEX_N6[2]
10000010HEX_W6[2]
10000100DBL_N1[2]
10001000DBL_N2[1]
virtex2 INT_GT_CLKPAD switchbox INT muxes DBL_W0[3]
BitsDestination
MAIN[16][30]MAIN[16][29]MAIN[17][30]MAIN[17][29]MAIN[15][31]MAIN[14][29]MAIN[14][28]MAIN[15][30]DBL_W0[3]
Source
00000000off
00010001OMUX_W6
00010010HEX_E6[3]
00010100OUT_FAN[4]
00011000HEX_N6[3]
00100001OMUX_NW10
00100010HEX_S6[4]
00100100OUT_FAN[2]
00101000HEX_W6[3]
01000001DBL_W2[1]
01000010DBL_S1[3]
01000100DBL_S2[5]
01001000DBL_N1[3]
10000001DBL_W2[3]
10000010HEX_N3[3]
10000100HEX_S3[3]
10001000DBL_N2[2]
virtex2 INT_GT_CLKPAD switchbox INT muxes DBL_W0[4]
BitsDestination
MAIN[16][38]MAIN[16][37]MAIN[17][38]MAIN[17][37]MAIN[15][39]MAIN[14][37]MAIN[14][36]MAIN[15][38]DBL_W0[4]
Source
00000000off
00010001OMUX_WS1
00010010HEX_E6[4]
00010100OUT_FAN[5]
00011000HEX_N6[4]
00100001OMUX_N12
00100010HEX_S6[5]
00100100OUT_FAN[6]
00101000HEX_W6[4]
01000001DBL_W2[2]
01000010DBL_S1[4]
01000100DBL_S2[6]
01001000DBL_N1[4]
10000001DBL_W2[4]
10000010HEX_N3[4]
10000100HEX_S3[4]
10001000DBL_N2[3]
virtex2 INT_GT_CLKPAD switchbox INT muxes DBL_W0[5]
BitsDestination
MAIN[16][46]MAIN[16][45]MAIN[17][46]MAIN[17][45]MAIN[15][47]MAIN[14][45]MAIN[14][44]MAIN[15][46]DBL_W0[5]
Source
00000000off
00010001OMUX_S3
00010010HEX_E6[5]
00010100OUT_FAN[1]
00011000HEX_N6[5]
00100001OMUX_WN14
00100010HEX_S6[6]
00100100OUT_FAN[7]
00101000HEX_W6[5]
01000001DBL_W2[3]
01000010DBL_S1[5]
01000100DBL_S2[7]
01001000DBL_N1[5]
10000001DBL_W2[5]
10000010HEX_N3[5]
10000100HEX_S3[5]
10001000DBL_N2[4]
virtex2 INT_GT_CLKPAD switchbox INT muxes DBL_W0[6]
BitsDestination
MAIN[15][55]MAIN[14][52]MAIN[15][54]MAIN[14][53]MAIN[16][54]MAIN[16][53]MAIN[17][53]MAIN[17][54]DBL_W0[6]
Source
00000000off
00010001OMUX[11]
00010010OUT_FAN[0]
00010100DBL_S2[8]
00011000HEX_S3[6]
00100001OMUX_W9
00100010OMUX_SW5
00100100DBL_W2[4]
00101000DBL_W2[6]
01000001HEX_S6[7]
01000010HEX_E6[6]
01000100DBL_S1[6]
01001000HEX_N3[6]
10000001HEX_W6[6]
10000010HEX_N6[6]
10000100DBL_N1[6]
10001000DBL_N2[5]
virtex2 INT_GT_CLKPAD switchbox INT muxes DBL_W0[7]
BitsDestination
MAIN[16][62]MAIN[16][61]MAIN[17][61]MAIN[17][62]MAIN[15][63]MAIN[14][61]MAIN[14][60]MAIN[15][62]DBL_W0[7]
Source
00000000off
00010001OMUX[9]
00010010HEX_S6[8]
00010100OUT_FAN[1]
00011000HEX_W6[7]
00100001OMUX_WS1
00100010HEX_E6[7]
00100100OUT_FAN[6]
00101000HEX_N6[7]
01000001DBL_W2[5]
01000010DBL_S1[7]
01000100DBL_S2[9]
01001000DBL_N1[7]
10000001DBL_W2[7]
10000010HEX_N3[7]
10000100HEX_S3[7]
10001000DBL_N2[6]
virtex2 INT_GT_CLKPAD switchbox INT muxes DBL_W0[8]
BitsDestination
MAIN[16][70]MAIN[16][69]MAIN[17][69]MAIN[17][70]MAIN[15][71]MAIN[14][69]MAIN[14][68]MAIN[15][70]DBL_W0[8]
Source
00000000off
00010001OMUX[13]
00010010HEX_S6[9]
00010100OUT_FAN[0]
00011000HEX_W6[8]
00100001OMUX_W14
00100010HEX_E6[8]
00100100OUT_FAN[7]
00101000HEX_N6[8]
01000001DBL_W2[6]
01000010DBL_S1[8]
01000100DBL_S3[0]
01001000DBL_N1[8]
10000001DBL_W2[8]
10000010HEX_N3[8]
10000100HEX_S3[8]
10001000DBL_N2[7]
virtex2 INT_GT_CLKPAD switchbox INT muxes DBL_W0[9]
BitsDestination
MAIN[15][79]MAIN[14][76]MAIN[14][77]MAIN[15][78]MAIN[16][78]MAIN[16][77]MAIN[17][77]MAIN[17][78]DBL_W0[9]
Source
00000000off
00010001OMUX[13]
00010010OMUX_SW5
00010100DBL_W2[7]
00011000DBL_W2[9]
00100001OMUX_S0
00100010OMUX[15]
00100100DBL_S3[1]
00101000HEX_S3[9]
01000001HEX_S7[0]
01000010HEX_E6[9]
01000100DBL_S1[9]
01001000HEX_N3[9]
10000001HEX_W6[9]
10000010HEX_N6[9]
10000100DBL_N1[9]
10001000DBL_N2[8]
virtex2 INT_GT_CLKPAD switchbox INT muxes DBL_E0[0]
BitsDestination
MAIN[17][7]MAIN[17][4]MAIN[16][4]MAIN[16][7]MAIN[15][5]MAIN[14][7]MAIN[15][4]MAIN[14][6]DBL_E0[0]
Source
00000000off
00010001OMUX_E2
00010010HEX_S6[1]
00010100OUT_FAN[4]
00011000HEX_W6[0]
00100001OMUX_EN8
00100010HEX_E6[0]
00100100OUT_FAN[3]
00101000HEX_N6[0]
01000001DBL_E2[0]
01000010DBL_S1[0]
01000100DBL_S2[2]
01001000DBL_N1[0]
10000001DBL_E2[2]
10000010HEX_N3[0]
10000100HEX_S3[0]
10001000DBL_N3[9]
virtex2 INT_GT_CLKPAD switchbox INT muxes DBL_E0[1]
BitsDestination
MAIN[17][15]MAIN[17][12]MAIN[16][12]MAIN[16][15]MAIN[15][13]MAIN[14][15]MAIN[15][12]MAIN[14][14]DBL_E0[1]
Source
00000000off
00010001OMUX_S4
00010010HEX_S6[2]
00010100OUT_FAN[5]
00011000HEX_W6[1]
00100001OMUX_N10
00100010HEX_E6[1]
00100100OUT_FAN[2]
00101000HEX_N6[1]
01000001DBL_E2[1]
01000010DBL_S1[1]
01000100DBL_S2[3]
01001000DBL_N1[1]
10000001DBL_E2[3]
10000010HEX_N3[1]
10000100HEX_S3[1]
10001000DBL_N2[0]
virtex2 INT_GT_CLKPAD switchbox INT muxes DBL_E0[2]
BitsDestination
MAIN[15][21]MAIN[15][20]MAIN[14][22]MAIN[14][23]MAIN[17][23]MAIN[17][20]MAIN[16][23]MAIN[16][20]DBL_E0[2]
Source
00000000off
00010001OMUX[4]
00010010OUT_FAN[3]
00010100DBL_S2[4]
00011000HEX_S3[2]
00100001OMUX_NE12
00100010OMUX[6]
00100100DBL_E2[2]
00101000DBL_E2[4]
01000001HEX_E6[2]
01000010HEX_S6[3]
01000100DBL_S1[2]
01001000HEX_N3[2]
10000001HEX_N6[2]
10000010HEX_W6[2]
10000100DBL_N1[2]
10001000DBL_N2[1]
virtex2 INT_GT_CLKPAD switchbox INT muxes DBL_E0[3]
BitsDestination
MAIN[17][31]MAIN[17][28]MAIN[16][28]MAIN[16][31]MAIN[15][29]MAIN[14][31]MAIN[15][28]MAIN[14][30]DBL_E0[3]
Source
00000000off
00010001OMUX_SE3
00010010HEX_S6[4]
00010100OUT_FAN[2]
00011000HEX_W6[3]
00100001OMUX_EN8
00100010HEX_E6[3]
00100100OUT_FAN[4]
00101000HEX_N6[3]
01000001DBL_E2[3]
01000010DBL_S1[3]
01000100DBL_S2[5]
01001000DBL_N1[3]
10000001DBL_E2[5]
10000010HEX_N3[3]
10000100HEX_S3[3]
10001000DBL_N2[2]
virtex2 INT_GT_CLKPAD switchbox INT muxes DBL_E0[4]
BitsDestination
MAIN[17][39]MAIN[17][36]MAIN[16][39]MAIN[16][36]MAIN[15][37]MAIN[14][39]MAIN[15][36]MAIN[14][38]DBL_E0[4]
Source
00000000off
00010001OMUX_E7
00010010HEX_E6[4]
00010100OUT_FAN[5]
00011000HEX_N6[4]
00100001OMUX_E8
00100010HEX_S6[5]
00100100OUT_FAN[6]
00101000HEX_W6[4]
01000001DBL_E2[4]
01000010DBL_S1[4]
01000100DBL_S2[6]
01001000DBL_N1[4]
10000001DBL_E2[6]
10000010HEX_N3[4]
10000100HEX_S3[4]
10001000DBL_N2[3]
virtex2 INT_GT_CLKPAD switchbox INT muxes DBL_E0[5]
BitsDestination
MAIN[17][47]MAIN[17][44]MAIN[16][44]MAIN[16][47]MAIN[15][45]MAIN[14][47]MAIN[15][44]MAIN[14][46]DBL_E0[5]
Source
00000000off
00010001OMUX_ES7
00010010HEX_S6[6]
00010100OUT_FAN[7]
00011000HEX_W6[5]
00100001OMUX_NE12
00100010HEX_E6[5]
00100100OUT_FAN[1]
00101000HEX_N6[5]
01000001DBL_E2[5]
01000010DBL_S1[5]
01000100DBL_S2[7]
01001000DBL_N1[5]
10000001DBL_E2[7]
10000010HEX_N3[5]
10000100HEX_S3[5]
10001000DBL_N2[4]
virtex2 INT_GT_CLKPAD switchbox INT muxes DBL_E0[6]
BitsDestination
MAIN[17][55]MAIN[17][52]MAIN[16][55]MAIN[16][52]MAIN[15][53]MAIN[15][52]MAIN[14][55]MAIN[14][54]DBL_E0[6]
Source
00000000off
00010001OMUX[9]
00010010OUT_FAN[0]
00010100HEX_E6[6]
00011000HEX_N6[6]
00100001OMUX_SE3
00100010OMUX[11]
00100100HEX_S6[7]
00101000HEX_W6[6]
01000001DBL_E2[6]
01000010DBL_S2[8]
01000100DBL_S1[6]
01001000DBL_N1[6]
10000001DBL_E2[8]
10000010HEX_S3[6]
10000100HEX_N3[6]
10001000DBL_N2[5]
virtex2 INT_GT_CLKPAD switchbox INT muxes DBL_E0[7]
BitsDestination
MAIN[17][63]MAIN[17][60]MAIN[16][60]MAIN[16][63]MAIN[15][61]MAIN[14][63]MAIN[15][60]MAIN[14][62]DBL_E0[7]
Source
00000000off
00010001OMUX_S5
00010010HEX_S6[8]
00010100OUT_FAN[1]
00011000HEX_W6[7]
00100001OMUX_N11
00100010HEX_E6[7]
00100100OUT_FAN[6]
00101000HEX_N6[7]
01000001DBL_E2[7]
01000010DBL_S1[7]
01000100DBL_S2[9]
01001000DBL_N1[7]
10000001DBL_E2[9]
10000010HEX_N3[7]
10000100HEX_S3[7]
10001000DBL_N2[6]
virtex2 INT_GT_CLKPAD switchbox INT muxes DBL_E0[8]
BitsDestination
MAIN[17][71]MAIN[17][68]MAIN[16][68]MAIN[16][71]MAIN[15][69]MAIN[14][71]MAIN[15][68]MAIN[14][70]DBL_E0[8]
Source
00000000off
00010001OMUX_ES7
00010010HEX_S6[9]
00010100OUT_FAN[0]
00011000HEX_W6[8]
00100001OMUX_E13
00100010HEX_E6[8]
00100100OUT_FAN[7]
00101000HEX_N6[8]
01000001DBL_E2[8]
01000010DBL_S1[8]
01000100DBL_S3[0]
01001000DBL_N1[8]
10000001DBL_E2_S[0]
10000010HEX_N3[8]
10000100HEX_S3[8]
10001000DBL_N2[7]
virtex2 INT_GT_CLKPAD switchbox INT muxes DBL_E0[9]
BitsDestination
MAIN[17][79]MAIN[17][76]MAIN[16][79]MAIN[16][76]MAIN[15][77]MAIN[15][76]MAIN[14][78]MAIN[14][79]DBL_E0[9]
Source
00000000off
00010001OMUX[15]
00010010OMUX_N15
00010100HEX_E6[9]
00011000HEX_N6[9]
00100001OMUX_S0
00100010OMUX_S2
00100100HEX_S7[0]
00101000HEX_W6[9]
01000001DBL_S3[1]
01000010DBL_E2[9]
01000100DBL_S1[9]
01001000DBL_N1[9]
10000001HEX_S3[9]
10000010DBL_E2_S[1]
10000100HEX_N3[9]
10001000DBL_N2[8]
virtex2 INT_GT_CLKPAD switchbox INT muxes DBL_S0[0]
BitsDestination
MAIN[15][0]MAIN[15][1]MAIN[14][2]MAIN[14][3]MAIN[17][3]MAIN[17][0]MAIN[16][3]MAIN[16][0]DBL_S0[0]
Source
00000000off
00010001OMUX[0]
00010010OUT_FAN[3]
00010100DBL_E2[1]
00011000HEX_E3[0]
00100001OMUX[2]
00100010OMUX_S0
00100100DBL_S2[0]
00101000DBL_S2[2]
01000001HEX_W6_N[9]
01000010HEX_N6[0]
01000100DBL_W1[0]
01001000DBL_W2_N[8]
10000001HEX_S6[0]
10000010HEX_E6[0]
10000100DBL_E1[0]
10001000HEX_W3[0]
virtex2 INT_GT_CLKPAD switchbox INT muxes DBL_S0[1]
BitsDestination
MAIN[17][11]MAIN[17][8]MAIN[16][8]MAIN[16][11]MAIN[14][11]MAIN[15][8]MAIN[15][9]MAIN[14][10]DBL_S0[1]
Source
00000000off
00010001OMUX[2]
00010010HEX_N6[1]
00010100HEX_E6[1]
00011000OUT_FAN[2]
00100001OMUX_E2
00100010HEX_W6[0]
00100100HEX_S6[1]
00101000OUT_FAN[4]
01000001DBL_S2[1]
01000010DBL_W1[1]
01000100DBL_E1[1]
01001000DBL_E2[2]
10000001DBL_S2[3]
10000010DBL_W2_N[9]
10000100HEX_W3[1]
10001000HEX_E3[1]
virtex2 INT_GT_CLKPAD switchbox INT muxes DBL_S0[2]
BitsDestination
MAIN[15][16]MAIN[15][17]MAIN[14][18]MAIN[14][19]MAIN[17][19]MAIN[17][16]MAIN[16][16]MAIN[16][19]DBL_S0[2]
Source
00000000off
00010001OMUX[4]
00010010OUT_FAN[5]
00010100DBL_E2[3]
00011000HEX_E3[2]
00100001OMUX[6]
00100010OMUX_S4
00100100DBL_S2[2]
00101000DBL_S2[4]
01000001HEX_N6[2]
01000010HEX_W6[1]
01000100DBL_W1[2]
01001000DBL_W2[0]
10000001HEX_E6[2]
10000010HEX_S6[2]
10000100DBL_E1[2]
10001000HEX_W3[2]
virtex2 INT_GT_CLKPAD switchbox INT muxes DBL_S0[3]
BitsDestination
MAIN[17][27]MAIN[17][24]MAIN[16][27]MAIN[16][24]MAIN[14][27]MAIN[15][24]MAIN[15][25]MAIN[14][26]DBL_S0[3]
Source
00000000off
00010001OMUX[6]
00010010HEX_W6[2]
00010100HEX_S6[3]
00011000OUT_FAN[3]
00100001OMUX_W6
00100010HEX_N6[3]
00100100HEX_E6[3]
00101000OUT_FAN[4]
01000001DBL_S2[3]
01000010DBL_W1[3]
01000100DBL_E1[3]
01001000DBL_E2[4]
10000001DBL_S2[5]
10000010DBL_W2[1]
10000100HEX_W3[3]
10001000HEX_E3[3]
virtex2 INT_GT_CLKPAD switchbox INT muxes DBL_S0[4]
BitsDestination
MAIN[17][35]MAIN[17][32]MAIN[16][32]MAIN[16][35]MAIN[14][35]MAIN[15][32]MAIN[15][33]MAIN[14][34]DBL_S0[4]
Source
00000000off
00010001OMUX_WS1
00010010HEX_N6[4]
00010100HEX_E6[4]
00011000OUT_FAN[5]
00100001OMUX_SE3
00100010HEX_W6[3]
00100100HEX_S6[4]
00101000OUT_FAN[2]
01000001DBL_S2[4]
01000010DBL_W1[4]
01000100DBL_E1[4]
01001000DBL_E2[5]
10000001DBL_S2[6]
10000010DBL_W2[2]
10000100HEX_W3[4]
10001000HEX_E3[4]
virtex2 INT_GT_CLKPAD switchbox INT muxes DBL_S0[5]
BitsDestination
MAIN[17][43]MAIN[17][40]MAIN[16][40]MAIN[16][43]MAIN[14][43]MAIN[15][40]MAIN[15][41]MAIN[14][42]DBL_S0[5]
Source
00000000off
00010001OMUX_S3
00010010HEX_N6[5]
00010100HEX_E6[5]
00011000OUT_FAN[1]
00100001OMUX_E8
00100010HEX_W6[4]
00100100HEX_S6[5]
00101000OUT_FAN[6]
01000001DBL_S2[5]
01000010DBL_W1[5]
01000100DBL_E1[5]
01001000DBL_E2[6]
10000001DBL_S2[7]
10000010DBL_W2[3]
10000100HEX_W3[5]
10001000HEX_E3[5]
virtex2 INT_GT_CLKPAD switchbox INT muxes DBL_S0[6]
BitsDestination
MAIN[17][51]MAIN[17][48]MAIN[16][48]MAIN[16][51]MAIN[14][51]MAIN[15][48]MAIN[15][49]MAIN[14][50]DBL_S0[6]
Source
00000000off
00010001OMUX_SW5
00010010HEX_N6[6]
00010100HEX_E6[6]
00011000OUT_FAN[0]
00100001OMUX_ES7
00100010HEX_W6[5]
00100100HEX_S6[6]
00101000OUT_FAN[7]
01000001DBL_S2[6]
01000010DBL_W1[6]
01000100DBL_E1[6]
01001000DBL_E2[7]
10000001DBL_S2[8]
10000010DBL_W2[4]
10000100HEX_W3[6]
10001000HEX_E3[6]
virtex2 INT_GT_CLKPAD switchbox INT muxes DBL_S0[7]
BitsDestination
MAIN[15][56]MAIN[15][57]MAIN[14][58]MAIN[14][59]MAIN[17][59]MAIN[17][56]MAIN[16][59]MAIN[16][56]DBL_S0[7]
Source
00000000off
00010001OMUX[11]
00010010OUT_FAN[6]
00010100DBL_E2[8]
00011000HEX_E3[7]
00100001OMUX_SE3
00100010OMUX_WS1
00100100DBL_S2[7]
00101000DBL_S2[9]
01000001HEX_W6[6]
01000010HEX_N6[7]
01000100DBL_W1[7]
01001000DBL_W2[5]
10000001HEX_S6[7]
10000010HEX_E6[7]
10000100DBL_E1[7]
10001000HEX_W3[7]
virtex2 INT_GT_CLKPAD switchbox INT muxes DBL_S0[8]
BitsDestination
MAIN[17][67]MAIN[17][64]MAIN[16][67]MAIN[16][64]MAIN[14][67]MAIN[15][64]MAIN[15][65]MAIN[14][66]DBL_S0[8]
Source
00000000off
00010001OMUX_S5
00010010HEX_W6[7]
00010100HEX_S6[8]
00011000OUT_FAN[1]
00100001OMUX_W14
00100010HEX_N6[8]
00100100HEX_E6[8]
00101000OUT_FAN[7]
01000001DBL_S2[8]
01000010DBL_W1[8]
01000100DBL_E1[8]
01001000DBL_E2[9]
10000001DBL_S3[0]
10000010DBL_W2[6]
10000100HEX_W3[8]
10001000HEX_E3[8]
virtex2 INT_GT_CLKPAD switchbox INT muxes DBL_S0[9]
BitsDestination
MAIN[15][72]MAIN[15][73]MAIN[14][74]MAIN[14][75]MAIN[17][75]MAIN[17][72]MAIN[16][72]MAIN[16][75]DBL_S0[9]
Source
00000000off
00010001OMUX[15]
00010010OUT_FAN[0]
00010100DBL_E2_S[0]
00011000HEX_E3[9]
00100001OMUX_SW5
00100010OMUX_ES7
00100100DBL_S2[9]
00101000DBL_S3[1]
01000001HEX_N6[9]
01000010HEX_W6[8]
01000100DBL_W1[9]
01001000DBL_W2[7]
10000001HEX_E6[9]
10000010HEX_S6[9]
10000100DBL_E1[9]
10001000HEX_W3[9]
virtex2 INT_GT_CLKPAD switchbox INT muxes DBL_N0[0]
BitsDestination
MAIN[14][0]MAIN[15][3]MAIN[15][2]MAIN[14][1]MAIN[16][2]MAIN[16][1]MAIN[17][2]MAIN[17][1]DBL_N0[0]
Source
00000000off
00010001OMUX[0]
00010010OUT_FAN[3]
00010100DBL_E2[1]
00011000HEX_E3[0]
00100001OMUX_N13
00100010OMUX_EN8
00100100DBL_N3[8]
00101000DBL_N2[0]
01000001HEX_W6_N[9]
01000010HEX_N6[0]
01000100DBL_W1[0]
01001000DBL_W2_N[8]
10000001HEX_S6[0]
10000010HEX_E6[0]
10000100DBL_E1[0]
10001000HEX_W3[0]
virtex2 INT_GT_CLKPAD switchbox INT muxes DBL_N0[1]
BitsDestination
MAIN[16][10]MAIN[16][9]MAIN[17][9]MAIN[17][10]MAIN[14][9]MAIN[14][8]MAIN[15][11]MAIN[15][10]DBL_N0[1]
Source
00000000off
00010001OMUX_N10
00010010HEX_N6[1]
00010100HEX_E6[1]
00011000OUT_FAN[2]
00100001OMUX_NW10
00100010HEX_W6[0]
00100100HEX_S6[1]
00101000OUT_FAN[4]
01000001DBL_N3[9]
01000010DBL_W1[1]
01000100DBL_E1[1]
01001000DBL_E2[2]
10000001DBL_N2[1]
10000010DBL_W2_N[9]
10000100HEX_W3[1]
10001000HEX_E3[1]
virtex2 INT_GT_CLKPAD switchbox INT muxes DBL_N0[2]
BitsDestination
MAIN[14][16]MAIN[15][19]MAIN[15][18]MAIN[14][17]MAIN[16][18]MAIN[16][17]MAIN[17][17]MAIN[17][18]DBL_N0[2]
Source
00000000off
00010001OMUX[4]
00010010OUT_FAN[5]
00010100DBL_E2[3]
00011000HEX_E3[2]
00100001OMUX_NE12
00100010OMUX_W1
00100100DBL_N2[0]
00101000DBL_N2[2]
01000001HEX_N6[2]
01000010HEX_W6[1]
01000100DBL_W1[2]
01001000DBL_W2[0]
10000001HEX_E6[2]
10000010HEX_S6[2]
10000100DBL_E1[2]
10001000HEX_W3[2]
virtex2 INT_GT_CLKPAD switchbox INT muxes DBL_N0[3]
BitsDestination
MAIN[16][26]MAIN[16][25]MAIN[17][25]MAIN[17][26]MAIN[14][25]MAIN[14][24]MAIN[15][27]MAIN[15][26]DBL_N0[3]
Source
00000000off
00010001OMUX_EN8
00010010HEX_N6[3]
00010100HEX_E6[3]
00011000OUT_FAN[4]
00100001OMUX_WN14
00100010HEX_W6[2]
00100100HEX_S6[3]
00101000OUT_FAN[3]
01000001DBL_N2[1]
01000010DBL_W1[3]
01000100DBL_E1[3]
01001000DBL_E2[4]
10000001DBL_N2[3]
10000010DBL_W2[1]
10000100HEX_W3[3]
10001000HEX_E3[3]
virtex2 INT_GT_CLKPAD switchbox INT muxes DBL_N0[4]
BitsDestination
MAIN[16][34]MAIN[16][33]MAIN[17][33]MAIN[17][34]MAIN[14][33]MAIN[14][32]MAIN[15][35]MAIN[15][34]DBL_N0[4]
Source
00000000off
00010001OMUX_E7
00010010HEX_N6[4]
00010100HEX_E6[4]
00011000OUT_FAN[5]
00100001OMUX_NW10
00100010HEX_W6[3]
00100100HEX_S6[4]
00101000OUT_FAN[2]
01000001DBL_N2[2]
01000010DBL_W1[4]
01000100DBL_E1[4]
01001000DBL_E2[5]
10000001DBL_N2[4]
10000010DBL_W2[2]
10000100HEX_W3[4]
10001000HEX_E3[4]
virtex2 INT_GT_CLKPAD switchbox INT muxes DBL_N0[5]
BitsDestination
MAIN[16][42]MAIN[16][41]MAIN[17][42]MAIN[17][41]MAIN[14][41]MAIN[14][40]MAIN[15][43]MAIN[15][42]DBL_N0[5]
Source
00000000off
00010001OMUX_N12
00010010HEX_W6[4]
00010100HEX_S6[5]
00011000OUT_FAN[6]
00100001OMUX_NE12
00100010HEX_N6[5]
00100100HEX_E6[5]
00101000OUT_FAN[1]
01000001DBL_N2[3]
01000010DBL_W1[5]
01000100DBL_E1[5]
01001000DBL_E2[6]
10000001DBL_N2[5]
10000010DBL_W2[3]
10000100HEX_W3[5]
10001000HEX_E3[5]
virtex2 INT_GT_CLKPAD switchbox INT muxes DBL_N0[6]
BitsDestination
MAIN[16][50]MAIN[16][49]MAIN[17][49]MAIN[17][50]MAIN[14][49]MAIN[14][48]MAIN[15][51]MAIN[15][50]DBL_N0[6]
Source
00000000off
00010001OMUX[9]
00010010HEX_N6[6]
00010100HEX_E6[6]
00011000OUT_FAN[0]
00100001OMUX_WN14
00100010HEX_W6[5]
00100100HEX_S6[6]
00101000OUT_FAN[7]
01000001DBL_N2[4]
01000010DBL_W1[6]
01000100DBL_E1[6]
01001000DBL_E2[7]
10000001DBL_N2[6]
10000010DBL_W2[4]
10000100HEX_W3[6]
10001000HEX_E3[6]
virtex2 INT_GT_CLKPAD switchbox INT muxes DBL_N0[7]
BitsDestination
MAIN[14][56]MAIN[15][59]MAIN[15][58]MAIN[14][57]MAIN[16][58]MAIN[16][57]MAIN[17][58]MAIN[17][57]DBL_N0[7]
Source
00000000off
00010001OMUX[11]
00010010OUT_FAN[6]
00010100DBL_E2[8]
00011000HEX_E3[7]
00100001OMUX_W9
00100010OMUX_N11
00100100DBL_N2[5]
00101000DBL_N2[7]
01000001HEX_W6[6]
01000010HEX_N6[7]
01000100DBL_W1[7]
01001000DBL_W2[5]
10000001HEX_S6[7]
10000010HEX_E6[7]
10000100DBL_E1[7]
10001000HEX_W3[7]
virtex2 INT_GT_CLKPAD switchbox INT muxes DBL_N0[8]
BitsDestination
MAIN[16][66]MAIN[16][65]MAIN[17][66]MAIN[17][65]MAIN[14][65]MAIN[14][64]MAIN[15][67]MAIN[15][66]DBL_N0[8]
Source
00000000off
00010001OMUX[9]
00010010HEX_W6[7]
00010100HEX_S6[8]
00011000OUT_FAN[1]
00100001OMUX_E13
00100010HEX_N6[8]
00100100HEX_E6[8]
00101000OUT_FAN[7]
01000001DBL_N2[6]
01000010DBL_W1[8]
01000100DBL_E1[8]
01001000DBL_E2[9]
10000001DBL_N2[8]
10000010DBL_W2[6]
10000100HEX_W3[8]
10001000HEX_E3[8]
virtex2 INT_GT_CLKPAD switchbox INT muxes DBL_N0[9]
BitsDestination
MAIN[16][74]MAIN[16][73]MAIN[17][74]MAIN[17][73]MAIN[14][72]MAIN[15][75]MAIN[14][73]MAIN[15][74]DBL_N0[9]
Source
00000000off
00010001OMUX[13]
00010010OUT_FAN[0]
00010100HEX_W6[8]
00011000HEX_S6[9]
00100001OMUX_N15
00100010OMUX[15]
00100100HEX_N6[9]
00101000HEX_E6[9]
01000001DBL_N2[7]
01000010DBL_E2_S[0]
01000100DBL_W1[9]
01001000DBL_E1[9]
10000001DBL_N2[9]
10000010HEX_E3[9]
10000100DBL_W2[7]
10001000HEX_W3[9]
virtex2 INT_GT_CLKPAD switchbox INT muxes HEX_W0[0]
BitsDestination
MAIN[20][4]MAIN[20][6]MAIN[20][5]MAIN[18][4]MAIN[19][6]MAIN[18][6]MAIN[19][4]HEX_W0[0]
Source
0000000off
0010001OMUX_S0
0010010HEX_S3[0]
0010100HEX_N3[0]
0011000LH[6]
0100001OUT_FAN[4]
0100010OMUX_NW10
0100100HEX_W6[0]
0101000HEX_W6_N[8]
1000001OUT_FAN[3]
1000010LH[18]
1000100HEX_N7[9]
1001000HEX_S6[2]
virtex2 INT_GT_CLKPAD switchbox INT muxes HEX_W0[1]
BitsDestination
MAIN[21][12]MAIN[20][15]MAIN[21][14]MAIN[18][13]MAIN[19][15]MAIN[18][15]MAIN[19][13]HEX_W0[1]
Source
0000000off
0010001OMUX[2]
0010010OUT_FAN[5]
0010100HEX_W6[1]
0011000HEX_W6_N[9]
0100001LH[0]
0100010OMUX_W1
0100100HEX_S3[1]
0101000HEX_N3[1]
1000001OUT_FAN[2]
1000010LH[12]
1000100HEX_N6[0]
1001000HEX_S6[3]
virtex2 INT_GT_CLKPAD switchbox INT muxes HEX_W0[2]
BitsDestination
MAIN[20][22]MAIN[20][21]MAIN[20][20]MAIN[19][22]MAIN[18][20]MAIN[18][22]MAIN[19][20]HEX_W0[2]
Source
0000000off
0010001OMUX[4]
0010010LH[18]
0010100HEX_S6[4]
0011000HEX_N6[1]
0100001OMUX[6]
0100010HEX_S3[2]
0100100LH[6]
0101000HEX_N3[2]
1000001OUT_FAN[3]
1000010OMUX_WN14
1000100HEX_W6[0]
1001000HEX_W6[2]
virtex2 INT_GT_CLKPAD switchbox INT muxes HEX_W0[3]
BitsDestination
MAIN[21][28]MAIN[20][31]MAIN[21][30]MAIN[19][31]MAIN[18][29]MAIN[18][31]MAIN[19][29]HEX_W0[3]
Source
0000000off
0010001OMUX_W6
0010010OUT_FAN[2]
0010100HEX_W6[1]
0011000HEX_W6[3]
0100001LH[0]
0100010OMUX_NW10
0100100HEX_N3[3]
0101000HEX_S3[3]
1000001OUT_FAN[4]
1000010LH[12]
1000100HEX_S6[5]
1001000HEX_N6[2]
virtex2 INT_GT_CLKPAD switchbox INT muxes HEX_W0[4]
BitsDestination
MAIN[20][36]MAIN[20][38]MAIN[20][37]MAIN[19][38]MAIN[18][36]MAIN[18][38]MAIN[19][36]HEX_W0[4]
Source
0000000off
0010001OMUX_WS1
0010010HEX_S3[4]
0010100LH[6]
0011000HEX_N3[4]
0100001OUT_FAN[6]
0100010OMUX_N12
0100100HEX_W6[2]
0101000HEX_W6[4]
1000001OUT_FAN[5]
1000010LH[18]
1000100HEX_S6[6]
1001000HEX_N6[3]
virtex2 INT_GT_CLKPAD switchbox INT muxes HEX_W0[5]
BitsDestination
MAIN[21][44]MAIN[20][47]MAIN[21][46]MAIN[19][47]MAIN[18][45]MAIN[18][47]MAIN[19][45]HEX_W0[5]
Source
0000000off
0010001OMUX_S3
0010010OUT_FAN[7]
0010100HEX_W6[3]
0011000HEX_W6[5]
0100001LH[0]
0100010OMUX_WN14
0100100HEX_N3[5]
0101000HEX_S3[5]
1000001OUT_FAN[1]
1000010LH[12]
1000100HEX_S6[7]
1001000HEX_N6[4]
virtex2 INT_GT_CLKPAD switchbox INT muxes HEX_W0[6]
BitsDestination
MAIN[20][52]MAIN[20][53]MAIN[20][54]MAIN[19][54]MAIN[18][52]MAIN[18][54]MAIN[19][52]HEX_W0[6]
Source
0000000off
0010001OMUX[11]
0010010OMUX_W9
0010100HEX_W6[4]
0011000HEX_W6[6]
0100001OMUX_SW5
0100010HEX_S3[6]
0100100LH[6]
0101000HEX_N3[6]
1000001OUT_FAN[0]
1000010LH[18]
1000100HEX_S6[8]
1001000HEX_N6[5]
virtex2 INT_GT_CLKPAD switchbox INT muxes HEX_W0[7]
BitsDestination
MAIN[21][60]MAIN[21][62]MAIN[20][63]MAIN[19][63]MAIN[18][61]MAIN[19][61]MAIN[18][63]HEX_W0[7]
Source
0000000off
0010001OMUX[9]
0010010LH[0]
0010100HEX_N3[7]
0011000HEX_S3[7]
0100001OUT_FAN[1]
0100010OMUX_WS1
0100100HEX_W6[5]
0101000HEX_W6[7]
1000001LH[12]
1000010OUT_FAN[6]
1000100HEX_S6[9]
1001000HEX_N6[6]
virtex2 INT_GT_CLKPAD switchbox INT muxes HEX_W0[8]
BitsDestination
MAIN[20][68]MAIN[20][69]MAIN[20][70]MAIN[19][70]MAIN[18][68]MAIN[19][68]MAIN[18][70]HEX_W0[8]
Source
0000000off
0010001OMUX[13]
0010010OUT_FAN[0]
0010100HEX_W6[6]
0011000HEX_W6[8]
0100001HEX_S3[8]
0100010OMUX_W14
0100100LH[6]
0101000HEX_N3[8]
1000001LH[18]
1000010OUT_FAN[7]
1000100HEX_S7[0]
1001000HEX_N6[7]
virtex2 INT_GT_CLKPAD switchbox INT muxes HEX_W0[9]
BitsDestination
MAIN[21][78]MAIN[21][76]MAIN[20][79]MAIN[19][79]MAIN[18][77]MAIN[19][77]MAIN[18][79]HEX_W0[9]
Source
0000000off
0010001OMUX[13]
0010010LH[0]
0010100HEX_N3[9]
0011000HEX_S3[9]
0100001LH[12]
0100010OMUX[15]
0100100HEX_S7[1]
0101000HEX_N6[8]
1000001OMUX_S0
1000010OMUX_SW5
1000100HEX_W6[7]
1001000HEX_W6[9]
virtex2 INT_GT_CLKPAD switchbox INT muxes HEX_E0[0]
BitsDestination
MAIN[21][4]MAIN[21][6]MAIN[20][7]MAIN[19][7]MAIN[18][5]MAIN[19][5]MAIN[18][7]HEX_E0[0]
Source
0000000off
0010001OMUX_E2
0010010LH[6]
0010100HEX_N3[0]
0011000HEX_S3[0]
0100001OUT_FAN[4]
0100010OMUX_EN8
0100100HEX_E6[0]
0101000HEX_E6[2]
1000001LH[18]
1000010OUT_FAN[3]
1000100HEX_S6[2]
1001000HEX_N7[9]
virtex2 INT_GT_CLKPAD switchbox INT muxes HEX_E0[1]
BitsDestination
MAIN[20][12]MAIN[20][13]MAIN[20][14]MAIN[19][14]MAIN[18][12]MAIN[19][12]MAIN[18][14]HEX_E0[1]
Source
0000000off
0010001OMUX_S4
0010010OUT_FAN[5]
0010100HEX_E6[1]
0011000HEX_E6[3]
0100001HEX_S3[1]
0100010OMUX_N10
0100100LH[0]
0101000HEX_N3[1]
1000001LH[12]
1000010OUT_FAN[2]
1000100HEX_S6[3]
1001000HEX_N6[0]
virtex2 INT_GT_CLKPAD switchbox INT muxes HEX_E0[2]
BitsDestination
MAIN[21][22]MAIN[20][23]MAIN[21][20]MAIN[19][23]MAIN[18][21]MAIN[18][23]MAIN[19][21]HEX_E0[2]
Source
0000000off
0010001OMUX[4]
0010010LH[18]
0010100HEX_S6[4]
0011000HEX_N6[1]
0100001LH[6]
0100010OMUX[6]
0100100HEX_N3[2]
0101000HEX_S3[2]
1000001OMUX_NE12
1000010OUT_FAN[3]
1000100HEX_E6[2]
1001000HEX_E6[4]
virtex2 INT_GT_CLKPAD switchbox INT muxes HEX_E0[3]
BitsDestination
MAIN[20][28]MAIN[20][29]MAIN[20][30]MAIN[19][30]MAIN[18][28]MAIN[19][28]MAIN[18][30]HEX_E0[3]
Source
0000000off
0010001OMUX_SE3
0010010OUT_FAN[2]
0010100HEX_E6[3]
0011000HEX_E6[5]
0100001HEX_S3[3]
0100010OMUX_EN8
0100100LH[0]
0101000HEX_N3[3]
1000001LH[12]
1000010OUT_FAN[4]
1000100HEX_S6[5]
1001000HEX_N6[2]
virtex2 INT_GT_CLKPAD switchbox INT muxes HEX_E0[4]
BitsDestination
MAIN[21][36]MAIN[20][39]MAIN[21][38]MAIN[19][39]MAIN[18][37]MAIN[18][39]MAIN[19][37]HEX_E0[4]
Source
0000000off
0010001OMUX_E7
0010010OUT_FAN[6]
0010100HEX_E6[4]
0011000HEX_E6[6]
0100001LH[6]
0100010OMUX_E8
0100100HEX_N3[4]
0101000HEX_S3[4]
1000001OUT_FAN[5]
1000010LH[18]
1000100HEX_S6[6]
1001000HEX_N6[3]
virtex2 INT_GT_CLKPAD switchbox INT muxes HEX_E0[5]
BitsDestination
MAIN[20][44]MAIN[20][45]MAIN[20][46]MAIN[19][46]MAIN[18][44]MAIN[19][44]MAIN[18][46]HEX_E0[5]
Source
0000000off
0010001OMUX_ES7
0010010OUT_FAN[7]
0010100HEX_E6[5]
0011000HEX_E6[7]
0100001HEX_S3[5]
0100010OMUX_NE12
0100100LH[0]
0101000HEX_N3[5]
1000001LH[12]
1000010OUT_FAN[1]
1000100HEX_S6[7]
1001000HEX_N6[4]
virtex2 INT_GT_CLKPAD switchbox INT muxes HEX_E0[6]
BitsDestination
MAIN[21][52]MAIN[20][55]MAIN[21][54]MAIN[19][55]MAIN[18][53]MAIN[18][55]MAIN[19][53]HEX_E0[6]
Source
0000000off
0010001OMUX[9]
0010010OMUX[11]
0010100HEX_E6[6]
0011000HEX_E6[8]
0100001LH[6]
0100010OMUX_SE3
0100100HEX_N3[6]
0101000HEX_S3[6]
1000001OUT_FAN[0]
1000010LH[18]
1000100HEX_S6[8]
1001000HEX_N6[5]
virtex2 INT_GT_CLKPAD switchbox INT muxes HEX_E0[7]
BitsDestination
MAIN[20][60]MAIN[20][61]MAIN[20][62]MAIN[19][62]MAIN[18][60]MAIN[19][60]MAIN[18][62]HEX_E0[7]
Source
0000000off
0010001OMUX_S5
0010010OUT_FAN[1]
0010100HEX_E6[7]
0011000HEX_E6[9]
0100001HEX_S3[7]
0100010OMUX_N11
0100100LH[0]
0101000HEX_N3[7]
1000001LH[12]
1000010OUT_FAN[6]
1000100HEX_S6[9]
1001000HEX_N6[6]
virtex2 INT_GT_CLKPAD switchbox INT muxes HEX_E0[8]
BitsDestination
MAIN[21][68]MAIN[21][70]MAIN[20][71]MAIN[19][71]MAIN[18][69]MAIN[19][69]MAIN[18][71]HEX_E0[8]
Source
0000000off
0010001OMUX_ES7
0010010LH[6]
0010100HEX_N3[8]
0011000HEX_S3[8]
0100001OUT_FAN[0]
0100010OMUX_E13
0100100HEX_E6[8]
0101000HEX_E6_S[0]
1000001LH[18]
1000010OUT_FAN[7]
1000100HEX_S7[0]
1001000HEX_N6[7]
virtex2 INT_GT_CLKPAD switchbox INT muxes HEX_E0[9]
BitsDestination
MAIN[20][77]MAIN[20][78]MAIN[20][76]MAIN[19][78]MAIN[18][76]MAIN[18][78]MAIN[19][76]HEX_E0[9]
Source
0000000off
0010001OMUX[15]
0010010LH[12]
0010100HEX_S7[1]
0011000HEX_N6[8]
0100001OMUX_S0
0100010OMUX_S2
0100100HEX_E6[9]
0101000HEX_E6_S[1]
1000001OMUX_N15
1000010HEX_S3[9]
1000100LH[0]
1001000HEX_N3[9]
virtex2 INT_GT_CLKPAD switchbox INT muxes HEX_S0[0]
BitsDestination
MAIN[20][3]MAIN[21][2]MAIN[21][0]MAIN[19][3]MAIN[18][1]MAIN[18][3]MAIN[19][1]HEX_S0[0]
Source
0000000off
0010001OMUX[0]
0010010LV[0]
0010100HEX_E6[1]
0011000HEX_W6_N[8]
0100001OMUX[2]
0100010OUT_FAN[3]
0100100HEX_S6[0]
0101000HEX_S6[2]
1000001LV[12]
1000010OMUX_S0
1000100HEX_W3[0]
1001000HEX_E3[0]
virtex2 INT_GT_CLKPAD switchbox INT muxes HEX_S0[1]
BitsDestination
MAIN[20][8]MAIN[20][9]MAIN[20][10]MAIN[18][8]MAIN[19][10]MAIN[19][8]MAIN[18][10]HEX_S0[1]
Source
0000000off
0010001OMUX[2]
0010010OUT_FAN[2]
0010100HEX_S6[3]
0011000HEX_S6[1]
0100001HEX_E3[1]
0100010OMUX_E2
0100100HEX_W3[1]
0101000LV[18]
1000001LV[6]
1000010OUT_FAN[4]
1000100HEX_W6_N[9]
1001000HEX_E6[2]
virtex2 INT_GT_CLKPAD switchbox INT muxes HEX_S0[2]
BitsDestination
MAIN[21][16]MAIN[20][19]MAIN[21][18]MAIN[19][19]MAIN[18][17]MAIN[19][17]MAIN[18][19]HEX_S0[2]
Source
0000000off
0010001OMUX[4]
0010010OMUX_S4
0010100HEX_S6[2]
0011000HEX_S6[4]
0100001OMUX[6]
0100010LV[12]
0100100HEX_W3[2]
0101000HEX_E3[2]
1000001LV[0]
1000010OUT_FAN[5]
1000100HEX_E6[3]
1001000HEX_W6[0]
virtex2 INT_GT_CLKPAD switchbox INT muxes HEX_S0[3]
BitsDestination
MAIN[20][24]MAIN[20][26]MAIN[20][25]MAIN[18][24]MAIN[19][26]MAIN[18][26]MAIN[19][24]HEX_S0[3]
Source
0000000off
0010001OMUX[6]
0010010HEX_E3[3]
0010100HEX_W3[3]
0011000LV[18]
0100001OUT_FAN[4]
0100010OMUX_W6
0100100HEX_S6[5]
0101000HEX_S6[3]
1000001OUT_FAN[3]
1000010LV[6]
1000100HEX_W6[1]
1001000HEX_E6[4]
virtex2 INT_GT_CLKPAD switchbox INT muxes HEX_S0[4]
BitsDestination
MAIN[21][32]MAIN[21][34]MAIN[20][35]MAIN[19][35]MAIN[18][33]MAIN[19][33]MAIN[18][35]HEX_S0[4]
Source
0000000off
0010001OMUX_WS1
0010010LV[12]
0010100HEX_W3[4]
0011000HEX_E3[4]
0100001OUT_FAN[5]
0100010OMUX_SE3
0100100HEX_S6[4]
0101000HEX_S6[6]
1000001LV[0]
1000010OUT_FAN[2]
1000100HEX_E6[5]
1001000HEX_W6[2]
virtex2 INT_GT_CLKPAD switchbox INT muxes HEX_S0[5]
BitsDestination
MAIN[20][40]MAIN[20][41]MAIN[20][42]MAIN[18][40]MAIN[19][42]MAIN[19][40]MAIN[18][42]HEX_S0[5]
Source
0000000off
0010001OMUX_S3
0010010OUT_FAN[1]
0010100HEX_S6[7]
0011000HEX_S6[5]
0100001HEX_E3[5]
0100010OMUX_E8
0100100HEX_W3[5]
0101000LV[18]
1000001LV[6]
1000010OUT_FAN[6]
1000100HEX_W6[3]
1001000HEX_E6[6]
virtex2 INT_GT_CLKPAD switchbox INT muxes HEX_S0[6]
BitsDestination
MAIN[21][48]MAIN[21][50]MAIN[20][51]MAIN[19][51]MAIN[18][49]MAIN[19][49]MAIN[18][51]HEX_S0[6]
Source
0000000off
0010001OMUX_SW5
0010010LV[12]
0010100HEX_W3[6]
0011000HEX_E3[6]
0100001OUT_FAN[0]
0100010OMUX_ES7
0100100HEX_S6[6]
0101000HEX_S6[8]
1000001LV[0]
1000010OUT_FAN[7]
1000100HEX_E6[7]
1001000HEX_W6[4]
virtex2 INT_GT_CLKPAD switchbox INT muxes HEX_S0[7]
BitsDestination
MAIN[20][57]MAIN[20][58]MAIN[20][56]MAIN[18][56]MAIN[19][58]MAIN[18][58]MAIN[19][56]HEX_S0[7]
Source
0000000off
0010001OMUX[11]
0010010LV[6]
0010100HEX_W6[5]
0011000HEX_E6[8]
0100001OUT_FAN[6]
0100010OMUX_WS1
0100100HEX_S6[9]
0101000HEX_S6[7]
1000001OMUX_SE3
1000010HEX_E3[7]
1000100HEX_W3[7]
1001000LV[18]
virtex2 INT_GT_CLKPAD switchbox INT muxes HEX_S0[8]
BitsDestination
MAIN[21][64]MAIN[20][67]MAIN[21][66]MAIN[19][67]MAIN[18][65]MAIN[18][67]MAIN[19][65]HEX_S0[8]
Source
0000000off
0010001OMUX_S5
0010010OUT_FAN[7]
0010100HEX_S6[8]
0011000HEX_S7[0]
0100001LV[12]
0100010OMUX_W14
0100100HEX_W3[8]
0101000HEX_E3[8]
1000001OUT_FAN[1]
1000010LV[0]
1000100HEX_E6[9]
1001000HEX_W6[6]
virtex2 INT_GT_CLKPAD switchbox INT muxes HEX_S0[9]
BitsDestination
MAIN[20][72]MAIN[20][73]MAIN[20][74]MAIN[18][72]MAIN[19][74]MAIN[18][74]MAIN[19][72]HEX_S0[9]
Source
0000000off
0010001OMUX[15]
0010010OMUX_SW5
0010100HEX_S7[1]
0011000HEX_S6[9]
0100001OMUX_ES7
0100010HEX_E3[9]
0100100HEX_W3[9]
0101000LV[18]
1000001OUT_FAN[0]
1000010LV[6]
1000100HEX_W6[7]
1001000HEX_E6_S[0]
virtex2 INT_GT_CLKPAD switchbox INT muxes HEX_N0[0]
BitsDestination
MAIN[20][1]MAIN[20][2]MAIN[20][0]MAIN[18][0]MAIN[19][2]MAIN[18][2]MAIN[19][0]HEX_N0[0]
Source
0000000off
0010001OMUX[0]
0010010LV[0]
0010100HEX_W6_N[8]
0011000HEX_E6[1]
0100001OUT_FAN[3]
0100010OMUX_EN8
0100100HEX_N6[0]
0101000HEX_N7[8]
1000001OMUX_N13
1000010HEX_E3[0]
1000100HEX_W3[0]
1001000LV[12]
virtex2 INT_GT_CLKPAD switchbox INT muxes HEX_N0[1]
BitsDestination
MAIN[21][8]MAIN[21][10]MAIN[20][11]MAIN[19][11]MAIN[18][9]MAIN[19][9]MAIN[18][11]HEX_N0[1]
Source
0000000off
0010001OMUX_N10
0010010LV[18]
0010100HEX_W3[1]
0011000HEX_E3[1]
0100001OUT_FAN[2]
0100010OMUX_NW10
0100100HEX_N7[9]
0101000HEX_N6[1]
1000001LV[6]
1000010OUT_FAN[4]
1000100HEX_E6[2]
1001000HEX_W6_N[9]
virtex2 INT_GT_CLKPAD switchbox INT muxes HEX_N0[2]
BitsDestination
MAIN[20][16]MAIN[20][17]MAIN[20][18]MAIN[18][16]MAIN[19][18]MAIN[18][18]MAIN[19][16]HEX_N0[2]
Source
0000000off
0010001OMUX[4]
0010010OMUX_NE12
0010100HEX_N6[2]
0011000HEX_N6[0]
0100001OMUX_W1
0100010HEX_E3[2]
0100100HEX_W3[2]
0101000LV[12]
1000001OUT_FAN[5]
1000010LV[0]
1000100HEX_W6[0]
1001000HEX_E6[3]
virtex2 INT_GT_CLKPAD switchbox INT muxes HEX_N0[3]
BitsDestination
MAIN[21][24]MAIN[21][26]MAIN[20][27]MAIN[19][27]MAIN[18][25]MAIN[19][25]MAIN[18][27]HEX_N0[3]
Source
0000000off
0010001OMUX_EN8
0010010LV[18]
0010100HEX_W3[3]
0011000HEX_E3[3]
0100001OUT_FAN[4]
0100010OMUX_WN14
0100100HEX_N6[1]
0101000HEX_N6[3]
1000001LV[6]
1000010OUT_FAN[3]
1000100HEX_E6[4]
1001000HEX_W6[1]
virtex2 INT_GT_CLKPAD switchbox INT muxes HEX_N0[4]
BitsDestination
MAIN[20][32]MAIN[20][33]MAIN[20][34]MAIN[18][32]MAIN[19][34]MAIN[19][32]MAIN[18][34]HEX_N0[4]
Source
0000000off
0010001OMUX_E7
0010010OUT_FAN[5]
0010100HEX_N6[4]
0011000HEX_N6[2]
0100001HEX_E3[4]
0100010OMUX_NW10
0100100HEX_W3[4]
0101000LV[12]
1000001LV[0]
1000010OUT_FAN[2]
1000100HEX_W6[2]
1001000HEX_E6[5]
virtex2 INT_GT_CLKPAD switchbox INT muxes HEX_N0[5]
BitsDestination
MAIN[21][40]MAIN[20][43]MAIN[21][42]MAIN[19][43]MAIN[18][41]MAIN[18][43]MAIN[19][41]HEX_N0[5]
Source
0000000off
0010001OMUX_N12
0010010OUT_FAN[1]
0010100HEX_N6[3]
0011000HEX_N6[5]
0100001LV[18]
0100010OMUX_NE12
0100100HEX_W3[5]
0101000HEX_E3[5]
1000001OUT_FAN[6]
1000010LV[6]
1000100HEX_E6[6]
1001000HEX_W6[3]
virtex2 INT_GT_CLKPAD switchbox INT muxes HEX_N0[6]
BitsDestination
MAIN[20][48]MAIN[20][49]MAIN[20][50]MAIN[18][48]MAIN[19][50]MAIN[19][48]MAIN[18][50]HEX_N0[6]
Source
0000000off
0010001OMUX[9]
0010010OUT_FAN[0]
0010100HEX_N6[6]
0011000HEX_N6[4]
0100001HEX_E3[6]
0100010OMUX_WN14
0100100HEX_W3[6]
0101000LV[12]
1000001LV[0]
1000010OUT_FAN[7]
1000100HEX_W6[4]
1001000HEX_E6[7]
virtex2 INT_GT_CLKPAD switchbox INT muxes HEX_N0[7]
BitsDestination
MAIN[20][59]MAIN[21][58]MAIN[21][56]MAIN[19][59]MAIN[18][57]MAIN[18][59]MAIN[19][57]HEX_N0[7]
Source
0000000off
0010001OMUX[11]
0010010LV[6]
0010100HEX_E6[8]
0011000HEX_W6[5]
0100001OMUX_W9
0100010OUT_FAN[6]
0100100HEX_N6[5]
0101000HEX_N6[7]
1000001LV[18]
1000010OMUX_N11
1000100HEX_W3[7]
1001000HEX_E3[7]
virtex2 INT_GT_CLKPAD switchbox INT muxes HEX_N0[8]
BitsDestination
MAIN[20][64]MAIN[20][66]MAIN[20][65]MAIN[18][64]MAIN[19][66]MAIN[18][66]MAIN[19][64]HEX_N0[8]
Source
0000000off
0010001OMUX[9]
0010010HEX_E3[8]
0010100HEX_W3[8]
0011000LV[12]
0100001OUT_FAN[7]
0100010OMUX_E13
0100100HEX_N6[8]
0101000HEX_N6[6]
1000001OUT_FAN[1]
1000010LV[0]
1000100HEX_W6[6]
1001000HEX_E6[9]
virtex2 INT_GT_CLKPAD switchbox INT muxes HEX_N0[9]
BitsDestination
MAIN[21][72]MAIN[20][75]MAIN[21][74]MAIN[19][75]MAIN[18][73]MAIN[18][75]MAIN[19][73]HEX_N0[9]
Source
0000000off
0010001OMUX[13]
0010010OMUX[15]
0010100HEX_N6[7]
0011000HEX_N6[9]
0100001LV[18]
0100010OMUX_N15
0100100HEX_W3[9]
0101000HEX_E3[9]
1000001OUT_FAN[0]
1000010LV[6]
1000100HEX_E6_S[0]
1001000HEX_W6[7]
virtex2 INT_GT_CLKPAD switchbox INT muxes LH[0]
BitsDestination
MAIN[21][47]MAIN[21][49]MAIN[21][51]LH[0]
Source
000off
001DBL_W1[5]
011OMUX_S4
101DBL_E1[6]
111OMUX[11]
virtex2 INT_GT_CLKPAD switchbox INT muxes LH[6]
BitsDestination
MAIN[21][31]MAIN[21][33]MAIN[21][29]LH[6]
Source
000off
001OMUX[4]
011OMUX_N15
101DBL_E1[4]
111DBL_W1[3]
virtex2 INT_GT_CLKPAD switchbox INT muxes LH[12]
BitsDestination
MAIN[21][41]MAIN[21][45]MAIN[21][43]LH[12]
Source
000off
001DBL_W1[5]
011OMUX_S4
101DBL_E1[6]
111OMUX[11]
virtex2 INT_GT_CLKPAD switchbox INT muxes LH[18]
BitsDestination
MAIN[21][39]MAIN[21][37]MAIN[21][35]LH[18]
Source
000off
001OMUX[4]
011OMUX_N15
101DBL_E1[4]
111DBL_W1[3]
virtex2 INT_GT_CLKPAD switchbox INT muxes LV[0]
BitsDestination
MAIN[21][7]MAIN[21][9]MAIN[21][19]MAIN[21][25]MAIN[21][21]MAIN[21][11]MAIN[21][5]LV[0]
Source
0000000off
0000011HEX_E1[1]
0000101OMUX_E2
0001001DBL_W1[1]
0010001HEX_E6[1]
0100001HEX_E4[1]
1000011OMUX[0]
1000101HEX_E2[1]
1001001HEX_E5[1]
1010001DBL_E1[2]
1100001HEX_E3[1]
virtex2 INT_GT_CLKPAD switchbox INT muxes LV[6]
BitsDestination
MAIN[21][73]MAIN[21][61]MAIN[21][55]MAIN[21][69]MAIN[21][71]MAIN[21][65]MAIN[21][75]LV[6]
Source
0000000off
0000011OMUX_W9
0000101DBL_W1[7]
0001001HEX_W5[7]
0010001HEX_W3[7]
0100001HEX_W4[7]
1000011OMUX[15]
1000101HEX_W2[7]
1001001DBL_E1[8]
1010001HEX_W0[7]
1100001HEX_W1[7]
virtex2 INT_GT_CLKPAD switchbox INT muxes LV[12]
BitsDestination
MAIN[21][13]MAIN[21][1]MAIN[21][27]MAIN[21][23]MAIN[21][17]MAIN[21][3]MAIN[21][15]LV[12]
Source
0000000off
0000011HEX_E1[1]
0000101OMUX_E2
0001001DBL_W1[1]
0010001HEX_E6[1]
0100001HEX_E4[1]
1000011OMUX[0]
1000101HEX_E2[1]
1001001HEX_E5[1]
1010001DBL_E1[2]
1100001HEX_E3[1]
virtex2 INT_GT_CLKPAD switchbox INT muxes LV[18]
BitsDestination
MAIN[21][67]MAIN[21][53]MAIN[21][57]MAIN[21][77]MAIN[21][59]MAIN[21][79]MAIN[21][63]LV[18]
Source
0000000off
0000011OMUX_W9
0000101DBL_W1[7]
0001001HEX_W5[7]
0010001HEX_W3[7]
0100001HEX_W4[7]
1000011OMUX[15]
1000101HEX_W2[7]
1001001DBL_E1[8]
1010001HEX_W0[7]
1100001HEX_W1[7]
virtex2 INT_GT_CLKPAD switchbox INT muxes IMUX_DCM_CLK[0]
BitsDestination
MAIN[5][38]MAIN[5][39]MAIN[5][37]MAIN[4][39]MAIN[5][40]MAIN[5][42]MAIN[4][42]MAIN[4][40]MAIN[4][46]MAIN[5][48]MAIN[4][44]MAIN[5][44]IMUX_DCM_CLK[0]
Source
000000000000PULLUP
000100000001GCLK[0]
000100000010GCLK[1]
000100000100DCM_CLKPAD[0]
000100001000DCM_CLKPAD[1]
000100010000HEX_N3[6]
000100100000HEX_N0[6]
000101000000HEX_S6[6]
000110000000HEX_S3[6]
001000000001GCLK[2]
001000000010GCLK[3]
001000000100DCM_CLKPAD[2]
001000001000DCM_CLKPAD[3]
001000010000HEX_S2[6]
001000100000HEX_N1[6]
001001000000HEX_N4[6]
001010000000HEX_S4[6]
010000000001GCLK[4]
010000000010GCLK[5]
010000000100DCM_CLKPAD[4]
010000001000DCM_CLKPAD[5]
010000010000HEX_S1[6]
010000100000HEX_S5[6]
010001000000HEX_N5[6]
010010000000HEX_N2[6]
100000000001GCLK[7]
100000000010GCLK[6]
100000000100DCM_CLKPAD[6]
100000001000DCM_CLKPAD[7]
100000010000DBL_W1[5]
100000100000DBL_W2[5]
100001000000DBL_E0[5]
100010000000DBL_E1[5]
virtex2 INT_GT_CLKPAD switchbox INT muxes IMUX_DCM_CLK[1]
BitsDestination
MAIN[5][46]MAIN[5][47]MAIN[5][49]MAIN[4][47]MAIN[4][37]MAIN[4][41]MAIN[5][43]MAIN[5][41]MAIN[4][45]MAIN[4][49]MAIN[5][45]MAIN[4][43]IMUX_DCM_CLK[1]
Source
000000000000PULLUP
000100000001GCLK[0]
000100000010GCLK[1]
000100000100DCM_CLKPAD[0]
000100001000DCM_CLKPAD[1]
000100010000HEX_N3[6]
000100100000HEX_N0[6]
000101000000HEX_S6[6]
000110000000HEX_S3[6]
001000000001GCLK[2]
001000000010GCLK[3]
001000000100DCM_CLKPAD[2]
001000001000DCM_CLKPAD[3]
001000010000HEX_S2[6]
001000100000HEX_N1[6]
001001000000HEX_N4[6]
001010000000HEX_S4[6]
010000000001GCLK[4]
010000000010GCLK[5]
010000000100DCM_CLKPAD[4]
010000001000DCM_CLKPAD[5]
010000010000HEX_S1[6]
010000100000HEX_S5[6]
010001000000HEX_N5[6]
010010000000HEX_N2[6]
100000000001GCLK[7]
100000000010GCLK[6]
100000000100DCM_CLKPAD[6]
100000001000DCM_CLKPAD[7]
100000010000DBL_W1[5]
100000100000DBL_W2[5]
100001000000DBL_E0[5]
100010000000DBL_E1[5]
virtex2 INT_GT_CLKPAD switchbox INT muxes IMUX_DCM_CLK[2]
BitsDestination
MAIN[5][53]MAIN[5][52]MAIN[5][50]MAIN[4][52]MAIN[4][62]MAIN[4][58]MAIN[5][56]MAIN[5][58]MAIN[4][54]MAIN[4][50]MAIN[5][54]MAIN[4][56]IMUX_DCM_CLK[2]
Source
000000000000PULLUP
000100000001GCLK[0]
000100000010GCLK[1]
000100000100DCM_CLKPAD[0]
000100001000DCM_CLKPAD[1]
000100010000HEX_S6[6]
000100100000HEX_N3[6]
000101000000HEX_N0[6]
000110000000HEX_S4[6]
001000000001GCLK[2]
001000000010GCLK[3]
001000000100DCM_CLKPAD[2]
001000001000DCM_CLKPAD[3]
001000010000HEX_N5[6]
001000100000HEX_S3[6]
001001000000HEX_S2[6]
001010000000HEX_N2[6]
010000000001GCLK[4]
010000000010GCLK[5]
010000000100DCM_CLKPAD[4]
010000001000DCM_CLKPAD[5]
010000010000HEX_S1[6]
010000100000HEX_S5[6]
010001000000HEX_N4[6]
010010000000HEX_N1[6]
100000000001GCLK[7]
100000000010GCLK[6]
100000000100DCM_CLKPAD[6]
100000001000DCM_CLKPAD[7]
100000010000DBL_W1[6]
100000100000DBL_W2[6]
100001000000DBL_E0[6]
100010000000DBL_E1[6]
virtex2 INT_GT_CLKPAD switchbox INT muxes IMUX_DCM_CLK[3]
BitsDestination
MAIN[5][61]MAIN[5][60]MAIN[5][62]MAIN[4][60]MAIN[5][59]MAIN[5][57]MAIN[4][57]MAIN[4][59]MAIN[4][53]MAIN[5][51]MAIN[4][55]MAIN[5][55]IMUX_DCM_CLK[3]
Source
000000000000PULLUP
000100000001GCLK[0]
000100000010GCLK[1]
000100000100DCM_CLKPAD[0]
000100001000DCM_CLKPAD[1]
000100010000HEX_S6[6]
000100100000HEX_N3[6]
000101000000HEX_N0[6]
000110000000HEX_S4[6]
001000000001GCLK[2]
001000000010GCLK[3]
001000000100DCM_CLKPAD[2]
001000001000DCM_CLKPAD[3]
001000010000HEX_N5[6]
001000100000HEX_S3[6]
001001000000HEX_S2[6]
001010000000HEX_N2[6]
010000000001GCLK[4]
010000000010GCLK[5]
010000000100DCM_CLKPAD[4]
010000001000DCM_CLKPAD[5]
010000010000HEX_S1[6]
010000100000HEX_S5[6]
010001000000HEX_N4[6]
010010000000HEX_N1[6]
100000000001GCLK[7]
100000000010GCLK[6]
100000000100DCM_CLKPAD[6]
100000001000DCM_CLKPAD[7]
100000010000DBL_W1[6]
100000100000DBL_W2[6]
100001000000DBL_E0[6]
100010000000DBL_E1[6]
virtex2 INT_GT_CLKPAD switchbox INT muxes IMUX_SR[0]
BitsDestination
MAIN[5][3]MAIN[4][3]MAIN[5][5]MAIN[4][5]MAIN[5][1]MAIN[5][2]MAIN[4][2]MAIN[5][0]IMUX_SR[0]
Source
00000000PULLUP
00010001DBL_W1[0]
00010010HEX_N1[0]
00010100HEX_N5[0]
00011000HEX_S4[0]
00100001DBL_W2[0]
00100010HEX_S5[0]
00100100HEX_S1[0]
00101000HEX_N3[0]
01000001HEX_N2[0]
01000010DBL_E0[0]
01000100HEX_S2[0]
01001000HEX_N0[0]
10000001HEX_S3[0]
10000010DBL_E1[0]
10000100HEX_N4[0]
10001000HEX_S6[0]
virtex2 INT_GT_CLKPAD switchbox INT muxes IMUX_SR[1]
BitsDestination
MAIN[4][12]MAIN[5][12]MAIN[5][14]MAIN[4][14]MAIN[5][16]MAIN[5][15]MAIN[5][17]MAIN[4][15]IMUX_SR[1]
Source
00000000PULLUP
00010001DBL_W1[1]
00010010HEX_N2[0]
00010100HEX_S2[0]
00011000HEX_N0[0]
00100001DBL_W2[1]
00100010HEX_S3[0]
00100100HEX_N4[0]
00101000HEX_S6[0]
01000001HEX_S5[0]
01000010DBL_E0[1]
01000100HEX_S1[0]
01001000HEX_N3[0]
10000001HEX_N1[0]
10000010DBL_E1[1]
10000100HEX_N5[0]
10001000HEX_S4[0]
virtex2 INT_GT_CLKPAD switchbox INT muxes IMUX_SR[2]
BitsDestination
MAIN[4][0]MAIN[4][4]MAIN[4][8]MAIN[5][4]MAIN[5][7]MAIN[5][8]MAIN[4][6]MAIN[5][6]IMUX_SR[2]
Source
00000000PULLUP
00010001DBL_W1[0]
00010010HEX_N1[0]
00010100HEX_N5[0]
00011000HEX_S4[0]
00100001DBL_W2[0]
00100010HEX_S5[0]
00100100HEX_S1[0]
00101000HEX_N3[0]
01000001HEX_N2[0]
01000010DBL_E0[0]
01000100HEX_S2[0]
01001000HEX_N0[0]
10000001HEX_S3[0]
10000010DBL_E1[0]
10000100HEX_N4[0]
10001000HEX_S6[0]
virtex2 INT_GT_CLKPAD switchbox INT muxes IMUX_SR[3]
BitsDestination
MAIN[5][13]MAIN[4][9]MAIN[4][17]MAIN[4][13]MAIN[5][10]MAIN[5][9]MAIN[5][11]MAIN[4][11]IMUX_SR[3]
Source
00000000PULLUP
00010001DBL_W1[1]
00010010HEX_N2[0]
00010100HEX_S2[0]
00011000HEX_N0[0]
00100001DBL_W2[1]
00100010HEX_S3[0]
00100100HEX_N4[0]
00101000HEX_S6[0]
01000001HEX_S5[0]
01000010DBL_E0[1]
01000100HEX_S1[0]
01001000HEX_N3[0]
10000001HEX_N1[0]
10000010DBL_E1[1]
10000100HEX_N5[0]
10001000HEX_S4[0]
virtex2 INT_GT_CLKPAD switchbox INT muxes IMUX_CE[2]
BitsDestination
MAIN[5][75]MAIN[4][71]MAIN[4][79]MAIN[4][75]MAIN[5][72]MAIN[5][71]MAIN[5][73]MAIN[4][73]IMUX_CE[2]
Source
00000000PULLUP
00010001DBL_W1[9]
00010010HEX_S1[9]
00010100HEX_S2[9]
00011000HEX_S5[9]
00100001DBL_W2[9]
00100010HEX_N5[9]
00100100HEX_N4[9]
00101000HEX_N1[9]
01000001HEX_S6[9]
01000010DBL_E0[9]
01000100HEX_S4[9]
01001000HEX_S3[9]
10000001HEX_N0[9]
10000010DBL_E1[9]
10000100HEX_N2[9]
10001000HEX_N3[9]
virtex2 INT_GT_CLKPAD switchbox INT muxes IMUX_CE[3]
BitsDestination
MAIN[4][74]MAIN[5][74]MAIN[5][76]MAIN[4][76]MAIN[5][78]MAIN[5][77]MAIN[5][79]MAIN[4][77]IMUX_CE[3]
Source
00000000PULLUP
00010001DBL_W1[9]
00010010HEX_S1[9]
00010100HEX_S2[9]
00011000HEX_S5[9]
00100001DBL_W2[9]
00100010HEX_N5[9]
00100100HEX_N4[9]
00101000HEX_N1[9]
01000001HEX_S6[9]
01000010DBL_E0[9]
01000100HEX_S4[9]
01001000HEX_S3[9]
10000001HEX_N0[9]
10000010DBL_E1[9]
10000100HEX_N2[9]
10001000HEX_N3[9]
virtex2 INT_GT_CLKPAD switchbox INT muxes IMUX_TI[0]
BitsDestination
MAIN[5][18]MAIN[5][19]MAIN[4][20]MAIN[5][20]MAIN[5][27]MAIN[4][25]MAIN[4][23]MAIN[5][23]MAIN[4][21]MAIN[5][21]IMUX_TI[0]
Source
0000000000PULLUP
0001000001OMUX[2]
0001000010OMUX[3]
0001000100HEX_N5[3]
0001001000HEX_N2[3]
0001010000HEX_S5[3]
0001100000HEX_S2[3]
0010000001OMUX[4]
0010000010HEX_N0[3]
0010000100DBL_W1[2]
0010001000DBL_W2[2]
0010010000HEX_N3[3]
0010100000HEX_S4[3]
0100000001OMUX[5]
0100000010DBL_W2[3]
0100000100DBL_W1[3]
0100001000DBL_E1[3]
0100010000DBL_E0[3]
0100100000HEX_S1[3]
1000000001DBL_E0[2]
1000000010HEX_S6[3]
1000000100DBL_E1[2]
1000001000HEX_S3[3]
1000010000HEX_N1[3]
1000100000HEX_N4[3]
virtex2 INT_GT_CLKPAD switchbox INT muxes IMUX_TI[1]
BitsDestination
MAIN[5][28]MAIN[5][25]MAIN[4][26]MAIN[5][26]MAIN[4][28]MAIN[4][24]MAIN[5][22]MAIN[5][24]MAIN[4][22]MAIN[4][18]IMUX_TI[1]
Source
0000000000PULLUP
0001000001OMUX[2]
0001000010OMUX[3]
0001000100HEX_N5[3]
0001001000HEX_N2[3]
0001010000HEX_S5[3]
0001100000HEX_S2[3]
0010000001OMUX[4]
0010000010HEX_N0[3]
0010000100DBL_W1[2]
0010001000DBL_W2[2]
0010010000HEX_N3[3]
0010100000HEX_S4[3]
0100000001OMUX[5]
0100000010DBL_W2[3]
0100000100DBL_W1[3]
0100001000DBL_E1[3]
0100010000DBL_E0[3]
0100100000HEX_S1[3]
1000000001DBL_E0[2]
1000000010HEX_S6[3]
1000000100DBL_E1[2]
1000001000HEX_S3[3]
1000010000HEX_N1[3]
1000100000HEX_N4[3]
virtex2 INT_GT_CLKPAD switchbox INT muxes IMUX_G0_FAN[0]
BitsDestination
MAIN[9][16]MAIN[9][19]MAIN[8][19]MAIN[8][16]MAIN[10][17]MAIN[10][19]MAIN[11][19]MAIN[11][17]MAIN[13][17]MAIN[12][19]MAIN[13][19]MAIN[12][17]IMUX_G0_FAN[0]
Source
000000000000off
000100000001OMUX_W1
000100000010OMUX_E2
000100000100OMUX_NW10
000100001000OMUX_N10
000100010000DBL_S1[0]
000100100000IMUX_G1_FAN[0]
000101000000DBL_N2[0]
000110000000IMUX_G2_FAN[0]
001000000001DBL_E0[1]
001000000010DBL_S0[0]
001000000100OMUX_EN8
001000001000DBL_W0[0]
001000010000DBL_N1[1]
001000100000DBL_S1[2]
001001000000DBL_W2[1]
001010000000DBL_S1[1]
010000000001DBL_E2[1]
010000000010DBL_S0[2]
010000000100DBL_E2[0]
010000001000DBL_E2[2]
010000010000DBL_W1[0]
010000100000DBL_E1[2]
010001000000DBL_E1[1]
010010000000DBL_N2[1]
100000000001DBL_S2[0]
100000000010DBL_S2[2]
100000000100DBL_N0[1]
100000001000DBL_S2[1]
100000010000DBL_E1[0]
100000100000DBL_W1[1]
100001000000DBL_W2[0]
100010000000DBL_N1[0]
virtex2 INT_GT_CLKPAD switchbox INT muxes IMUX_G0_FAN[1]
BitsDestination
MAIN[9][17]MAIN[9][18]MAIN[8][18]MAIN[8][17]MAIN[10][16]MAIN[10][18]MAIN[11][18]MAIN[11][16]MAIN[13][16]MAIN[12][18]MAIN[13][18]MAIN[12][16]IMUX_G0_FAN[1]
Source
000000000000off
000100000001OMUX_W1
000100000010OMUX_E2
000100000100OMUX_NW10
000100001000OMUX_N10
000100010000DBL_S1[0]
000100100000IMUX_G1_FAN[0]
000101000000DBL_N2[0]
000110000000IMUX_G2_FAN[0]
001000000001DBL_E0[1]
001000000010DBL_S0[0]
001000000100OMUX_EN8
001000001000DBL_W0[0]
001000010000DBL_N1[1]
001000100000DBL_S1[2]
001001000000DBL_W2[1]
001010000000DBL_S1[1]
010000000001DBL_E2[1]
010000000010DBL_S0[2]
010000000100DBL_E2[0]
010000001000DBL_E2[2]
010000010000DBL_W1[0]
010000100000DBL_E1[2]
010001000000DBL_E1[1]
010010000000DBL_N2[1]
100000000001DBL_S2[0]
100000000010DBL_S2[2]
100000000100DBL_N0[1]
100000001000DBL_S2[1]
100000010000DBL_E1[0]
100000100000DBL_W1[1]
100001000000DBL_W2[0]
100010000000DBL_N1[0]
virtex2 INT_GT_CLKPAD switchbox INT muxes IMUX_G0_DATA[0]
BitsDestination
MAIN[9][0]MAIN[9][3]MAIN[8][3]MAIN[8][0]MAIN[10][1]MAIN[10][3]MAIN[11][3]MAIN[11][1]MAIN[13][1]MAIN[12][3]MAIN[13][3]MAIN[12][1]IMUX_G0_DATA[0]
Source
000000000000PULLUP
000100000001OMUX_W1
000100000010OMUX_E2
000100000100OMUX_NW10
000100001000OMUX_N10
000100010000DBL_S1[0]
000100100000IMUX_G1_FAN[0]
000101000000DBL_N2[0]
000110000000IMUX_G2_FAN[0]
001000000001DBL_E0[1]
001000000010DBL_S0[0]
001000000100OMUX_EN8
001000001000DBL_W0[0]
001000010000DBL_N1[1]
001000100000DBL_S1[2]
001001000000DBL_W2[1]
001010000000DBL_S1[1]
010000000001DBL_E2[1]
010000000010DBL_S0[2]
010000000100DBL_E2[0]
010000001000DBL_E2[2]
010000010000DBL_W1[0]
010000100000DBL_E1[2]
010001000000DBL_E1[1]
010010000000DBL_N2[1]
100000000001DBL_S2[0]
100000000010DBL_S2[2]
100000000100DBL_N0[1]
100000001000DBL_S2[1]
100000010000DBL_E1[0]
100000100000DBL_W1[1]
100001000000DBL_W2[0]
100010000000DBL_N1[0]
virtex2 INT_GT_CLKPAD switchbox INT muxes IMUX_G0_DATA[1]
BitsDestination
MAIN[9][1]MAIN[9][2]MAIN[8][2]MAIN[8][1]MAIN[10][0]MAIN[10][2]MAIN[11][2]MAIN[11][0]MAIN[13][0]MAIN[12][2]MAIN[13][2]MAIN[12][0]IMUX_G0_DATA[1]
Source
000000000000PULLUP
000100000001OMUX_W1
000100000010OMUX_E2
000100000100OMUX_NW10
000100001000OMUX_N10
000100010000DBL_S1[0]
000100100000IMUX_G1_FAN[0]
000101000000DBL_N2[0]
000110000000IMUX_G2_FAN[0]
001000000001DBL_E0[1]
001000000010DBL_S0[0]
001000000100OMUX_EN8
001000001000DBL_W0[0]
001000010000DBL_N1[1]
001000100000DBL_S1[2]
001001000000DBL_W2[1]
001010000000DBL_S1[1]
010000000001DBL_E2[1]
010000000010DBL_S0[2]
010000000100DBL_E2[0]
010000001000DBL_E2[2]
010000010000DBL_W1[0]
010000100000DBL_E1[2]
010001000000DBL_E1[1]
010010000000DBL_N2[1]
100000000001DBL_S2[0]
100000000010DBL_S2[2]
100000000100DBL_N0[1]
100000001000DBL_S2[1]
100000010000DBL_E1[0]
100000100000DBL_W1[1]
100001000000DBL_W2[0]
100010000000DBL_N1[0]
virtex2 INT_GT_CLKPAD switchbox INT muxes IMUX_G0_DATA[2]
BitsDestination
MAIN[9][7]MAIN[9][4]MAIN[8][4]MAIN[8][7]MAIN[10][6]MAIN[10][4]MAIN[11][4]MAIN[11][6]MAIN[13][6]MAIN[12][4]MAIN[13][4]MAIN[12][6]IMUX_G0_DATA[2]
Source
000000000000PULLUP
000100000001OMUX_W1
000100000010OMUX_E2
000100000100OMUX_NW10
000100001000OMUX_N10
000100010000DBL_S1[0]
000100100000IMUX_G1_FAN[0]
000101000000DBL_N2[0]
000110000000IMUX_G2_FAN[0]
001000000001DBL_E0[1]
001000000010DBL_S0[0]
001000000100OMUX_EN8
001000001000DBL_W0[0]
001000010000DBL_N1[1]
001000100000DBL_S1[2]
001001000000DBL_W2[1]
001010000000DBL_S1[1]
010000000001DBL_E2[1]
010000000010DBL_S0[2]
010000000100DBL_E2[0]
010000001000DBL_E2[2]
010000010000DBL_W1[0]
010000100000DBL_E1[2]
010001000000DBL_E1[1]
010010000000DBL_N2[1]
100000000001DBL_S2[0]
100000000010DBL_S2[2]
100000000100DBL_N0[1]
100000001000DBL_S2[1]
100000010000DBL_E1[0]
100000100000DBL_W1[1]
100001000000DBL_W2[0]
100010000000DBL_N1[0]
virtex2 INT_GT_CLKPAD switchbox INT muxes IMUX_G0_DATA[3]
BitsDestination
MAIN[9][6]MAIN[9][5]MAIN[8][5]MAIN[8][6]MAIN[10][7]MAIN[10][5]MAIN[11][5]MAIN[11][7]MAIN[13][7]MAIN[12][5]MAIN[13][5]MAIN[12][7]IMUX_G0_DATA[3]
Source
000000000000PULLUP
000100000001OMUX_W1
000100000010OMUX_E2
000100000100OMUX_NW10
000100001000OMUX_N10
000100010000DBL_S1[0]
000100100000IMUX_G1_FAN[0]
000101000000DBL_N2[0]
000110000000IMUX_G2_FAN[0]
001000000001DBL_E0[1]
001000000010DBL_S0[0]
001000000100OMUX_EN8
001000001000DBL_W0[0]
001000010000DBL_N1[1]
001000100000DBL_S1[2]
001001000000DBL_W2[1]
001010000000DBL_S1[1]
010000000001DBL_E2[1]
010000000010DBL_S0[2]
010000000100DBL_E2[0]
010000001000DBL_E2[2]
010000010000DBL_W1[0]
010000100000DBL_E1[2]
010001000000DBL_E1[1]
010010000000DBL_N2[1]
100000000001DBL_S2[0]
100000000010DBL_S2[2]
100000000100DBL_N0[1]
100000001000DBL_S2[1]
100000010000DBL_E1[0]
100000100000DBL_W1[1]
100001000000DBL_W2[0]
100010000000DBL_N1[0]
virtex2 INT_GT_CLKPAD switchbox INT muxes IMUX_G0_DATA[4]
BitsDestination
MAIN[9][8]MAIN[9][11]MAIN[8][11]MAIN[8][8]MAIN[10][9]MAIN[10][11]MAIN[11][11]MAIN[11][9]MAIN[13][9]MAIN[12][11]MAIN[13][11]MAIN[12][9]IMUX_G0_DATA[4]
Source
000000000000PULLUP
000100000001OMUX_W1
000100000010OMUX_E2
000100000100OMUX_NW10
000100001000OMUX_N10
000100010000DBL_S1[0]
000100100000IMUX_G1_FAN[0]
000101000000DBL_N2[0]
000110000000IMUX_G2_FAN[0]
001000000001DBL_E0[1]
001000000010DBL_S0[0]
001000000100OMUX_EN8
001000001000DBL_W0[0]
001000010000DBL_N1[1]
001000100000DBL_S1[2]
001001000000DBL_W2[1]
001010000000DBL_S1[1]
010000000001DBL_E2[1]
010000000010DBL_S0[2]
010000000100DBL_E2[0]
010000001000DBL_E2[2]
010000010000DBL_W1[0]
010000100000DBL_E1[2]
010001000000DBL_E1[1]
010010000000DBL_N2[1]
100000000001DBL_S2[0]
100000000010DBL_S2[2]
100000000100DBL_N0[1]
100000001000DBL_S2[1]
100000010000DBL_E1[0]
100000100000DBL_W1[1]
100001000000DBL_W2[0]
100010000000DBL_N1[0]
virtex2 INT_GT_CLKPAD switchbox INT muxes IMUX_G0_DATA[5]
BitsDestination
MAIN[9][9]MAIN[9][10]MAIN[8][10]MAIN[8][9]MAIN[10][8]MAIN[10][10]MAIN[11][10]MAIN[11][8]MAIN[13][8]MAIN[12][10]MAIN[13][10]MAIN[12][8]IMUX_G0_DATA[5]
Source
000000000000PULLUP
000100000001OMUX_W1
000100000010OMUX_E2
000100000100OMUX_NW10
000100001000OMUX_N10
000100010000DBL_S1[0]
000100100000IMUX_G1_FAN[0]
000101000000DBL_N2[0]
000110000000IMUX_G2_FAN[0]
001000000001DBL_E0[1]
001000000010DBL_S0[0]
001000000100OMUX_EN8
001000001000DBL_W0[0]
001000010000DBL_N1[1]
001000100000DBL_S1[2]
001001000000DBL_W2[1]
001010000000DBL_S1[1]
010000000001DBL_E2[1]
010000000010DBL_S0[2]
010000000100DBL_E2[0]
010000001000DBL_E2[2]
010000010000DBL_W1[0]
010000100000DBL_E1[2]
010001000000DBL_E1[1]
010010000000DBL_N2[1]
100000000001DBL_S2[0]
100000000010DBL_S2[2]
100000000100DBL_N0[1]
100000001000DBL_S2[1]
100000010000DBL_E1[0]
100000100000DBL_W1[1]
100001000000DBL_W2[0]
100010000000DBL_N1[0]
virtex2 INT_GT_CLKPAD switchbox INT muxes IMUX_G0_DATA[6]
BitsDestination
MAIN[9][15]MAIN[9][12]MAIN[8][12]MAIN[8][15]MAIN[10][14]MAIN[10][12]MAIN[11][12]MAIN[11][14]MAIN[13][14]MAIN[12][12]MAIN[13][12]MAIN[12][14]IMUX_G0_DATA[6]
Source
000000000000PULLUP
000100000001OMUX_W1
000100000010OMUX_E2
000100000100OMUX_NW10
000100001000OMUX_N10
000100010000DBL_S1[0]
000100100000IMUX_G1_FAN[0]
000101000000DBL_N2[0]
000110000000IMUX_G2_FAN[0]
001000000001DBL_E0[1]
001000000010DBL_S0[0]
001000000100OMUX_EN8
001000001000DBL_W0[0]
001000010000DBL_N1[1]
001000100000DBL_S1[2]
001001000000DBL_W2[1]
001010000000DBL_S1[1]
010000000001DBL_E2[1]
010000000010DBL_S0[2]
010000000100DBL_E2[0]
010000001000DBL_E2[2]
010000010000DBL_W1[0]
010000100000DBL_E1[2]
010001000000DBL_E1[1]
010010000000DBL_N2[1]
100000000001DBL_S2[0]
100000000010DBL_S2[2]
100000000100DBL_N0[1]
100000001000DBL_S2[1]
100000010000DBL_E1[0]
100000100000DBL_W1[1]
100001000000DBL_W2[0]
100010000000DBL_N1[0]
virtex2 INT_GT_CLKPAD switchbox INT muxes IMUX_G0_DATA[7]
BitsDestination
MAIN[9][14]MAIN[9][13]MAIN[8][13]MAIN[8][14]MAIN[10][15]MAIN[10][13]MAIN[11][13]MAIN[11][15]MAIN[13][15]MAIN[12][13]MAIN[13][13]MAIN[12][15]IMUX_G0_DATA[7]
Source
000000000000PULLUP
000100000001OMUX_W1
000100000010OMUX_E2
000100000100OMUX_NW10
000100001000OMUX_N10
000100010000DBL_S1[0]
000100100000IMUX_G1_FAN[0]
000101000000DBL_N2[0]
000110000000IMUX_G2_FAN[0]
001000000001DBL_E0[1]
001000000010DBL_S0[0]
001000000100OMUX_EN8
001000001000DBL_W0[0]
001000010000DBL_N1[1]
001000100000DBL_S1[2]
001001000000DBL_W2[1]
001010000000DBL_S1[1]
010000000001DBL_E2[1]
010000000010DBL_S0[2]
010000000100DBL_E2[0]
010000001000DBL_E2[2]
010000010000DBL_W1[0]
010000100000DBL_E1[2]
010001000000DBL_E1[1]
010010000000DBL_N2[1]
100000000001DBL_S2[0]
100000000010DBL_S2[2]
100000000100DBL_N0[1]
100000001000DBL_S2[1]
100000010000DBL_E1[0]
100000100000DBL_W1[1]
100001000000DBL_W2[0]
100010000000DBL_N1[0]
virtex2 INT_GT_CLKPAD switchbox INT muxes IMUX_G1_FAN[0]
BitsDestination
MAIN[9][23]MAIN[9][20]MAIN[8][23]MAIN[8][20]MAIN[10][22]MAIN[10][20]MAIN[11][22]MAIN[11][20]MAIN[13][20]MAIN[13][22]MAIN[12][22]MAIN[12][20]IMUX_G1_FAN[0]
Source
000000000000off
000100000001OMUX_W6
000100000010DBL_S0[4]
000100000100DBL_W0[4]
000100001000DBL_E0[3]
000100010000DBL_W1[2]
000100100000DBL_N1[4]
000101000000DBL_W2[4]
000110000000DBL_N2[4]
001000000001OMUX_N12
001000000010OMUX_E7
001000000100OMUX_NE12
001000001000OMUX_WN14
001000010000IMUX_G3_FAN[1]
001000100000DBL_S1[3]
001001000000DBL_E1[4]
001010000000IMUX_G0_FAN[1]
010000000001DBL_E2[4]
010000000010DBL_E2[3]
010000000100DBL_W2[3]
010000001000DBL_W0[2]
010000010000DBL_N1[2]
010000100000DBL_W1[3]
010001000000DBL_W1[4]
010010000000DBL_N2[3]
100000000001DBL_N0[3]
100000000010DBL_S2[4]
100000000100DBL_S2[3]
100000001000DBL_W2[2]
100000010000DBL_S1[4]
100000100000DBL_E1[3]
100001000000DBL_N2[2]
100010000000DBL_N1[3]
virtex2 INT_GT_CLKPAD switchbox INT muxes IMUX_G1_FAN[1]
BitsDestination
MAIN[9][22]MAIN[9][21]MAIN[8][22]MAIN[8][21]MAIN[10][23]MAIN[10][21]MAIN[11][23]MAIN[11][21]MAIN[13][21]MAIN[13][23]MAIN[12][23]MAIN[12][21]IMUX_G1_FAN[1]
Source
000000000000off
000100000001OMUX_W6
000100000010DBL_S0[4]
000100000100DBL_W0[4]
000100001000DBL_E0[3]
000100010000DBL_W1[2]
000100100000DBL_N1[4]
000101000000DBL_W2[4]
000110000000DBL_N2[4]
001000000001OMUX_N12
001000000010OMUX_E7
001000000100OMUX_NE12
001000001000OMUX_WN14
001000010000IMUX_G3_FAN[1]
001000100000DBL_S1[3]
001001000000DBL_E1[4]
001010000000IMUX_G0_FAN[1]
010000000001DBL_E2[4]
010000000010DBL_E2[3]
010000000100DBL_W2[3]
010000001000DBL_W0[2]
010000010000DBL_N1[2]
010000100000DBL_W1[3]
010001000000DBL_W1[4]
010010000000DBL_N2[3]
100000000001DBL_N0[3]
100000000010DBL_S2[4]
100000000100DBL_S2[3]
100000001000DBL_W2[2]
100000010000DBL_S1[4]
100000100000DBL_E1[3]
100001000000DBL_N2[2]
100010000000DBL_N1[3]
virtex2 INT_GT_CLKPAD switchbox INT muxes IMUX_G1_DATA[0]
BitsDestination
MAIN[9][39]MAIN[9][36]MAIN[8][39]MAIN[8][36]MAIN[10][38]MAIN[10][36]MAIN[11][38]MAIN[11][36]MAIN[13][36]MAIN[13][38]MAIN[12][38]MAIN[12][36]IMUX_G1_DATA[0]
Source
000000000000PULLUP
000100000001OMUX_W6
000100000010DBL_S0[4]
000100000100DBL_W0[4]
000100001000DBL_E0[3]
000100010000DBL_W1[2]
000100100000DBL_N1[4]
000101000000DBL_W2[4]
000110000000DBL_N2[4]
001000000001OMUX_N12
001000000010OMUX_E7
001000000100OMUX_NE12
001000001000OMUX_WN14
001000010000IMUX_G3_FAN[1]
001000100000DBL_S1[3]
001001000000DBL_E1[4]
001010000000IMUX_G0_FAN[1]
010000000001DBL_E2[4]
010000000010DBL_E2[3]
010000000100DBL_W2[3]
010000001000DBL_W0[2]
010000010000DBL_N1[2]
010000100000DBL_W1[3]
010001000000DBL_W1[4]
010010000000DBL_N2[3]
100000000001DBL_N0[3]
100000000010DBL_S2[4]
100000000100DBL_S2[3]
100000001000DBL_W2[2]
100000010000DBL_S1[4]
100000100000DBL_E1[3]
100001000000DBL_N2[2]
100010000000DBL_N1[3]
virtex2 INT_GT_CLKPAD switchbox INT muxes IMUX_G1_DATA[1]
BitsDestination
MAIN[9][38]MAIN[9][37]MAIN[8][38]MAIN[8][37]MAIN[10][39]MAIN[10][37]MAIN[11][39]MAIN[11][37]MAIN[13][37]MAIN[13][39]MAIN[12][39]MAIN[12][37]IMUX_G1_DATA[1]
Source
000000000000PULLUP
000100000001OMUX_W6
000100000010DBL_S0[4]
000100000100DBL_W0[4]
000100001000DBL_E0[3]
000100010000DBL_W1[2]
000100100000DBL_N1[4]
000101000000DBL_W2[4]
000110000000DBL_N2[4]
001000000001OMUX_N12
001000000010OMUX_E7
001000000100OMUX_NE12
001000001000OMUX_WN14
001000010000IMUX_G3_FAN[1]
001000100000DBL_S1[3]
001001000000DBL_E1[4]
001010000000IMUX_G0_FAN[1]
010000000001DBL_E2[4]
010000000010DBL_E2[3]
010000000100DBL_W2[3]
010000001000DBL_W0[2]
010000010000DBL_N1[2]
010000100000DBL_W1[3]
010001000000DBL_W1[4]
010010000000DBL_N2[3]
100000000001DBL_N0[3]
100000000010DBL_S2[4]
100000000100DBL_S2[3]
100000001000DBL_W2[2]
100000010000DBL_S1[4]
100000100000DBL_E1[3]
100001000000DBL_N2[2]
100010000000DBL_N1[3]
virtex2 INT_GT_CLKPAD switchbox INT muxes IMUX_G1_DATA[2]
BitsDestination
MAIN[9][32]MAIN[9][35]MAIN[8][32]MAIN[8][35]MAIN[10][33]MAIN[10][35]MAIN[11][33]MAIN[11][35]MAIN[13][35]MAIN[13][33]MAIN[12][33]MAIN[12][35]IMUX_G1_DATA[2]
Source
000000000000PULLUP
000100000001OMUX_W6
000100000010DBL_S0[4]
000100000100DBL_W0[4]
000100001000DBL_E0[3]
000100010000DBL_W1[2]
000100100000DBL_N1[4]
000101000000DBL_W2[4]
000110000000DBL_N2[4]
001000000001OMUX_N12
001000000010OMUX_E7
001000000100OMUX_NE12
001000001000OMUX_WN14
001000010000IMUX_G3_FAN[1]
001000100000DBL_S1[3]
001001000000DBL_E1[4]
001010000000IMUX_G0_FAN[1]
010000000001DBL_E2[4]
010000000010DBL_E2[3]
010000000100DBL_W2[3]
010000001000DBL_W0[2]
010000010000DBL_N1[2]
010000100000DBL_W1[3]
010001000000DBL_W1[4]
010010000000DBL_N2[3]
100000000001DBL_N0[3]
100000000010DBL_S2[4]
100000000100DBL_S2[3]
100000001000DBL_W2[2]
100000010000DBL_S1[4]
100000100000DBL_E1[3]
100001000000DBL_N2[2]
100010000000DBL_N1[3]
virtex2 INT_GT_CLKPAD switchbox INT muxes IMUX_G1_DATA[3]
BitsDestination
MAIN[9][33]MAIN[9][34]MAIN[8][33]MAIN[8][34]MAIN[10][32]MAIN[10][34]MAIN[11][32]MAIN[11][34]MAIN[13][34]MAIN[13][32]MAIN[12][32]MAIN[12][34]IMUX_G1_DATA[3]
Source
000000000000PULLUP
000100000001OMUX_W6
000100000010DBL_S0[4]
000100000100DBL_W0[4]
000100001000DBL_E0[3]
000100010000DBL_W1[2]
000100100000DBL_N1[4]
000101000000DBL_W2[4]
000110000000DBL_N2[4]
001000000001OMUX_N12
001000000010OMUX_E7
001000000100OMUX_NE12
001000001000OMUX_WN14
001000010000IMUX_G3_FAN[1]
001000100000DBL_S1[3]
001001000000DBL_E1[4]
001010000000IMUX_G0_FAN[1]
010000000001DBL_E2[4]
010000000010DBL_E2[3]
010000000100DBL_W2[3]
010000001000DBL_W0[2]
010000010000DBL_N1[2]
010000100000DBL_W1[3]
010001000000DBL_W1[4]
010010000000DBL_N2[3]
100000000001DBL_N0[3]
100000000010DBL_S2[4]
100000000100DBL_S2[3]
100000001000DBL_W2[2]
100000010000DBL_S1[4]
100000100000DBL_E1[3]
100001000000DBL_N2[2]
100010000000DBL_N1[3]
virtex2 INT_GT_CLKPAD switchbox INT muxes IMUX_G1_DATA[4]
BitsDestination
MAIN[9][31]MAIN[9][28]MAIN[8][31]MAIN[8][28]MAIN[10][30]MAIN[10][28]MAIN[11][30]MAIN[11][28]MAIN[13][28]MAIN[13][30]MAIN[12][30]MAIN[12][28]IMUX_G1_DATA[4]
Source
000000000000PULLUP
000100000001OMUX_W6
000100000010DBL_S0[4]
000100000100DBL_W0[4]
000100001000DBL_E0[3]
000100010000DBL_W1[2]
000100100000DBL_N1[4]
000101000000DBL_W2[4]
000110000000DBL_N2[4]
001000000001OMUX_N12
001000000010OMUX_E7
001000000100OMUX_NE12
001000001000OMUX_WN14
001000010000IMUX_G3_FAN[1]
001000100000DBL_S1[3]
001001000000DBL_E1[4]
001010000000IMUX_G0_FAN[1]
010000000001DBL_E2[4]
010000000010DBL_E2[3]
010000000100DBL_W2[3]
010000001000DBL_W0[2]
010000010000DBL_N1[2]
010000100000DBL_W1[3]
010001000000DBL_W1[4]
010010000000DBL_N2[3]
100000000001DBL_N0[3]
100000000010DBL_S2[4]
100000000100DBL_S2[3]
100000001000DBL_W2[2]
100000010000DBL_S1[4]
100000100000DBL_E1[3]
100001000000DBL_N2[2]
100010000000DBL_N1[3]
virtex2 INT_GT_CLKPAD switchbox INT muxes IMUX_G1_DATA[5]
BitsDestination
MAIN[9][30]MAIN[9][29]MAIN[8][30]MAIN[8][29]MAIN[10][31]MAIN[10][29]MAIN[11][31]MAIN[11][29]MAIN[13][29]MAIN[13][31]MAIN[12][31]MAIN[12][29]IMUX_G1_DATA[5]
Source
000000000000PULLUP
000100000001OMUX_W6
000100000010DBL_S0[4]
000100000100DBL_W0[4]
000100001000DBL_E0[3]
000100010000DBL_W1[2]
000100100000DBL_N1[4]
000101000000DBL_W2[4]
000110000000DBL_N2[4]
001000000001OMUX_N12
001000000010OMUX_E7
001000000100OMUX_NE12
001000001000OMUX_WN14
001000010000IMUX_G3_FAN[1]
001000100000DBL_S1[3]
001001000000DBL_E1[4]
001010000000IMUX_G0_FAN[1]
010000000001DBL_E2[4]
010000000010DBL_E2[3]
010000000100DBL_W2[3]
010000001000DBL_W0[2]
010000010000DBL_N1[2]
010000100000DBL_W1[3]
010001000000DBL_W1[4]
010010000000DBL_N2[3]
100000000001DBL_N0[3]
100000000010DBL_S2[4]
100000000100DBL_S2[3]
100000001000DBL_W2[2]
100000010000DBL_S1[4]
100000100000DBL_E1[3]
100001000000DBL_N2[2]
100010000000DBL_N1[3]
virtex2 INT_GT_CLKPAD switchbox INT muxes IMUX_G1_DATA[6]
BitsDestination
MAIN[9][24]MAIN[9][27]MAIN[8][24]MAIN[8][27]MAIN[10][25]MAIN[10][27]MAIN[11][25]MAIN[11][27]MAIN[13][27]MAIN[13][25]MAIN[12][25]MAIN[12][27]IMUX_G1_DATA[6]
Source
000000000000PULLUP
000100000001OMUX_W6
000100000010DBL_S0[4]
000100000100DBL_W0[4]
000100001000DBL_E0[3]
000100010000DBL_W1[2]
000100100000DBL_N1[4]
000101000000DBL_W2[4]
000110000000DBL_N2[4]
001000000001OMUX_N12
001000000010OMUX_E7
001000000100OMUX_NE12
001000001000OMUX_WN14
001000010000IMUX_G3_FAN[1]
001000100000DBL_S1[3]
001001000000DBL_E1[4]
001010000000IMUX_G0_FAN[1]
010000000001DBL_E2[4]
010000000010DBL_E2[3]
010000000100DBL_W2[3]
010000001000DBL_W0[2]
010000010000DBL_N1[2]
010000100000DBL_W1[3]
010001000000DBL_W1[4]
010010000000DBL_N2[3]
100000000001DBL_N0[3]
100000000010DBL_S2[4]
100000000100DBL_S2[3]
100000001000DBL_W2[2]
100000010000DBL_S1[4]
100000100000DBL_E1[3]
100001000000DBL_N2[2]
100010000000DBL_N1[3]
virtex2 INT_GT_CLKPAD switchbox INT muxes IMUX_G1_DATA[7]
BitsDestination
MAIN[9][25]MAIN[9][26]MAIN[8][25]MAIN[8][26]MAIN[10][24]MAIN[10][26]MAIN[11][24]MAIN[11][26]MAIN[13][26]MAIN[13][24]MAIN[12][24]MAIN[12][26]IMUX_G1_DATA[7]
Source
000000000000PULLUP
000100000001OMUX_W6
000100000010DBL_S0[4]
000100000100DBL_W0[4]
000100001000DBL_E0[3]
000100010000DBL_W1[2]
000100100000DBL_N1[4]
000101000000DBL_W2[4]
000110000000DBL_N2[4]
001000000001OMUX_N12
001000000010OMUX_E7
001000000100OMUX_NE12
001000001000OMUX_WN14
001000010000IMUX_G3_FAN[1]
001000100000DBL_S1[3]
001001000000DBL_E1[4]
001010000000IMUX_G0_FAN[1]
010000000001DBL_E2[4]
010000000010DBL_E2[3]
010000000100DBL_W2[3]
010000001000DBL_W0[2]
010000010000DBL_N1[2]
010000100000DBL_W1[3]
010001000000DBL_W1[4]
010010000000DBL_N2[3]
100000000001DBL_N0[3]
100000000010DBL_S2[4]
100000000100DBL_S2[3]
100000001000DBL_W2[2]
100000010000DBL_S1[4]
100000100000DBL_E1[3]
100001000000DBL_N2[2]
100010000000DBL_N1[3]
virtex2 INT_GT_CLKPAD switchbox INT muxes IMUX_G2_FAN[0]
BitsDestination
MAIN[9][56]MAIN[9][59]MAIN[8][59]MAIN[8][56]MAIN[10][57]MAIN[10][59]MAIN[11][59]MAIN[11][57]MAIN[13][59]MAIN[13][57]MAIN[12][59]MAIN[12][57]IMUX_G2_FAN[0]
Source
000000000000off
000100000001OMUX_WS1
000100000010OMUX_E8
000100000100OMUX_SE3
000100001000OMUX_W9
000100010000DBL_S1[5]
000100100000IMUX_G3_FAN[0]
000101000000DBL_N2[5]
000110000000IMUX_G0_FAN[0]
001000000001DBL_E0[5]
001000000010OMUX_S3
001000000100DBL_W0[6]
001000001000DBL_S0[6]
001000010000DBL_N1[6]
001000100000DBL_S1[7]
001001000000DBL_W2[6]
001010000000DBL_S1[6]
010000000001DBL_E2[6]
010000000010DBL_E2[5]
010000000100DBL_E2[7]
010000001000DBL_E0[7]
010000010000DBL_W1[5]
010000100000DBL_E1[7]
010001000000DBL_E1[6]
010010000000DBL_N2[6]
100000000001DBL_S2[5]
100000000010DBL_N0[5]
100000000100DBL_S2[6]
100000001000DBL_S2[7]
100000010000DBL_E1[5]
100000100000DBL_W1[6]
100001000000DBL_W2[5]
100010000000DBL_N1[5]
virtex2 INT_GT_CLKPAD switchbox INT muxes IMUX_G2_FAN[1]
BitsDestination
MAIN[9][57]MAIN[9][58]MAIN[8][58]MAIN[8][57]MAIN[10][56]MAIN[10][58]MAIN[11][58]MAIN[11][56]MAIN[13][58]MAIN[13][56]MAIN[12][58]MAIN[12][56]IMUX_G2_FAN[1]
Source
000000000000off
000100000001OMUX_WS1
000100000010OMUX_E8
000100000100OMUX_SE3
000100001000OMUX_W9
000100010000DBL_S1[5]
000100100000IMUX_G3_FAN[0]
000101000000DBL_N2[5]
000110000000IMUX_G0_FAN[0]
001000000001DBL_E0[5]
001000000010OMUX_S3
001000000100DBL_W0[6]
001000001000DBL_S0[6]
001000010000DBL_N1[6]
001000100000DBL_S1[7]
001001000000DBL_W2[6]
001010000000DBL_S1[6]
010000000001DBL_E2[6]
010000000010DBL_E2[5]
010000000100DBL_E2[7]
010000001000DBL_E0[7]
010000010000DBL_W1[5]
010000100000DBL_E1[7]
010001000000DBL_E1[6]
010010000000DBL_N2[6]
100000000001DBL_S2[5]
100000000010DBL_N0[5]
100000000100DBL_S2[6]
100000001000DBL_S2[7]
100000010000DBL_E1[5]
100000100000DBL_W1[6]
100001000000DBL_W2[5]
100010000000DBL_N1[5]
virtex2 INT_GT_CLKPAD switchbox INT muxes IMUX_G2_DATA[0]
BitsDestination
MAIN[9][40]MAIN[9][43]MAIN[8][43]MAIN[8][40]MAIN[10][41]MAIN[10][43]MAIN[11][43]MAIN[11][41]MAIN[13][43]MAIN[13][41]MAIN[12][43]MAIN[12][41]IMUX_G2_DATA[0]
Source
000000000000PULLUP
000100000001OMUX_WS1
000100000010OMUX_E8
000100000100OMUX_SE3
000100001000OMUX_W9
000100010000DBL_S1[5]
000100100000IMUX_G3_FAN[0]
000101000000DBL_N2[5]
000110000000IMUX_G0_FAN[0]
001000000001DBL_E0[5]
001000000010OMUX_S3
001000000100DBL_W0[6]
001000001000DBL_S0[6]
001000010000DBL_N1[6]
001000100000DBL_S1[7]
001001000000DBL_W2[6]
001010000000DBL_S1[6]
010000000001DBL_E2[6]
010000000010DBL_E2[5]
010000000100DBL_E2[7]
010000001000DBL_E0[7]
010000010000DBL_W1[5]
010000100000DBL_E1[7]
010001000000DBL_E1[6]
010010000000DBL_N2[6]
100000000001DBL_S2[5]
100000000010DBL_N0[5]
100000000100DBL_S2[6]
100000001000DBL_S2[7]
100000010000DBL_E1[5]
100000100000DBL_W1[6]
100001000000DBL_W2[5]
100010000000DBL_N1[5]
virtex2 INT_GT_CLKPAD switchbox INT muxes IMUX_G2_DATA[1]
BitsDestination
MAIN[9][41]MAIN[9][42]MAIN[8][42]MAIN[8][41]MAIN[10][40]MAIN[10][42]MAIN[11][42]MAIN[11][40]MAIN[13][42]MAIN[13][40]MAIN[12][42]MAIN[12][40]IMUX_G2_DATA[1]
Source
000000000000PULLUP
000100000001OMUX_WS1
000100000010OMUX_E8
000100000100OMUX_SE3
000100001000OMUX_W9
000100010000DBL_S1[5]
000100100000IMUX_G3_FAN[0]
000101000000DBL_N2[5]
000110000000IMUX_G0_FAN[0]
001000000001DBL_E0[5]
001000000010OMUX_S3
001000000100DBL_W0[6]
001000001000DBL_S0[6]
001000010000DBL_N1[6]
001000100000DBL_S1[7]
001001000000DBL_W2[6]
001010000000DBL_S1[6]
010000000001DBL_E2[6]
010000000010DBL_E2[5]
010000000100DBL_E2[7]
010000001000DBL_E0[7]
010000010000DBL_W1[5]
010000100000DBL_E1[7]
010001000000DBL_E1[6]
010010000000DBL_N2[6]
100000000001DBL_S2[5]
100000000010DBL_N0[5]
100000000100DBL_S2[6]
100000001000DBL_S2[7]
100000010000DBL_E1[5]
100000100000DBL_W1[6]
100001000000DBL_W2[5]
100010000000DBL_N1[5]
virtex2 INT_GT_CLKPAD switchbox INT muxes IMUX_G2_DATA[2]
BitsDestination
MAIN[9][47]MAIN[9][44]MAIN[8][44]MAIN[8][47]MAIN[10][46]MAIN[10][44]MAIN[11][44]MAIN[11][46]MAIN[13][44]MAIN[13][46]MAIN[12][44]MAIN[12][46]IMUX_G2_DATA[2]
Source
000000000000PULLUP
000100000001OMUX_WS1
000100000010OMUX_E8
000100000100OMUX_SE3
000100001000OMUX_W9
000100010000DBL_S1[5]
000100100000IMUX_G3_FAN[0]
000101000000DBL_N2[5]
000110000000IMUX_G0_FAN[0]
001000000001DBL_E0[5]
001000000010OMUX_S3
001000000100DBL_W0[6]
001000001000DBL_S0[6]
001000010000DBL_N1[6]
001000100000DBL_S1[7]
001001000000DBL_W2[6]
001010000000DBL_S1[6]
010000000001DBL_E2[6]
010000000010DBL_E2[5]
010000000100DBL_E2[7]
010000001000DBL_E0[7]
010000010000DBL_W1[5]
010000100000DBL_E1[7]
010001000000DBL_E1[6]
010010000000DBL_N2[6]
100000000001DBL_S2[5]
100000000010DBL_N0[5]
100000000100DBL_S2[6]
100000001000DBL_S2[7]
100000010000DBL_E1[5]
100000100000DBL_W1[6]
100001000000DBL_W2[5]
100010000000DBL_N1[5]
virtex2 INT_GT_CLKPAD switchbox INT muxes IMUX_G2_DATA[3]
BitsDestination
MAIN[9][46]MAIN[9][45]MAIN[8][45]MAIN[8][46]MAIN[10][47]MAIN[10][45]MAIN[11][45]MAIN[11][47]MAIN[13][45]MAIN[13][47]MAIN[12][45]MAIN[12][47]IMUX_G2_DATA[3]
Source
000000000000PULLUP
000100000001OMUX_WS1
000100000010OMUX_E8
000100000100OMUX_SE3
000100001000OMUX_W9
000100010000DBL_S1[5]
000100100000IMUX_G3_FAN[0]
000101000000DBL_N2[5]
000110000000IMUX_G0_FAN[0]
001000000001DBL_E0[5]
001000000010OMUX_S3
001000000100DBL_W0[6]
001000001000DBL_S0[6]
001000010000DBL_N1[6]
001000100000DBL_S1[7]
001001000000DBL_W2[6]
001010000000DBL_S1[6]
010000000001DBL_E2[6]
010000000010DBL_E2[5]
010000000100DBL_E2[7]
010000001000DBL_E0[7]
010000010000DBL_W1[5]
010000100000DBL_E1[7]
010001000000DBL_E1[6]
010010000000DBL_N2[6]
100000000001DBL_S2[5]
100000000010DBL_N0[5]
100000000100DBL_S2[6]
100000001000DBL_S2[7]
100000010000DBL_E1[5]
100000100000DBL_W1[6]
100001000000DBL_W2[5]
100010000000DBL_N1[5]
virtex2 INT_GT_CLKPAD switchbox INT muxes IMUX_G2_DATA[4]
BitsDestination
MAIN[9][48]MAIN[9][51]MAIN[8][51]MAIN[8][48]MAIN[10][49]MAIN[10][51]MAIN[11][51]MAIN[11][49]MAIN[13][51]MAIN[13][49]MAIN[12][51]MAIN[12][49]IMUX_G2_DATA[4]
Source
000000000000PULLUP
000100000001OMUX_WS1
000100000010OMUX_E8
000100000100OMUX_SE3
000100001000OMUX_W9
000100010000DBL_S1[5]
000100100000IMUX_G3_FAN[0]
000101000000DBL_N2[5]
000110000000IMUX_G0_FAN[0]
001000000001DBL_E0[5]
001000000010OMUX_S3
001000000100DBL_W0[6]
001000001000DBL_S0[6]
001000010000DBL_N1[6]
001000100000DBL_S1[7]
001001000000DBL_W2[6]
001010000000DBL_S1[6]
010000000001DBL_E2[6]
010000000010DBL_E2[5]
010000000100DBL_E2[7]
010000001000DBL_E0[7]
010000010000DBL_W1[5]
010000100000DBL_E1[7]
010001000000DBL_E1[6]
010010000000DBL_N2[6]
100000000001DBL_S2[5]
100000000010DBL_N0[5]
100000000100DBL_S2[6]
100000001000DBL_S2[7]
100000010000DBL_E1[5]
100000100000DBL_W1[6]
100001000000DBL_W2[5]
100010000000DBL_N1[5]
virtex2 INT_GT_CLKPAD switchbox INT muxes IMUX_G2_DATA[5]
BitsDestination
MAIN[9][49]MAIN[9][50]MAIN[8][50]MAIN[8][49]MAIN[10][48]MAIN[10][50]MAIN[11][50]MAIN[11][48]MAIN[13][50]MAIN[13][48]MAIN[12][50]MAIN[12][48]IMUX_G2_DATA[5]
Source
000000000000PULLUP
000100000001OMUX_WS1
000100000010OMUX_E8
000100000100OMUX_SE3
000100001000OMUX_W9
000100010000DBL_S1[5]
000100100000IMUX_G3_FAN[0]
000101000000DBL_N2[5]
000110000000IMUX_G0_FAN[0]
001000000001DBL_E0[5]
001000000010OMUX_S3
001000000100DBL_W0[6]
001000001000DBL_S0[6]
001000010000DBL_N1[6]
001000100000DBL_S1[7]
001001000000DBL_W2[6]
001010000000DBL_S1[6]
010000000001DBL_E2[6]
010000000010DBL_E2[5]
010000000100DBL_E2[7]
010000001000DBL_E0[7]
010000010000DBL_W1[5]
010000100000DBL_E1[7]
010001000000DBL_E1[6]
010010000000DBL_N2[6]
100000000001DBL_S2[5]
100000000010DBL_N0[5]
100000000100DBL_S2[6]
100000001000DBL_S2[7]
100000010000DBL_E1[5]
100000100000DBL_W1[6]
100001000000DBL_W2[5]
100010000000DBL_N1[5]
virtex2 INT_GT_CLKPAD switchbox INT muxes IMUX_G2_DATA[6]
BitsDestination
MAIN[9][55]MAIN[9][52]MAIN[8][52]MAIN[8][55]MAIN[10][54]MAIN[10][52]MAIN[11][52]MAIN[11][54]MAIN[13][52]MAIN[13][54]MAIN[12][52]MAIN[12][54]IMUX_G2_DATA[6]
Source
000000000000PULLUP
000100000001OMUX_WS1
000100000010OMUX_E8
000100000100OMUX_SE3
000100001000OMUX_W9
000100010000DBL_S1[5]
000100100000IMUX_G3_FAN[0]
000101000000DBL_N2[5]
000110000000IMUX_G0_FAN[0]
001000000001DBL_E0[5]
001000000010OMUX_S3
001000000100DBL_W0[6]
001000001000DBL_S0[6]
001000010000DBL_N1[6]
001000100000DBL_S1[7]
001001000000DBL_W2[6]
001010000000DBL_S1[6]
010000000001DBL_E2[6]
010000000010DBL_E2[5]
010000000100DBL_E2[7]
010000001000DBL_E0[7]
010000010000DBL_W1[5]
010000100000DBL_E1[7]
010001000000DBL_E1[6]
010010000000DBL_N2[6]
100000000001DBL_S2[5]
100000000010DBL_N0[5]
100000000100DBL_S2[6]
100000001000DBL_S2[7]
100000010000DBL_E1[5]
100000100000DBL_W1[6]
100001000000DBL_W2[5]
100010000000DBL_N1[5]
virtex2 INT_GT_CLKPAD switchbox INT muxes IMUX_G2_DATA[7]
BitsDestination
MAIN[9][54]MAIN[9][53]MAIN[8][53]MAIN[8][54]MAIN[10][55]MAIN[10][53]MAIN[11][53]MAIN[11][55]MAIN[13][53]MAIN[13][55]MAIN[12][53]MAIN[12][55]IMUX_G2_DATA[7]
Source
000000000000PULLUP
000100000001OMUX_WS1
000100000010OMUX_E8
000100000100OMUX_SE3
000100001000OMUX_W9
000100010000DBL_S1[5]
000100100000IMUX_G3_FAN[0]
000101000000DBL_N2[5]
000110000000IMUX_G0_FAN[0]
001000000001DBL_E0[5]
001000000010OMUX_S3
001000000100DBL_W0[6]
001000001000DBL_S0[6]
001000010000DBL_N1[6]
001000100000DBL_S1[7]
001001000000DBL_W2[6]
001010000000DBL_S1[6]
010000000001DBL_E2[6]
010000000010DBL_E2[5]
010000000100DBL_E2[7]
010000001000DBL_E0[7]
010000010000DBL_W1[5]
010000100000DBL_E1[7]
010001000000DBL_E1[6]
010010000000DBL_N2[6]
100000000001DBL_S2[5]
100000000010DBL_N0[5]
100000000100DBL_S2[6]
100000001000DBL_S2[7]
100000010000DBL_E1[5]
100000100000DBL_W1[6]
100001000000DBL_W2[5]
100010000000DBL_N1[5]
virtex2 INT_GT_CLKPAD switchbox INT muxes IMUX_G3_FAN[0]
BitsDestination
MAIN[9][63]MAIN[9][60]MAIN[8][60]MAIN[8][63]MAIN[10][62]MAIN[10][60]MAIN[11][62]MAIN[11][60]MAIN[13][62]MAIN[12][62]MAIN[12][60]MAIN[13][60]IMUX_G3_FAN[0]
Source
000000000000off
000100000001OMUX_S5
000100000010OMUX_W14
000100000100OMUX_ES7
000100001000OMUX_E13
000100010000IMUX_G1_FAN[1]
000100100000DBL_S1[8]
000101000000DBL_E1[9]
000110000000IMUX_G2_FAN[1]
001000000001DBL_W0[8]
001000000010OMUX_SW5
001000000100DBL_S0[8]
001000001000DBL_E0[9]
001000010000DBL_W1[7]
001000100000DBL_N1[9]
001001000000DBL_W2[9]
001010000000DBL_N2[9]
010000000001DBL_N0[7]
010000000010DBL_E2[9]
010000000100DBL_E2[8]
010000001000DBL_W2[8]
010000010000DBL_N1[7]
010000100000DBL_W1[8]
010001000000DBL_W1[9]
010010000000DBL_N2[8]
100000000001DBL_W2[7]
100000000010DBL_N0[9]
100000000100DBL_S2[9]
100000001000DBL_S2[8]
100000010000DBL_S1[9]
100000100000DBL_E1[8]
100001000000DBL_N2[7]
100010000000DBL_N1[8]
virtex2 INT_GT_CLKPAD switchbox INT muxes IMUX_G3_FAN[1]
BitsDestination
MAIN[9][62]MAIN[9][61]MAIN[8][61]MAIN[8][62]MAIN[10][63]MAIN[10][61]MAIN[11][63]MAIN[11][61]MAIN[13][63]MAIN[12][63]MAIN[12][61]MAIN[13][61]IMUX_G3_FAN[1]
Source
000000000000off
000100000001OMUX_S5
000100000010OMUX_W14
000100000100OMUX_ES7
000100001000OMUX_E13
000100010000IMUX_G1_FAN[1]
000100100000DBL_S1[8]
000101000000DBL_E1[9]
000110000000IMUX_G2_FAN[1]
001000000001DBL_W0[8]
001000000010OMUX_SW5
001000000100DBL_S0[8]
001000001000DBL_E0[9]
001000010000DBL_W1[7]
001000100000DBL_N1[9]
001001000000DBL_W2[9]
001010000000DBL_N2[9]
010000000001DBL_N0[7]
010000000010DBL_E2[9]
010000000100DBL_E2[8]
010000001000DBL_W2[8]
010000010000DBL_N1[7]
010000100000DBL_W1[8]
010001000000DBL_W1[9]
010010000000DBL_N2[8]
100000000001DBL_W2[7]
100000000010DBL_N0[9]
100000000100DBL_S2[9]
100000001000DBL_S2[8]
100000010000DBL_S1[9]
100000100000DBL_E1[8]
100001000000DBL_N2[7]
100010000000DBL_N1[8]
virtex2 INT_GT_CLKPAD switchbox INT muxes IMUX_G3_DATA[0]
BitsDestination
MAIN[9][79]MAIN[9][76]MAIN[8][76]MAIN[8][79]MAIN[10][78]MAIN[10][76]MAIN[11][78]MAIN[11][76]MAIN[13][78]MAIN[12][78]MAIN[12][76]MAIN[13][76]IMUX_G3_DATA[0]
Source
000000000000PULLUP
000100000001OMUX_S5
000100000010OMUX_W14
000100000100OMUX_ES7
000100001000OMUX_E13
000100010000IMUX_G1_FAN[1]
000100100000DBL_S1[8]
000101000000DBL_E1[9]
000110000000IMUX_G2_FAN[1]
001000000001DBL_W0[8]
001000000010OMUX_SW5
001000000100DBL_S0[8]
001000001000DBL_E0[9]
001000010000DBL_W1[7]
001000100000DBL_N1[9]
001001000000DBL_W2[9]
001010000000DBL_N2[9]
010000000001DBL_N0[7]
010000000010DBL_E2[9]
010000000100DBL_E2[8]
010000001000DBL_W2[8]
010000010000DBL_N1[7]
010000100000DBL_W1[8]
010001000000DBL_W1[9]
010010000000DBL_N2[8]
100000000001DBL_W2[7]
100000000010DBL_N0[9]
100000000100DBL_S2[9]
100000001000DBL_S2[8]
100000010000DBL_S1[9]
100000100000DBL_E1[8]
100001000000DBL_N2[7]
100010000000DBL_N1[8]
virtex2 INT_GT_CLKPAD switchbox INT muxes IMUX_G3_DATA[1]
BitsDestination
MAIN[9][78]MAIN[9][77]MAIN[8][77]MAIN[8][78]MAIN[10][79]MAIN[10][77]MAIN[11][79]MAIN[11][77]MAIN[13][79]MAIN[12][79]MAIN[12][77]MAIN[13][77]IMUX_G3_DATA[1]
Source
000000000000PULLUP
000100000001OMUX_S5
000100000010OMUX_W14
000100000100OMUX_ES7
000100001000OMUX_E13
000100010000IMUX_G1_FAN[1]
000100100000DBL_S1[8]
000101000000DBL_E1[9]
000110000000IMUX_G2_FAN[1]
001000000001DBL_W0[8]
001000000010OMUX_SW5
001000000100DBL_S0[8]
001000001000DBL_E0[9]
001000010000DBL_W1[7]
001000100000DBL_N1[9]
001001000000DBL_W2[9]
001010000000DBL_N2[9]
010000000001DBL_N0[7]
010000000010DBL_E2[9]
010000000100DBL_E2[8]
010000001000DBL_W2[8]
010000010000DBL_N1[7]
010000100000DBL_W1[8]
010001000000DBL_W1[9]
010010000000DBL_N2[8]
100000000001DBL_W2[7]
100000000010DBL_N0[9]
100000000100DBL_S2[9]
100000001000DBL_S2[8]
100000010000DBL_S1[9]
100000100000DBL_E1[8]
100001000000DBL_N2[7]
100010000000DBL_N1[8]
virtex2 INT_GT_CLKPAD switchbox INT muxes IMUX_G3_DATA[2]
BitsDestination
MAIN[9][72]MAIN[9][75]MAIN[8][75]MAIN[8][72]MAIN[10][73]MAIN[10][75]MAIN[11][73]MAIN[11][75]MAIN[13][73]MAIN[12][73]MAIN[12][75]MAIN[13][75]IMUX_G3_DATA[2]
Source
000000000000PULLUP
000100000001OMUX_S5
000100000010OMUX_W14
000100000100OMUX_ES7
000100001000OMUX_E13
000100010000IMUX_G1_FAN[1]
000100100000DBL_S1[8]
000101000000DBL_E1[9]
000110000000IMUX_G2_FAN[1]
001000000001DBL_W0[8]
001000000010OMUX_SW5
001000000100DBL_S0[8]
001000001000DBL_E0[9]
001000010000DBL_W1[7]
001000100000DBL_N1[9]
001001000000DBL_W2[9]
001010000000DBL_N2[9]
010000000001DBL_N0[7]
010000000010DBL_E2[9]
010000000100DBL_E2[8]
010000001000DBL_W2[8]
010000010000DBL_N1[7]
010000100000DBL_W1[8]
010001000000DBL_W1[9]
010010000000DBL_N2[8]
100000000001DBL_W2[7]
100000000010DBL_N0[9]
100000000100DBL_S2[9]
100000001000DBL_S2[8]
100000010000DBL_S1[9]
100000100000DBL_E1[8]
100001000000DBL_N2[7]
100010000000DBL_N1[8]
virtex2 INT_GT_CLKPAD switchbox INT muxes IMUX_G3_DATA[3]
BitsDestination
MAIN[9][73]MAIN[9][74]MAIN[8][74]MAIN[8][73]MAIN[10][72]MAIN[10][74]MAIN[11][72]MAIN[11][74]MAIN[13][72]MAIN[12][72]MAIN[12][74]MAIN[13][74]IMUX_G3_DATA[3]
Source
000000000000PULLUP
000100000001OMUX_S5
000100000010OMUX_W14
000100000100OMUX_ES7
000100001000OMUX_E13
000100010000IMUX_G1_FAN[1]
000100100000DBL_S1[8]
000101000000DBL_E1[9]
000110000000IMUX_G2_FAN[1]
001000000001DBL_W0[8]
001000000010OMUX_SW5
001000000100DBL_S0[8]
001000001000DBL_E0[9]
001000010000DBL_W1[7]
001000100000DBL_N1[9]
001001000000DBL_W2[9]
001010000000DBL_N2[9]
010000000001DBL_N0[7]
010000000010DBL_E2[9]
010000000100DBL_E2[8]
010000001000DBL_W2[8]
010000010000DBL_N1[7]
010000100000DBL_W1[8]
010001000000DBL_W1[9]
010010000000DBL_N2[8]
100000000001DBL_W2[7]
100000000010DBL_N0[9]
100000000100DBL_S2[9]
100000001000DBL_S2[8]
100000010000DBL_S1[9]
100000100000DBL_E1[8]
100001000000DBL_N2[7]
100010000000DBL_N1[8]
virtex2 INT_GT_CLKPAD switchbox INT muxes IMUX_G3_DATA[4]
BitsDestination
MAIN[9][71]MAIN[9][68]MAIN[8][68]MAIN[8][71]MAIN[10][70]MAIN[10][68]MAIN[11][70]MAIN[11][68]MAIN[13][70]MAIN[12][70]MAIN[12][68]MAIN[13][68]IMUX_G3_DATA[4]
Source
000000000000PULLUP
000100000001OMUX_S5
000100000010OMUX_W14
000100000100OMUX_ES7
000100001000OMUX_E13
000100010000IMUX_G1_FAN[1]
000100100000DBL_S1[8]
000101000000DBL_E1[9]
000110000000IMUX_G2_FAN[1]
001000000001DBL_W0[8]
001000000010OMUX_SW5
001000000100DBL_S0[8]
001000001000DBL_E0[9]
001000010000DBL_W1[7]
001000100000DBL_N1[9]
001001000000DBL_W2[9]
001010000000DBL_N2[9]
010000000001DBL_N0[7]
010000000010DBL_E2[9]
010000000100DBL_E2[8]
010000001000DBL_W2[8]
010000010000DBL_N1[7]
010000100000DBL_W1[8]
010001000000DBL_W1[9]
010010000000DBL_N2[8]
100000000001DBL_W2[7]
100000000010DBL_N0[9]
100000000100DBL_S2[9]
100000001000DBL_S2[8]
100000010000DBL_S1[9]
100000100000DBL_E1[8]
100001000000DBL_N2[7]
100010000000DBL_N1[8]
virtex2 INT_GT_CLKPAD switchbox INT muxes IMUX_G3_DATA[5]
BitsDestination
MAIN[9][70]MAIN[9][69]MAIN[8][69]MAIN[8][70]MAIN[10][71]MAIN[10][69]MAIN[11][71]MAIN[11][69]MAIN[13][71]MAIN[12][71]MAIN[12][69]MAIN[13][69]IMUX_G3_DATA[5]
Source
000000000000PULLUP
000100000001OMUX_S5
000100000010OMUX_W14
000100000100OMUX_ES7
000100001000OMUX_E13
000100010000IMUX_G1_FAN[1]
000100100000DBL_S1[8]
000101000000DBL_E1[9]
000110000000IMUX_G2_FAN[1]
001000000001DBL_W0[8]
001000000010OMUX_SW5
001000000100DBL_S0[8]
001000001000DBL_E0[9]
001000010000DBL_W1[7]
001000100000DBL_N1[9]
001001000000DBL_W2[9]
001010000000DBL_N2[9]
010000000001DBL_N0[7]
010000000010DBL_E2[9]
010000000100DBL_E2[8]
010000001000DBL_W2[8]
010000010000DBL_N1[7]
010000100000DBL_W1[8]
010001000000DBL_W1[9]
010010000000DBL_N2[8]
100000000001DBL_W2[7]
100000000010DBL_N0[9]
100000000100DBL_S2[9]
100000001000DBL_S2[8]
100000010000DBL_S1[9]
100000100000DBL_E1[8]
100001000000DBL_N2[7]
100010000000DBL_N1[8]
virtex2 INT_GT_CLKPAD switchbox INT muxes IMUX_G3_DATA[6]
BitsDestination
MAIN[9][64]MAIN[9][67]MAIN[8][67]MAIN[8][64]MAIN[10][65]MAIN[10][67]MAIN[11][65]MAIN[11][67]MAIN[13][65]MAIN[12][65]MAIN[12][67]MAIN[13][67]IMUX_G3_DATA[6]
Source
000000000000PULLUP
000100000001OMUX_S5
000100000010OMUX_W14
000100000100OMUX_ES7
000100001000OMUX_E13
000100010000IMUX_G1_FAN[1]
000100100000DBL_S1[8]
000101000000DBL_E1[9]
000110000000IMUX_G2_FAN[1]
001000000001DBL_W0[8]
001000000010OMUX_SW5
001000000100DBL_S0[8]
001000001000DBL_E0[9]
001000010000DBL_W1[7]
001000100000DBL_N1[9]
001001000000DBL_W2[9]
001010000000DBL_N2[9]
010000000001DBL_N0[7]
010000000010DBL_E2[9]
010000000100DBL_E2[8]
010000001000DBL_W2[8]
010000010000DBL_N1[7]
010000100000DBL_W1[8]
010001000000DBL_W1[9]
010010000000DBL_N2[8]
100000000001DBL_W2[7]
100000000010DBL_N0[9]
100000000100DBL_S2[9]
100000001000DBL_S2[8]
100000010000DBL_S1[9]
100000100000DBL_E1[8]
100001000000DBL_N2[7]
100010000000DBL_N1[8]
virtex2 INT_GT_CLKPAD switchbox INT muxes IMUX_G3_DATA[7]
BitsDestination
MAIN[9][65]MAIN[9][66]MAIN[8][66]MAIN[8][65]MAIN[10][64]MAIN[10][66]MAIN[11][64]MAIN[11][66]MAIN[13][64]MAIN[12][64]MAIN[12][66]MAIN[13][66]IMUX_G3_DATA[7]
Source
000000000000PULLUP
000100000001OMUX_S5
000100000010OMUX_W14
000100000100OMUX_ES7
000100001000OMUX_E13
000100010000IMUX_G1_FAN[1]
000100100000DBL_S1[8]
000101000000DBL_E1[9]
000110000000IMUX_G2_FAN[1]
001000000001DBL_W0[8]
001000000010OMUX_SW5
001000000100DBL_S0[8]
001000001000DBL_E0[9]
001000010000DBL_W1[7]
001000100000DBL_N1[9]
001001000000DBL_W2[9]
001010000000DBL_N2[9]
010000000001DBL_N0[7]
010000000010DBL_E2[9]
010000000100DBL_E2[8]
010000001000DBL_W2[8]
010000010000DBL_N1[7]
010000100000DBL_W1[8]
010001000000DBL_W1[9]
010010000000DBL_N2[8]
100000000001DBL_W2[7]
100000000010DBL_N0[9]
100000000100DBL_S2[9]
100000001000DBL_S2[8]
100000010000DBL_S1[9]
100000100000DBL_E1[8]
100001000000DBL_N2[7]
100010000000DBL_N1[8]

Bitstream

virtex2 INT_GT_CLKPAD rect MAIN
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21
B79 - - - - INT: mux IMUX_CE[2] bit 5 INT: mux IMUX_CE[3] bit 1 INT: mux OMUX[14] bit 0 INT: mux OMUX[15] bit 6 INT: mux IMUX_G3_DATA[0] bit 8 INT: mux IMUX_G3_DATA[0] bit 11 INT: mux IMUX_G3_DATA[1] bit 7 INT: mux IMUX_G3_DATA[1] bit 5 INT: mux IMUX_G3_DATA[1] bit 2 INT: mux IMUX_G3_DATA[1] bit 3 INT: mux DBL_E0[9] bit 0 INT: mux DBL_W0[9] bit 7 INT: mux DBL_E0[9] bit 5 INT: mux DBL_E0[9] bit 7 INT: mux HEX_W0[9] bit 0 INT: mux HEX_W0[9] bit 3 INT: mux HEX_W0[9] bit 4 INT: mux LV[18] bit 1
B78 - - - - INT: !invert IMUX_CE_OPTINV[3] ← IMUX_CE[3] INT: mux IMUX_CE[3] bit 3 INT: mux OMUX[15] bit 9 INT: mux OMUX[15] bit 7 INT: mux IMUX_G3_DATA[1] bit 8 INT: mux IMUX_G3_DATA[1] bit 11 INT: mux IMUX_G3_DATA[0] bit 7 INT: mux IMUX_G3_DATA[0] bit 5 INT: mux IMUX_G3_DATA[0] bit 2 INT: mux IMUX_G3_DATA[0] bit 3 INT: mux DBL_E0[9] bit 1 INT: mux DBL_W0[9] bit 4 INT: mux DBL_W0[9] bit 3 INT: mux DBL_W0[9] bit 0 INT: mux HEX_E0[9] bit 1 INT: mux HEX_E0[9] bit 3 INT: mux HEX_E0[9] bit 5 INT: mux HEX_W0[9] bit 6
B77 - - - - INT: mux IMUX_CE[3] bit 0 INT: mux IMUX_CE[3] bit 2 INT: mux OMUX[15] bit 0 INT: mux OMUX[15] bit 8 INT: mux IMUX_G3_DATA[1] bit 9 INT: mux IMUX_G3_DATA[1] bit 10 INT: mux IMUX_G3_DATA[1] bit 6 INT: mux IMUX_G3_DATA[1] bit 4 INT: mux IMUX_G3_DATA[1] bit 1 INT: mux IMUX_G3_DATA[1] bit 0 INT: mux DBL_W0[9] bit 5 INT: mux DBL_E0[9] bit 3 INT: mux DBL_W0[9] bit 2 INT: mux DBL_W0[9] bit 1 INT: mux HEX_W0[9] bit 2 INT: mux HEX_W0[9] bit 1 INT: mux HEX_E0[9] bit 6 INT: mux LV[18] bit 3
B76 - - - - INT: mux IMUX_CE[3] bit 4 INT: mux IMUX_CE[3] bit 5 INT: mux OMUX[14] bit 1 INT: mux OMUX[15] bit 1 INT: mux IMUX_G3_DATA[0] bit 9 INT: mux IMUX_G3_DATA[0] bit 10 INT: mux IMUX_G3_DATA[0] bit 6 INT: mux IMUX_G3_DATA[0] bit 4 INT: mux IMUX_G3_DATA[0] bit 1 INT: mux IMUX_G3_DATA[0] bit 0 INT: mux DBL_W0[9] bit 6 INT: mux DBL_E0[9] bit 2 INT: mux DBL_E0[9] bit 4 INT: mux DBL_E0[9] bit 6 INT: mux HEX_E0[9] bit 2 INT: mux HEX_E0[9] bit 0 INT: mux HEX_E0[9] bit 4 INT: mux HEX_W0[9] bit 5
B75 - - - - INT: mux IMUX_CE[2] bit 4 INT: mux IMUX_CE[2] bit 7 INT: mux OMUX[15] bit 2 INT: mux OMUX[14] bit 2 INT: mux IMUX_G3_DATA[2] bit 9 INT: mux IMUX_G3_DATA[2] bit 10 INT: mux IMUX_G3_DATA[2] bit 6 INT: mux IMUX_G3_DATA[2] bit 4 INT: mux IMUX_G3_DATA[2] bit 1 INT: mux IMUX_G3_DATA[2] bit 0 INT: mux DBL_S0[9] bit 4 INT: mux DBL_N0[9] bit 2 INT: mux DBL_S0[9] bit 0 INT: mux DBL_S0[9] bit 3 INT: mux HEX_N0[9] bit 1 INT: mux HEX_N0[9] bit 3 INT: mux HEX_N0[9] bit 5 INT: mux LV[6] bit 0
B74 - - - - INT: mux IMUX_CE[3] bit 7 INT: mux IMUX_CE[3] bit 6 INT: mux OMUX[15] bit 3 INT: mux OMUX[14] bit 3 INT: mux IMUX_G3_DATA[3] bit 9 INT: mux IMUX_G3_DATA[3] bit 10 INT: mux IMUX_G3_DATA[3] bit 6 INT: mux IMUX_G3_DATA[3] bit 4 INT: mux IMUX_G3_DATA[3] bit 1 INT: mux IMUX_G3_DATA[3] bit 0 INT: mux DBL_S0[9] bit 5 INT: mux DBL_N0[9] bit 0 INT: mux DBL_N0[9] bit 7 INT: mux DBL_N0[9] bit 5 INT: mux HEX_S0[9] bit 1 INT: mux HEX_S0[9] bit 2 INT: mux HEX_S0[9] bit 4 INT: mux HEX_N0[9] bit 4
B73 - - - - INT: mux IMUX_CE[2] bit 0 INT: mux IMUX_CE[2] bit 1 INT: mux OMUX[14] bit 4 INT: mux OMUX[15] bit 4 INT: mux IMUX_G3_DATA[3] bit 8 INT: mux IMUX_G3_DATA[3] bit 11 INT: mux IMUX_G3_DATA[2] bit 7 INT: mux IMUX_G3_DATA[2] bit 5 INT: mux IMUX_G3_DATA[2] bit 2 INT: mux IMUX_G3_DATA[2] bit 3 INT: mux DBL_N0[9] bit 1 INT: mux DBL_S0[9] bit 6 INT: mux DBL_N0[9] bit 6 INT: mux DBL_N0[9] bit 4 INT: mux HEX_N0[9] bit 2 INT: mux HEX_N0[9] bit 0 INT: mux HEX_S0[9] bit 5 INT: mux LV[6] bit 6
B72 - - - - INT: !invert IMUX_CE_OPTINV[2] ← IMUX_CE[2] INT: mux IMUX_CE[2] bit 3 INT: mux OMUX[15] bit 5 INT: mux OMUX[14] bit 8 INT: mux IMUX_G3_DATA[2] bit 8 INT: mux IMUX_G3_DATA[2] bit 11 INT: mux IMUX_G3_DATA[3] bit 7 INT: mux IMUX_G3_DATA[3] bit 5 INT: mux IMUX_G3_DATA[3] bit 2 INT: mux IMUX_G3_DATA[3] bit 3 INT: mux DBL_N0[9] bit 3 INT: mux DBL_S0[9] bit 7 INT: mux DBL_S0[9] bit 1 INT: mux DBL_S0[9] bit 2 INT: mux HEX_S0[9] bit 3 INT: mux HEX_S0[9] bit 0 INT: mux HEX_S0[9] bit 6 INT: mux HEX_N0[9] bit 6
B71 - - - - INT: mux IMUX_CE[2] bit 6 INT: mux IMUX_CE[2] bit 2 INT: mux OMUX[14] bit 9 INT: mux OMUX[14] bit 7 INT: mux IMUX_G3_DATA[4] bit 8 INT: mux IMUX_G3_DATA[4] bit 11 INT: mux IMUX_G3_DATA[5] bit 7 INT: mux IMUX_G3_DATA[5] bit 5 INT: mux IMUX_G3_DATA[5] bit 2 INT: mux IMUX_G3_DATA[5] bit 3 INT: mux DBL_E0[8] bit 2 INT: mux DBL_W0[8] bit 3 INT: mux DBL_E0[8] bit 4 INT: mux DBL_E0[8] bit 7 INT: mux HEX_E0[8] bit 0 INT: mux HEX_E0[8] bit 3 INT: mux HEX_E0[8] bit 4 INT: mux LV[6] bit 2
B70 - - - - - - INT: mux OMUX[14] bit 5 INT: mux OMUX[14] bit 6 INT: mux IMUX_G3_DATA[5] bit 8 INT: mux IMUX_G3_DATA[5] bit 11 INT: mux IMUX_G3_DATA[4] bit 7 INT: mux IMUX_G3_DATA[4] bit 5 INT: mux IMUX_G3_DATA[4] bit 2 INT: mux IMUX_G3_DATA[4] bit 3 INT: mux DBL_E0[8] bit 0 INT: mux DBL_W0[8] bit 0 INT: mux DBL_W0[8] bit 7 INT: mux DBL_W0[8] bit 4 INT: mux HEX_W0[8] bit 0 INT: mux HEX_W0[8] bit 3 INT: mux HEX_W0[8] bit 4 INT: mux HEX_E0[8] bit 5
B69 - - - - - - INT: mux OMUX[12] bit 1 INT: mux OMUX[13] bit 6 INT: mux IMUX_G3_DATA[5] bit 9 INT: mux IMUX_G3_DATA[5] bit 10 INT: mux IMUX_G3_DATA[5] bit 6 INT: mux IMUX_G3_DATA[5] bit 4 INT: mux IMUX_G3_DATA[5] bit 1 INT: mux IMUX_G3_DATA[5] bit 0 INT: mux DBL_W0[8] bit 2 INT: mux DBL_E0[8] bit 3 INT: mux DBL_W0[8] bit 6 INT: mux DBL_W0[8] bit 5 INT: mux HEX_E0[8] bit 2 INT: mux HEX_E0[8] bit 1 INT: mux HEX_W0[8] bit 5 INT: mux LV[6] bit 3
B68 - - - - - - INT: mux OMUX[13] bit 9 INT: mux OMUX[13] bit 7 INT: mux IMUX_G3_DATA[4] bit 9 INT: mux IMUX_G3_DATA[4] bit 10 INT: mux IMUX_G3_DATA[4] bit 6 INT: mux IMUX_G3_DATA[4] bit 4 INT: mux IMUX_G3_DATA[4] bit 1 INT: mux IMUX_G3_DATA[4] bit 0 INT: mux DBL_W0[8] bit 1 INT: mux DBL_E0[8] bit 1 INT: mux DBL_E0[8] bit 5 INT: mux DBL_E0[8] bit 6 INT: mux HEX_W0[8] bit 2 INT: mux HEX_W0[8] bit 1 INT: mux HEX_W0[8] bit 6 INT: mux HEX_E0[8] bit 6
B67 - - - - - - INT: mux OMUX[13] bit 1 INT: mux OMUX[13] bit 8 INT: mux IMUX_G3_DATA[6] bit 9 INT: mux IMUX_G3_DATA[6] bit 10 INT: mux IMUX_G3_DATA[6] bit 6 INT: mux IMUX_G3_DATA[6] bit 4 INT: mux IMUX_G3_DATA[6] bit 1 INT: mux IMUX_G3_DATA[6] bit 0 INT: mux DBL_S0[8] bit 3 INT: mux DBL_N0[8] bit 1 INT: mux DBL_S0[8] bit 5 INT: mux DBL_S0[8] bit 7 INT: mux HEX_S0[8] bit 1 INT: mux HEX_S0[8] bit 3 INT: mux HEX_S0[8] bit 5 INT: mux LV[18] bit 6
B66 - - - - - - INT: mux OMUX[12] bit 0 INT: mux OMUX[13] bit 0 INT: mux IMUX_G3_DATA[7] bit 9 INT: mux IMUX_G3_DATA[7] bit 10 INT: mux IMUX_G3_DATA[7] bit 6 INT: mux IMUX_G3_DATA[7] bit 4 INT: mux IMUX_G3_DATA[7] bit 1 INT: mux IMUX_G3_DATA[7] bit 0 INT: mux DBL_S0[8] bit 0 INT: mux DBL_N0[8] bit 0 INT: mux DBL_N0[8] bit 7 INT: mux DBL_N0[8] bit 5 INT: mux HEX_N0[8] bit 1 INT: mux HEX_N0[8] bit 2 INT: mux HEX_N0[8] bit 5 INT: mux HEX_S0[8] bit 4
B65 - - - - - - INT: mux OMUX[13] bit 2 INT: mux OMUX[12] bit 2 INT: mux IMUX_G3_DATA[7] bit 8 INT: mux IMUX_G3_DATA[7] bit 11 INT: mux IMUX_G3_DATA[6] bit 7 INT: mux IMUX_G3_DATA[6] bit 5 INT: mux IMUX_G3_DATA[6] bit 2 INT: mux IMUX_G3_DATA[6] bit 3 INT: mux DBL_N0[8] bit 3 INT: mux DBL_S0[8] bit 1 INT: mux DBL_N0[8] bit 6 INT: mux DBL_N0[8] bit 4 INT: mux HEX_S0[8] bit 2 INT: mux HEX_S0[8] bit 0 INT: mux HEX_N0[8] bit 4 INT: mux LV[6] bit 1
B64 - - - - - - INT: mux OMUX[13] bit 3 INT: mux OMUX[12] bit 3 INT: mux IMUX_G3_DATA[6] bit 8 INT: mux IMUX_G3_DATA[6] bit 11 INT: mux IMUX_G3_DATA[7] bit 7 INT: mux IMUX_G3_DATA[7] bit 5 INT: mux IMUX_G3_DATA[7] bit 2 INT: mux IMUX_G3_DATA[7] bit 3 INT: mux DBL_N0[8] bit 2 INT: mux DBL_S0[8] bit 2 INT: mux DBL_S0[8] bit 4 INT: mux DBL_S0[8] bit 6 INT: mux HEX_N0[8] bit 3 INT: mux HEX_N0[8] bit 0 INT: mux HEX_N0[8] bit 6 INT: mux HEX_S0[8] bit 6
B63 - - - - - - INT: mux OMUX[12] bit 4 INT: mux OMUX[13] bit 4 INT: mux IMUX_G3_FAN[0] bit 8 INT: mux IMUX_G3_FAN[0] bit 11 INT: mux IMUX_G3_FAN[1] bit 7 INT: mux IMUX_G3_FAN[1] bit 5 INT: mux IMUX_G3_FAN[1] bit 2 INT: mux IMUX_G3_FAN[1] bit 3 INT: mux DBL_E0[7] bit 2 INT: mux DBL_W0[7] bit 3 INT: mux DBL_E0[7] bit 4 INT: mux DBL_E0[7] bit 7 INT: mux HEX_W0[7] bit 0 INT: mux HEX_W0[7] bit 3 INT: mux HEX_W0[7] bit 4 INT: mux LV[18] bit 0
B62 - - - - INT: mux IMUX_DCM_CLK[2] bit 7 INT: mux IMUX_DCM_CLK[3] bit 9 INT: mux OMUX[13] bit 5 INT: mux OMUX[12] bit 8 INT: mux IMUX_G3_FAN[1] bit 8 INT: mux IMUX_G3_FAN[1] bit 11 INT: mux IMUX_G3_FAN[0] bit 7 INT: mux IMUX_G3_FAN[0] bit 5 INT: mux IMUX_G3_FAN[0] bit 2 INT: mux IMUX_G3_FAN[0] bit 3 INT: mux DBL_E0[7] bit 0 INT: mux DBL_W0[7] bit 0 INT: mux DBL_W0[7] bit 7 INT: mux DBL_W0[7] bit 4 INT: mux HEX_E0[7] bit 0 INT: mux HEX_E0[7] bit 3 INT: mux HEX_E0[7] bit 4 INT: mux HEX_W0[7] bit 5
B61 - - - - INT: invert IMUX_DCM_CLK_OPTINV[3] ← IMUX_DCM_CLK[3] INT: mux IMUX_DCM_CLK[3] bit 11 INT: mux OMUX[12] bit 9 INT: mux OMUX[12] bit 7 INT: mux IMUX_G3_FAN[1] bit 9 INT: mux IMUX_G3_FAN[1] bit 10 INT: mux IMUX_G3_FAN[1] bit 6 INT: mux IMUX_G3_FAN[1] bit 4 INT: mux IMUX_G3_FAN[1] bit 1 INT: mux IMUX_G3_FAN[1] bit 0 INT: mux DBL_W0[7] bit 2 INT: mux DBL_E0[7] bit 3 INT: mux DBL_W0[7] bit 6 INT: mux DBL_W0[7] bit 5 INT: mux HEX_W0[7] bit 2 INT: mux HEX_W0[7] bit 1 INT: mux HEX_E0[7] bit 5 INT: mux LV[6] bit 5
B60 - - - - INT: mux IMUX_DCM_CLK[3] bit 8 INT: mux IMUX_DCM_CLK[3] bit 10 INT: mux OMUX[12] bit 5 INT: mux OMUX[12] bit 6 INT: mux IMUX_G3_FAN[0] bit 9 INT: mux IMUX_G3_FAN[0] bit 10 INT: mux IMUX_G3_FAN[0] bit 6 INT: mux IMUX_G3_FAN[0] bit 4 INT: mux IMUX_G3_FAN[0] bit 1 INT: mux IMUX_G3_FAN[0] bit 0 INT: mux DBL_W0[7] bit 1 INT: mux DBL_E0[7] bit 1 INT: mux DBL_E0[7] bit 5 INT: mux DBL_E0[7] bit 6 INT: mux HEX_E0[7] bit 2 INT: mux HEX_E0[7] bit 1 INT: mux HEX_E0[7] bit 6 INT: mux HEX_W0[7] bit 6
B59 - - - - INT: mux IMUX_DCM_CLK[3] bit 4 INT: mux IMUX_DCM_CLK[3] bit 7 INT: mux OMUX[10] bit 1 INT: mux OMUX[11] bit 6 INT: mux IMUX_G2_FAN[0] bit 9 INT: mux IMUX_G2_FAN[0] bit 10 INT: mux IMUX_G2_FAN[0] bit 6 INT: mux IMUX_G2_FAN[0] bit 5 INT: mux IMUX_G2_FAN[0] bit 1 INT: mux IMUX_G2_FAN[0] bit 3 INT: mux DBL_S0[7] bit 4 INT: mux DBL_N0[7] bit 6 INT: mux DBL_S0[7] bit 1 INT: mux DBL_S0[7] bit 3 INT: mux HEX_N0[7] bit 1 INT: mux HEX_N0[7] bit 3 INT: mux HEX_N0[7] bit 6 INT: mux LV[18] bit 2
B58 - - - - INT: mux IMUX_DCM_CLK[2] bit 6 INT: mux IMUX_DCM_CLK[2] bit 4 INT: mux OMUX[11] bit 9 INT: mux OMUX[11] bit 7 INT: mux IMUX_G2_FAN[1] bit 9 INT: mux IMUX_G2_FAN[1] bit 10 INT: mux IMUX_G2_FAN[1] bit 6 INT: mux IMUX_G2_FAN[1] bit 5 INT: mux IMUX_G2_FAN[1] bit 1 INT: mux IMUX_G2_FAN[1] bit 3 INT: mux DBL_S0[7] bit 5 INT: mux DBL_N0[7] bit 5 INT: mux DBL_N0[7] bit 3 INT: mux DBL_N0[7] bit 1 INT: mux HEX_S0[7] bit 1 INT: mux HEX_S0[7] bit 2 INT: mux HEX_S0[7] bit 5 INT: mux HEX_N0[7] bit 5
B57 - - - - INT: mux IMUX_DCM_CLK[3] bit 5 INT: mux IMUX_DCM_CLK[3] bit 6 INT: mux OMUX[11] bit 1 INT: mux OMUX[11] bit 8 INT: mux IMUX_G2_FAN[1] bit 8 INT: mux IMUX_G2_FAN[1] bit 11 INT: mux IMUX_G2_FAN[0] bit 7 INT: mux IMUX_G2_FAN[0] bit 4 INT: mux IMUX_G2_FAN[0] bit 0 INT: mux IMUX_G2_FAN[0] bit 2 INT: mux DBL_N0[7] bit 4 INT: mux DBL_S0[7] bit 6 INT: mux DBL_N0[7] bit 2 INT: mux DBL_N0[7] bit 0 INT: mux HEX_N0[7] bit 2 INT: mux HEX_N0[7] bit 0 INT: mux HEX_S0[7] bit 6 INT: mux LV[18] bit 4
B56 - - - - INT: mux IMUX_DCM_CLK[2] bit 0 INT: mux IMUX_DCM_CLK[2] bit 5 INT: mux OMUX[10] bit 0 INT: mux OMUX[11] bit 0 INT: mux IMUX_G2_FAN[0] bit 8 INT: mux IMUX_G2_FAN[0] bit 11 INT: mux IMUX_G2_FAN[1] bit 7 INT: mux IMUX_G2_FAN[1] bit 4 INT: mux IMUX_G2_FAN[1] bit 0 INT: mux IMUX_G2_FAN[1] bit 2 INT: mux DBL_N0[7] bit 7 INT: mux DBL_S0[7] bit 7 INT: mux DBL_S0[7] bit 0 INT: mux DBL_S0[7] bit 2 INT: mux HEX_S0[7] bit 3 INT: mux HEX_S0[7] bit 0 INT: mux HEX_S0[7] bit 4 INT: mux HEX_N0[7] bit 4
B55 - - - - INT: mux IMUX_DCM_CLK[3] bit 1 INT: mux IMUX_DCM_CLK[3] bit 0 INT: mux OMUX[11] bit 2 INT: mux OMUX[10] bit 2 INT: mux IMUX_G2_DATA[6] bit 8 INT: mux IMUX_G2_DATA[6] bit 11 INT: mux IMUX_G2_DATA[7] bit 7 INT: mux IMUX_G2_DATA[7] bit 4 INT: mux IMUX_G2_DATA[7] bit 0 INT: mux IMUX_G2_DATA[7] bit 2 INT: mux DBL_E0[6] bit 1 INT: mux DBL_W0[6] bit 7 INT: mux DBL_E0[6] bit 5 INT: mux DBL_E0[6] bit 7 INT: mux HEX_E0[6] bit 1 INT: mux HEX_E0[6] bit 3 INT: mux HEX_E0[6] bit 5 INT: mux LV[6] bit 4
B54 - - - - INT: mux IMUX_DCM_CLK[2] bit 3 INT: mux IMUX_DCM_CLK[2] bit 1 INT: mux OMUX[11] bit 3 INT: mux OMUX[10] bit 3 INT: mux IMUX_G2_DATA[7] bit 8 INT: mux IMUX_G2_DATA[7] bit 11 INT: mux IMUX_G2_DATA[6] bit 7 INT: mux IMUX_G2_DATA[6] bit 4 INT: mux IMUX_G2_DATA[6] bit 0 INT: mux IMUX_G2_DATA[6] bit 2 INT: mux DBL_E0[6] bit 0 INT: mux DBL_W0[6] bit 5 INT: mux DBL_W0[6] bit 3 INT: mux DBL_W0[6] bit 0 INT: mux HEX_W0[6] bit 1 INT: mux HEX_W0[6] bit 3 INT: mux HEX_W0[6] bit 4 INT: mux HEX_E0[6] bit 4
B53 - - - - INT: mux IMUX_DCM_CLK[3] bit 3 INT: mux IMUX_DCM_CLK[2] bit 11 INT: mux OMUX[10] bit 4 INT: mux OMUX[11] bit 4 INT: mux IMUX_G2_DATA[7] bit 9 INT: mux IMUX_G2_DATA[7] bit 10 INT: mux IMUX_G2_DATA[7] bit 6 INT: mux IMUX_G2_DATA[7] bit 5 INT: mux IMUX_G2_DATA[7] bit 1 INT: mux IMUX_G2_DATA[7] bit 3 INT: mux DBL_W0[6] bit 4 INT: mux DBL_E0[6] bit 3 INT: mux DBL_W0[6] bit 2 INT: mux DBL_W0[6] bit 1 INT: mux HEX_E0[6] bit 2 INT: mux HEX_E0[6] bit 0 INT: mux HEX_W0[6] bit 5 INT: mux LV[18] bit 5
B52 - - - - INT: mux IMUX_DCM_CLK[2] bit 8 INT: mux IMUX_DCM_CLK[2] bit 10 INT: mux OMUX[11] bit 5 INT: mux OMUX[10] bit 8 INT: mux IMUX_G2_DATA[6] bit 9 INT: mux IMUX_G2_DATA[6] bit 10 INT: mux IMUX_G2_DATA[6] bit 6 INT: mux IMUX_G2_DATA[6] bit 5 INT: mux IMUX_G2_DATA[6] bit 1 INT: mux IMUX_G2_DATA[6] bit 3 INT: mux DBL_W0[6] bit 6 INT: mux DBL_E0[6] bit 2 INT: mux DBL_E0[6] bit 4 INT: mux DBL_E0[6] bit 6 INT: mux HEX_W0[6] bit 2 INT: mux HEX_W0[6] bit 0 INT: mux HEX_W0[6] bit 6 INT: mux HEX_E0[6] bit 6
B51 - - - - INT: invert IMUX_DCM_CLK_OPTINV[2] ← IMUX_DCM_CLK[2] INT: mux IMUX_DCM_CLK[3] bit 2 INT: mux OMUX[10] bit 9 INT: mux OMUX[10] bit 7 INT: mux IMUX_G2_DATA[4] bit 9 INT: mux IMUX_G2_DATA[4] bit 10 INT: mux IMUX_G2_DATA[4] bit 6 INT: mux IMUX_G2_DATA[4] bit 5 INT: mux IMUX_G2_DATA[4] bit 1 INT: mux IMUX_G2_DATA[4] bit 3 INT: mux DBL_S0[6] bit 3 INT: mux DBL_N0[6] bit 1 INT: mux DBL_S0[6] bit 4 INT: mux DBL_S0[6] bit 7 INT: mux HEX_S0[6] bit 0 INT: mux HEX_S0[6] bit 3 INT: mux HEX_S0[6] bit 4 INT: mux LH[0] bit 0
B50 - - - - INT: mux IMUX_DCM_CLK[2] bit 2 INT: mux IMUX_DCM_CLK[2] bit 9 INT: mux OMUX[10] bit 5 INT: mux OMUX[10] bit 6 INT: mux IMUX_G2_DATA[5] bit 9 INT: mux IMUX_G2_DATA[5] bit 10 INT: mux IMUX_G2_DATA[5] bit 6 INT: mux IMUX_G2_DATA[5] bit 5 INT: mux IMUX_G2_DATA[5] bit 1 INT: mux IMUX_G2_DATA[5] bit 3 INT: mux DBL_S0[6] bit 0 INT: mux DBL_N0[6] bit 0 INT: mux DBL_N0[6] bit 7 INT: mux DBL_N0[6] bit 4 INT: mux HEX_N0[6] bit 0 INT: mux HEX_N0[6] bit 2 INT: mux HEX_N0[6] bit 4 INT: mux HEX_S0[6] bit 5
B49 - - - - INT: mux IMUX_DCM_CLK[1] bit 2 INT: mux IMUX_DCM_CLK[1] bit 9 INT: mux OMUX[8] bit 0 INT: mux OMUX[9] bit 6 INT: mux IMUX_G2_DATA[5] bit 8 INT: mux IMUX_G2_DATA[5] bit 11 INT: mux IMUX_G2_DATA[4] bit 7 INT: mux IMUX_G2_DATA[4] bit 4 INT: mux IMUX_G2_DATA[4] bit 0 INT: mux IMUX_G2_DATA[4] bit 2 INT: mux DBL_N0[6] bit 3 INT: mux DBL_S0[6] bit 1 INT: mux DBL_N0[6] bit 6 INT: mux DBL_N0[6] bit 5 INT: mux HEX_S0[6] bit 2 INT: mux HEX_S0[6] bit 1 INT: mux HEX_N0[6] bit 5 INT: mux LH[0] bit 1
B48 - - - - INT: invert IMUX_DCM_CLK_OPTINV[1] ← IMUX_DCM_CLK[1] INT: mux IMUX_DCM_CLK[0] bit 2 INT: mux OMUX[9] bit 9 INT: mux OMUX[9] bit 7 INT: mux IMUX_G2_DATA[4] bit 8 INT: mux IMUX_G2_DATA[4] bit 11 INT: mux IMUX_G2_DATA[5] bit 7 INT: mux IMUX_G2_DATA[5] bit 4 INT: mux IMUX_G2_DATA[5] bit 0 INT: mux IMUX_G2_DATA[5] bit 2 INT: mux DBL_N0[6] bit 2 INT: mux DBL_S0[6] bit 2 INT: mux DBL_S0[6] bit 5 INT: mux DBL_S0[6] bit 6 INT: mux HEX_N0[6] bit 3 INT: mux HEX_N0[6] bit 1 INT: mux HEX_N0[6] bit 6 INT: mux HEX_S0[6] bit 6
B47 - - - - INT: mux IMUX_DCM_CLK[1] bit 8 INT: mux IMUX_DCM_CLK[1] bit 10 INT: mux OMUX[9] bit 0 INT: mux OMUX[9] bit 8 INT: mux IMUX_G2_DATA[2] bit 8 INT: mux IMUX_G2_DATA[2] bit 11 INT: mux IMUX_G2_DATA[3] bit 7 INT: mux IMUX_G2_DATA[3] bit 4 INT: mux IMUX_G2_DATA[3] bit 0 INT: mux IMUX_G2_DATA[3] bit 2 INT: mux DBL_E0[5] bit 2 INT: mux DBL_W0[5] bit 3 INT: mux DBL_E0[5] bit 4 INT: mux DBL_E0[5] bit 7 INT: mux HEX_W0[5] bit 1 INT: mux HEX_W0[5] bit 3 INT: mux HEX_W0[5] bit 5 INT: mux LH[0] bit 2
B46 - - - - INT: mux IMUX_DCM_CLK[0] bit 3 INT: mux IMUX_DCM_CLK[1] bit 11 INT: mux OMUX[8] bit 1 INT: mux OMUX[9] bit 1 INT: mux IMUX_G2_DATA[3] bit 8 INT: mux IMUX_G2_DATA[3] bit 11 INT: mux IMUX_G2_DATA[2] bit 7 INT: mux IMUX_G2_DATA[2] bit 4 INT: mux IMUX_G2_DATA[2] bit 0 INT: mux IMUX_G2_DATA[2] bit 2 INT: mux DBL_E0[5] bit 0 INT: mux DBL_W0[5] bit 0 INT: mux DBL_W0[5] bit 7 INT: mux DBL_W0[5] bit 5 INT: mux HEX_E0[5] bit 0 INT: mux HEX_E0[5] bit 3 INT: mux HEX_E0[5] bit 4 INT: mux HEX_W0[5] bit 4
B45 - - - - INT: mux IMUX_DCM_CLK[1] bit 3 INT: mux IMUX_DCM_CLK[1] bit 1 INT: mux OMUX[9] bit 2 INT: mux OMUX[8] bit 2 INT: mux IMUX_G2_DATA[3] bit 9 INT: mux IMUX_G2_DATA[3] bit 10 INT: mux IMUX_G2_DATA[3] bit 6 INT: mux IMUX_G2_DATA[3] bit 5 INT: mux IMUX_G2_DATA[3] bit 1 INT: mux IMUX_G2_DATA[3] bit 3 INT: mux DBL_W0[5] bit 2 INT: mux DBL_E0[5] bit 3 INT: mux DBL_W0[5] bit 6 INT: mux DBL_W0[5] bit 4 INT: mux HEX_W0[5] bit 2 INT: mux HEX_W0[5] bit 0 INT: mux HEX_E0[5] bit 5 INT: mux LH[12] bit 1
B44 - - - - INT: mux IMUX_DCM_CLK[0] bit 1 INT: mux IMUX_DCM_CLK[0] bit 0 INT: mux OMUX[9] bit 3 INT: mux OMUX[8] bit 3 INT: mux IMUX_G2_DATA[2] bit 9 INT: mux IMUX_G2_DATA[2] bit 10 INT: mux IMUX_G2_DATA[2] bit 6 INT: mux IMUX_G2_DATA[2] bit 5 INT: mux IMUX_G2_DATA[2] bit 1 INT: mux IMUX_G2_DATA[2] bit 3 INT: mux DBL_W0[5] bit 1 INT: mux DBL_E0[5] bit 1 INT: mux DBL_E0[5] bit 5 INT: mux DBL_E0[5] bit 6 INT: mux HEX_E0[5] bit 2 INT: mux HEX_E0[5] bit 1 INT: mux HEX_E0[5] bit 6 INT: mux HEX_W0[5] bit 6
B43 - - - - INT: mux IMUX_DCM_CLK[1] bit 0 INT: mux IMUX_DCM_CLK[1] bit 5 INT: mux OMUX[8] bit 4 INT: mux OMUX[9] bit 4 INT: mux IMUX_G2_DATA[0] bit 9 INT: mux IMUX_G2_DATA[0] bit 10 INT: mux IMUX_G2_DATA[0] bit 6 INT: mux IMUX_G2_DATA[0] bit 5 INT: mux IMUX_G2_DATA[0] bit 1 INT: mux IMUX_G2_DATA[0] bit 3 INT: mux DBL_S0[5] bit 3 INT: mux DBL_N0[5] bit 1 INT: mux DBL_S0[5] bit 4 INT: mux DBL_S0[5] bit 7 INT: mux HEX_N0[5] bit 1 INT: mux HEX_N0[5] bit 3 INT: mux HEX_N0[5] bit 5 INT: mux LH[12] bit 0
B42 - - - - INT: mux IMUX_DCM_CLK[0] bit 5 INT: mux IMUX_DCM_CLK[0] bit 6 INT: mux OMUX[9] bit 5 INT: mux OMUX[8] bit 8 INT: mux IMUX_G2_DATA[1] bit 9 INT: mux IMUX_G2_DATA[1] bit 10 INT: mux IMUX_G2_DATA[1] bit 6 INT: mux IMUX_G2_DATA[1] bit 5 INT: mux IMUX_G2_DATA[1] bit 1 INT: mux IMUX_G2_DATA[1] bit 3 INT: mux DBL_S0[5] bit 0 INT: mux DBL_N0[5] bit 0 INT: mux DBL_N0[5] bit 7 INT: mux DBL_N0[5] bit 5 INT: mux HEX_S0[5] bit 0 INT: mux HEX_S0[5] bit 2 INT: mux HEX_S0[5] bit 4 INT: mux HEX_N0[5] bit 4
B41 - - - - INT: mux IMUX_DCM_CLK[1] bit 6 INT: mux IMUX_DCM_CLK[1] bit 4 INT: mux OMUX[8] bit 9 INT: mux OMUX[8] bit 7 INT: mux IMUX_G2_DATA[1] bit 8 INT: mux IMUX_G2_DATA[1] bit 11 INT: mux IMUX_G2_DATA[0] bit 7 INT: mux IMUX_G2_DATA[0] bit 4 INT: mux IMUX_G2_DATA[0] bit 0 INT: mux IMUX_G2_DATA[0] bit 2 INT: mux DBL_N0[5] bit 3 INT: mux DBL_S0[5] bit 1 INT: mux DBL_N0[5] bit 6 INT: mux DBL_N0[5] bit 4 INT: mux HEX_N0[5] bit 2 INT: mux HEX_N0[5] bit 0 INT: mux HEX_S0[5] bit 5 INT: mux LH[12] bit 2
B40 - - - - INT: mux IMUX_DCM_CLK[0] bit 4 INT: mux IMUX_DCM_CLK[0] bit 7 INT: mux OMUX[8] bit 5 INT: mux OMUX[8] bit 6 INT: mux IMUX_G2_DATA[0] bit 8 INT: mux IMUX_G2_DATA[0] bit 11 INT: mux IMUX_G2_DATA[1] bit 7 INT: mux IMUX_G2_DATA[1] bit 4 INT: mux IMUX_G2_DATA[1] bit 0 INT: mux IMUX_G2_DATA[1] bit 2 INT: mux DBL_N0[5] bit 2 INT: mux DBL_S0[5] bit 2 INT: mux DBL_S0[5] bit 5 INT: mux DBL_S0[5] bit 6 INT: mux HEX_S0[5] bit 3 INT: mux HEX_S0[5] bit 1 INT: mux HEX_S0[5] bit 6 INT: mux HEX_N0[5] bit 6
B39 - - - - INT: mux IMUX_DCM_CLK[0] bit 8 INT: mux IMUX_DCM_CLK[0] bit 10 INT: mux OMUX[6] bit 0 INT: mux OMUX[7] bit 6 INT: mux IMUX_G1_DATA[0] bit 9 INT: mux IMUX_G1_DATA[0] bit 11 INT: mux IMUX_G1_DATA[1] bit 7 INT: mux IMUX_G1_DATA[1] bit 5 INT: mux IMUX_G1_DATA[1] bit 1 INT: mux IMUX_G1_DATA[1] bit 2 INT: mux DBL_E0[4] bit 2 INT: mux DBL_W0[4] bit 3 INT: mux DBL_E0[4] bit 5 INT: mux DBL_E0[4] bit 7 INT: mux HEX_E0[4] bit 1 INT: mux HEX_E0[4] bit 3 INT: mux HEX_E0[4] bit 5 INT: mux LH[18] bit 2
B38 - - - - INT: invert IMUX_DCM_CLK_OPTINV[0] ← IMUX_DCM_CLK[0] INT: mux IMUX_DCM_CLK[0] bit 11 INT: mux OMUX[7] bit 9 INT: mux OMUX[7] bit 7 INT: mux IMUX_G1_DATA[1] bit 9 INT: mux IMUX_G1_DATA[1] bit 11 INT: mux IMUX_G1_DATA[0] bit 7 INT: mux IMUX_G1_DATA[0] bit 5 INT: mux IMUX_G1_DATA[0] bit 1 INT: mux IMUX_G1_DATA[0] bit 2 INT: mux DBL_E0[4] bit 0 INT: mux DBL_W0[4] bit 0 INT: mux DBL_W0[4] bit 7 INT: mux DBL_W0[4] bit 5 INT: mux HEX_W0[4] bit 1 INT: mux HEX_W0[4] bit 3 INT: mux HEX_W0[4] bit 5 INT: mux HEX_E0[4] bit 4
B37 - - - - INT: mux IMUX_DCM_CLK[1] bit 7 INT: mux IMUX_DCM_CLK[0] bit 9 INT: mux OMUX[7] bit 0 INT: mux OMUX[7] bit 8 INT: mux IMUX_G1_DATA[1] bit 8 INT: mux IMUX_G1_DATA[1] bit 10 INT: mux IMUX_G1_DATA[1] bit 6 INT: mux IMUX_G1_DATA[1] bit 4 INT: mux IMUX_G1_DATA[1] bit 0 INT: mux IMUX_G1_DATA[1] bit 3 INT: mux DBL_W0[4] bit 2 INT: mux DBL_E0[4] bit 3 INT: mux DBL_W0[4] bit 6 INT: mux DBL_W0[4] bit 4 INT: mux HEX_E0[4] bit 2 INT: mux HEX_E0[4] bit 0 INT: mux HEX_W0[4] bit 4 INT: mux LH[18] bit 1
B36 - - - - - - INT: mux OMUX[6] bit 1 INT: mux OMUX[7] bit 1 INT: mux IMUX_G1_DATA[0] bit 8 INT: mux IMUX_G1_DATA[0] bit 10 INT: mux IMUX_G1_DATA[0] bit 6 INT: mux IMUX_G1_DATA[0] bit 4 INT: mux IMUX_G1_DATA[0] bit 0 INT: mux IMUX_G1_DATA[0] bit 3 INT: mux DBL_W0[4] bit 1 INT: mux DBL_E0[4] bit 1 INT: mux DBL_E0[4] bit 4 INT: mux DBL_E0[4] bit 6 INT: mux HEX_W0[4] bit 2 INT: mux HEX_W0[4] bit 0 INT: mux HEX_W0[4] bit 6 INT: mux HEX_E0[4] bit 6
B35 - - - - - - INT: mux OMUX[7] bit 2 INT: mux OMUX[6] bit 2 INT: mux IMUX_G1_DATA[2] bit 8 INT: mux IMUX_G1_DATA[2] bit 10 INT: mux IMUX_G1_DATA[2] bit 6 INT: mux IMUX_G1_DATA[2] bit 4 INT: mux IMUX_G1_DATA[2] bit 0 INT: mux IMUX_G1_DATA[2] bit 3 INT: mux DBL_S0[4] bit 3 INT: mux DBL_N0[4] bit 1 INT: mux DBL_S0[4] bit 4 INT: mux DBL_S0[4] bit 7 INT: mux HEX_S0[4] bit 0 INT: mux HEX_S0[4] bit 3 INT: mux HEX_S0[4] bit 4 INT: mux LH[18] bit 0
B34 - - - - - - INT: mux OMUX[7] bit 3 INT: mux OMUX[6] bit 3 INT: mux IMUX_G1_DATA[3] bit 8 INT: mux IMUX_G1_DATA[3] bit 10 INT: mux IMUX_G1_DATA[3] bit 6 INT: mux IMUX_G1_DATA[3] bit 4 INT: mux IMUX_G1_DATA[3] bit 0 INT: mux IMUX_G1_DATA[3] bit 3 INT: mux DBL_S0[4] bit 0 INT: mux DBL_N0[4] bit 0 INT: mux DBL_N0[4] bit 7 INT: mux DBL_N0[4] bit 4 INT: mux HEX_N0[4] bit 0 INT: mux HEX_N0[4] bit 2 INT: mux HEX_N0[4] bit 4 INT: mux HEX_S0[4] bit 5
B33 - - - - - - INT: mux OMUX[6] bit 4 INT: mux OMUX[7] bit 4 INT: mux IMUX_G1_DATA[3] bit 9 INT: mux IMUX_G1_DATA[3] bit 11 INT: mux IMUX_G1_DATA[2] bit 7 INT: mux IMUX_G1_DATA[2] bit 5 INT: mux IMUX_G1_DATA[2] bit 1 INT: mux IMUX_G1_DATA[2] bit 2 INT: mux DBL_N0[4] bit 3 INT: mux DBL_S0[4] bit 1 INT: mux DBL_N0[4] bit 6 INT: mux DBL_N0[4] bit 5 INT: mux HEX_S0[4] bit 2 INT: mux HEX_S0[4] bit 1 INT: mux HEX_N0[4] bit 5 INT: mux LH[6] bit 1
B32 - - - - - - INT: mux OMUX[7] bit 5 INT: mux OMUX[6] bit 8 INT: mux IMUX_G1_DATA[2] bit 9 INT: mux IMUX_G1_DATA[2] bit 11 INT: mux IMUX_G1_DATA[3] bit 7 INT: mux IMUX_G1_DATA[3] bit 5 INT: mux IMUX_G1_DATA[3] bit 1 INT: mux IMUX_G1_DATA[3] bit 2 INT: mux DBL_N0[4] bit 2 INT: mux DBL_S0[4] bit 2 INT: mux DBL_S0[4] bit 5 INT: mux DBL_S0[4] bit 6 INT: mux HEX_N0[4] bit 3 INT: mux HEX_N0[4] bit 1 INT: mux HEX_N0[4] bit 6 INT: mux HEX_S0[4] bit 6
B31 - - - - - - INT: mux OMUX[6] bit 9 INT: mux OMUX[6] bit 7 INT: mux IMUX_G1_DATA[4] bit 9 INT: mux IMUX_G1_DATA[4] bit 11 INT: mux IMUX_G1_DATA[5] bit 7 INT: mux IMUX_G1_DATA[5] bit 5 INT: mux IMUX_G1_DATA[5] bit 1 INT: mux IMUX_G1_DATA[5] bit 2 INT: mux DBL_E0[3] bit 2 INT: mux DBL_W0[3] bit 3 INT: mux DBL_E0[3] bit 4 INT: mux DBL_E0[3] bit 7 INT: mux HEX_W0[3] bit 1 INT: mux HEX_W0[3] bit 3 INT: mux HEX_W0[3] bit 5 INT: mux LH[6] bit 2
B30 - - - - - - INT: mux OMUX[6] bit 5 INT: mux OMUX[6] bit 6 INT: mux IMUX_G1_DATA[5] bit 9 INT: mux IMUX_G1_DATA[5] bit 11 INT: mux IMUX_G1_DATA[4] bit 7 INT: mux IMUX_G1_DATA[4] bit 5 INT: mux IMUX_G1_DATA[4] bit 1 INT: mux IMUX_G1_DATA[4] bit 2 INT: mux DBL_E0[3] bit 0 INT: mux DBL_W0[3] bit 0 INT: mux DBL_W0[3] bit 7 INT: mux DBL_W0[3] bit 5 INT: mux HEX_E0[3] bit 0 INT: mux HEX_E0[3] bit 3 INT: mux HEX_E0[3] bit 4 INT: mux HEX_W0[3] bit 4
B29 - - - - - - INT: mux OMUX[4] bit 0 INT: mux OMUX[5] bit 6 INT: mux IMUX_G1_DATA[5] bit 8 INT: mux IMUX_G1_DATA[5] bit 10 INT: mux IMUX_G1_DATA[5] bit 6 INT: mux IMUX_G1_DATA[5] bit 4 INT: mux IMUX_G1_DATA[5] bit 0 INT: mux IMUX_G1_DATA[5] bit 3 INT: mux DBL_W0[3] bit 2 INT: mux DBL_E0[3] bit 3 INT: mux DBL_W0[3] bit 6 INT: mux DBL_W0[3] bit 4 INT: mux HEX_W0[3] bit 2 INT: mux HEX_W0[3] bit 0 INT: mux HEX_E0[3] bit 5 INT: mux LH[6] bit 0
B28 - - - - INT: mux IMUX_TI[1] bit 5 INT: mux IMUX_TI[1] bit 9 INT: mux OMUX[5] bit 9 INT: mux OMUX[5] bit 7 INT: mux IMUX_G1_DATA[4] bit 8 INT: mux IMUX_G1_DATA[4] bit 10 INT: mux IMUX_G1_DATA[4] bit 6 INT: mux IMUX_G1_DATA[4] bit 4 INT: mux IMUX_G1_DATA[4] bit 0 INT: mux IMUX_G1_DATA[4] bit 3 INT: mux DBL_W0[3] bit 1 INT: mux DBL_E0[3] bit 1 INT: mux DBL_E0[3] bit 5 INT: mux DBL_E0[3] bit 6 INT: mux HEX_E0[3] bit 2 INT: mux HEX_E0[3] bit 1 INT: mux HEX_E0[3] bit 6 INT: mux HEX_W0[3] bit 6
B27 - - - - INT: !invert IMUX_TI_OPTINV[1] ← IMUX_TI[1] INT: mux IMUX_TI[0] bit 5 INT: mux OMUX[5] bit 0 INT: mux OMUX[5] bit 8 INT: mux IMUX_G1_DATA[6] bit 8 INT: mux IMUX_G1_DATA[6] bit 10 INT: mux IMUX_G1_DATA[6] bit 6 INT: mux IMUX_G1_DATA[6] bit 4 INT: mux IMUX_G1_DATA[6] bit 0 INT: mux IMUX_G1_DATA[6] bit 3 INT: mux DBL_S0[3] bit 3 INT: mux DBL_N0[3] bit 1 INT: mux DBL_S0[3] bit 5 INT: mux DBL_S0[3] bit 7 INT: mux HEX_N0[3] bit 0 INT: mux HEX_N0[3] bit 3 INT: mux HEX_N0[3] bit 4 INT: mux LV[12] bit 4
B26 - - - - INT: mux IMUX_TI[1] bit 7 INT: mux IMUX_TI[1] bit 6 INT: mux OMUX[4] bit 1 INT: mux OMUX[5] bit 1 INT: mux IMUX_G1_DATA[7] bit 8 INT: mux IMUX_G1_DATA[7] bit 10 INT: mux IMUX_G1_DATA[7] bit 6 INT: mux IMUX_G1_DATA[7] bit 4 INT: mux IMUX_G1_DATA[7] bit 0 INT: mux IMUX_G1_DATA[7] bit 3 INT: mux DBL_S0[3] bit 0 INT: mux DBL_N0[3] bit 0 INT: mux DBL_N0[3] bit 7 INT: mux DBL_N0[3] bit 4 INT: mux HEX_S0[3] bit 1 INT: mux HEX_S0[3] bit 2 INT: mux HEX_S0[3] bit 5 INT: mux HEX_N0[3] bit 5
B25 - - - - INT: mux IMUX_TI[0] bit 4 INT: mux IMUX_TI[1] bit 8 INT: mux OMUX[5] bit 2 INT: mux OMUX[4] bit 2 INT: mux IMUX_G1_DATA[7] bit 9 INT: mux IMUX_G1_DATA[7] bit 11 INT: mux IMUX_G1_DATA[6] bit 7 INT: mux IMUX_G1_DATA[6] bit 5 INT: mux IMUX_G1_DATA[6] bit 1 INT: mux IMUX_G1_DATA[6] bit 2 INT: mux DBL_N0[3] bit 3 INT: mux DBL_S0[3] bit 1 INT: mux DBL_N0[3] bit 6 INT: mux DBL_N0[3] bit 5 INT: mux HEX_N0[3] bit 2 INT: mux HEX_N0[3] bit 1 INT: mux HEX_S0[3] bit 4 INT: mux LV[0] bit 3
B24 - - - - INT: mux IMUX_TI[1] bit 4 INT: mux IMUX_TI[1] bit 2 INT: mux OMUX[5] bit 3 INT: mux OMUX[4] bit 3 INT: mux IMUX_G1_DATA[6] bit 9 INT: mux IMUX_G1_DATA[6] bit 11 INT: mux IMUX_G1_DATA[7] bit 7 INT: mux IMUX_G1_DATA[7] bit 5 INT: mux IMUX_G1_DATA[7] bit 1 INT: mux IMUX_G1_DATA[7] bit 2 INT: mux DBL_N0[3] bit 2 INT: mux DBL_S0[3] bit 2 INT: mux DBL_S0[3] bit 4 INT: mux DBL_S0[3] bit 6 INT: mux HEX_S0[3] bit 3 INT: mux HEX_S0[3] bit 0 INT: mux HEX_S0[3] bit 6 INT: mux HEX_N0[3] bit 6
B23 - - - - INT: mux IMUX_TI[0] bit 3 INT: mux IMUX_TI[0] bit 2 INT: mux OMUX[4] bit 4 INT: mux OMUX[5] bit 4 INT: mux IMUX_G1_FAN[0] bit 9 INT: mux IMUX_G1_FAN[0] bit 11 INT: mux IMUX_G1_FAN[1] bit 7 INT: mux IMUX_G1_FAN[1] bit 5 INT: mux IMUX_G1_FAN[1] bit 1 INT: mux IMUX_G1_FAN[1] bit 2 INT: mux DBL_E0[2] bit 4 INT: mux DBL_W0[2] bit 7 INT: mux DBL_E0[2] bit 1 INT: mux DBL_E0[2] bit 3 INT: mux HEX_E0[2] bit 1 INT: mux HEX_E0[2] bit 3 INT: mux HEX_E0[2] bit 5 INT: mux LV[12] bit 3
B22 - - - - INT: mux IMUX_TI[1] bit 1 INT: mux IMUX_TI[1] bit 3 INT: mux OMUX[5] bit 5 INT: mux OMUX[4] bit 8 INT: mux IMUX_G1_FAN[1] bit 9 INT: mux IMUX_G1_FAN[1] bit 11 INT: mux IMUX_G1_FAN[0] bit 7 INT: mux IMUX_G1_FAN[0] bit 5 INT: mux IMUX_G1_FAN[0] bit 1 INT: mux IMUX_G1_FAN[0] bit 2 INT: mux DBL_E0[2] bit 5 INT: mux DBL_W0[2] bit 5 INT: mux DBL_W0[2] bit 3 INT: mux DBL_W0[2] bit 1 INT: mux HEX_W0[2] bit 1 INT: mux HEX_W0[2] bit 3 INT: mux HEX_W0[2] bit 6 INT: mux HEX_E0[2] bit 6
B21 - - - - INT: mux IMUX_TI[0] bit 1 INT: mux IMUX_TI[0] bit 0 INT: mux OMUX[4] bit 9 INT: mux OMUX[4] bit 7 INT: mux IMUX_G1_FAN[1] bit 8 INT: mux IMUX_G1_FAN[1] bit 10 INT: mux IMUX_G1_FAN[1] bit 6 INT: mux IMUX_G1_FAN[1] bit 4 INT: mux IMUX_G1_FAN[1] bit 0 INT: mux IMUX_G1_FAN[1] bit 3 INT: mux DBL_W0[2] bit 4 INT: mux DBL_E0[2] bit 7 INT: mux DBL_W0[2] bit 2 INT: mux DBL_W0[2] bit 0 INT: mux HEX_E0[2] bit 2 INT: mux HEX_E0[2] bit 0 INT: mux HEX_W0[2] bit 5 INT: mux LV[0] bit 2
B20 - - - - INT: mux IMUX_TI[0] bit 7 INT: mux IMUX_TI[0] bit 6 INT: mux OMUX[4] bit 5 INT: mux OMUX[4] bit 6 INT: mux IMUX_G1_FAN[0] bit 8 INT: mux IMUX_G1_FAN[0] bit 10 INT: mux IMUX_G1_FAN[0] bit 6 INT: mux IMUX_G1_FAN[0] bit 4 INT: mux IMUX_G1_FAN[0] bit 0 INT: mux IMUX_G1_FAN[0] bit 3 INT: mux DBL_W0[2] bit 6 INT: mux DBL_E0[2] bit 6 INT: mux DBL_E0[2] bit 0 INT: mux DBL_E0[2] bit 2 INT: mux HEX_W0[2] bit 2 INT: mux HEX_W0[2] bit 0 INT: mux HEX_W0[2] bit 4 INT: mux HEX_E0[2] bit 4
B19 - - - - INT: !invert IMUX_TI_OPTINV[0] ← IMUX_TI[0] INT: mux IMUX_TI[0] bit 8 INT: mux OMUX[2] bit 0 INT: mux OMUX[3] bit 6 INT: mux IMUX_G0_FAN[0] bit 9 INT: mux IMUX_G0_FAN[0] bit 10 INT: mux IMUX_G0_FAN[0] bit 6 INT: mux IMUX_G0_FAN[0] bit 5 INT: mux IMUX_G0_FAN[0] bit 2 INT: mux IMUX_G0_FAN[0] bit 1 INT: mux DBL_S0[2] bit 4 INT: mux DBL_N0[2] bit 6 INT: mux DBL_S0[2] bit 0 INT: mux DBL_S0[2] bit 3 INT: mux HEX_S0[2] bit 0 INT: mux HEX_S0[2] bit 3 INT: mux HEX_S0[2] bit 5 INT: mux LV[0] bit 4
B18 - - - - INT: mux IMUX_TI[1] bit 0 INT: mux IMUX_TI[0] bit 9 INT: mux OMUX[3] bit 9 INT: mux OMUX[3] bit 7 INT: mux IMUX_G0_FAN[1] bit 9 INT: mux IMUX_G0_FAN[1] bit 10 INT: mux IMUX_G0_FAN[1] bit 6 INT: mux IMUX_G0_FAN[1] bit 5 INT: mux IMUX_G0_FAN[1] bit 2 INT: mux IMUX_G0_FAN[1] bit 1 INT: mux DBL_S0[2] bit 5 INT: mux DBL_N0[2] bit 5 INT: mux DBL_N0[2] bit 3 INT: mux DBL_N0[2] bit 0 INT: mux HEX_N0[2] bit 1 INT: mux HEX_N0[2] bit 2 INT: mux HEX_N0[2] bit 4 INT: mux HEX_S0[2] bit 4
B17 - - - - INT: mux IMUX_SR[3] bit 5 INT: mux IMUX_SR[1] bit 1 INT: mux OMUX[3] bit 0 INT: mux OMUX[3] bit 8 INT: mux IMUX_G0_FAN[1] bit 8 INT: mux IMUX_G0_FAN[1] bit 11 INT: mux IMUX_G0_FAN[0] bit 7 INT: mux IMUX_G0_FAN[0] bit 4 INT: mux IMUX_G0_FAN[0] bit 0 INT: mux IMUX_G0_FAN[0] bit 3 INT: mux DBL_N0[2] bit 4 INT: mux DBL_S0[2] bit 6 INT: mux DBL_N0[2] bit 2 INT: mux DBL_N0[2] bit 1 INT: mux HEX_S0[2] bit 2 INT: mux HEX_S0[2] bit 1 INT: mux HEX_N0[2] bit 5 INT: mux LV[12] bit 2
B16 - - - - INT: !invert IMUX_SR_OPTINV[1] ← IMUX_SR[1] INT: mux IMUX_SR[1] bit 3 INT: mux OMUX[2] bit 1 INT: mux OMUX[3] bit 1 INT: mux IMUX_G0_FAN[0] bit 8 INT: mux IMUX_G0_FAN[0] bit 11 INT: mux IMUX_G0_FAN[1] bit 7 INT: mux IMUX_G0_FAN[1] bit 4 INT: mux IMUX_G0_FAN[1] bit 0 INT: mux IMUX_G0_FAN[1] bit 3 INT: mux DBL_N0[2] bit 7 INT: mux DBL_S0[2] bit 7 INT: mux DBL_S0[2] bit 1 INT: mux DBL_S0[2] bit 2 INT: mux HEX_N0[2] bit 3 INT: mux HEX_N0[2] bit 0 INT: mux HEX_N0[2] bit 6 INT: mux HEX_S0[2] bit 6
B15 - - - - INT: mux IMUX_SR[1] bit 0 INT: mux IMUX_SR[1] bit 2 INT: mux OMUX[3] bit 2 INT: mux OMUX[2] bit 2 INT: mux IMUX_G0_DATA[6] bit 8 INT: mux IMUX_G0_DATA[6] bit 11 INT: mux IMUX_G0_DATA[7] bit 7 INT: mux IMUX_G0_DATA[7] bit 4 INT: mux IMUX_G0_DATA[7] bit 0 INT: mux IMUX_G0_DATA[7] bit 3 INT: mux DBL_E0[1] bit 2 INT: mux DBL_W0[1] bit 3 INT: mux DBL_E0[1] bit 4 INT: mux DBL_E0[1] bit 7 INT: mux HEX_W0[1] bit 1 INT: mux HEX_W0[1] bit 2 INT: mux HEX_W0[1] bit 5 INT: mux LV[12] bit 0
B14 - - - - INT: mux IMUX_SR[1] bit 4 INT: mux IMUX_SR[1] bit 5 INT: mux OMUX[3] bit 3 INT: mux OMUX[2] bit 3 INT: mux IMUX_G0_DATA[7] bit 8 INT: mux IMUX_G0_DATA[7] bit 11 INT: mux IMUX_G0_DATA[6] bit 7 INT: mux IMUX_G0_DATA[6] bit 4 INT: mux IMUX_G0_DATA[6] bit 0 INT: mux IMUX_G0_DATA[6] bit 3 INT: mux DBL_E0[1] bit 0 INT: mux DBL_W0[1] bit 0 INT: mux DBL_W0[1] bit 6 INT: mux DBL_W0[1] bit 5 INT: mux HEX_E0[1] bit 0 INT: mux HEX_E0[1] bit 3 INT: mux HEX_E0[1] bit 4 INT: mux HEX_W0[1] bit 4
B13 - - - - INT: mux IMUX_SR[3] bit 4 INT: mux IMUX_SR[3] bit 7 INT: mux OMUX[2] bit 4 INT: mux OMUX[3] bit 4 INT: mux IMUX_G0_DATA[7] bit 9 INT: mux IMUX_G0_DATA[7] bit 10 INT: mux IMUX_G0_DATA[7] bit 6 INT: mux IMUX_G0_DATA[7] bit 5 INT: mux IMUX_G0_DATA[7] bit 2 INT: mux IMUX_G0_DATA[7] bit 1 INT: mux DBL_W0[1] bit 2 INT: mux DBL_E0[1] bit 3 INT: mux DBL_W0[1] bit 7 INT: mux DBL_W0[1] bit 4 INT: mux HEX_W0[1] bit 3 INT: mux HEX_W0[1] bit 0 INT: mux HEX_E0[1] bit 5 INT: mux LV[12] bit 6
B12 - - - - INT: mux IMUX_SR[1] bit 7 INT: mux IMUX_SR[1] bit 6 INT: mux OMUX[3] bit 5 INT: mux OMUX[2] bit 8 INT: mux IMUX_G0_DATA[6] bit 9 INT: mux IMUX_G0_DATA[6] bit 10 INT: mux IMUX_G0_DATA[6] bit 6 INT: mux IMUX_G0_DATA[6] bit 5 INT: mux IMUX_G0_DATA[6] bit 2 INT: mux IMUX_G0_DATA[6] bit 1 INT: mux DBL_W0[1] bit 1 INT: mux DBL_E0[1] bit 1 INT: mux DBL_E0[1] bit 5 INT: mux DBL_E0[1] bit 6 INT: mux HEX_E0[1] bit 2 INT: mux HEX_E0[1] bit 1 INT: mux HEX_E0[1] bit 6 INT: mux HEX_W0[1] bit 6
B11 - - - - INT: mux IMUX_SR[3] bit 0 INT: mux IMUX_SR[3] bit 1 INT: mux OMUX[2] bit 9 INT: mux OMUX[2] bit 7 INT: mux IMUX_G0_DATA[4] bit 9 INT: mux IMUX_G0_DATA[4] bit 10 INT: mux IMUX_G0_DATA[4] bit 6 INT: mux IMUX_G0_DATA[4] bit 5 INT: mux IMUX_G0_DATA[4] bit 2 INT: mux IMUX_G0_DATA[4] bit 1 INT: mux DBL_S0[1] bit 3 INT: mux DBL_N0[1] bit 1 INT: mux DBL_S0[1] bit 4 INT: mux DBL_S0[1] bit 7 INT: mux HEX_N0[1] bit 0 INT: mux HEX_N0[1] bit 3 INT: mux HEX_N0[1] bit 4 INT: mux LV[0] bit 1
B10 - - - - INT: !invert IMUX_SR_OPTINV[3] ← IMUX_SR[3] INT: mux IMUX_SR[3] bit 3 INT: mux OMUX[2] bit 5 INT: mux OMUX[2] bit 6 INT: mux IMUX_G0_DATA[5] bit 9 INT: mux IMUX_G0_DATA[5] bit 10 INT: mux IMUX_G0_DATA[5] bit 6 INT: mux IMUX_G0_DATA[5] bit 5 INT: mux IMUX_G0_DATA[5] bit 2 INT: mux IMUX_G0_DATA[5] bit 1 INT: mux DBL_S0[1] bit 0 INT: mux DBL_N0[1] bit 0 INT: mux DBL_N0[1] bit 7 INT: mux DBL_N0[1] bit 4 INT: mux HEX_S0[1] bit 0 INT: mux HEX_S0[1] bit 2 INT: mux HEX_S0[1] bit 4 INT: mux HEX_N0[1] bit 5
B9 - - - - INT: mux IMUX_SR[3] bit 6 INT: mux IMUX_SR[3] bit 2 INT: mux OMUX[0] bit 0 INT: mux OMUX[1] bit 6 INT: mux IMUX_G0_DATA[5] bit 8 INT: mux IMUX_G0_DATA[5] bit 11 INT: mux IMUX_G0_DATA[4] bit 7 INT: mux IMUX_G0_DATA[4] bit 4 INT: mux IMUX_G0_DATA[4] bit 0 INT: mux IMUX_G0_DATA[4] bit 3 INT: mux DBL_N0[1] bit 3 INT: mux DBL_S0[1] bit 1 INT: mux DBL_N0[1] bit 6 INT: mux DBL_N0[1] bit 5 INT: mux HEX_N0[1] bit 2 INT: mux HEX_N0[1] bit 1 INT: mux HEX_S0[1] bit 5 INT: mux LV[0] bit 5
B8 - - - - INT: mux IMUX_SR[2] bit 5 INT: mux IMUX_SR[2] bit 2 INT: mux OMUX[1] bit 9 INT: mux OMUX[1] bit 7 INT: mux IMUX_G0_DATA[4] bit 8 INT: mux IMUX_G0_DATA[4] bit 11 INT: mux IMUX_G0_DATA[5] bit 7 INT: mux IMUX_G0_DATA[5] bit 4 INT: mux IMUX_G0_DATA[5] bit 0 INT: mux IMUX_G0_DATA[5] bit 3 INT: mux DBL_N0[1] bit 2 INT: mux DBL_S0[1] bit 2 INT: mux DBL_S0[1] bit 5 INT: mux DBL_S0[1] bit 6 INT: mux HEX_S0[1] bit 3 INT: mux HEX_S0[1] bit 1 INT: mux HEX_S0[1] bit 6 INT: mux HEX_N0[1] bit 6
B7 - - - - INT: !invert IMUX_SR_OPTINV[2] ← IMUX_SR[2] INT: mux IMUX_SR[2] bit 3 INT: mux OMUX[1] bit 0 INT: mux OMUX[1] bit 8 INT: mux IMUX_G0_DATA[2] bit 8 INT: mux IMUX_G0_DATA[2] bit 11 INT: mux IMUX_G0_DATA[3] bit 7 INT: mux IMUX_G0_DATA[3] bit 4 INT: mux IMUX_G0_DATA[3] bit 0 INT: mux IMUX_G0_DATA[3] bit 3 INT: mux DBL_E0[0] bit 2 INT: mux DBL_W0[0] bit 3 INT: mux DBL_E0[0] bit 4 INT: mux DBL_E0[0] bit 7 INT: mux HEX_E0[0] bit 0 INT: mux HEX_E0[0] bit 3 INT: mux HEX_E0[0] bit 4 INT: mux LV[0] bit 6
B6 - - - - INT: mux IMUX_SR[2] bit 1 INT: mux IMUX_SR[2] bit 0 INT: mux OMUX[0] bit 1 INT: mux OMUX[1] bit 1 INT: mux IMUX_G0_DATA[3] bit 8 INT: mux IMUX_G0_DATA[3] bit 11 INT: mux IMUX_G0_DATA[2] bit 7 INT: mux IMUX_G0_DATA[2] bit 4 INT: mux IMUX_G0_DATA[2] bit 0 INT: mux IMUX_G0_DATA[2] bit 3 INT: mux DBL_E0[0] bit 0 INT: mux DBL_W0[0] bit 0 INT: mux DBL_W0[0] bit 6 INT: mux DBL_W0[0] bit 5 INT: mux HEX_W0[0] bit 1 INT: mux HEX_W0[0] bit 2 INT: mux HEX_W0[0] bit 5 INT: mux HEX_E0[0] bit 5
B5 - - - - INT: mux IMUX_SR[0] bit 4 INT: mux IMUX_SR[0] bit 5 INT: mux OMUX[1] bit 2 INT: mux OMUX[0] bit 2 INT: mux IMUX_G0_DATA[3] bit 9 INT: mux IMUX_G0_DATA[3] bit 10 INT: mux IMUX_G0_DATA[3] bit 6 INT: mux IMUX_G0_DATA[3] bit 5 INT: mux IMUX_G0_DATA[3] bit 2 INT: mux IMUX_G0_DATA[3] bit 1 INT: mux DBL_W0[0] bit 2 INT: mux DBL_E0[0] bit 3 INT: mux DBL_W0[0] bit 7 INT: mux DBL_W0[0] bit 4 INT: mux HEX_E0[0] bit 2 INT: mux HEX_E0[0] bit 1 INT: mux HEX_W0[0] bit 4 INT: mux LV[0] bit 0
B4 - - - - INT: mux IMUX_SR[2] bit 6 INT: mux IMUX_SR[2] bit 4 INT: mux OMUX[1] bit 3 INT: mux OMUX[0] bit 3 INT: mux IMUX_G0_DATA[2] bit 9 INT: mux IMUX_G0_DATA[2] bit 10 INT: mux IMUX_G0_DATA[2] bit 6 INT: mux IMUX_G0_DATA[2] bit 5 INT: mux IMUX_G0_DATA[2] bit 2 INT: mux IMUX_G0_DATA[2] bit 1 INT: mux DBL_W0[0] bit 1 INT: mux DBL_E0[0] bit 1 INT: mux DBL_E0[0] bit 5 INT: mux DBL_E0[0] bit 6 INT: mux HEX_W0[0] bit 3 INT: mux HEX_W0[0] bit 0 INT: mux HEX_W0[0] bit 6 INT: mux HEX_E0[0] bit 6
B3 - - - - INT: mux IMUX_SR[0] bit 6 INT: mux IMUX_SR[0] bit 7 INT: mux OMUX[0] bit 4 INT: mux OMUX[1] bit 4 INT: mux IMUX_G0_DATA[0] bit 9 INT: mux IMUX_G0_DATA[0] bit 10 INT: mux IMUX_G0_DATA[0] bit 6 INT: mux IMUX_G0_DATA[0] bit 5 INT: mux IMUX_G0_DATA[0] bit 2 INT: mux IMUX_G0_DATA[0] bit 1 INT: mux DBL_S0[0] bit 4 INT: mux DBL_N0[0] bit 6 INT: mux DBL_S0[0] bit 1 INT: mux DBL_S0[0] bit 3 INT: mux HEX_S0[0] bit 1 INT: mux HEX_S0[0] bit 3 INT: mux HEX_S0[0] bit 6 INT: mux LV[12] bit 1
B2 - - - - INT: mux IMUX_SR[0] bit 1 INT: mux IMUX_SR[0] bit 2 INT: mux OMUX[1] bit 5 INT: mux OMUX[0] bit 8 INT: mux IMUX_G0_DATA[1] bit 9 INT: mux IMUX_G0_DATA[1] bit 10 INT: mux IMUX_G0_DATA[1] bit 6 INT: mux IMUX_G0_DATA[1] bit 5 INT: mux IMUX_G0_DATA[1] bit 2 INT: mux IMUX_G0_DATA[1] bit 1 INT: mux DBL_S0[0] bit 5 INT: mux DBL_N0[0] bit 5 INT: mux DBL_N0[0] bit 3 INT: mux DBL_N0[0] bit 1 INT: mux HEX_N0[0] bit 1 INT: mux HEX_N0[0] bit 2 INT: mux HEX_N0[0] bit 5 INT: mux HEX_S0[0] bit 5
B1 - - - - INT: !invert IMUX_SR_OPTINV[0] ← IMUX_SR[0] INT: mux IMUX_SR[0] bit 3 INT: mux OMUX[0] bit 9 INT: mux OMUX[0] bit 7 INT: mux IMUX_G0_DATA[1] bit 8 INT: mux IMUX_G0_DATA[1] bit 11 INT: mux IMUX_G0_DATA[0] bit 7 INT: mux IMUX_G0_DATA[0] bit 4 INT: mux IMUX_G0_DATA[0] bit 0 INT: mux IMUX_G0_DATA[0] bit 3 INT: mux DBL_N0[0] bit 4 INT: mux DBL_S0[0] bit 6 INT: mux DBL_N0[0] bit 2 INT: mux DBL_N0[0] bit 0 INT: mux HEX_S0[0] bit 2 INT: mux HEX_S0[0] bit 0 INT: mux HEX_N0[0] bit 6 INT: mux LV[12] bit 5
B0 - - - - INT: mux IMUX_SR[2] bit 7 INT: mux IMUX_SR[0] bit 0 INT: mux OMUX[0] bit 5 INT: mux OMUX[0] bit 6 INT: mux IMUX_G0_DATA[0] bit 8 INT: mux IMUX_G0_DATA[0] bit 11 INT: mux IMUX_G0_DATA[1] bit 7 INT: mux IMUX_G0_DATA[1] bit 4 INT: mux IMUX_G0_DATA[1] bit 0 INT: mux IMUX_G0_DATA[1] bit 3 INT: mux DBL_N0[0] bit 7 INT: mux DBL_S0[0] bit 7 INT: mux DBL_S0[0] bit 0 INT: mux DBL_S0[0] bit 2 INT: mux HEX_N0[0] bit 3 INT: mux HEX_N0[0] bit 0 INT: mux HEX_N0[0] bit 4 INT: mux HEX_S0[0] bit 4